1 #include <dt-bindings/clock/tegra210-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/memory/tegra210-mc.h>
4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 compatible = "nvidia,tegra210";
9 interrupt-parent = <&lic>;
14 compatible = "nvidia,tegra210-host1x", "simple-bus";
15 reg = <0x0 0x50000000 0x0 0x00034000>;
16 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
17 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
18 clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
19 clock-names = "host1x";
20 resets = <&tegra_car 28>;
21 reset-names = "host1x";
26 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>;
28 dpaux1: dpaux@54040000 {
29 compatible = "nvidia,tegra210-dpaux";
30 reg = <0x0 0x54040000 0x0 0x00040000>;
31 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
32 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>,
33 <&tegra_car TEGRA210_CLK_PLL_DP>;
34 clock-names = "dpaux", "parent";
35 resets = <&tegra_car 207>;
36 reset-names = "dpaux";
41 compatible = "nvidia,tegra210-vi";
42 reg = <0x0 0x54080000 0x0 0x00040000>;
43 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
48 compatible = "nvidia,tegra210-tsec";
49 reg = <0x0 0x54100000 0x0 0x00040000>;
53 compatible = "nvidia,tegra210-dc";
54 reg = <0x0 0x54200000 0x0 0x00040000>;
55 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
56 clocks = <&tegra_car TEGRA210_CLK_DISP1>,
57 <&tegra_car TEGRA210_CLK_PLL_P>;
58 clock-names = "dc", "parent";
59 resets = <&tegra_car 27>;
62 iommus = <&mc TEGRA_SWGROUP_DC>;
68 compatible = "nvidia,tegra210-dc";
69 reg = <0x0 0x54240000 0x0 0x00040000>;
70 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
71 clocks = <&tegra_car TEGRA210_CLK_DISP2>,
72 <&tegra_car TEGRA210_CLK_PLL_P>;
73 clock-names = "dc", "parent";
74 resets = <&tegra_car 26>;
77 iommus = <&mc TEGRA_SWGROUP_DCB>;
83 compatible = "nvidia,tegra210-dsi";
84 reg = <0x0 0x54300000 0x0 0x00040000>;
85 clocks = <&tegra_car TEGRA210_CLK_DSIA>,
86 <&tegra_car TEGRA210_CLK_DSIALP>,
87 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
88 clock-names = "dsi", "lp", "parent";
89 resets = <&tegra_car 48>;
91 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */
100 compatible = "nvidia,tegra210-vic";
101 reg = <0x0 0x54340000 0x0 0x00040000>;
106 compatible = "nvidia,tegra210-nvjpg";
107 reg = <0x0 0x54380000 0x0 0x00040000>;
112 compatible = "nvidia,tegra210-dsi";
113 reg = <0x0 0x54400000 0x0 0x00040000>;
114 clocks = <&tegra_car TEGRA210_CLK_DSIB>,
115 <&tegra_car TEGRA210_CLK_DSIBLP>,
116 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
117 clock-names = "dsi", "lp", "parent";
118 resets = <&tegra_car 82>;
120 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */
124 #address-cells = <1>;
129 compatible = "nvidia,tegra210-nvdec";
130 reg = <0x0 0x54480000 0x0 0x00040000>;
135 compatible = "nvidia,tegra210-nvenc";
136 reg = <0x0 0x544c0000 0x0 0x00040000>;
141 compatible = "nvidia,tegra210-tsec";
142 reg = <0x0 0x54500000 0x0 0x00040000>;
147 compatible = "nvidia,tegra210-sor";
148 reg = <0x0 0x54540000 0x0 0x00040000>;
149 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
150 clocks = <&tegra_car TEGRA210_CLK_SOR0>,
151 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
152 <&tegra_car TEGRA210_CLK_PLL_DP>,
153 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
154 clock-names = "sor", "parent", "dp", "safe";
155 resets = <&tegra_car 182>;
161 compatible = "nvidia,tegra210-sor1";
162 reg = <0x0 0x54580000 0x0 0x00040000>;
163 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
164 clocks = <&tegra_car TEGRA210_CLK_SOR1>,
165 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>,
166 <&tegra_car TEGRA210_CLK_PLL_DP>,
167 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
168 clock-names = "sor", "parent", "dp", "safe";
169 resets = <&tegra_car 183>;
174 dpaux: dpaux@545c0000 {
175 compatible = "nvidia,tegra124-dpaux";
176 reg = <0x0 0x545c0000 0x0 0x00040000>;
177 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
178 clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
179 <&tegra_car TEGRA210_CLK_PLL_DP>;
180 clock-names = "dpaux", "parent";
181 resets = <&tegra_car 181>;
182 reset-names = "dpaux";
187 compatible = "nvidia,tegra210-isp";
188 reg = <0x0 0x54600000 0x0 0x00040000>;
189 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
194 compatible = "nvidia,tegra210-isp";
195 reg = <0x0 0x54680000 0x0 0x00040000>;
196 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
201 compatible = "nvidia,tegra210-i2c-vi";
202 reg = <0x0 0x546c0000 0x0 0x00040000>;
203 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
208 gic: interrupt-controller@50041000 {
209 compatible = "arm,gic-400";
210 #interrupt-cells = <3>;
211 interrupt-controller;
212 reg = <0x0 0x50041000 0x0 0x1000>,
213 <0x0 0x50042000 0x0 0x2000>,
214 <0x0 0x50044000 0x0 0x2000>,
215 <0x0 0x50046000 0x0 0x2000>;
216 interrupts = <GIC_PPI 9
217 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
218 interrupt-parent = <&gic>;
222 compatible = "nvidia,gm20b";
223 reg = <0x0 0x57000000 0x0 0x01000000>,
224 <0x0 0x58000000 0x0 0x01000000>;
225 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
227 interrupt-names = "stall", "nonstall";
228 clocks = <&tegra_car TEGRA210_CLK_GPU>,
229 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
230 <&tegra_car TEGRA210_CLK_PLL_G_REF>;
231 clock-names = "gpu", "pwr", "ref";
232 resets = <&tegra_car 184>;
235 iommus = <&mc TEGRA_SWGROUP_GPU>;
240 lic: interrupt-controller@60004000 {
241 compatible = "nvidia,tegra210-ictlr";
242 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */
243 <0x0 0x60004100 0x0 0x40>, /* secondary controller */
244 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */
245 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */
246 <0x0 0x60004400 0x0 0x40>, /* quinary controller */
247 <0x0 0x60004500 0x0 0x40>; /* senary controller */
248 interrupt-controller;
249 #interrupt-cells = <3>;
250 interrupt-parent = <&gic>;
254 compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer";
255 reg = <0x0 0x60005000 0x0 0x400>;
256 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
257 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
258 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
259 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
260 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
261 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
262 clocks = <&tegra_car TEGRA210_CLK_TIMER>;
263 clock-names = "timer";
266 tegra_car: clock@60006000 {
267 compatible = "nvidia,tegra210-car";
268 reg = <0x0 0x60006000 0x0 0x1000>;
273 flow-controller@60007000 {
274 compatible = "nvidia,tegra210-flowctrl";
275 reg = <0x0 0x60007000 0x0 0x1000>;
278 gpio: gpio@6000d000 {
279 compatible = "nvidia,tegra210-gpio", "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
280 reg = <0x0 0x6000d000 0x0 0x1000>;
281 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
291 #interrupt-cells = <2>;
292 interrupt-controller;
295 apbdma: dma@60020000 {
296 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma";
297 reg = <0x0 0x60020000 0x0 0x1400>;
298 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
301 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
302 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
306 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
307 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
308 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
309 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
310 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
312 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
313 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
314 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
315 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
316 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
317 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
318 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
320 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
326 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
327 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
328 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&tegra_car TEGRA210_CLK_APBDMA>;
332 resets = <&tegra_car 34>;
338 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc";
339 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
340 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */
343 pinmux: pinmux@700008d4 {
344 compatible = "nvidia,tegra210-pinmux";
345 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
346 <0x0 0x70003000 0x0 0x294>; /* Mux registers */
350 * There are two serial driver i.e. 8250 based simple serial
351 * driver and APB DMA based serial driver for higher baudrate
352 * and performance. To enable the 8250 based driver, the compatible
353 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
354 * the APB DMA based serial driver, the compatible is
355 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
357 uarta: serial@70006000 {
358 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
359 reg = <0x0 0x70006000 0x0 0x40>;
361 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&tegra_car TEGRA210_CLK_UARTA>;
363 clock-names = "serial";
364 resets = <&tegra_car 6>;
365 reset-names = "serial";
366 dmas = <&apbdma 8>, <&apbdma 8>;
367 dma-names = "rx", "tx";
371 uartb: serial@70006040 {
372 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
373 reg = <0x0 0x70006040 0x0 0x40>;
375 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
376 clocks = <&tegra_car TEGRA210_CLK_UARTB>;
377 clock-names = "serial";
378 resets = <&tegra_car 7>;
379 reset-names = "serial";
380 dmas = <&apbdma 9>, <&apbdma 9>;
381 dma-names = "rx", "tx";
385 uartc: serial@70006200 {
386 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
387 reg = <0x0 0x70006200 0x0 0x40>;
389 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&tegra_car TEGRA210_CLK_UARTC>;
391 clock-names = "serial";
392 resets = <&tegra_car 55>;
393 reset-names = "serial";
394 dmas = <&apbdma 10>, <&apbdma 10>;
395 dma-names = "rx", "tx";
399 uartd: serial@70006300 {
400 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
401 reg = <0x0 0x70006300 0x0 0x40>;
403 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
404 clocks = <&tegra_car TEGRA210_CLK_UARTD>;
405 clock-names = "serial";
406 resets = <&tegra_car 65>;
407 reset-names = "serial";
408 dmas = <&apbdma 19>, <&apbdma 19>;
409 dma-names = "rx", "tx";
414 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm";
415 reg = <0x0 0x7000a000 0x0 0x100>;
417 clocks = <&tegra_car TEGRA210_CLK_PWM>;
419 resets = <&tegra_car 17>;
425 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
426 reg = <0x0 0x7000c000 0x0 0x100>;
427 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
428 #address-cells = <1>;
430 clocks = <&tegra_car TEGRA210_CLK_I2C1>;
431 clock-names = "div-clk";
432 resets = <&tegra_car 12>;
434 dmas = <&apbdma 21>, <&apbdma 21>;
435 dma-names = "rx", "tx";
440 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
441 reg = <0x0 0x7000c400 0x0 0x100>;
442 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
443 #address-cells = <1>;
445 clocks = <&tegra_car TEGRA210_CLK_I2C2>;
446 clock-names = "div-clk";
447 resets = <&tegra_car 54>;
449 dmas = <&apbdma 22>, <&apbdma 22>;
450 dma-names = "rx", "tx";
455 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
456 reg = <0x0 0x7000c500 0x0 0x100>;
457 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
458 #address-cells = <1>;
460 clocks = <&tegra_car TEGRA210_CLK_I2C3>;
461 clock-names = "div-clk";
462 resets = <&tegra_car 67>;
464 dmas = <&apbdma 23>, <&apbdma 23>;
465 dma-names = "rx", "tx";
470 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
471 reg = <0x0 0x7000c700 0x0 0x100>;
472 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
473 #address-cells = <1>;
475 clocks = <&tegra_car TEGRA210_CLK_I2C4>;
476 clock-names = "div-clk";
477 resets = <&tegra_car 103>;
479 dmas = <&apbdma 26>, <&apbdma 26>;
480 dma-names = "rx", "tx";
485 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
486 reg = <0x0 0x7000d000 0x0 0x100>;
487 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
488 #address-cells = <1>;
490 clocks = <&tegra_car TEGRA210_CLK_I2C5>;
491 clock-names = "div-clk";
492 resets = <&tegra_car 47>;
494 dmas = <&apbdma 24>, <&apbdma 24>;
495 dma-names = "rx", "tx";
500 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
501 reg = <0x0 0x7000d100 0x0 0x100>;
502 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
503 #address-cells = <1>;
505 clocks = <&tegra_car TEGRA210_CLK_I2C6>;
506 clock-names = "div-clk";
507 resets = <&tegra_car 166>;
509 dmas = <&apbdma 30>, <&apbdma 30>;
510 dma-names = "rx", "tx";
515 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
516 reg = <0x0 0x7000d400 0x0 0x200>;
517 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
518 #address-cells = <1>;
520 clocks = <&tegra_car TEGRA210_CLK_SBC1>;
522 resets = <&tegra_car 41>;
524 dmas = <&apbdma 15>, <&apbdma 15>;
525 dma-names = "rx", "tx";
530 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
531 reg = <0x0 0x7000d600 0x0 0x200>;
532 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
533 #address-cells = <1>;
535 clocks = <&tegra_car TEGRA210_CLK_SBC2>;
537 resets = <&tegra_car 44>;
539 dmas = <&apbdma 16>, <&apbdma 16>;
540 dma-names = "rx", "tx";
545 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
546 reg = <0x0 0x7000d800 0x0 0x200>;
547 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
548 #address-cells = <1>;
550 clocks = <&tegra_car TEGRA210_CLK_SBC3>;
552 resets = <&tegra_car 46>;
554 dmas = <&apbdma 17>, <&apbdma 17>;
555 dma-names = "rx", "tx";
560 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
561 reg = <0x0 0x7000da00 0x0 0x200>;
562 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
563 #address-cells = <1>;
565 clocks = <&tegra_car TEGRA210_CLK_SBC4>;
567 resets = <&tegra_car 68>;
569 dmas = <&apbdma 18>, <&apbdma 18>;
570 dma-names = "rx", "tx";
575 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc";
576 reg = <0x0 0x7000e000 0x0 0x100>;
577 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
578 clocks = <&tegra_car TEGRA210_CLK_RTC>;
583 compatible = "nvidia,tegra210-pmc";
584 reg = <0x0 0x7000e400 0x0 0x400>;
585 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
586 clock-names = "pclk", "clk32k_in";
590 compatible = "nvidia,tegra210-efuse";
591 reg = <0x0 0x7000f800 0x0 0x400>;
592 clocks = <&tegra_car TEGRA210_CLK_FUSE>;
593 clock-names = "fuse";
594 resets = <&tegra_car 39>;
595 reset-names = "fuse";
598 mc: memory-controller@70019000 {
599 compatible = "nvidia,tegra210-mc";
600 reg = <0x0 0x70019000 0x0 0x1000>;
601 clocks = <&tegra_car TEGRA210_CLK_MC>;
604 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
610 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda";
611 reg = <0x0 0x70030000 0x0 0x10000>;
612 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
613 clocks = <&tegra_car TEGRA210_CLK_HDA>,
614 <&tegra_car TEGRA210_CLK_HDA2HDMI>,
615 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>;
616 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
617 resets = <&tegra_car 125>, /* hda */
618 <&tegra_car 128>, /* hda2hdmi */
619 <&tegra_car 111>; /* hda2codec_2x */
620 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
625 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
626 reg = <0x0 0x700b0000 0x0 0x200>;
627 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
628 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
629 clock-names = "sdhci";
630 resets = <&tegra_car 14>;
631 reset-names = "sdhci";
636 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
637 reg = <0x0 0x700b0200 0x0 0x200>;
638 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
639 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>;
640 clock-names = "sdhci";
641 resets = <&tegra_car 9>;
642 reset-names = "sdhci";
647 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
648 reg = <0x0 0x700b0400 0x0 0x200>;
649 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
650 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>;
651 clock-names = "sdhci";
652 resets = <&tegra_car 69>;
653 reset-names = "sdhci";
658 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
659 reg = <0x0 0x700b0600 0x0 0x200>;
660 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
661 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>;
662 clock-names = "sdhci";
663 resets = <&tegra_car 15>;
664 reset-names = "sdhci";
668 mipi: mipi@700e3000 {
669 compatible = "nvidia,tegra210-mipi";
670 reg = <0x0 0x700e3000 0x0 0x100>;
671 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>;
672 clock-names = "mipi-cal";
673 #nvidia,mipi-calibrate-cells = <1>;
677 compatible = "nvidia,tegra210-qspi";
678 reg = <0x0 0x70410000 0x0 0x1000>;
679 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
680 #address-cells = <1>;
682 clocks = <&tegra_car TEGRA210_CLK_QSPI>;
683 clock-names = "qspi";
684 resets = <&tegra_car 211>;
685 reset-names = "qspi";
686 dmas = <&apbdma 5>, <&apbdma 5>;
687 dma-names = "rx", "tx";
692 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
693 reg = <0x0 0x7d000000 0x0 0x4000>;
694 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
696 clocks = <&tegra_car TEGRA210_CLK_USBD>;
698 resets = <&tegra_car 22>;
700 nvidia,phy = <&phy1>;
704 phy1: usb-phy@7d000000 {
705 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
706 reg = <0x0 0x7d000000 0x0 0x4000>,
707 <0x0 0x7d000000 0x0 0x4000>;
709 clocks = <&tegra_car TEGRA210_CLK_USBD>,
710 <&tegra_car TEGRA210_CLK_PLL_U>,
711 <&tegra_car TEGRA210_CLK_USBD>;
712 clock-names = "reg", "pll_u", "utmi-pads";
713 resets = <&tegra_car 22>, <&tegra_car 22>;
714 reset-names = "usb", "utmi-pads";
715 nvidia,hssync-start-delay = <0>;
716 nvidia,idle-wait-delay = <17>;
717 nvidia,elastic-limit = <16>;
718 nvidia,term-range-adj = <6>;
719 nvidia,xcvr-setup = <9>;
720 nvidia,xcvr-lsfslew = <0>;
721 nvidia,xcvr-lsrslew = <3>;
722 nvidia,hssquelch-level = <2>;
723 nvidia,hsdiscon-level = <5>;
724 nvidia,xcvr-hsslew = <12>;
725 nvidia,has-utmi-pad-registers;
730 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
731 reg = <0x0 0x7d004000 0x0 0x4000>;
732 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
734 clocks = <&tegra_car TEGRA210_CLK_USB2>;
736 resets = <&tegra_car 58>;
738 nvidia,phy = <&phy2>;
742 phy2: usb-phy@7d004000 {
743 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
744 reg = <0x0 0x7d004000 0x0 0x4000>,
745 <0x0 0x7d000000 0x0 0x4000>;
747 clocks = <&tegra_car TEGRA210_CLK_USB2>,
748 <&tegra_car TEGRA210_CLK_PLL_U>,
749 <&tegra_car TEGRA210_CLK_USBD>;
750 clock-names = "reg", "pll_u", "utmi-pads";
751 resets = <&tegra_car 58>, <&tegra_car 22>;
752 reset-names = "usb", "utmi-pads";
753 nvidia,hssync-start-delay = <0>;
754 nvidia,idle-wait-delay = <17>;
755 nvidia,elastic-limit = <16>;
756 nvidia,term-range-adj = <6>;
757 nvidia,xcvr-setup = <9>;
758 nvidia,xcvr-lsfslew = <0>;
759 nvidia,xcvr-lsrslew = <3>;
760 nvidia,hssquelch-level = <2>;
761 nvidia,hsdiscon-level = <5>;
762 nvidia,xcvr-hsslew = <12>;
767 #address-cells = <1>;
772 compatible = "arm,cortex-a57";
778 compatible = "arm,cortex-a57";
784 compatible = "arm,cortex-a57";
790 compatible = "arm,cortex-a57";
796 compatible = "arm,armv8-timer";
797 interrupts = <GIC_PPI 13
798 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
800 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
802 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
804 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
805 interrupt-parent = <&gic>;