2 * Device Tree Source for UniPhier LD20 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
46 /memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */
49 compatible = "socionext,uniphier-ld20";
52 interrupt-parent = <&gic>;
80 compatible = "arm,cortex-a72", "arm,armv8";
82 enable-method = "spin-table";
83 cpu-release-addr = <0 0x80000000>;
88 compatible = "arm,cortex-a72", "arm,armv8";
90 enable-method = "spin-table";
91 cpu-release-addr = <0 0x80000000>;
96 compatible = "arm,cortex-a53", "arm,armv8";
98 enable-method = "spin-table";
99 cpu-release-addr = <0 0x80000000>;
104 compatible = "arm,cortex-a53", "arm,armv8";
106 enable-method = "spin-table";
107 cpu-release-addr = <0 0x80000000>;
113 compatible = "fixed-clock";
115 clock-frequency = <25000000>;
120 compatible = "fixed-clock";
121 clock-frequency = <58820000>;
126 compatible = "fixed-clock";
127 clock-frequency = <50000000>;
132 compatible = "arm,armv8-timer";
133 interrupts = <1 13 0xf01>,
140 compatible = "simple-bus";
141 #address-cells = <1>;
143 ranges = <0 0 0 0xffffffff>;
145 serial0: serial@54006800 {
146 compatible = "socionext,uniphier-uart";
148 reg = <0x54006800 0x40>;
149 interrupts = <0 33 4>;
150 pinctrl-names = "default";
151 pinctrl-0 = <&pinctrl_uart0>;
152 clocks = <&uart_clk>;
155 serial1: serial@54006900 {
156 compatible = "socionext,uniphier-uart";
158 reg = <0x54006900 0x40>;
159 interrupts = <0 35 4>;
160 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_uart1>;
162 clocks = <&uart_clk>;
165 serial2: serial@54006a00 {
166 compatible = "socionext,uniphier-uart";
168 reg = <0x54006a00 0x40>;
169 interrupts = <0 37 4>;
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_uart2>;
172 clocks = <&uart_clk>;
175 serial3: serial@54006b00 {
176 compatible = "socionext,uniphier-uart";
178 reg = <0x54006b00 0x40>;
179 interrupts = <0 177 4>;
180 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_uart3>;
182 clocks = <&uart_clk>;
186 compatible = "socionext,uniphier-fi2c";
188 reg = <0x58780000 0x80>;
189 #address-cells = <1>;
191 interrupts = <0 41 4>;
192 pinctrl-names = "default";
193 pinctrl-0 = <&pinctrl_i2c0>;
195 clock-frequency = <100000>;
199 compatible = "socionext,uniphier-fi2c";
201 reg = <0x58781000 0x80>;
202 #address-cells = <1>;
204 interrupts = <0 42 4>;
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_i2c1>;
208 clock-frequency = <100000>;
212 compatible = "socionext,uniphier-fi2c";
213 reg = <0x58782000 0x80>;
214 #address-cells = <1>;
216 interrupts = <0 43 4>;
218 clock-frequency = <400000>;
222 compatible = "socionext,uniphier-fi2c";
224 reg = <0x58783000 0x80>;
225 #address-cells = <1>;
227 interrupts = <0 44 4>;
228 pinctrl-names = "default";
229 pinctrl-0 = <&pinctrl_i2c3>;
231 clock-frequency = <100000>;
235 compatible = "socionext,uniphier-fi2c";
237 reg = <0x58784000 0x80>;
238 #address-cells = <1>;
240 interrupts = <0 45 4>;
241 pinctrl-names = "default";
242 pinctrl-0 = <&pinctrl_i2c4>;
244 clock-frequency = <100000>;
248 compatible = "socionext,uniphier-fi2c";
249 reg = <0x58785000 0x80>;
250 #address-cells = <1>;
252 interrupts = <0 25 4>;
254 clock-frequency = <400000>;
257 system_bus: system-bus@58c00000 {
258 compatible = "socionext,uniphier-system-bus";
260 reg = <0x58c00000 0x400>;
261 #address-cells = <2>;
266 compatible = "socionext,uniphier-smpctrl";
267 reg = <0x59801000 0x400>;
271 compatible = "simple-mfd", "syscon";
272 reg = <0x5f800000 0x2000>;
275 compatible = "socionext,uniphier-ld20-pinctrl";
279 gic: interrupt-controller@5fe00000 {
280 compatible = "arm,gic-v3";
281 reg = <0x5fe00000 0x10000>, /* GICD */
282 <0x5fe80000 0x80000>; /* GICR */
283 interrupt-controller;
284 #interrupt-cells = <3>;
285 interrupts = <1 9 4>;
290 /include/ "uniphier-pinctrl.dtsi"