2 * Based on arch/arm/include/asm/mmu_context.h
4 * Copyright (C) 1996 Russell King.
5 * Copyright (C) 2012 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #ifndef __ASM_MMU_CONTEXT_H
20 #define __ASM_MMU_CONTEXT_H
22 #include <linux/compiler.h>
23 #include <linux/sched.h>
25 #include <asm/cacheflush.h>
26 #include <asm/proc-fns.h>
27 #include <asm-generic/mm_hooks.h>
28 #include <asm/cputype.h>
29 #include <asm/pgtable.h>
30 #include <asm/sysreg.h>
31 #include <asm/tlbflush.h>
33 #ifdef CONFIG_PID_IN_CONTEXTIDR
34 static inline void contextidr_thread_switch(struct task_struct *next)
36 write_sysreg(task_pid_nr(next), contextidr_el1);
40 static inline void contextidr_thread_switch(struct task_struct *next)
46 * Set TTBR0 to empty_zero_page. No translations will be possible via TTBR0.
48 static inline void cpu_set_reserved_ttbr0(void)
50 unsigned long ttbr = virt_to_phys(empty_zero_page);
52 write_sysreg(ttbr, ttbr0_el1);
57 * TCR.T0SZ value to use when the ID map is active. Usually equals
58 * TCR_T0SZ(VA_BITS), unless system RAM is positioned very high in
59 * physical memory, in which case it will be smaller.
61 extern u64 idmap_t0sz;
63 static inline bool __cpu_uses_extended_idmap(void)
65 return (!IS_ENABLED(CONFIG_ARM64_VA_BITS_48) &&
66 unlikely(idmap_t0sz != TCR_T0SZ(VA_BITS)));
70 * Set TCR.T0SZ to its default value (based on VA_BITS)
72 static inline void __cpu_set_tcr_t0sz(unsigned long t0sz)
76 if (!__cpu_uses_extended_idmap())
79 tcr = read_sysreg(tcr_el1);
80 tcr &= ~TCR_T0SZ_MASK;
81 tcr |= t0sz << TCR_T0SZ_OFFSET;
82 write_sysreg(tcr, tcr_el1);
86 #define cpu_set_default_tcr_t0sz() __cpu_set_tcr_t0sz(TCR_T0SZ(VA_BITS))
87 #define cpu_set_idmap_tcr_t0sz() __cpu_set_tcr_t0sz(idmap_t0sz)
90 * Remove the idmap from TTBR0_EL1 and install the pgd of the active mm.
92 * The idmap lives in the same VA range as userspace, but uses global entries
93 * and may use a different TCR_EL1.T0SZ. To avoid issues resulting from
94 * speculative TLB fetches, we must temporarily install the reserved page
95 * tables while we invalidate the TLBs and set up the correct TCR_EL1.T0SZ.
97 * If current is a not a user task, the mm covers the TTBR1_EL1 page tables,
98 * which should not be installed in TTBR0_EL1. In this case we can leave the
99 * reserved page tables in place.
101 static inline void cpu_uninstall_idmap(void)
103 struct mm_struct *mm = current->active_mm;
105 cpu_set_reserved_ttbr0();
106 local_flush_tlb_all();
107 cpu_set_default_tcr_t0sz();
110 cpu_switch_mm(mm->pgd, mm);
113 static inline void cpu_install_idmap(void)
115 cpu_set_reserved_ttbr0();
116 local_flush_tlb_all();
117 cpu_set_idmap_tcr_t0sz();
119 cpu_switch_mm(idmap_pg_dir, &init_mm);
123 * Atomically replaces the active TTBR1_EL1 PGD with a new VA-compatible PGD,
124 * avoiding the possibility of conflicting TLB entries being allocated.
126 static inline void cpu_replace_ttbr1(pgd_t *pgd)
128 typedef void (ttbr_replace_func)(phys_addr_t);
129 extern ttbr_replace_func idmap_cpu_replace_ttbr1;
130 ttbr_replace_func *replace_phys;
132 phys_addr_t pgd_phys = virt_to_phys(pgd);
134 replace_phys = (void *)virt_to_phys(idmap_cpu_replace_ttbr1);
137 replace_phys(pgd_phys);
138 cpu_uninstall_idmap();
142 * It would be nice to return ASIDs back to the allocator, but unfortunately
143 * that introduces a race with a generation rollover where we could erroneously
144 * free an ASID allocated in a future generation. We could workaround this by
145 * freeing the ASID from the context of the dying mm (e.g. in arch_exit_mmap),
146 * but we'd then need to make sure that we didn't dirty any TLBs afterwards.
147 * Setting a reserved TTBR0 or EPD0 would work, but it all gets ugly when you
148 * take CPU migration into account.
150 #define destroy_context(mm) do { } while(0)
151 void check_and_switch_context(struct mm_struct *mm, unsigned int cpu);
153 #define init_new_context(tsk,mm) ({ atomic64_set(&(mm)->context.id, 0); 0; })
156 * This is called when "tsk" is about to enter lazy TLB mode.
158 * mm: describes the currently active mm context
159 * tsk: task which is entering lazy tlb
160 * cpu: cpu number which is entering lazy tlb
162 * tsk->mm will be NULL
165 enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
170 * This is the actual mm switch as far as the scheduler
171 * is concerned. No registers are touched. We avoid
172 * calling the CPU specific function when the mm hasn't
176 switch_mm(struct mm_struct *prev, struct mm_struct *next,
177 struct task_struct *tsk)
179 unsigned int cpu = smp_processor_id();
185 * init_mm.pgd does not contain any user mappings and it is always
186 * active for kernel addresses in TTBR1. Just set the reserved TTBR0.
188 if (next == &init_mm) {
189 cpu_set_reserved_ttbr0();
193 check_and_switch_context(next, cpu);
196 #define deactivate_mm(tsk,mm) do { } while (0)
197 #define activate_mm(prev,next) switch_mm(prev, next, NULL)
199 void verify_cpu_asid_bits(void);