2 * Low-level CPU initialisation
3 * Based on arch/arm/kernel/head.S
5 * Copyright (C) 1994-2002 Russell King
6 * Copyright (C) 2003-2012 ARM Ltd.
7 * Authors: Catalin Marinas <catalin.marinas@arm.com>
8 * Will Deacon <will.deacon@arm.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 #include <linux/linkage.h>
24 #include <linux/init.h>
26 #include <asm/assembler.h>
27 #include <asm/ptrace.h>
28 #include <asm/asm-offsets.h>
29 #include <asm/memory.h>
30 #include <asm/thread_info.h>
31 #include <asm/pgtable-hwdef.h>
32 #include <asm/pgtable.h>
37 * swapper_pg_dir is the virtual address of the initial page table. We place
38 * the page tables 3 * PAGE_SIZE below KERNEL_RAM_VADDR. The idmap_pg_dir has
39 * 2 pages and is placed below swapper_pg_dir.
41 #define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET)
43 #if (KERNEL_RAM_VADDR & 0xfffff) != 0x80000
44 #error KERNEL_RAM_VADDR must start at 0xXXX80000
47 #define SWAPPER_DIR_SIZE (3 * PAGE_SIZE)
48 #define IDMAP_DIR_SIZE (2 * PAGE_SIZE)
51 .equ swapper_pg_dir, KERNEL_RAM_VADDR - SWAPPER_DIR_SIZE
54 .equ idmap_pg_dir, swapper_pg_dir - IDMAP_DIR_SIZE
56 .macro pgtbl, ttb0, ttb1, phys
57 add \ttb1, \phys, #TEXT_OFFSET - SWAPPER_DIR_SIZE
58 sub \ttb0, \ttb1, #IDMAP_DIR_SIZE
61 #ifdef CONFIG_ARM64_64K_PAGES
62 #define BLOCK_SHIFT PAGE_SHIFT
63 #define BLOCK_SIZE PAGE_SIZE
65 #define BLOCK_SHIFT SECTION_SHIFT
66 #define BLOCK_SIZE SECTION_SIZE
69 #define KERNEL_START KERNEL_RAM_VADDR
70 #define KERNEL_END _end
73 * Initial memory map attributes.
76 #define PTE_FLAGS PTE_TYPE_PAGE | PTE_AF
77 #define PMD_FLAGS PMD_TYPE_SECT | PMD_SECT_AF
79 #define PTE_FLAGS PTE_TYPE_PAGE | PTE_AF | PTE_SHARED
80 #define PMD_FLAGS PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S
83 #ifdef CONFIG_ARM64_64K_PAGES
84 #define MM_MMUFLAGS PTE_ATTRINDX(MT_NORMAL) | PTE_FLAGS
85 #define IO_MMUFLAGS PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_XN | PTE_FLAGS
87 #define MM_MMUFLAGS PMD_ATTRINDX(MT_NORMAL) | PMD_FLAGS
88 #define IO_MMUFLAGS PMD_ATTRINDX(MT_DEVICE_nGnRE) | PMD_SECT_XN | PMD_FLAGS
92 * Kernel startup entry point.
93 * ---------------------------
95 * The requirements are:
96 * MMU = off, D-cache = off, I-cache = on or off,
97 * x0 = physical address to the FDT blob.
99 * This code is mostly position independent so you call this at
100 * __pa(PAGE_OFFSET + TEXT_OFFSET).
102 * Note that the callee-saved registers are used for storing variables
103 * that are useful before the MMU is enabled. The allocations are described
104 * in the entry routines.
109 * DO NOT MODIFY. Image header expected by Linux boot-loaders.
111 b stext // branch to kernel start, magic
113 .quad TEXT_OFFSET // Image load offset from start of RAM
118 mov x21, x0 // x21=FDT
119 bl __calc_phys_offset // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET
120 bl el2_setup // Drop to EL1
121 mrs x22, midr_el1 // x22=cpuid
123 bl lookup_processor_type
124 mov x23, x0 // x23=current cpu_table
125 cbz x23, __error_p // invalid processor (x23=0)?
127 bl __create_page_tables // x25=TTBR0, x26=TTBR1
129 * The following calls CPU specific code in a position independent
130 * manner. See arch/arm64/mm/proc.S for details. x23 = base of
131 * cpu_info structure selected by lookup_processor_type above.
132 * On return, the CPU will be ready for the MMU to be turned on and
133 * the TCR will have been set.
135 ldr x27, __switch_data // address to jump to after
136 // MMU has been enabled
137 adr lr, __enable_mmu // return (PIC) address
138 ldr x12, [x23, #CPU_INFO_SETUP]
139 add x12, x12, x28 // __virt_to_phys
140 br x12 // initialise processor
144 * If we're fortunate enough to boot at EL2, ensure that the world is
145 * sane before dropping to EL1.
149 cmp x0, #PSR_MODE_EL2t
150 ccmp x0, #PSR_MODE_EL2h, #0x4, ne
151 ldr x0, =__boot_cpu_mode // Compute __boot_cpu_mode
154 str wzr, [x0] // Remember we don't have EL2...
157 /* Hyp configuration. */
158 1: ldr w1, =BOOT_CPU_MODE_EL2
159 str w1, [x0, #4] // This CPU has EL2
160 mov x0, #(1 << 31) // 64-bit EL1
163 /* Generic timers. */
165 orr x0, x0, #3 // Enable EL1 physical timers
167 msr cntvoff_el2, xzr // Clear virtual offset
169 /* Populate ID registers. */
176 mov x0, #0x0800 // Set/clear RES{1,0} bits
177 movk x0, #0x30d0, lsl #16
180 /* Coprocessor traps. */
182 msr cptr_el2, x0 // Disable copro. traps to EL2
185 msr hstr_el2, xzr // Disable CP15 traps to EL2
189 mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\
197 * We need to find out the CPU boot mode long after boot, so we need to
198 * store it in a writable variable.
200 * This is not in .bss, because we set it sufficiently early that the boot-time
201 * zeroing of .bss would clobber it.
204 ENTRY(__boot_cpu_mode)
205 .long BOOT_CPU_MODE_EL2
214 .pushsection .smp.pen.text, "ax"
217 .quad secondary_holding_pen_release
220 * This provides a "holding pen" for platforms to hold all secondary
221 * cores are held until we're ready for them to initialise.
223 ENTRY(secondary_holding_pen)
224 bl __calc_phys_offset // x24=phys offset
225 bl el2_setup // Drop to EL1
227 and x0, x0, #15 // CPU number
234 b.eq secondary_startup
237 ENDPROC(secondary_holding_pen)
240 ENTRY(secondary_startup)
242 * Common entry point for secondary CPUs.
244 mrs x22, midr_el1 // x22=cpuid
246 bl lookup_processor_type
247 mov x23, x0 // x23=current cpu_table
248 cbz x23, __error_p // invalid processor (x23=0)?
250 pgtbl x25, x26, x24 // x25=TTBR0, x26=TTBR1
251 ldr x12, [x23, #CPU_INFO_SETUP]
252 add x12, x12, x28 // __virt_to_phys
253 blr x12 // initialise processor
255 ldr x21, =secondary_data
256 ldr x27, =__secondary_switched // address to jump to after enabling the MMU
258 ENDPROC(secondary_startup)
260 ENTRY(__secondary_switched)
261 ldr x0, [x21] // get secondary_data.stack
264 b secondary_start_kernel
265 ENDPROC(__secondary_switched)
266 #endif /* CONFIG_SMP */
269 * Setup common bits before finally enabling the MMU. Essentially this is just
270 * loading the page table pointer and vector base registers.
272 * On entry to this code, x0 must contain the SCTLR_EL1 value for turning on
278 msr ttbr0_el1, x25 // load TTBR0
279 msr ttbr1_el1, x26 // load TTBR1
282 ENDPROC(__enable_mmu)
285 * Enable the MMU. This completely changes the structure of the visible memory
286 * space. You will not be able to trace execution through this.
288 * x0 = system control register
289 * x27 = *virtual* address to jump to upon completion
291 * other registers depend on the function called upon completion
298 ENDPROC(__turn_mmu_on)
301 * Calculate the start of physical memory.
306 sub x28, x0, x1 // x28 = PHYS_OFFSET - PAGE_OFFSET
307 add x24, x2, x28 // x24 = PHYS_OFFSET
309 ENDPROC(__calc_phys_offset)
316 * Macro to populate the PGD for the corresponding block entry in the next
317 * level (tbl) for the given virtual address.
319 * Preserves: pgd, tbl, virt
320 * Corrupts: tmp1, tmp2
322 .macro create_pgd_entry, pgd, tbl, virt, tmp1, tmp2
323 lsr \tmp1, \virt, #PGDIR_SHIFT
324 and \tmp1, \tmp1, #PTRS_PER_PGD - 1 // PGD index
325 orr \tmp2, \tbl, #3 // PGD entry table type
326 str \tmp2, [\pgd, \tmp1, lsl #3]
330 * Macro to populate block entries in the page table for the start..end
331 * virtual range (inclusive).
333 * Preserves: tbl, flags
334 * Corrupts: phys, start, end, pstate
336 .macro create_block_map, tbl, flags, phys, start, end, idmap=0
337 lsr \phys, \phys, #BLOCK_SHIFT
339 and \start, \phys, #PTRS_PER_PTE - 1 // table index
341 lsr \start, \start, #BLOCK_SHIFT
342 and \start, \start, #PTRS_PER_PTE - 1 // table index
344 orr \phys, \flags, \phys, lsl #BLOCK_SHIFT // table entry
346 lsr \end, \end, #BLOCK_SHIFT
347 and \end, \end, #PTRS_PER_PTE - 1 // table end index
349 9999: str \phys, [\tbl, \start, lsl #3] // store the entry
351 add \start, \start, #1 // next entry
352 add \phys, \phys, #BLOCK_SIZE // next block
359 * Setup the initial page tables. We only setup the barest amount which is
360 * required to get the kernel running. The following sections are required:
361 * - identity mapping to enable the MMU (low address, TTBR0)
362 * - first few MB of the kernel linear mapping to jump to once the MMU has
363 * been enabled, including the FDT blob (TTBR1)
365 __create_page_tables:
366 pgtbl x25, x26, x24 // idmap_pg_dir and swapper_pg_dir addresses
369 * Clear the idmap and swapper page tables.
372 add x6, x26, #SWAPPER_DIR_SIZE
373 1: stp xzr, xzr, [x0], #16
374 stp xzr, xzr, [x0], #16
375 stp xzr, xzr, [x0], #16
376 stp xzr, xzr, [x0], #16
383 * Create the identity mapping.
385 add x0, x25, #PAGE_SIZE // section table address
386 adr x3, __turn_mmu_on // virtual/physical address
387 create_pgd_entry x25, x0, x3, x5, x6
388 create_block_map x0, x7, x3, x5, x5, idmap=1
391 * Map the kernel image (starting with PHYS_OFFSET).
393 add x0, x26, #PAGE_SIZE // section table address
395 create_pgd_entry x26, x0, x5, x3, x6
396 ldr x6, =KERNEL_END - 1
397 mov x3, x24 // phys offset
398 create_block_map x0, x7, x3, x5, x6
401 * Map the FDT blob (maximum 2MB; must be within 512MB of
404 mov x3, x21 // FDT phys address
405 and x3, x3, #~((1 << 21) - 1) // 2MB aligned
407 sub x5, x3, x24 // subtract PHYS_OFFSET
408 tst x5, #~((1 << 29) - 1) // within 512MB?
409 csel x21, xzr, x21, ne // zero the FDT pointer
411 add x5, x5, x6 // __va(FDT blob)
412 add x6, x5, #1 << 21 // 2MB for the FDT blob
413 sub x6, x6, #1 // inclusive range
414 create_block_map x0, x7, x3, x5, x6
417 ENDPROC(__create_page_tables)
421 .type __switch_data, %object
423 .quad __mmap_switched
424 .quad __data_loc // x4
426 .quad __bss_start // x6
428 .quad processor_id // x4
429 .quad __fdt_pointer // x5
430 .quad memstart_addr // x6
431 .quad init_thread_union + THREAD_START_SP // sp
434 * The following fragment of code is executed with the MMU on in MMU mode, and
435 * uses absolute addresses; this is not position independent.
438 adr x3, __switch_data + 8
440 ldp x4, x5, [x3], #16
441 ldp x6, x7, [x3], #16
442 cmp x4, x5 // Copy data segment if needed
443 1: ccmp x5, x6, #4, ne
451 str xzr, [x6], #8 // Clear BSS
454 ldp x4, x5, [x3], #16
458 str x22, [x4] // Save processor ID
459 str x21, [x5] // Save FDT pointer
460 str x24, [x6] // Save PHYS_OFFSET
463 ENDPROC(__mmap_switched)
466 * Exception handling. Something went wrong and we can't proceed. We ought to
467 * tell the user, but since we don't have any guarantee that we're even
468 * running on the right architecture, we do virtually nothing.
479 * This function gets the processor ID in w0 and searches the cpu_table[] for
480 * a match. It returns a pointer to the struct cpu_info it found. The
481 * cpu_table[] must end with an empty (all zeros) structure.
483 * This routine can be called via C code and it needs to work with the MMU
484 * both disabled and enabled (the offset is calculated automatically).
486 ENTRY(lookup_processor_type)
487 adr x1, __lookup_processor_type_data
489 sub x1, x1, x2 // get offset between VA and PA
490 add x3, x3, x1 // convert VA to PA
492 ldp w5, w6, [x3] // load cpu_id_val and cpu_id_mask
493 cbz w5, 2f // end of list?
497 add x3, x3, #CPU_INFO_SZ
500 mov x3, #0 // unknown processor
504 ENDPROC(lookup_processor_type)
507 .type __lookup_processor_type_data, %object
508 __lookup_processor_type_data:
511 .size __lookup_processor_type_data, . - __lookup_processor_type_data
514 * Determine validity of the x21 FDT pointer.
515 * The dtb must be 8-byte aligned and live in the first 512M of memory.