2 * Low-level CPU initialisation
3 * Based on arch/arm/kernel/head.S
5 * Copyright (C) 1994-2002 Russell King
6 * Copyright (C) 2003-2012 ARM Ltd.
7 * Authors: Catalin Marinas <catalin.marinas@arm.com>
8 * Will Deacon <will.deacon@arm.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 #include <linux/linkage.h>
24 #include <linux/init.h>
25 #include <linux/irqchip/arm-gic-v3.h>
27 #include <asm/assembler.h>
28 #include <asm/ptrace.h>
29 #include <asm/asm-offsets.h>
30 #include <asm/cache.h>
31 #include <asm/cputype.h>
33 #include <asm/kernel-pgtable.h>
34 #include <asm/kvm_arm.h>
35 #include <asm/memory.h>
36 #include <asm/pgtable-hwdef.h>
37 #include <asm/pgtable.h>
40 #include <asm/sysreg.h>
41 #include <asm/thread_info.h>
44 #define __PHYS_OFFSET (KERNEL_START - TEXT_OFFSET)
46 #if (TEXT_OFFSET & 0xfff) != 0
47 #error TEXT_OFFSET must be at least 4KB aligned
48 #elif (PAGE_OFFSET & 0x1fffff) != 0
49 #error PAGE_OFFSET must be at least 2MB aligned
50 #elif TEXT_OFFSET > 0x1fffff
51 #error TEXT_OFFSET must be less than 2MB
54 #define KERNEL_START _text
55 #define KERNEL_END _end
58 * Kernel startup entry point.
59 * ---------------------------
61 * The requirements are:
62 * MMU = off, D-cache = off, I-cache = on or off,
63 * x0 = physical address to the FDT blob.
65 * This code is mostly position independent so you call this at
66 * __pa(PAGE_OFFSET + TEXT_OFFSET).
68 * Note that the callee-saved registers are used for storing variables
69 * that are useful before the MMU is enabled. The allocations are described
70 * in the entry routines.
75 * DO NOT MODIFY. Image header expected by Linux boot-loaders.
79 * This add instruction has no meaningful effect except that
80 * its opcode forms the magic "MZ" signature required by UEFI.
85 b stext // branch to kernel start, magic
88 le64sym _kernel_offset_le // Image load offset from start of RAM, little-endian
89 le64sym _kernel_size_le // Effective size of kernel image, little-endian
90 le64sym _kernel_flags_le // Informative flags, little-endian
94 .byte 0x41 // Magic number, "ARM\x64"
99 .long pe_header - _head // Offset to the PE header.
110 .short 0xaa64 // AArch64
111 .short 2 // nr_sections
112 .long 0 // TimeDateStamp
113 .long 0 // PointerToSymbolTable
114 .long 1 // NumberOfSymbols
115 .short section_table - optional_header // SizeOfOptionalHeader
116 .short 0x206 // Characteristics.
117 // IMAGE_FILE_DEBUG_STRIPPED |
118 // IMAGE_FILE_EXECUTABLE_IMAGE |
119 // IMAGE_FILE_LINE_NUMS_STRIPPED
121 .short 0x20b // PE32+ format
122 .byte 0x02 // MajorLinkerVersion
123 .byte 0x14 // MinorLinkerVersion
124 .long _end - efi_header_end // SizeOfCode
125 .long 0 // SizeOfInitializedData
126 .long 0 // SizeOfUninitializedData
127 .long __efistub_entry - _head // AddressOfEntryPoint
128 .long efi_header_end - _head // BaseOfCode
132 .long 0x1000 // SectionAlignment
133 .long PECOFF_FILE_ALIGNMENT // FileAlignment
134 .short 0 // MajorOperatingSystemVersion
135 .short 0 // MinorOperatingSystemVersion
136 .short 0 // MajorImageVersion
137 .short 0 // MinorImageVersion
138 .short 0 // MajorSubsystemVersion
139 .short 0 // MinorSubsystemVersion
140 .long 0 // Win32VersionValue
142 .long _end - _head // SizeOfImage
144 // Everything before the kernel image is considered part of the header
145 .long efi_header_end - _head // SizeOfHeaders
147 .short 0xa // Subsystem (EFI application)
148 .short 0 // DllCharacteristics
149 .quad 0 // SizeOfStackReserve
150 .quad 0 // SizeOfStackCommit
151 .quad 0 // SizeOfHeapReserve
152 .quad 0 // SizeOfHeapCommit
153 .long 0 // LoaderFlags
154 .long 0x6 // NumberOfRvaAndSizes
156 .quad 0 // ExportTable
157 .quad 0 // ImportTable
158 .quad 0 // ResourceTable
159 .quad 0 // ExceptionTable
160 .quad 0 // CertificationTable
161 .quad 0 // BaseRelocationTable
167 * The EFI application loader requires a relocation section
168 * because EFI applications must be relocatable. This is a
169 * dummy section as far as we are concerned.
173 .byte 0 // end of 0 padding of section name
176 .long 0 // SizeOfRawData
177 .long 0 // PointerToRawData
178 .long 0 // PointerToRelocations
179 .long 0 // PointerToLineNumbers
180 .short 0 // NumberOfRelocations
181 .short 0 // NumberOfLineNumbers
182 .long 0x42100040 // Characteristics (section flags)
188 .byte 0 // end of 0 padding of section name
189 .long _end - efi_header_end // VirtualSize
190 .long efi_header_end - _head // VirtualAddress
191 .long _edata - efi_header_end // SizeOfRawData
192 .long efi_header_end - _head // PointerToRawData
194 .long 0 // PointerToRelocations (0 for executables)
195 .long 0 // PointerToLineNumbers (0 for executables)
196 .short 0 // NumberOfRelocations (0 for executables)
197 .short 0 // NumberOfLineNumbers (0 for executables)
198 .long 0xe0500020 // Characteristics (section flags)
201 * EFI will load .text onwards at the 4k section alignment
202 * described in the PE/COFF header. To ensure that instruction
203 * sequences using an adrp and a :lo12: immediate will function
204 * correctly at this alignment, we must ensure that .text is
205 * placed at a 4k boundary in the Image to begin with.
214 bl preserve_boot_args
215 bl el2_setup // Drop to EL1, w20=cpu_boot_mode
216 mov x23, xzr // KASLR offset, defaults to 0
217 adrp x24, __PHYS_OFFSET
218 bl set_cpu_boot_mode_flag
219 bl __create_page_tables // x25=TTBR0, x26=TTBR1
221 * The following calls CPU setup code, see arch/arm64/mm/proc.S for
223 * On return, the CPU will be ready for the MMU to be turned on and
224 * the TCR will have been set.
226 bl __cpu_setup // initialise processor
227 adr_l x27, __primary_switch // address to jump to after
228 // MMU has been enabled
233 * Preserve the arguments passed by the bootloader in x0 .. x3
236 mov x21, x0 // x21=FDT
238 adr_l x0, boot_args // record the contents of
239 stp x21, x1, [x0] // x0 .. x3 at kernel entry
240 stp x2, x3, [x0, #16]
242 dmb sy // needed before dc ivac with
245 add x1, x0, #0x20 // 4 x 8 bytes
246 b __inval_cache_range // tail call
247 ENDPROC(preserve_boot_args)
250 * Macro to create a table entry to the next page.
252 * tbl: page table address
253 * virt: virtual address
254 * shift: #imm page table shift
255 * ptrs: #imm pointers per table page
258 * Corrupts: tmp1, tmp2
259 * Returns: tbl -> next level table page address
261 .macro create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2
262 lsr \tmp1, \virt, #\shift
263 and \tmp1, \tmp1, #\ptrs - 1 // table index
264 add \tmp2, \tbl, #PAGE_SIZE
265 orr \tmp2, \tmp2, #PMD_TYPE_TABLE // address of next table and entry type
266 str \tmp2, [\tbl, \tmp1, lsl #3]
267 add \tbl, \tbl, #PAGE_SIZE // next level table page
271 * Macro to populate the PGD (and possibily PUD) for the corresponding
272 * block entry in the next level (tbl) for the given virtual address.
274 * Preserves: tbl, next, virt
275 * Corrupts: tmp1, tmp2
277 .macro create_pgd_entry, tbl, virt, tmp1, tmp2
278 create_table_entry \tbl, \virt, PGDIR_SHIFT, PTRS_PER_PGD, \tmp1, \tmp2
279 #if SWAPPER_PGTABLE_LEVELS > 3
280 create_table_entry \tbl, \virt, PUD_SHIFT, PTRS_PER_PUD, \tmp1, \tmp2
282 #if SWAPPER_PGTABLE_LEVELS > 2
283 create_table_entry \tbl, \virt, SWAPPER_TABLE_SHIFT, PTRS_PER_PTE, \tmp1, \tmp2
288 * Macro to populate block entries in the page table for the start..end
289 * virtual range (inclusive).
291 * Preserves: tbl, flags
292 * Corrupts: phys, start, end, pstate
294 .macro create_block_map, tbl, flags, phys, start, end
295 lsr \phys, \phys, #SWAPPER_BLOCK_SHIFT
296 lsr \start, \start, #SWAPPER_BLOCK_SHIFT
297 and \start, \start, #PTRS_PER_PTE - 1 // table index
298 orr \phys, \flags, \phys, lsl #SWAPPER_BLOCK_SHIFT // table entry
299 lsr \end, \end, #SWAPPER_BLOCK_SHIFT
300 and \end, \end, #PTRS_PER_PTE - 1 // table end index
301 9999: str \phys, [\tbl, \start, lsl #3] // store the entry
302 add \start, \start, #1 // next entry
303 add \phys, \phys, #SWAPPER_BLOCK_SIZE // next block
309 * Setup the initial page tables. We only setup the barest amount which is
310 * required to get the kernel running. The following sections are required:
311 * - identity mapping to enable the MMU (low address, TTBR0)
312 * - first few MB of the kernel linear mapping to jump to once the MMU has
315 __create_page_tables:
316 adrp x25, idmap_pg_dir
317 adrp x26, swapper_pg_dir
321 * Invalidate the idmap and swapper page tables to avoid potential
322 * dirty cache lines being evicted.
325 add x1, x26, #SWAPPER_DIR_SIZE
326 bl __inval_cache_range
329 * Clear the idmap and swapper page tables.
332 add x6, x26, #SWAPPER_DIR_SIZE
333 1: stp xzr, xzr, [x0], #16
334 stp xzr, xzr, [x0], #16
335 stp xzr, xzr, [x0], #16
336 stp xzr, xzr, [x0], #16
340 mov x7, SWAPPER_MM_MMUFLAGS
343 * Create the identity mapping.
345 mov x0, x25 // idmap_pg_dir
346 adrp x3, __idmap_text_start // __pa(__idmap_text_start)
348 #ifndef CONFIG_ARM64_VA_BITS_48
349 #define EXTRA_SHIFT (PGDIR_SHIFT + PAGE_SHIFT - 3)
350 #define EXTRA_PTRS (1 << (48 - EXTRA_SHIFT))
353 * If VA_BITS < 48, it may be too small to allow for an ID mapping to be
354 * created that covers system RAM if that is located sufficiently high
355 * in the physical address space. So for the ID map, use an extended
356 * virtual range in that case, by configuring an additional translation
358 * First, we have to verify our assumption that the current value of
359 * VA_BITS was chosen such that all translation levels are fully
360 * utilised, and that lowering T0SZ will always result in an additional
361 * translation level to be configured.
363 #if VA_BITS != EXTRA_SHIFT
364 #error "Mismatch between VA_BITS and page size/number of translation levels"
368 * Calculate the maximum allowed value for TCR_EL1.T0SZ so that the
369 * entire ID map region can be mapped. As T0SZ == (64 - #bits used),
370 * this number conveniently equals the number of leading zeroes in
371 * the physical address of __idmap_text_end.
373 adrp x5, __idmap_text_end
375 cmp x5, TCR_T0SZ(VA_BITS) // default T0SZ small enough?
376 b.ge 1f // .. then skip additional level
381 dc ivac, x6 // Invalidate potentially stale cache line
383 create_table_entry x0, x3, EXTRA_SHIFT, EXTRA_PTRS, x5, x6
387 create_pgd_entry x0, x3, x5, x6
388 mov x5, x3 // __pa(__idmap_text_start)
389 adr_l x6, __idmap_text_end // __pa(__idmap_text_end)
390 create_block_map x0, x7, x3, x5, x6
393 * Map the kernel image (starting with PHYS_OFFSET).
395 mov x0, x26 // swapper_pg_dir
396 mov_q x5, KIMAGE_VADDR
397 add x5, x5, x23 // add KASLR displacement
398 create_pgd_entry x0, x5, x3, x6
399 ldr w6, =kernel_img_size
401 mov x3, x24 // phys offset
402 create_block_map x0, x7, x3, x5, x6
405 * Since the page tables have been populated with non-cacheable
406 * accesses (MMU disabled), invalidate the idmap and swapper page
407 * tables again to remove any speculatively loaded cache lines.
410 add x1, x26, #SWAPPER_DIR_SIZE
412 bl __inval_cache_range
415 ENDPROC(__create_page_tables)
419 * The following fragment of code is executed with the MMU enabled.
421 .set initial_sp, init_thread_union + THREAD_START_SP
423 mov x28, lr // preserve LR
424 adr_l x8, vectors // load VBAR_EL1 with virtual
425 msr vbar_el1, x8 // vector table address
429 adr_l x0, __bss_start
434 dsb ishst // Make zero page visible to PTW
436 adr_l sp, initial_sp, x4
438 and x4, x4, #~(THREAD_SIZE - 1)
439 msr sp_el0, x4 // Save thread_info
440 str_l x21, __fdt_pointer, x5 // Save FDT pointer
442 ldr_l x4, kimage_vaddr // Save the offset between
443 sub x4, x4, x24 // the kernel virtual and
444 str_l x4, kimage_voffset, x5 // physical mappings
450 #ifdef CONFIG_RANDOMIZE_BASE
451 cbnz x23, 0f // already running randomized?
452 mov x0, x21 // pass FDT address in x0
453 bl kaslr_early_init // parse FDT for KASLR options
454 cbz x0, 0f // KASLR disabled? just proceed
455 mov x23, x0 // record KASLR offset
456 ret x28 // we must enable KASLR, return
461 ENDPROC(__primary_switched)
464 * end early head section, begin head code that is also used for
465 * hotplug and needs to have the same protections as the text region
467 .section ".text","ax"
470 .quad _text - TEXT_OFFSET
473 * If we're fortunate enough to boot at EL2, ensure that the world is
474 * sane before dropping to EL1.
476 * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in x20 if
477 * booted in EL1 or EL2 respectively.
481 cmp x0, #CurrentEL_EL2
484 CPU_BE( orr x0, x0, #(1 << 25) ) // Set the EE bit for EL2
485 CPU_LE( bic x0, x0, #(1 << 25) ) // Clear the EE bit for EL2
489 CPU_BE( orr x0, x0, #(3 << 24) ) // Set the EE and E0E bits for EL1
490 CPU_LE( bic x0, x0, #(3 << 24) ) // Clear the EE and E0E bits for EL1
492 mov w20, #BOOT_CPU_MODE_EL1 // This cpu booted in EL1
497 #ifdef CONFIG_ARM64_VHE
499 * Check for VHE being present. For the rest of the EL2 setup,
500 * x2 being non-zero indicates that we do have VHE, and that the
501 * kernel is intended to run at EL2.
503 mrs x2, id_aa64mmfr1_el1
509 /* Hyp configuration. */
510 mov x0, #HCR_RW // 64-bit EL1
512 orr x0, x0, #HCR_TGE // Enable Host Extensions
518 /* Generic timers. */
520 orr x0, x0, #3 // Enable EL1 physical timers
522 msr cntvoff_el2, xzr // Clear virtual offset
524 #ifdef CONFIG_ARM_GIC_V3
525 /* GICv3 system register access */
526 mrs x0, id_aa64pfr0_el1
531 mrs_s x0, ICC_SRE_EL2
532 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1
533 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1
534 msr_s ICC_SRE_EL2, x0
535 isb // Make sure SRE is now set
536 mrs_s x0, ICC_SRE_EL2 // Read SRE back,
537 tbz x0, #0, 3f // and check that it sticks
538 msr_s ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults
543 /* Populate ID registers. */
550 mov x0, #0x0800 // Set/clear RES{1,0} bits
551 CPU_BE( movk x0, #0x33d0, lsl #16 ) // Set EE and E0E on BE systems
552 CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems
555 /* Coprocessor traps. */
557 msr cptr_el2, x0 // Disable copro. traps to EL2
560 msr hstr_el2, xzr // Disable CP15 traps to EL2
564 mrs x0, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer
567 b.lt 4f // Skip if no PMU present
568 mrs x0, pmcr_el0 // Disable debug access traps
569 ubfx x0, x0, #11, #5 // to EL2 and allow access to
570 msr mdcr_el2, x0 // all PMU counters from EL1
573 /* Stage-2 translation */
576 cbz x2, install_el2_stub
578 mov w20, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2
583 /* Hypervisor stub */
584 adrp x0, __hyp_stub_vectors
585 add x0, x0, #:lo12:__hyp_stub_vectors
589 mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\
593 mov w20, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2
598 * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed
599 * in x20. See arch/arm64/include/asm/virt.h for more info.
601 set_cpu_boot_mode_flag:
602 adr_l x1, __boot_cpu_mode
603 cmp w20, #BOOT_CPU_MODE_EL2
606 1: str w20, [x1] // This CPU has booted in EL1
608 dc ivac, x1 // Invalidate potentially stale cache line
610 ENDPROC(set_cpu_boot_mode_flag)
613 * We need to find out the CPU boot mode long after boot, so we need to
614 * store it in a writable variable.
616 * This is not in .bss, because we set it sufficiently early that the boot-time
617 * zeroing of .bss would clobber it.
619 .pushsection .data..cacheline_aligned
620 .align L1_CACHE_SHIFT
621 ENTRY(__boot_cpu_mode)
622 .long BOOT_CPU_MODE_EL2
623 .long BOOT_CPU_MODE_EL1
627 * This provides a "holding pen" for platforms to hold all secondary
628 * cores are held until we're ready for them to initialise.
630 ENTRY(secondary_holding_pen)
631 bl el2_setup // Drop to EL1, w20=cpu_boot_mode
632 bl set_cpu_boot_mode_flag
634 mov_q x1, MPIDR_HWID_BITMASK
636 adr_l x3, secondary_holding_pen_release
639 b.eq secondary_startup
642 ENDPROC(secondary_holding_pen)
645 * Secondary entry point that jumps straight into the kernel. Only to
646 * be used where CPUs are brought online dynamically by the kernel.
648 ENTRY(secondary_entry)
649 bl el2_setup // Drop to EL1
650 bl set_cpu_boot_mode_flag
652 ENDPROC(secondary_entry)
656 * Common entry point for secondary CPUs.
658 adrp x25, idmap_pg_dir
659 adrp x26, swapper_pg_dir
660 bl __cpu_setup // initialise processor
662 adr_l x27, __secondary_switch // address to jump to after enabling the MMU
664 ENDPROC(secondary_startup)
666 __secondary_switched:
671 adr_l x0, secondary_data
672 ldr x0, [x0, #CPU_BOOT_STACK] // get secondary_data.stack
674 and x0, x0, #~(THREAD_SIZE - 1)
675 msr sp_el0, x0 // save thread_info
677 b secondary_start_kernel
678 ENDPROC(__secondary_switched)
681 * The booting CPU updates the failed status @__early_cpu_boot_status,
682 * with MMU turned off.
684 * update_early_cpu_boot_status tmp, status
685 * - Corrupts tmp1, tmp2
686 * - Writes 'status' to __early_cpu_boot_status and makes sure
687 * it is committed to memory.
690 .macro update_early_cpu_boot_status status, tmp1, tmp2
692 str_l \tmp2, __early_cpu_boot_status, \tmp1
694 dc ivac, \tmp1 // Invalidate potentially stale cache line
697 .pushsection .data..cacheline_aligned
698 .align L1_CACHE_SHIFT
699 ENTRY(__early_cpu_boot_status)
706 * x0 = SCTLR_EL1 value for turning on the MMU.
707 * x27 = *virtual* address to jump to upon completion
709 * Other registers depend on the function called upon completion.
711 * Checks if the selected granule size is supported by the CPU.
712 * If it isn't, park the CPU
714 .section ".idmap.text", "ax"
716 mrs x22, sctlr_el1 // preserve old SCTLR_EL1 value
717 mrs x1, ID_AA64MMFR0_EL1
718 ubfx x2, x1, #ID_AA64MMFR0_TGRAN_SHIFT, 4
719 cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED
720 b.ne __no_granule_support
721 update_early_cpu_boot_status 0, x1, x2
722 msr ttbr0_el1, x25 // load TTBR0
723 msr ttbr1_el1, x26 // load TTBR1
728 * Invalidate the local I-cache so that any instructions fetched
729 * speculatively from the PoC are discarded, since they may have
730 * been dynamically patched at the PoU.
735 #ifdef CONFIG_RANDOMIZE_BASE
736 mov x19, x0 // preserve new SCTLR_EL1 value
740 * If we return here, we have a KASLR displacement in x23 which we need
741 * to take into account by discarding the current kernel mapping and
742 * creating a new one.
744 msr sctlr_el1, x22 // disable the MMU
746 bl __create_page_tables // recreate kernel mapping
748 msr sctlr_el1, x19 // re-enable the MMU
750 ic iallu // flush instructions fetched
751 dsb nsh // via old mapping
755 ENDPROC(__enable_mmu)
757 __no_granule_support:
758 /* Indicate that this CPU can't boot and is stuck in the kernel */
759 update_early_cpu_boot_status CPU_STUCK_IN_KERNEL, x1, x2
764 ENDPROC(__no_granule_support)
767 #ifdef CONFIG_RELOCATABLE
769 * Iterate over each entry in the relocation table, and apply the
770 * relocations in place.
772 ldr w8, =__dynsym_offset // offset to symbol table
773 ldr w9, =__rela_offset // offset to reloc table
774 ldr w10, =__rela_size // size of reloc table
776 mov_q x11, KIMAGE_VADDR // default virtual offset
777 add x11, x11, x23 // actual virtual offset
778 add x8, x8, x11 // __va(.dynsym)
779 add x9, x9, x11 // __va(.rela)
780 add x10, x9, x10 // __va(.rela) + sizeof(.rela)
784 ldp x11, x12, [x9], #24
786 cmp w12, #R_AARCH64_RELATIVE
788 add x13, x13, x23 // relocate
792 1: cmp w12, #R_AARCH64_ABS64
794 add x12, x12, x12, lsl #1 // symtab offset: 24x top word
795 add x12, x8, x12, lsr #(32 - 3) // ... shifted into bottom word
796 ldrsh w14, [x12, #6] // Elf64_Sym::st_shndx
797 ldr x15, [x12, #8] // Elf64_Sym::st_value
798 cmp w14, #-0xf // SHN_ABS (0xfff1) ?
799 add x14, x15, x23 // relocate
800 csel x15, x14, x15, ne
807 ldr x8, =__primary_switched
809 ENDPROC(__primary_switch)
812 ldr x8, =__secondary_switched
814 ENDPROC(__secondary_switch)