2 * Based on arch/arm/kernel/setup.c
4 * Copyright (C) 1995-2001 Russell King
5 * Copyright (C) 2012 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #include <linux/export.h>
21 #include <linux/kernel.h>
22 #include <linux/stddef.h>
23 #include <linux/ioport.h>
24 #include <linux/delay.h>
25 #include <linux/utsname.h>
26 #include <linux/initrd.h>
27 #include <linux/console.h>
28 #include <linux/cache.h>
29 #include <linux/bootmem.h>
30 #include <linux/seq_file.h>
31 #include <linux/screen_info.h>
32 #include <linux/init.h>
33 #include <linux/kexec.h>
34 #include <linux/crash_dump.h>
35 #include <linux/root_dev.h>
36 #include <linux/clk-provider.h>
37 #include <linux/cpu.h>
38 #include <linux/interrupt.h>
39 #include <linux/smp.h>
41 #include <linux/proc_fs.h>
42 #include <linux/memblock.h>
43 #include <linux/of_fdt.h>
44 #include <linux/of_platform.h>
45 #include <linux/efi.h>
46 #include <linux/personality.h>
48 #include <asm/fixmap.h>
50 #include <asm/cputype.h>
52 #include <asm/cputable.h>
53 #include <asm/cpu_ops.h>
54 #include <asm/sections.h>
55 #include <asm/setup.h>
56 #include <asm/smp_plat.h>
57 #include <asm/cacheflush.h>
58 #include <asm/tlbflush.h>
59 #include <asm/traps.h>
60 #include <asm/memblock.h>
64 unsigned int processor_id;
65 EXPORT_SYMBOL(processor_id);
67 unsigned long elf_hwcap __read_mostly;
68 EXPORT_SYMBOL_GPL(elf_hwcap);
71 #define COMPAT_ELF_HWCAP_DEFAULT \
72 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
73 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
74 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
75 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
76 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
78 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
79 unsigned int compat_elf_hwcap2 __read_mostly;
82 static const char *cpu_name;
83 phys_addr_t __fdt_pointer __initdata;
86 * Standard memory resources
88 static struct resource mem_res[] = {
90 .name = "Kernel code",
93 .flags = IORESOURCE_MEM
96 .name = "Kernel data",
99 .flags = IORESOURCE_MEM
103 #define kernel_code mem_res[0]
104 #define kernel_data mem_res[1]
106 void __init early_print(const char *str, ...)
112 vsnprintf(buf, sizeof(buf), str, ap);
118 void __init smp_setup_processor_id(void)
120 u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
121 cpu_logical_map(0) = mpidr;
124 * clear __my_cpu_offset on boot CPU to avoid hang caused by
125 * using percpu variable early, for example, lockdep will
126 * access percpu variable inside lock_release
128 set_my_cpu_offset(0);
129 pr_info("Booting Linux on physical CPU 0x%lx\n", (unsigned long)mpidr);
132 bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
134 return phys_id == cpu_logical_map(cpu);
137 struct mpidr_hash mpidr_hash;
140 * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
141 * level in order to build a linear index from an
142 * MPIDR value. Resulting algorithm is a collision
143 * free hash carried out through shifting and ORing
145 static void __init smp_build_mpidr_hash(void)
147 u32 i, affinity, fs[4], bits[4], ls;
150 * Pre-scan the list of MPIDRS and filter out bits that do
151 * not contribute to affinity levels, ie they never toggle.
153 for_each_possible_cpu(i)
154 mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
155 pr_debug("mask of set bits %#llx\n", mask);
157 * Find and stash the last and first bit set at all affinity levels to
158 * check how many bits are required to represent them.
160 for (i = 0; i < 4; i++) {
161 affinity = MPIDR_AFFINITY_LEVEL(mask, i);
163 * Find the MSB bit and LSB bits position
164 * to determine how many bits are required
165 * to express the affinity level.
168 fs[i] = affinity ? ffs(affinity) - 1 : 0;
169 bits[i] = ls - fs[i];
172 * An index can be created from the MPIDR_EL1 by isolating the
173 * significant bits at each affinity level and by shifting
174 * them in order to compress the 32 bits values space to a
175 * compressed set of values. This is equivalent to hashing
176 * the MPIDR_EL1 through shifting and ORing. It is a collision free
177 * hash though not minimal since some levels might contain a number
178 * of CPUs that is not an exact power of 2 and their bit
179 * representation might contain holes, eg MPIDR_EL1[7:0] = {0x2, 0x80}.
181 mpidr_hash.shift_aff[0] = MPIDR_LEVEL_SHIFT(0) + fs[0];
182 mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0];
183 mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] -
185 mpidr_hash.shift_aff[3] = MPIDR_LEVEL_SHIFT(3) +
186 fs[3] - (bits[2] + bits[1] + bits[0]);
187 mpidr_hash.mask = mask;
188 mpidr_hash.bits = bits[3] + bits[2] + bits[1] + bits[0];
189 pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] aff3[%u] mask[%#llx] bits[%u]\n",
190 mpidr_hash.shift_aff[0],
191 mpidr_hash.shift_aff[1],
192 mpidr_hash.shift_aff[2],
193 mpidr_hash.shift_aff[3],
197 * 4x is an arbitrary value used to warn on a hash table much bigger
198 * than expected on most systems.
200 if (mpidr_hash_size() > 4 * num_possible_cpus())
201 pr_warn("Large number of MPIDR hash buckets detected\n");
202 __flush_dcache_area(&mpidr_hash, sizeof(struct mpidr_hash));
206 static void __init setup_processor(void)
208 struct cpu_info *cpu_info;
213 cpu_info = lookup_processor_type(read_cpuid_id());
215 printk("CPU configuration botched (ID %08x), unable to continue.\n",
220 cpu_name = cpu_info->cpu_name;
222 printk("CPU: %s [%08x] revision %d\n",
223 cpu_name, read_cpuid_id(), read_cpuid_id() & 15);
225 sprintf(init_utsname()->machine, ELF_PLATFORM);
228 cpuinfo_store_boot_cpu();
231 * Check for sane CTR_EL0.CWG value.
233 cwg = cache_type_cwg();
234 cls = cache_line_size();
236 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
238 if (L1_CACHE_BYTES < cls)
239 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
240 L1_CACHE_BYTES, cls);
243 * ID_AA64ISAR0_EL1 contains 4-bit wide signed feature blocks.
244 * The blocks we test below represent incremental functionality
245 * for non-negative values. Negative values are reserved.
247 features = read_cpuid(ID_AA64ISAR0_EL1);
248 block = (features >> 4) & 0xf;
249 if (!(block & 0x8)) {
253 elf_hwcap |= HWCAP_PMULL;
255 elf_hwcap |= HWCAP_AES;
261 block = (features >> 8) & 0xf;
262 if (block && !(block & 0x8))
263 elf_hwcap |= HWCAP_SHA1;
265 block = (features >> 12) & 0xf;
266 if (block && !(block & 0x8))
267 elf_hwcap |= HWCAP_SHA2;
269 block = (features >> 16) & 0xf;
270 if (block && !(block & 0x8))
271 elf_hwcap |= HWCAP_CRC32;
275 * ID_ISAR5_EL1 carries similar information as above, but pertaining to
276 * the Aarch32 32-bit execution state.
278 features = read_cpuid(ID_ISAR5_EL1);
279 block = (features >> 4) & 0xf;
280 if (!(block & 0x8)) {
284 compat_elf_hwcap2 |= COMPAT_HWCAP2_PMULL;
286 compat_elf_hwcap2 |= COMPAT_HWCAP2_AES;
292 block = (features >> 8) & 0xf;
293 if (block && !(block & 0x8))
294 compat_elf_hwcap2 |= COMPAT_HWCAP2_SHA1;
296 block = (features >> 12) & 0xf;
297 if (block && !(block & 0x8))
298 compat_elf_hwcap2 |= COMPAT_HWCAP2_SHA2;
300 block = (features >> 16) & 0xf;
301 if (block && !(block & 0x8))
302 compat_elf_hwcap2 |= COMPAT_HWCAP2_CRC32;
306 static void __init setup_machine_fdt(phys_addr_t dt_phys)
308 if (!dt_phys || !early_init_dt_scan(phys_to_virt(dt_phys))) {
310 "Error: invalid device tree blob at physical address 0x%p (virtual address 0x%p)\n"
311 "The dtb must be 8-byte aligned and passed in the first 512MB of memory\n"
312 "\nPlease check your bootloader.\n",
313 dt_phys, phys_to_virt(dt_phys));
319 dump_stack_set_arch_desc("%s (DT)", of_flat_dt_get_machine_name());
323 * Limit the memory size that was specified via FDT.
325 static int __init early_mem(char *p)
332 limit = memparse(p, &p) & PAGE_MASK;
333 pr_notice("Memory limited to %lldMB\n", limit >> 20);
335 memblock_enforce_memory_limit(limit);
339 early_param("mem", early_mem);
341 static void __init request_standard_resources(void)
343 struct memblock_region *region;
344 struct resource *res;
346 kernel_code.start = virt_to_phys(_text);
347 kernel_code.end = virt_to_phys(_etext - 1);
348 kernel_data.start = virt_to_phys(_sdata);
349 kernel_data.end = virt_to_phys(_end - 1);
351 for_each_memblock(memory, region) {
352 res = alloc_bootmem_low(sizeof(*res));
353 res->name = "System RAM";
354 res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
355 res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
356 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
358 request_resource(&iomem_resource, res);
360 if (kernel_code.start >= res->start &&
361 kernel_code.end <= res->end)
362 request_resource(res, &kernel_code);
363 if (kernel_data.start >= res->start &&
364 kernel_data.end <= res->end)
365 request_resource(res, &kernel_data);
369 u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID };
371 void __init setup_arch(char **cmdline_p)
375 setup_machine_fdt(__fdt_pointer);
377 init_mm.start_code = (unsigned long) _text;
378 init_mm.end_code = (unsigned long) _etext;
379 init_mm.end_data = (unsigned long) _edata;
380 init_mm.brk = (unsigned long) _end;
382 *cmdline_p = boot_command_line;
384 early_ioremap_init();
389 * Unmask asynchronous aborts after bringing up possible earlycon.
390 * (Report possible System Errors once we can report this occurred)
392 local_async_enable();
395 arm64_memblock_init();
398 request_standard_resources();
402 unflatten_device_tree();
406 cpu_read_bootcpu_ops();
409 smp_build_mpidr_hash();
413 #if defined(CONFIG_VGA_CONSOLE)
414 conswitchp = &vga_con;
415 #elif defined(CONFIG_DUMMY_CONSOLE)
416 conswitchp = &dummy_con;
421 static int __init arm64_device_init(void)
423 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
426 arch_initcall_sync(arm64_device_init);
428 static int __init topology_init(void)
432 for_each_possible_cpu(i) {
433 struct cpu *cpu = &per_cpu(cpu_data.cpu, i);
434 cpu->hotpluggable = 1;
435 register_cpu(cpu, i);
440 subsys_initcall(topology_init);
442 static const char *hwcap_str[] = {
455 static const char *compat_hwcap_str[] = {
480 static const char *compat_hwcap2_str[] = {
488 #endif /* CONFIG_COMPAT */
490 static int c_show(struct seq_file *m, void *v)
494 for_each_online_cpu(i) {
495 struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i);
496 u32 midr = cpuinfo->reg_midr;
499 * glibc reads /proc/cpuinfo to determine the number of
500 * online processors, looking for lines beginning with
501 * "processor". Give glibc what it expects.
504 seq_printf(m, "processor\t: %d\n", i);
508 * Dump out the common processor features in a single line.
509 * Userspace should read the hwcaps with getauxval(AT_HWCAP)
510 * rather than attempting to parse this, but there's a body of
511 * software which does already (at least for 32-bit).
513 seq_puts(m, "Features\t:");
514 if (personality(current->personality) == PER_LINUX32) {
516 for (j = 0; compat_hwcap_str[j]; j++)
517 if (compat_elf_hwcap & (1 << j))
518 seq_printf(m, " %s", compat_hwcap_str[j]);
520 for (j = 0; compat_hwcap2_str[j]; j++)
521 if (compat_elf_hwcap2 & (1 << j))
522 seq_printf(m, " %s", compat_hwcap2_str[j]);
523 #endif /* CONFIG_COMPAT */
525 for (j = 0; hwcap_str[j]; j++)
526 if (elf_hwcap & (1 << j))
527 seq_printf(m, " %s", hwcap_str[j]);
531 seq_printf(m, "CPU implementer\t: 0x%02x\n",
532 MIDR_IMPLEMENTOR(midr));
533 seq_printf(m, "CPU architecture: 8\n");
534 seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr));
535 seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr));
536 seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr));
542 static void *c_start(struct seq_file *m, loff_t *pos)
544 return *pos < 1 ? (void *)1 : NULL;
547 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
553 static void c_stop(struct seq_file *m, void *v)
557 const struct seq_operations cpuinfo_op = {