2 * Blackfin cache control code (simpler control-style functions)
4 * Copyright 2004-2009 Analog Devices Inc.
6 * Enter bugs at http://blackfin.uclinux.org/
8 * Licensed under the GPL-2 or later.
11 #include <linux/init.h>
12 #include <asm/blackfin.h>
13 #include <asm/cplbinit.h>
15 /* Invalidate the Entire Data cache by
16 * clearing DMC[1:0] bits
18 void blackfin_invalidate_entire_dcache(void)
20 u32 dmem = bfin_read_DMEM_CONTROL();
21 bfin_write_DMEM_CONTROL(dmem & ~0xc);
23 bfin_write_DMEM_CONTROL(dmem);
27 /* Invalidate the Entire Instruction cache by
30 void blackfin_invalidate_entire_icache(void)
32 u32 imem = bfin_read_IMEM_CONTROL();
33 bfin_write_IMEM_CONTROL(imem & ~0x4);
35 bfin_write_IMEM_CONTROL(imem);
39 #if defined(CONFIG_BFIN_ICACHE) || defined(CONFIG_BFIN_DCACHE)
42 bfin_cache_init(struct cplb_entry *cplb_tbl, unsigned long cplb_addr,
43 unsigned long cplb_data, unsigned long mem_control,
44 unsigned long mem_mask)
48 for (i = 0; i < MAX_CPLBS; i++) {
49 bfin_write32(cplb_addr + i * 4, cplb_tbl[i].addr);
50 bfin_write32(cplb_data + i * 4, cplb_tbl[i].data);
53 _enable_cplb(mem_control, mem_mask);
56 #ifdef CONFIG_BFIN_ICACHE
57 void __cpuinit bfin_icache_init(struct cplb_entry *icplb_tbl)
59 bfin_cache_init(icplb_tbl, ICPLB_ADDR0, ICPLB_DATA0, IMEM_CONTROL,
64 #ifdef CONFIG_BFIN_DCACHE
65 void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl)
69 * 05000287 - We implement workaround #2 - Change the DMEM_CONTROL
70 * register, so that the port preferences for DAG0 and DAG1 are set
73 bfin_cache_init(dcplb_tbl, DCPLB_ADDR0, DCPLB_DATA0, DMEM_CONTROL,
74 (DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0)));