2 * linux/arch/m32r/platforms/opsput/setup.c
4 * Setup routines for Renesas OPSPUT Board
6 * Copyright (c) 2002-2005
7 * Hiroyuki Kondo, Hirokazu Takata,
8 * Hitoshi Yamamoto, Takeo Takahashi, Mamoru Sakugawa
10 * This file is subject to the terms and conditions of the GNU General
11 * Public License. See the file "COPYING" in the main directory of this
12 * archive for more details.
15 #include <linux/irq.h>
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/platform_device.h>
20 #include <asm/system.h>
25 * OPSP Interrupt Control Unit (Level 1)
27 #define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
29 icu_data_t icu_data[OPSPUT_NUM_CPU_IRQ];
31 static void disable_opsput_irq(unsigned int irq)
33 unsigned long port, data;
36 data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
40 static void enable_opsput_irq(unsigned int irq)
42 unsigned long port, data;
45 data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
49 static void mask_opsput(struct irq_data *data)
51 disable_opsput_irq(data->irq);
54 static void unmask_opsput(struct irq_data *data)
56 enable_opsput_irq(data->irq);
59 static void shutdown_opsput(struct irq_data *data)
63 port = irq2port(data->irq);
64 outl(M32R_ICUCR_ILEVEL7, port);
67 static struct irq_chip opsput_irq_type =
70 .irq_shutdown = shutdown_opsput,
71 .irq_mask = mask_opsput,
72 .irq_unmask = unmask_opsput,
76 * Interrupt Control Unit of PLD on OPSPUT (Level 2)
78 #define irq2pldirq(x) ((x) - OPSPUT_PLD_IRQ_BASE)
79 #define pldirq2port(x) (unsigned long)((int)PLD_ICUCR1 + \
80 (((x) - 1) * sizeof(unsigned short)))
83 unsigned short icucr; /* ICU Control Register */
86 static pld_icu_data_t pld_icu_data[OPSPUT_NUM_PLD_IRQ];
88 static void disable_opsput_pld_irq(unsigned int irq)
90 unsigned long port, data;
93 pldirq = irq2pldirq(irq);
94 port = pldirq2port(pldirq);
95 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
99 static void enable_opsput_pld_irq(unsigned int irq)
101 unsigned long port, data;
104 pldirq = irq2pldirq(irq);
105 port = pldirq2port(pldirq);
106 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
110 static void mask_opsput_pld(struct irq_data *data)
112 disable_opsput_pld_irq(data->irq);
115 static void unmask_opsput_pld(struct irq_data *data)
117 enable_opsput_pld_irq(data->irq);
118 enable_opsput_irq(M32R_IRQ_INT1);
121 static void shutdown_opsput_pld(struct irq_data *data)
126 pldirq = irq2pldirq(data->irq);
127 port = pldirq2port(pldirq);
128 outw(PLD_ICUCR_ILEVEL7, port);
131 static struct irq_chip opsput_pld_irq_type =
133 .name = "OPSPUT-PLD-IRQ",
134 .irq_shutdown = shutdown_opsput_pld,
135 .irq_mask = mask_opsput_pld,
136 .irq_unmask = unmask_opsput_pld,
140 * Interrupt Control Unit of PLD on OPSPUT-LAN (Level 2)
142 #define irq2lanpldirq(x) ((x) - OPSPUT_LAN_PLD_IRQ_BASE)
143 #define lanpldirq2port(x) (unsigned long)((int)OPSPUT_LAN_ICUCR1 + \
144 (((x) - 1) * sizeof(unsigned short)))
146 static pld_icu_data_t lanpld_icu_data[OPSPUT_NUM_LAN_PLD_IRQ];
148 static void disable_opsput_lanpld_irq(unsigned int irq)
150 unsigned long port, data;
153 pldirq = irq2lanpldirq(irq);
154 port = lanpldirq2port(pldirq);
155 data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
159 static void enable_opsput_lanpld_irq(unsigned int irq)
161 unsigned long port, data;
164 pldirq = irq2lanpldirq(irq);
165 port = lanpldirq2port(pldirq);
166 data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
170 static void mask_and_ack_opsput_lanpld(unsigned int irq)
172 disable_opsput_lanpld_irq(irq);
175 static void end_opsput_lanpld_irq(unsigned int irq)
177 enable_opsput_lanpld_irq(irq);
178 enable_opsput_irq(M32R_IRQ_INT0);
181 static unsigned int startup_opsput_lanpld_irq(unsigned int irq)
183 enable_opsput_lanpld_irq(irq);
187 static void shutdown_opsput_lanpld_irq(unsigned int irq)
192 pldirq = irq2lanpldirq(irq);
193 port = lanpldirq2port(pldirq);
194 outw(PLD_ICUCR_ILEVEL7, port);
197 static struct irq_chip opsput_lanpld_irq_type =
199 .name = "OPSPUT-PLD-LAN-IRQ",
200 .startup = startup_opsput_lanpld_irq,
201 .shutdown = shutdown_opsput_lanpld_irq,
202 .enable = enable_opsput_lanpld_irq,
203 .disable = disable_opsput_lanpld_irq,
204 .ack = mask_and_ack_opsput_lanpld,
205 .end = end_opsput_lanpld_irq
209 * Interrupt Control Unit of PLD on OPSPUT-LCD (Level 2)
211 #define irq2lcdpldirq(x) ((x) - OPSPUT_LCD_PLD_IRQ_BASE)
212 #define lcdpldirq2port(x) (unsigned long)((int)OPSPUT_LCD_ICUCR1 + \
213 (((x) - 1) * sizeof(unsigned short)))
215 static pld_icu_data_t lcdpld_icu_data[OPSPUT_NUM_LCD_PLD_IRQ];
217 static void disable_opsput_lcdpld_irq(unsigned int irq)
219 unsigned long port, data;
222 pldirq = irq2lcdpldirq(irq);
223 port = lcdpldirq2port(pldirq);
224 data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
228 static void enable_opsput_lcdpld_irq(unsigned int irq)
230 unsigned long port, data;
233 pldirq = irq2lcdpldirq(irq);
234 port = lcdpldirq2port(pldirq);
235 data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
239 static void mask_and_ack_opsput_lcdpld(unsigned int irq)
241 disable_opsput_lcdpld_irq(irq);
244 static void end_opsput_lcdpld_irq(unsigned int irq)
246 enable_opsput_lcdpld_irq(irq);
247 enable_opsput_irq(M32R_IRQ_INT2);
250 static unsigned int startup_opsput_lcdpld_irq(unsigned int irq)
252 enable_opsput_lcdpld_irq(irq);
256 static void shutdown_opsput_lcdpld_irq(unsigned int irq)
261 pldirq = irq2lcdpldirq(irq);
262 port = lcdpldirq2port(pldirq);
263 outw(PLD_ICUCR_ILEVEL7, port);
266 static struct irq_chip opsput_lcdpld_irq_type =
268 "OPSPUT-PLD-LCD-IRQ",
269 startup_opsput_lcdpld_irq,
270 shutdown_opsput_lcdpld_irq,
271 enable_opsput_lcdpld_irq,
272 disable_opsput_lcdpld_irq,
273 mask_and_ack_opsput_lcdpld,
274 end_opsput_lcdpld_irq
277 void __init init_IRQ(void)
279 #if defined(CONFIG_SMC91X)
280 /* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/
281 set_irq_chip(OPSPUT_LAN_IRQ_LAN, &opsput_lanpld_irq_type);
282 lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */
283 disable_opsput_lanpld_irq(OPSPUT_LAN_IRQ_LAN);
284 #endif /* CONFIG_SMC91X */
286 /* MFT2 : system timer */
287 set_irq_chip_and_handler(M32R_IRQ_MFT2, &opsput_irq_type,
289 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
290 disable_opsput_irq(M32R_IRQ_MFT2);
293 set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &opsput_irq_type,
295 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
296 disable_opsput_irq(M32R_IRQ_SIO0_R);
299 set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &opsput_irq_type,
301 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
302 disable_opsput_irq(M32R_IRQ_SIO0_S);
305 set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &opsput_irq_type,
307 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
308 disable_opsput_irq(M32R_IRQ_SIO1_R);
311 set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &opsput_irq_type,
313 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
314 disable_opsput_irq(M32R_IRQ_SIO1_S);
317 set_irq_chip_and_handler(M32R_IRQ_DMA1, &opsput_irq_type,
319 icu_data[M32R_IRQ_DMA1].icucr = 0;
320 disable_opsput_irq(M32R_IRQ_DMA1);
322 #ifdef CONFIG_SERIAL_M32R_PLDSIO
323 /* INT#1: SIO0 Receive on PLD */
324 set_irq_chip_and_handler(PLD_IRQ_SIO0_RCV, &opsput_pld_irq_type,
326 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
327 disable_opsput_pld_irq(PLD_IRQ_SIO0_RCV);
329 /* INT#1: SIO0 Send on PLD */
330 set_irq_chip_and_handler(PLD_IRQ_SIO0_SND, &opsput_pld_irq_type,
332 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
333 disable_opsput_pld_irq(PLD_IRQ_SIO0_SND);
334 #endif /* CONFIG_SERIAL_M32R_PLDSIO */
336 /* INT#1: CFC IREQ on PLD */
337 set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &opsput_pld_irq_type,
339 pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */
340 disable_opsput_pld_irq(PLD_IRQ_CFIREQ);
342 /* INT#1: CFC Insert on PLD */
343 set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &opsput_pld_irq_type,
345 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
346 disable_opsput_pld_irq(PLD_IRQ_CFC_INSERT);
348 /* INT#1: CFC Eject on PLD */
349 set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &opsput_pld_irq_type,
351 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
352 disable_opsput_pld_irq(PLD_IRQ_CFC_EJECT);
355 * INT0# is used for LAN, DIO
358 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
359 enable_opsput_irq(M32R_IRQ_INT0);
362 * INT1# is used for UART, MMC, CF Controller in FPGA.
365 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
366 enable_opsput_irq(M32R_IRQ_INT1);
368 #if defined(CONFIG_USB)
369 outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */
371 set_irq_chip(OPSPUT_LCD_IRQ_USB_INT1, &opsput_lcdpld_irq_type);
372 lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */
373 disable_opsput_lcdpld_irq(OPSPUT_LCD_IRQ_USB_INT1);
376 * INT2# is used for BAT, USB, AUDIO
379 icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
380 enable_opsput_irq(M32R_IRQ_INT2);
382 #if defined(CONFIG_VIDEO_M32R_AR)
384 * INT3# is used for AR
386 set_irq_chip_and_handler(M32R_IRQ_INT3, &opsput_irq_type,
388 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
389 disable_opsput_irq(M32R_IRQ_INT3);
390 #endif /* CONFIG_VIDEO_M32R_AR */
393 #if defined(CONFIG_SMC91X)
395 #define LAN_IOSTART 0x300
396 #define LAN_IOEND 0x320
397 static struct resource smc91x_resources[] = {
399 .start = (LAN_IOSTART),
401 .flags = IORESOURCE_MEM,
404 .start = OPSPUT_LAN_IRQ_LAN,
405 .end = OPSPUT_LAN_IRQ_LAN,
406 .flags = IORESOURCE_IRQ,
410 static struct platform_device smc91x_device = {
413 .num_resources = ARRAY_SIZE(smc91x_resources),
414 .resource = smc91x_resources,
418 #if defined(CONFIG_FB_S1D13XXX)
420 #include <video/s1d13xxxfb.h>
421 #include <asm/s1d13806.h>
423 static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
424 .initregs = s1d13xxxfb_initregs,
425 .initregssize = ARRAY_SIZE(s1d13xxxfb_initregs),
426 .platform_init_video = NULL,
428 .platform_suspend_video = NULL,
429 .platform_resume_video = NULL,
433 static struct resource s1d13xxxfb_resources[] = {
435 .start = 0x10600000UL,
437 .flags = IORESOURCE_MEM,
440 .start = 0x10400000UL,
442 .flags = IORESOURCE_MEM,
446 static struct platform_device s1d13xxxfb_device = {
447 .name = S1D_DEVICENAME,
450 .platform_data = &s1d13xxxfb_data,
452 .num_resources = ARRAY_SIZE(s1d13xxxfb_resources),
453 .resource = s1d13xxxfb_resources,
457 static int __init platform_init(void)
459 #if defined(CONFIG_SMC91X)
460 platform_device_register(&smc91x_device);
462 #if defined(CONFIG_FB_S1D13XXX)
463 platform_device_register(&s1d13xxxfb_device);
467 arch_initcall(platform_init);