arch/m68k/include/asm/atomic.h

   1 #ifndef __ARCH_M68K_ATOMIC__
   2 #define __ARCH_M68K_ATOMIC__
   3
   4 #include <linux/types.h>
   5 #include <linux/irqflags.h>
   6 #include <asm/cmpxchg.h>
   7 #include <asm/barrier.h>
   8
   9 /*
  10  * Atomic operations that C can't guarantee us.  Useful for
  11  * resource counting etc..
  12  */
  13
  14 /*
  15  * We do not have SMP m68k systems, so we don't have to deal with that.
  16  */
  17
  18 #define ATOMIC_INIT(i)  { (i) }
  19
  20 #define atomic_read(v)          READ_ONCE((v)->counter)
  21 #define atomic_set(v, i)        WRITE_ONCE(((v)->counter), (i))
  22
  23 /*
  24  * The ColdFire parts cannot do some immediate to memory operations,
  25  * so for them we do not specify the "i" asm constraint.
  26  */
  27 #ifdef CONFIG_COLDFIRE
  28 #define ASM_DI  "d"
  29 #else
  30 #define ASM_DI  "di"
  31 #endif
  32
  33 #define ATOMIC_OP(op, c_op, asm_op)                                     \
  34 static inline void atomic_##op(int i, atomic_t *v)                      \
  35 {                                                                       \
  36         __asm__ __volatile__(#asm_op "l %1,%0" : "+m" (*v) : ASM_DI (i));\
  37 }                                                                       \
  38
  39 #ifdef CONFIG_RMW_INSNS
  40
  41 /*
  42  * Am I reading these CAS loops right in that %2 is the old value and the first
  43  * iteration uses an uninitialized value?
  44  *
  45  * Would it not make sense to add: tmp = atomic_read(v); to avoid this?
  46  */
  47
  48 #define ATOMIC_OP_RETURN(op, c_op, asm_op)                              \
  49 static inline int atomic_##op##_return(int i, atomic_t *v)              \
  50 {                                                                       \
  51         int t, tmp;                                                     \
  52                                                                         \
  53         __asm__ __volatile__(                                           \
  54                         "1:     movel %2,%1\n"                          \
  55                         "       " #asm_op "l %3,%1\n"                   \
  56                         "       casl %2,%1,%0\n"                        \
  57                         "       jne 1b"                                 \
  58                         : "+m" (*v), "=&d" (t), "=&d" (tmp)             \
  59                         : "g" (i), "2" (atomic_read(v)));               \
  60         return t;                                                       \
  61 }
  62
  63 #define ATOMIC_FETCH_OP(op, c_op, asm_op)                               \
  64 static inline int atomic_fetch_##op(int i, atomic_t *v)                 \
  65 {                                                                       \
  66         int t, tmp;                                                     \
  67                                                                         \
  68         __asm__ __volatile__(                                           \
  69                         "1:     movel %2,%1\n"                          \
  70                         "       " #asm_op "l %3,%1\n"                   \
  71                         "       casl %2,%1,%0\n"                        \
  72                         "       jne 1b"                                 \
  73                         : "+m" (*v), "=&d" (t), "=&d" (tmp)             \
  74                         : "g" (i), "2" (atomic_read(v)));               \
  75         return tmp;                                                     \
  76 }
  77
  78 #else
  79
  80 #define ATOMIC_OP_RETURN(op, c_op, asm_op)                              \
  81 static inline int atomic_##op##_return(int i, atomic_t * v)             \
  82 {                                                                       \
  83         unsigned long flags;                                            \
  84         int t;                                                          \
  85                                                                         \
  86         local_irq_save(flags);                                          \
  87         t = (v->counter c_op i);                                        \
  88         local_irq_restore(flags);                                       \
  89                                                                         \
  90         return t;                                                       \
  91 }
  92
  93 #define ATOMIC_FETCH_OP(op, c_op, asm_op)                               \
  94 static inline int atomic_fetch_##op(int i, atomic_t * v)                \
  95 {                                                                       \
  96         unsigned long flags;                                            \
  97         int t;                                                          \
  98                                                                         \
  99         local_irq_save(flags);                                          \
 100         t = v->counter;                                                 \
 101         v->counter c_op i;                                              \
 102         local_irq_restore(flags);                                       \
 103                                                                         \
 104         return t;                                                       \
 105 }
 106
 107 #endif /* CONFIG_RMW_INSNS */
 108
 109 #define ATOMIC_OPS(op, c_op, asm_op)                                    \
 110         ATOMIC_OP(op, c_op, asm_op)                                     \
 111         ATOMIC_OP_RETURN(op, c_op, asm_op)                              \
 112         ATOMIC_FETCH_OP(op, c_op, asm_op)
 113
 114 ATOMIC_OPS(add, +=, add)
 115 ATOMIC_OPS(sub, -=, sub)
 116
 117 #undef ATOMIC_OPS
 118 #define ATOMIC_OPS(op, c_op, asm_op)                                    \
 119         ATOMIC_OP(op, c_op, asm_op)                                     \
 120         ATOMIC_FETCH_OP(op, c_op, asm_op)
 121
 122 ATOMIC_OPS(and, &=, and)
 123 ATOMIC_OPS(or, |=, or)
 124 ATOMIC_OPS(xor, ^=, eor)
 125
 126 #undef ATOMIC_OPS
 127 #undef ATOMIC_FETCH_OP
 128 #undef ATOMIC_OP_RETURN
 129 #undef ATOMIC_OP
 130
 131 static inline void atomic_inc(atomic_t *v)
 132 {
 133         __asm__ __volatile__("addql #1,%0" : "+m" (*v));
 134 }
 135
 136 static inline void atomic_dec(atomic_t *v)
 137 {
 138         __asm__ __volatile__("subql #1,%0" : "+m" (*v));
 139 }
 140
 141 static inline int atomic_dec_and_test(atomic_t *v)
 142 {
 143         char c;
 144         __asm__ __volatile__("subql #1,%1; seq %0" : "=d" (c), "+m" (*v));
 145         return c != 0;
 146 }
 147
 148 static inline int atomic_dec_and_test_lt(atomic_t *v)
 149 {
 150         char c;
 151         __asm__ __volatile__(
 152                 "subql #1,%1; slt %0"
 153                 : "=d" (c), "=m" (*v)
 154                 : "m" (*v));
 155         return c != 0;
 156 }
 157
 158 static inline int atomic_inc_and_test(atomic_t *v)
 159 {
 160         char c;
 161         __asm__ __volatile__("addql #1,%1; seq %0" : "=d" (c), "+m" (*v));
 162         return c != 0;
 163 }
 164
 165 #ifdef CONFIG_RMW_INSNS
 166
 167 #define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
 168 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
 169
 170 #else /* !CONFIG_RMW_INSNS */
 171
 172 static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
 173 {
 174         unsigned long flags;
 175         int prev;
 176
 177         local_irq_save(flags);
 178         prev = atomic_read(v);
 179         if (prev == old)
 180                 atomic_set(v, new);
 181         local_irq_restore(flags);
 182         return prev;
 183 }
 184
 185 static inline int atomic_xchg(atomic_t *v, int new)
 186 {
 187         unsigned long flags;
 188         int prev;
 189
 190         local_irq_save(flags);
 191         prev = atomic_read(v);
 192         atomic_set(v, new);
 193         local_irq_restore(flags);
 194         return prev;
 195 }
 196
 197 #endif /* !CONFIG_RMW_INSNS */
 198
 199 #define atomic_dec_return(v)    atomic_sub_return(1, (v))
 200 #define atomic_inc_return(v)    atomic_add_return(1, (v))
 201
 202 static inline int atomic_sub_and_test(int i, atomic_t *v)
 203 {
 204         char c;
 205         __asm__ __volatile__("subl %2,%1; seq %0"
 206                              : "=d" (c), "+m" (*v)
 207                              : ASM_DI (i));
 208         return c != 0;
 209 }
 210
 211 static inline int atomic_add_negative(int i, atomic_t *v)
 212 {
 213         char c;
 214         __asm__ __volatile__("addl %2,%1; smi %0"
 215                              : "=d" (c), "+m" (*v)
 216                              : ASM_DI (i));
 217         return c != 0;
 218 }
 219
 220 static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u)
 221 {
 222         int c, old;
 223         c = atomic_read(v);
 224         for (;;) {
 225                 if (unlikely(c == (u)))
 226                         break;
 227                 old = atomic_cmpxchg((v), c, c + (a));
 228                 if (likely(old == c))
 229                         break;
 230                 c = old;
 231         }
 232         return c;
 233 }
 234
 235 #endif /* __ARCH_M68K_ATOMIC __ */