2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/bootmem.h>
25 #include <linux/list.h>
26 #include <linux/syscalls.h>
27 #include <linux/irq.h>
28 #include <linux/vmalloc.h>
29 #include <linux/slab.h>
31 #include <linux/of_address.h>
32 #include <linux/of_irq.h>
33 #include <linux/of_pci.h>
34 #include <linux/export.h>
36 #include <asm/processor.h>
38 #include <asm/pci-bridge.h>
39 #include <asm/byteorder.h>
41 static DEFINE_SPINLOCK(hose_spinlock);
44 /* XXX kill that some day ... */
45 static int global_phb_number; /* Global phb counter */
47 /* ISA Memory physical address */
48 resource_size_t isa_mem_base;
50 static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
52 unsigned long isa_io_base;
53 unsigned long pci_dram_offset;
54 static int pci_bus_count;
57 void set_pci_dma_ops(struct dma_map_ops *dma_ops)
59 pci_dma_ops = dma_ops;
62 struct dma_map_ops *get_pci_dma_ops(void)
66 EXPORT_SYMBOL(get_pci_dma_ops);
68 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
70 struct pci_controller *phb;
72 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
75 spin_lock(&hose_spinlock);
76 phb->global_number = global_phb_number++;
77 list_add_tail(&phb->list_node, &hose_list);
78 spin_unlock(&hose_spinlock);
80 phb->is_dynamic = mem_init_done;
84 void pcibios_free_controller(struct pci_controller *phb)
86 spin_lock(&hose_spinlock);
87 list_del(&phb->list_node);
88 spin_unlock(&hose_spinlock);
94 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
96 return resource_size(&hose->io_resource);
99 int pcibios_vaddr_is_ioport(void __iomem *address)
102 struct pci_controller *hose;
103 resource_size_t size;
105 spin_lock(&hose_spinlock);
106 list_for_each_entry(hose, &hose_list, list_node) {
107 size = pcibios_io_size(hose);
108 if (address >= hose->io_base_virt &&
109 address < (hose->io_base_virt + size)) {
114 spin_unlock(&hose_spinlock);
118 unsigned long pci_address_to_pio(phys_addr_t address)
120 struct pci_controller *hose;
121 resource_size_t size;
122 unsigned long ret = ~0;
124 spin_lock(&hose_spinlock);
125 list_for_each_entry(hose, &hose_list, list_node) {
126 size = pcibios_io_size(hose);
127 if (address >= hose->io_base_phys &&
128 address < (hose->io_base_phys + size)) {
130 (unsigned long)hose->io_base_virt - _IO_BASE;
131 ret = base + (address - hose->io_base_phys);
135 spin_unlock(&hose_spinlock);
139 EXPORT_SYMBOL_GPL(pci_address_to_pio);
142 * Return the domain number for this bus.
144 int pci_domain_nr(struct pci_bus *bus)
146 struct pci_controller *hose = pci_bus_to_host(bus);
148 return hose->global_number;
150 EXPORT_SYMBOL(pci_domain_nr);
152 /* This routine is meant to be used early during boot, when the
153 * PCI bus numbers have not yet been assigned, and you need to
154 * issue PCI config cycles to an OF device.
155 * It could also be used to "fix" RTAS config cycles if you want
156 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
159 struct pci_controller *pci_find_hose_for_OF_device(struct device_node *node)
162 struct pci_controller *hose, *tmp;
163 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
164 if (hose->dn == node)
171 static ssize_t pci_show_devspec(struct device *dev,
172 struct device_attribute *attr, char *buf)
174 struct pci_dev *pdev;
175 struct device_node *np;
177 pdev = to_pci_dev(dev);
178 np = pci_device_to_OF_node(pdev);
179 if (np == NULL || np->full_name == NULL)
181 return sprintf(buf, "%s", np->full_name);
183 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
185 /* Add sysfs properties */
186 int pcibios_add_platform_entries(struct pci_dev *pdev)
188 return device_create_file(&pdev->dev, &dev_attr_devspec);
191 void pcibios_set_master(struct pci_dev *dev)
193 /* No special bus mastering setup handling */
197 * Platform support for /proc/bus/pci/X/Y mmap()s,
198 * modelled on the sparc64 implementation by Dave Miller.
203 * Adjust vm_pgoff of VMA such that it is the physical page offset
204 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
206 * Basically, the user finds the base address for his device which he wishes
207 * to mmap. They read the 32-bit value from the config space base register,
208 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
209 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
211 * Returns negative error code on failure, zero on success.
213 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
214 resource_size_t *offset,
215 enum pci_mmap_state mmap_state)
217 struct pci_controller *hose = pci_bus_to_host(dev->bus);
218 unsigned long io_offset = 0;
222 return NULL; /* should never happen */
224 /* If memory, add on the PCI bridge address offset */
225 if (mmap_state == pci_mmap_mem) {
226 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
227 *offset += hose->pci_mem_offset;
229 res_bit = IORESOURCE_MEM;
231 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
232 *offset += io_offset;
233 res_bit = IORESOURCE_IO;
237 * Check that the offset requested corresponds to one of the
238 * resources of the device.
240 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
241 struct resource *rp = &dev->resource[i];
242 int flags = rp->flags;
244 /* treat ROM as memory (should be already) */
245 if (i == PCI_ROM_RESOURCE)
246 flags |= IORESOURCE_MEM;
248 /* Active and same type? */
249 if ((flags & res_bit) == 0)
252 /* In the range of this resource? */
253 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
256 /* found it! construct the final physical address */
257 if (mmap_state == pci_mmap_io)
258 *offset += hose->io_base_phys - io_offset;
266 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
269 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
271 enum pci_mmap_state mmap_state,
274 pgprot_t prot = protection;
276 /* Write combine is always 0 on non-memory space mappings. On
277 * memory space, if the user didn't pass 1, we check for a
278 * "prefetchable" resource. This is a bit hackish, but we use
279 * this to workaround the inability of /sysfs to provide a write
282 if (mmap_state != pci_mmap_mem)
284 else if (write_combine == 0) {
285 if (rp->flags & IORESOURCE_PREFETCH)
289 return pgprot_noncached(prot);
293 * This one is used by /dev/mem and fbdev who have no clue about the
294 * PCI device, it tries to find the PCI device first and calls the
297 pgprot_t pci_phys_mem_access_prot(struct file *file,
302 struct pci_dev *pdev = NULL;
303 struct resource *found = NULL;
304 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
307 if (page_is_ram(pfn))
310 prot = pgprot_noncached(prot);
311 for_each_pci_dev(pdev) {
312 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
313 struct resource *rp = &pdev->resource[i];
314 int flags = rp->flags;
316 /* Active and same type? */
317 if ((flags & IORESOURCE_MEM) == 0)
319 /* In the range of this resource? */
320 if (offset < (rp->start & PAGE_MASK) ||
330 if (found->flags & IORESOURCE_PREFETCH)
331 prot = pgprot_noncached_wc(prot);
335 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
336 (unsigned long long)offset, pgprot_val(prot));
342 * Perform the actual remap of the pages for a PCI device mapping, as
343 * appropriate for this architecture. The region in the process to map
344 * is described by vm_start and vm_end members of VMA, the base physical
345 * address is found in vm_pgoff.
346 * The pci device structure is provided so that architectures may make mapping
347 * decisions on a per-device or per-bus basis.
349 * Returns a negative error code on failure, zero on success.
351 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
352 enum pci_mmap_state mmap_state, int write_combine)
354 resource_size_t offset =
355 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
359 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
363 vma->vm_pgoff = offset >> PAGE_SHIFT;
364 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
366 mmap_state, write_combine);
368 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
369 vma->vm_end - vma->vm_start, vma->vm_page_prot);
374 /* This provides legacy IO read access on a bus */
375 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
377 unsigned long offset;
378 struct pci_controller *hose = pci_bus_to_host(bus);
379 struct resource *rp = &hose->io_resource;
382 /* Check if port can be supported by that bus. We only check
383 * the ranges of the PHB though, not the bus itself as the rules
384 * for forwarding legacy cycles down bridges are not our problem
385 * here. So if the host bridge supports it, we do it.
387 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
390 if (!(rp->flags & IORESOURCE_IO))
392 if (offset < rp->start || (offset + size) > rp->end)
394 addr = hose->io_base_virt + port;
398 *((u8 *)val) = in_8(addr);
403 *((u16 *)val) = in_le16(addr);
408 *((u32 *)val) = in_le32(addr);
414 /* This provides legacy IO write access on a bus */
415 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
417 unsigned long offset;
418 struct pci_controller *hose = pci_bus_to_host(bus);
419 struct resource *rp = &hose->io_resource;
422 /* Check if port can be supported by that bus. We only check
423 * the ranges of the PHB though, not the bus itself as the rules
424 * for forwarding legacy cycles down bridges are not our problem
425 * here. So if the host bridge supports it, we do it.
427 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
430 if (!(rp->flags & IORESOURCE_IO))
432 if (offset < rp->start || (offset + size) > rp->end)
434 addr = hose->io_base_virt + port;
436 /* WARNING: The generic code is idiotic. It gets passed a pointer
437 * to what can be a 1, 2 or 4 byte quantity and always reads that
438 * as a u32, which means that we have to correct the location of
439 * the data read within those 32 bits for size 1 and 2
443 out_8(addr, val >> 24);
448 out_le16(addr, val >> 16);
459 /* This provides legacy IO or memory mmap access on a bus */
460 int pci_mmap_legacy_page_range(struct pci_bus *bus,
461 struct vm_area_struct *vma,
462 enum pci_mmap_state mmap_state)
464 struct pci_controller *hose = pci_bus_to_host(bus);
465 resource_size_t offset =
466 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
467 resource_size_t size = vma->vm_end - vma->vm_start;
470 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
471 pci_domain_nr(bus), bus->number,
472 mmap_state == pci_mmap_mem ? "MEM" : "IO",
473 (unsigned long long)offset,
474 (unsigned long long)(offset + size - 1));
476 if (mmap_state == pci_mmap_mem) {
479 * Because X is lame and can fail starting if it gets an error
480 * trying to mmap legacy_mem (instead of just moving on without
481 * legacy memory access) we fake it here by giving it anonymous
482 * memory, effectively behaving just like /dev/zero
484 if ((offset + size) > hose->isa_mem_size) {
486 pr_debug("Process %s (pid:%d) mapped non-existing PCI",
487 current->comm, current->pid);
488 pr_debug("legacy memory for 0%04x:%02x\n",
489 pci_domain_nr(bus), bus->number);
491 if (vma->vm_flags & VM_SHARED)
492 return shmem_zero_setup(vma);
495 offset += hose->isa_mem_phys;
497 unsigned long io_offset = (unsigned long)hose->io_base_virt -
499 unsigned long roffset = offset + io_offset;
500 rp = &hose->io_resource;
501 if (!(rp->flags & IORESOURCE_IO))
503 if (roffset < rp->start || (roffset + size) > rp->end)
505 offset += hose->io_base_phys;
507 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
509 vma->vm_pgoff = offset >> PAGE_SHIFT;
510 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
511 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
512 vma->vm_end - vma->vm_start,
516 void pci_resource_to_user(const struct pci_dev *dev, int bar,
517 const struct resource *rsrc,
518 resource_size_t *start, resource_size_t *end)
520 struct pci_controller *hose = pci_bus_to_host(dev->bus);
521 resource_size_t offset = 0;
526 if (rsrc->flags & IORESOURCE_IO)
527 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
529 /* We pass a fully fixed up address to userland for MMIO instead of
530 * a BAR value because X is lame and expects to be able to use that
531 * to pass to /dev/mem !
533 * That means that we'll have potentially 64 bits values where some
534 * userland apps only expect 32 (like X itself since it thinks only
535 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
538 * Hopefully, the sysfs insterface is immune to that gunk. Once X
539 * has been fixed (and the fix spread enough), we can re-enable the
540 * 2 lines below and pass down a BAR value to userland. In that case
541 * we'll also have to re-enable the matching code in
542 * __pci_mmap_make_offset().
547 else if (rsrc->flags & IORESOURCE_MEM)
548 offset = hose->pci_mem_offset;
551 *start = rsrc->start - offset;
552 *end = rsrc->end - offset;
556 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
557 * @hose: newly allocated pci_controller to be setup
558 * @dev: device node of the host bridge
559 * @primary: set if primary bus (32 bits only, soon to be deprecated)
561 * This function will parse the "ranges" property of a PCI host bridge device
562 * node and setup the resource mapping of a pci controller based on its
565 * Life would be boring if it wasn't for a few issues that we have to deal
568 * - We can only cope with one IO space range and up to 3 Memory space
569 * ranges. However, some machines (thanks Apple !) tend to split their
570 * space into lots of small contiguous ranges. So we have to coalesce.
572 * - We can only cope with all memory ranges having the same offset
573 * between CPU addresses and PCI addresses. Unfortunately, some bridges
574 * are setup for a large 1:1 mapping along with a small "window" which
575 * maps PCI address 0 to some arbitrary high address of the CPU space in
576 * order to give access to the ISA memory hole.
577 * The way out of here that I've chosen for now is to always set the
578 * offset based on the first resource found, then override it if we
579 * have a different offset and the previous was set by an ISA hole.
581 * - Some busses have IO space not starting at 0, which causes trouble with
582 * the way we do our IO resource renumbering. The code somewhat deals with
583 * it for 64 bits but I would expect problems on 32 bits.
585 * - Some 32 bits platforms such as 4xx can have physical space larger than
586 * 32 bits so we need to use 64 bits values for the parsing
588 void pci_process_bridge_OF_ranges(struct pci_controller *hose,
589 struct device_node *dev, int primary)
591 int memno = 0, isa_hole = -1;
592 unsigned long long isa_mb = 0;
593 struct resource *res;
594 struct of_pci_range range;
595 struct of_pci_range_parser parser;
597 pr_info("PCI host bridge %s %s ranges:\n",
598 dev->full_name, primary ? "(primary)" : "");
600 /* Check for ranges property */
601 if (of_pci_range_parser_init(&parser, dev))
604 pr_debug("Parsing ranges property...\n");
605 for_each_of_pci_range(&parser, &range) {
606 /* Read next ranges element */
607 pr_debug("pci_space: 0x%08x pci_addr:0x%016llx ",
608 range.pci_space, range.pci_addr);
609 pr_debug("cpu_addr:0x%016llx size:0x%016llx\n",
610 range.cpu_addr, range.size);
612 /* If we failed translation or got a zero-sized region
613 * (some FW try to feed us with non sensical zero sized regions
614 * such as power3 which look like some kind of attempt
615 * at exposing the VGA memory hole)
617 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
620 /* Act based on address space type */
622 switch (range.flags & IORESOURCE_TYPE_BITS) {
624 pr_info(" IO 0x%016llx..0x%016llx -> 0x%016llx\n",
625 range.cpu_addr, range.cpu_addr + range.size - 1,
628 /* We support only one IO range */
629 if (hose->pci_io_size) {
630 pr_info(" \\--> Skipped (too many) !\n");
633 /* On 32 bits, limit I/O space to 16MB */
634 if (range.size > 0x01000000)
635 range.size = 0x01000000;
637 /* 32 bits needs to map IOs here */
638 hose->io_base_virt = ioremap(range.cpu_addr,
641 /* Expect trouble if pci_addr is not 0 */
644 (unsigned long)hose->io_base_virt;
645 /* pci_io_size and io_base_phys always represent IO
646 * space starting at 0 so we factor in pci_addr
648 hose->pci_io_size = range.pci_addr + range.size;
649 hose->io_base_phys = range.cpu_addr - range.pci_addr;
652 res = &hose->io_resource;
653 range.cpu_addr = range.pci_addr;
657 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
658 range.cpu_addr, range.cpu_addr + range.size - 1,
660 (range.pci_space & 0x40000000) ?
663 /* We support only 3 memory ranges */
665 pr_info(" \\--> Skipped (too many) !\n");
668 /* Handles ISA memory hole space here */
669 if (range.pci_addr == 0) {
670 isa_mb = range.cpu_addr;
672 if (primary || isa_mem_base == 0)
673 isa_mem_base = range.cpu_addr;
674 hose->isa_mem_phys = range.cpu_addr;
675 hose->isa_mem_size = range.size;
678 /* We get the PCI/Mem offset from the first range or
679 * the, current one if the offset came from an ISA
680 * hole. If they don't match, bugger.
683 (isa_hole >= 0 && range.pci_addr != 0 &&
684 hose->pci_mem_offset == isa_mb))
685 hose->pci_mem_offset = range.cpu_addr -
687 else if (range.pci_addr != 0 &&
688 hose->pci_mem_offset != range.cpu_addr -
690 pr_info(" \\--> Skipped (offset mismatch) !\n");
695 res = &hose->mem_resources[memno++];
699 of_pci_range_to_resource(&range, dev, res);
702 /* If there's an ISA hole and the pci_mem_offset is -not- matching
703 * the ISA hole offset, then we need to remove the ISA hole from
704 * the resource list for that brige
706 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) {
707 unsigned int next = isa_hole + 1;
708 pr_info(" Removing ISA hole at 0x%016llx\n", isa_mb);
710 memmove(&hose->mem_resources[isa_hole],
711 &hose->mem_resources[next],
712 sizeof(struct resource) * (memno - next));
713 hose->mem_resources[--memno].flags = 0;
717 /* Decide whether to display the domain number in /proc */
718 int pci_proc_domain(struct pci_bus *bus)
723 /* This header fixup will do the resource fixup for all devices as they are
724 * probed, but not for bridge ranges
726 static void pcibios_fixup_resources(struct pci_dev *dev)
728 struct pci_controller *hose = pci_bus_to_host(dev->bus);
732 pr_err("No host bridge for PCI dev %s !\n",
736 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
737 struct resource *res = dev->resource + i;
740 if (res->start == 0) {
741 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]",
743 (unsigned long long)res->start,
744 (unsigned long long)res->end,
745 (unsigned int)res->flags);
746 pr_debug("is unassigned\n");
747 res->end -= res->start;
749 res->flags |= IORESOURCE_UNSET;
753 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
755 (unsigned long long)res->start,
756 (unsigned long long)res->end,
757 (unsigned int)res->flags);
760 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
762 /* This function tries to figure out if a bridge resource has been initialized
763 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
764 * things go more smoothly when it gets it right. It should covers cases such
765 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
767 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
768 struct resource *res)
770 struct pci_controller *hose = pci_bus_to_host(bus);
771 struct pci_dev *dev = bus->self;
772 resource_size_t offset;
776 /* Job is a bit different between memory and IO */
777 if (res->flags & IORESOURCE_MEM) {
778 /* If the BAR is non-0 (res != pci_mem_offset) then it's
779 * probably been initialized by somebody
781 if (res->start != hose->pci_mem_offset)
784 /* The BAR is 0, let's check if memory decoding is enabled on
785 * the bridge. If not, we consider it unassigned
787 pci_read_config_word(dev, PCI_COMMAND, &command);
788 if ((command & PCI_COMMAND_MEMORY) == 0)
791 /* Memory decoding is enabled and the BAR is 0. If any of
792 * the bridge resources covers that starting address (0 then
793 * it's good enough for us for memory
795 for (i = 0; i < 3; i++) {
796 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
797 hose->mem_resources[i].start == hose->pci_mem_offset)
801 /* Well, it starts at 0 and we know it will collide so we may as
802 * well consider it as unassigned. That covers the Apple case.
806 /* If the BAR is non-0, then we consider it assigned */
807 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
808 if (((res->start - offset) & 0xfffffffful) != 0)
811 /* Here, we are a bit different than memory as typically IO
812 * space starting at low addresses -is- valid. What we do
813 * instead if that we consider as unassigned anything that
814 * doesn't have IO enabled in the PCI command register,
817 pci_read_config_word(dev, PCI_COMMAND, &command);
818 if (command & PCI_COMMAND_IO)
821 /* It's starting at 0 and IO is disabled in the bridge, consider
828 /* Fixup resources of a PCI<->PCI bridge */
829 static void pcibios_fixup_bridge(struct pci_bus *bus)
831 struct resource *res;
834 struct pci_dev *dev = bus->self;
836 pci_bus_for_each_resource(bus, res, i) {
841 if (i >= 3 && bus->self->transparent)
844 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
846 (unsigned long long)res->start,
847 (unsigned long long)res->end,
848 (unsigned int)res->flags);
850 /* Try to detect uninitialized P2P bridge resources,
851 * and clear them out so they get re-assigned later
853 if (pcibios_uninitialized_bridge_resource(bus, res)) {
855 pr_debug("PCI:%s (unassigned)\n",
858 pr_debug("PCI:%s %016llx-%016llx\n",
860 (unsigned long long)res->start,
861 (unsigned long long)res->end);
866 void pcibios_setup_bus_self(struct pci_bus *bus)
868 /* Fix up the bus resources for P2P bridges */
869 if (bus->self != NULL)
870 pcibios_fixup_bridge(bus);
873 void pcibios_setup_bus_devices(struct pci_bus *bus)
877 pr_debug("PCI: Fixup bus devices %d (%s)\n",
878 bus->number, bus->self ? pci_name(bus->self) : "PHB");
880 list_for_each_entry(dev, &bus->devices, bus_list) {
881 /* Setup OF node pointer in archdata */
882 dev->dev.of_node = pci_device_to_OF_node(dev);
884 /* Fixup NUMA node as it may not be setup yet by the generic
885 * code and is needed by the DMA init
887 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
889 /* Hook up default DMA ops */
890 set_dma_ops(&dev->dev, pci_dma_ops);
891 dev->dev.archdata.dma_data = (void *)PCI_DRAM_OFFSET;
893 /* Read default IRQs and fixup if necessary */
894 dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
898 void pcibios_fixup_bus(struct pci_bus *bus)
900 /* When called from the generic PCI probe, read PCI<->PCI bridge
901 * bases. This is -not- called when generating the PCI tree from
902 * the OF device-tree.
904 if (bus->self != NULL)
905 pci_read_bridge_bases(bus);
907 /* Now fixup the bus bus */
908 pcibios_setup_bus_self(bus);
910 /* Now fixup devices on that bus */
911 pcibios_setup_bus_devices(bus);
913 EXPORT_SYMBOL(pcibios_fixup_bus);
915 static int skip_isa_ioresource_align(struct pci_dev *dev)
921 * We need to avoid collisions with `mirrored' VGA ports
922 * and other strange ISA hardware, so we always want the
923 * addresses to be allocated in the 0x000-0x0ff region
926 * Why? Because some silly external IO cards only decode
927 * the low 10 bits of the IO address. The 0x00-0xff region
928 * is reserved for motherboard devices that decode all 16
929 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
930 * but we want to try to avoid allocating at 0x2900-0x2bff
931 * which might have be mirrored at 0x0100-0x03ff..
933 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
934 resource_size_t size, resource_size_t align)
936 struct pci_dev *dev = data;
937 resource_size_t start = res->start;
939 if (res->flags & IORESOURCE_IO) {
940 if (skip_isa_ioresource_align(dev))
943 start = (start + 0x3ff) & ~0x3ff;
948 EXPORT_SYMBOL(pcibios_align_resource);
951 * Reparent resource children of pr that conflict with res
952 * under res, and make res replace those children.
954 static int __init reparent_resources(struct resource *parent,
955 struct resource *res)
957 struct resource *p, **pp;
958 struct resource **firstpp = NULL;
960 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
961 if (p->end < res->start)
963 if (res->end < p->start)
965 if (p->start < res->start || p->end > res->end)
966 return -1; /* not completely contained */
971 return -1; /* didn't find any conflicting entries? */
972 res->parent = parent;
973 res->child = *firstpp;
977 for (p = res->child; p != NULL; p = p->sibling) {
979 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
981 (unsigned long long)p->start,
982 (unsigned long long)p->end, res->name);
988 * Handle resources of PCI devices. If the world were perfect, we could
989 * just allocate all the resource regions and do nothing more. It isn't.
990 * On the other hand, we cannot just re-allocate all devices, as it would
991 * require us to know lots of host bridge internals. So we attempt to
992 * keep as much of the original configuration as possible, but tweak it
993 * when it's found to be wrong.
995 * Known BIOS problems we have to work around:
996 * - I/O or memory regions not configured
997 * - regions configured, but not enabled in the command register
998 * - bogus I/O addresses above 64K used
999 * - expansion ROMs left enabled (this may sound harmless, but given
1000 * the fact the PCI specs explicitly allow address decoders to be
1001 * shared between expansion ROMs and other resource regions, it's
1002 * at least dangerous)
1005 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1006 * This gives us fixed barriers on where we can allocate.
1007 * (2) Allocate resources for all enabled devices. If there is
1008 * a collision, just mark the resource as unallocated. Also
1009 * disable expansion ROMs during this step.
1010 * (3) Try to allocate resources for disabled devices. If the
1011 * resources were assigned correctly, everything goes well,
1012 * if they weren't, they won't disturb allocation of other
1014 * (4) Assign new addresses to resources which were either
1015 * not configured at all or misconfigured. If explicitly
1016 * requested by the user, configure expansion ROM address
1020 static void pcibios_allocate_bus_resources(struct pci_bus *bus)
1024 struct resource *res, *pr;
1026 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1027 pci_domain_nr(bus), bus->number);
1029 pci_bus_for_each_resource(bus, res, i) {
1030 if (!res || !res->flags
1031 || res->start > res->end || res->parent)
1033 if (bus->parent == NULL)
1034 pr = (res->flags & IORESOURCE_IO) ?
1035 &ioport_resource : &iomem_resource;
1037 /* Don't bother with non-root busses when
1038 * re-assigning all resources. We clear the
1039 * resource flags as if they were colliding
1040 * and as such ensure proper re-allocation
1043 pr = pci_find_parent_resource(bus->self, res);
1045 /* this happens when the generic PCI
1046 * code (wrongly) decides that this
1047 * bridge is transparent -- paulus
1053 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx ",
1054 bus->self ? pci_name(bus->self) : "PHB",
1056 (unsigned long long)res->start,
1057 (unsigned long long)res->end);
1058 pr_debug("[0x%x], parent %p (%s)\n",
1059 (unsigned int)res->flags,
1060 pr, (pr && pr->name) ? pr->name : "nil");
1062 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1063 if (request_resource(pr, res) == 0)
1066 * Must be a conflict with an existing entry.
1067 * Move that entry (or entries) under the
1068 * bridge resource and try again.
1070 if (reparent_resources(pr, res) == 0)
1073 pr_warn("PCI: Cannot allocate resource region ");
1074 pr_cont("%d of PCI bridge %d, will remap\n", i, bus->number);
1075 res->start = res->end = 0;
1079 list_for_each_entry(b, &bus->children, node)
1080 pcibios_allocate_bus_resources(b);
1083 static inline void alloc_resource(struct pci_dev *dev, int idx)
1085 struct resource *pr, *r = &dev->resource[idx];
1087 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1089 (unsigned long long)r->start,
1090 (unsigned long long)r->end,
1091 (unsigned int)r->flags);
1093 pr = pci_find_parent_resource(dev, r);
1094 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1095 request_resource(pr, r) < 0) {
1096 pr_warn("PCI: Cannot allocate resource region %d ", idx);
1097 pr_cont("of device %s, will remap\n", pci_name(dev));
1099 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1101 (unsigned long long)pr->start,
1102 (unsigned long long)pr->end,
1103 (unsigned int)pr->flags);
1104 /* We'll assign a new address later */
1105 r->flags |= IORESOURCE_UNSET;
1111 static void __init pcibios_allocate_resources(int pass)
1113 struct pci_dev *dev = NULL;
1118 for_each_pci_dev(dev) {
1119 pci_read_config_word(dev, PCI_COMMAND, &command);
1120 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1121 r = &dev->resource[idx];
1122 if (r->parent) /* Already allocated */
1124 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1125 continue; /* Not assigned at all */
1126 /* We only allocate ROMs on pass 1 just in case they
1127 * have been screwed up by firmware
1129 if (idx == PCI_ROM_RESOURCE)
1131 if (r->flags & IORESOURCE_IO)
1132 disabled = !(command & PCI_COMMAND_IO);
1134 disabled = !(command & PCI_COMMAND_MEMORY);
1135 if (pass == disabled)
1136 alloc_resource(dev, idx);
1140 r = &dev->resource[PCI_ROM_RESOURCE];
1142 /* Turn the ROM off, leave the resource region,
1143 * but keep it unregistered.
1146 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1147 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1148 pr_debug("PCI: Switching off ROM of %s\n",
1150 r->flags &= ~IORESOURCE_ROM_ENABLE;
1151 pci_write_config_dword(dev, dev->rom_base_reg,
1152 reg & ~PCI_ROM_ADDRESS_ENABLE);
1158 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1160 struct pci_controller *hose = pci_bus_to_host(bus);
1161 resource_size_t offset;
1162 struct resource *res, *pres;
1165 pr_debug("Reserving legacy ranges for domain %04x\n",
1166 pci_domain_nr(bus));
1169 if (!(hose->io_resource.flags & IORESOURCE_IO))
1171 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1172 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1173 BUG_ON(res == NULL);
1174 res->name = "Legacy IO";
1175 res->flags = IORESOURCE_IO;
1176 res->start = offset;
1177 res->end = (offset + 0xfff) & 0xfffffffful;
1178 pr_debug("Candidate legacy IO: %pR\n", res);
1179 if (request_resource(&hose->io_resource, res)) {
1180 pr_debug("PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1181 pci_domain_nr(bus), bus->number, res);
1186 /* Check for memory */
1187 offset = hose->pci_mem_offset;
1188 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset);
1189 for (i = 0; i < 3; i++) {
1190 pres = &hose->mem_resources[i];
1191 if (!(pres->flags & IORESOURCE_MEM))
1193 pr_debug("hose mem res: %pR\n", pres);
1194 if ((pres->start - offset) <= 0xa0000 &&
1195 (pres->end - offset) >= 0xbffff)
1200 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1201 BUG_ON(res == NULL);
1202 res->name = "Legacy VGA memory";
1203 res->flags = IORESOURCE_MEM;
1204 res->start = 0xa0000 + offset;
1205 res->end = 0xbffff + offset;
1206 pr_debug("Candidate VGA memory: %pR\n", res);
1207 if (request_resource(pres, res)) {
1208 pr_debug("PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1209 pci_domain_nr(bus), bus->number, res);
1214 void __init pcibios_resource_survey(void)
1218 /* Allocate and assign resources. If we re-assign everything, then
1219 * we skip the allocate phase
1221 list_for_each_entry(b, &pci_root_buses, node)
1222 pcibios_allocate_bus_resources(b);
1224 pcibios_allocate_resources(0);
1225 pcibios_allocate_resources(1);
1227 /* Before we start assigning unassigned resource, we try to reserve
1228 * the low IO area and the VGA memory area if they intersect the
1229 * bus available resources to avoid allocating things on top of them
1231 list_for_each_entry(b, &pci_root_buses, node)
1232 pcibios_reserve_legacy_regions(b);
1234 /* Now proceed to assigning things that were left unassigned */
1235 pr_debug("PCI: Assigning unassigned resources...\n");
1236 pci_assign_unassigned_resources();
1239 /* This is used by the PCI hotplug driver to allocate resource
1240 * of newly plugged busses. We can try to consolidate with the
1241 * rest of the code later, for now, keep it as-is as our main
1242 * resource allocation function doesn't deal with sub-trees yet.
1244 void pcibios_claim_one_bus(struct pci_bus *bus)
1246 struct pci_dev *dev;
1247 struct pci_bus *child_bus;
1249 list_for_each_entry(dev, &bus->devices, bus_list) {
1252 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1253 struct resource *r = &dev->resource[i];
1255 if (r->parent || !r->start || !r->flags)
1258 pr_debug("PCI: Claiming %s: ", pci_name(dev));
1259 pr_debug("Resource %d: %016llx..%016llx [%x]\n",
1260 i, (unsigned long long)r->start,
1261 (unsigned long long)r->end,
1262 (unsigned int)r->flags);
1264 pci_claim_resource(dev, i);
1268 list_for_each_entry(child_bus, &bus->children, node)
1269 pcibios_claim_one_bus(child_bus);
1271 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1274 /* pcibios_finish_adding_to_bus
1276 * This is to be called by the hotplug code after devices have been
1277 * added to a bus, this include calling it for a PHB that is just
1280 void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1282 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1283 pci_domain_nr(bus), bus->number);
1285 /* Allocate bus and devices resources */
1286 pcibios_allocate_bus_resources(bus);
1287 pcibios_claim_one_bus(bus);
1289 /* Add new devices to global lists. Register in proc, sysfs. */
1290 pci_bus_add_devices(bus);
1293 /* eeh_add_device_tree_late(bus); */
1295 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1297 int pcibios_enable_device(struct pci_dev *dev, int mask)
1299 return pci_enable_resources(dev, mask);
1302 static void pcibios_setup_phb_resources(struct pci_controller *hose,
1303 struct list_head *resources)
1305 unsigned long io_offset;
1306 struct resource *res;
1309 /* Hookup PHB IO resource */
1310 res = &hose->io_resource;
1312 /* Fixup IO space offset */
1313 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
1314 res->start = (res->start + io_offset) & 0xffffffffu;
1315 res->end = (res->end + io_offset) & 0xffffffffu;
1318 pr_warn("PCI: I/O resource not set for host ");
1319 pr_cont("bridge %s (domain %d)\n",
1320 hose->dn->full_name, hose->global_number);
1321 /* Workaround for lack of IO resource only on 32-bit */
1322 res->start = (unsigned long)hose->io_base_virt - isa_io_base;
1323 res->end = res->start + IO_SPACE_LIMIT;
1324 res->flags = IORESOURCE_IO;
1326 pci_add_resource_offset(resources, res,
1327 (__force resource_size_t)(hose->io_base_virt - _IO_BASE));
1329 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1330 (unsigned long long)res->start,
1331 (unsigned long long)res->end,
1332 (unsigned long)res->flags);
1334 /* Hookup PHB Memory resources */
1335 for (i = 0; i < 3; ++i) {
1336 res = &hose->mem_resources[i];
1340 pr_err("PCI: Memory resource 0 not set for ");
1341 pr_cont("host bridge %s (domain %d)\n",
1342 hose->dn->full_name, hose->global_number);
1344 /* Workaround for lack of MEM resource only on 32-bit */
1345 res->start = hose->pci_mem_offset;
1346 res->end = (resource_size_t)-1LL;
1347 res->flags = IORESOURCE_MEM;
1350 pci_add_resource_offset(resources, res, hose->pci_mem_offset);
1352 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n",
1353 i, (unsigned long long)res->start,
1354 (unsigned long long)res->end,
1355 (unsigned long)res->flags);
1358 pr_debug("PCI: PHB MEM offset = %016llx\n",
1359 (unsigned long long)hose->pci_mem_offset);
1360 pr_debug("PCI: PHB IO offset = %08lx\n",
1361 (unsigned long)hose->io_base_virt - _IO_BASE);
1364 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1366 struct pci_controller *hose = bus->sysdata;
1368 return of_node_get(hose->dn);
1371 static void pcibios_scan_phb(struct pci_controller *hose)
1373 LIST_HEAD(resources);
1374 struct pci_bus *bus;
1375 struct device_node *node = hose->dn;
1377 pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node));
1379 pcibios_setup_phb_resources(hose, &resources);
1381 bus = pci_scan_root_bus(hose->parent, hose->first_busno,
1382 hose->ops, hose, &resources);
1384 pr_err("Failed to create bus for PCI domain %04x\n",
1385 hose->global_number);
1386 pci_free_resource_list(&resources);
1389 bus->busn_res.start = hose->first_busno;
1392 hose->last_busno = bus->busn_res.end;
1395 static int __init pcibios_init(void)
1397 struct pci_controller *hose, *tmp;
1400 pr_info("PCI: Probing PCI hardware\n");
1402 /* Scan all of the recorded PCI controllers. */
1403 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1404 hose->last_busno = 0xff;
1405 pcibios_scan_phb(hose);
1406 if (next_busno <= hose->last_busno)
1407 next_busno = hose->last_busno + 1;
1409 pci_bus_count = next_busno;
1411 /* Call common code to handle resource allocation */
1412 pcibios_resource_survey();
1417 subsys_initcall(pcibios_init);
1419 static struct pci_controller *pci_bus_to_hose(int bus)
1421 struct pci_controller *hose, *tmp;
1423 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1424 if (bus >= hose->first_busno && bus <= hose->last_busno)
1429 /* Provide information on locations of various I/O regions in physical
1430 * memory. Do this on a per-card basis so that we choose the right
1432 * Note that the returned IO or memory base is a physical address
1435 long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
1437 struct pci_controller *hose;
1438 long result = -EOPNOTSUPP;
1440 hose = pci_bus_to_hose(bus);
1445 case IOBASE_BRIDGE_NUMBER:
1446 return (long)hose->first_busno;
1448 return (long)hose->pci_mem_offset;
1450 return (long)hose->io_base_phys;
1452 return (long)isa_io_base;
1453 case IOBASE_ISA_MEM:
1454 return (long)isa_mem_base;
1461 * Null PCI config access functions, for the case when we can't
1464 #define NULL_PCI_OP(rw, size, type) \
1466 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1468 return PCIBIOS_DEVICE_NOT_FOUND; \
1472 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1475 return PCIBIOS_DEVICE_NOT_FOUND;
1479 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1482 return PCIBIOS_DEVICE_NOT_FOUND;
1485 static struct pci_ops null_pci_ops = {
1486 .read = null_read_config,
1487 .write = null_write_config,
1491 * These functions are used early on before PCI scanning is done
1492 * and all of the pci_dev and pci_bus structures have been created.
1494 static struct pci_bus *
1495 fake_pci_bus(struct pci_controller *hose, int busnr)
1497 static struct pci_bus bus;
1500 pr_err("Can't find hose for PCI bus %d!\n", busnr);
1504 bus.ops = hose ? hose->ops : &null_pci_ops;
1508 #define EARLY_PCI_OP(rw, size, type) \
1509 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1510 int devfn, int offset, type value) \
1512 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1513 devfn, offset, value); \
1516 EARLY_PCI_OP(read, byte, u8 *)
1517 EARLY_PCI_OP(read, word, u16 *)
1518 EARLY_PCI_OP(read, dword, u32 *)
1519 EARLY_PCI_OP(write, byte, u8)
1520 EARLY_PCI_OP(write, word, u16)
1521 EARLY_PCI_OP(write, dword, u32)
1523 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1526 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);