arch/mips/ath79/clock.c

   1 /*
   2  *  Atheros AR71XX/AR724X/AR913X common routines
   3  *
   4  *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
   5  *  Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
   6  *
   7  *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/err.h>
  18 #include <linux/clk.h>
  19 #include <linux/clkdev.h>
  20 #include <linux/clk-provider.h>
  21
  22 #include <asm/div64.h>
  23
  24 #include <asm/mach-ath79/ath79.h>
  25 #include <asm/mach-ath79/ar71xx_regs.h>
  26 #include "common.h"
  27
  28 #define AR71XX_BASE_FREQ        40000000
  29 #define AR724X_BASE_FREQ        40000000
  30
  31 static struct clk *clks[3];
  32 static struct clk_onecell_data clk_data = {
  33         .clks = clks,
  34         .clk_num = ARRAY_SIZE(clks),
  35 };
  36
  37 static struct clk *__init ath79_add_sys_clkdev(
  38         const char *id, unsigned long rate)
  39 {
  40         struct clk *clk;
  41         int err;
  42
  43         clk = clk_register_fixed_rate(NULL, id, NULL, CLK_IS_ROOT, rate);
  44         if (!clk)
  45                 panic("failed to allocate %s clock structure", id);
  46
  47         err = clk_register_clkdev(clk, id, NULL);
  48         if (err)
  49                 panic("unable to register %s clock device", id);
  50
  51         return clk;
  52 }
  53
  54 static void __init ar71xx_clocks_init(void)
  55 {
  56         unsigned long ref_rate;
  57         unsigned long cpu_rate;
  58         unsigned long ddr_rate;
  59         unsigned long ahb_rate;
  60         u32 pll;
  61         u32 freq;
  62         u32 div;
  63
  64         ref_rate = AR71XX_BASE_FREQ;
  65
  66         pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
  67
  68         div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1;
  69         freq = div * ref_rate;
  70
  71         div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
  72         cpu_rate = freq / div;
  73
  74         div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
  75         ddr_rate = freq / div;
  76
  77         div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
  78         ahb_rate = cpu_rate / div;
  79
  80         ath79_add_sys_clkdev("ref", ref_rate);
  81         clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
  82         clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
  83         clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
  84
  85         clk_add_alias("wdt", NULL, "ahb", NULL);
  86         clk_add_alias("uart", NULL, "ahb", NULL);
  87 }
  88
  89 static void __init ar724x_clocks_init(void)
  90 {
  91         unsigned long ref_rate;
  92         unsigned long cpu_rate;
  93         unsigned long ddr_rate;
  94         unsigned long ahb_rate;
  95         u32 pll;
  96         u32 freq;
  97         u32 div;
  98
  99         ref_rate = AR724X_BASE_FREQ;
 100         pll = ath79_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
 101
 102         div = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK);
 103         freq = div * ref_rate;
 104
 105         div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2;
 106         freq /= div;
 107
 108         cpu_rate = freq;
 109
 110         div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
 111         ddr_rate = freq / div;
 112
 113         div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
 114         ahb_rate = cpu_rate / div;
 115
 116         ath79_add_sys_clkdev("ref", ref_rate);
 117         clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
 118         clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
 119         clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
 120
 121         clk_add_alias("wdt", NULL, "ahb", NULL);
 122         clk_add_alias("uart", NULL, "ahb", NULL);
 123 }
 124
 125 static void __init ar933x_clocks_init(void)
 126 {
 127         unsigned long ref_rate;
 128         unsigned long cpu_rate;
 129         unsigned long ddr_rate;
 130         unsigned long ahb_rate;
 131         u32 clock_ctrl;
 132         u32 cpu_config;
 133         u32 freq;
 134         u32 t;
 135
 136         t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
 137         if (t & AR933X_BOOTSTRAP_REF_CLK_40)
 138                 ref_rate = (40 * 1000 * 1000);
 139         else
 140                 ref_rate = (25 * 1000 * 1000);
 141
 142         clock_ctrl = ath79_pll_rr(AR933X_PLL_CLOCK_CTRL_REG);
 143         if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
 144                 cpu_rate = ref_rate;
 145                 ahb_rate = ref_rate;
 146                 ddr_rate = ref_rate;
 147         } else {
 148                 cpu_config = ath79_pll_rr(AR933X_PLL_CPU_CONFIG_REG);
 149
 150                 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
 151                     AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
 152                 freq = ref_rate / t;
 153
 154                 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
 155                     AR933X_PLL_CPU_CONFIG_NINT_MASK;
 156                 freq *= t;
 157
 158                 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
 159                     AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
 160                 if (t == 0)
 161                         t = 1;
 162
 163                 freq >>= t;
 164
 165                 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
 166                      AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
 167                 cpu_rate = freq / t;
 168
 169                 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
 170                       AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
 171                 ddr_rate = freq / t;
 172
 173                 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
 174                      AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
 175                 ahb_rate = freq / t;
 176         }
 177
 178         ath79_add_sys_clkdev("ref", ref_rate);
 179         clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
 180         clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
 181         clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
 182
 183         clk_add_alias("wdt", NULL, "ahb", NULL);
 184         clk_add_alias("uart", NULL, "ref", NULL);
 185 }
 186
 187 static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
 188                                       u32 frac, u32 out_div)
 189 {
 190         u64 t;
 191         u32 ret;
 192
 193         t = ref;
 194         t *= nint;
 195         do_div(t, ref_div);
 196         ret = t;
 197
 198         t = ref;
 199         t *= nfrac;
 200         do_div(t, ref_div * frac);
 201         ret += t;
 202
 203         ret /= (1 << out_div);
 204         return ret;
 205 }
 206
 207 static void __init ar934x_clocks_init(void)
 208 {
 209         unsigned long ref_rate;
 210         unsigned long cpu_rate;
 211         unsigned long ddr_rate;
 212         unsigned long ahb_rate;
 213         u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv;
 214         u32 cpu_pll, ddr_pll;
 215         u32 bootstrap;
 216         void __iomem *dpll_base;
 217
 218         dpll_base = ioremap(AR934X_SRIF_BASE, AR934X_SRIF_SIZE);
 219
 220         bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
 221         if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
 222                 ref_rate = 40 * 1000 * 1000;
 223         else
 224                 ref_rate = 25 * 1000 * 1000;
 225
 226         pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
 227         if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
 228                 out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
 229                           AR934X_SRIF_DPLL2_OUTDIV_MASK;
 230                 pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG);
 231                 nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
 232                        AR934X_SRIF_DPLL1_NINT_MASK;
 233                 nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
 234                 ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
 235                           AR934X_SRIF_DPLL1_REFDIV_MASK;
 236                 frac = 1 << 18;
 237         } else {
 238                 pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
 239                 out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
 240                         AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
 241                 ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
 242                           AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
 243                 nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
 244                        AR934X_PLL_CPU_CONFIG_NINT_MASK;
 245                 nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
 246                         AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
 247                 frac = 1 << 6;
 248         }
 249
 250         cpu_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
 251                                       nfrac, frac, out_div);
 252
 253         pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG);
 254         if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
 255                 out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
 256                           AR934X_SRIF_DPLL2_OUTDIV_MASK;
 257                 pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG);
 258                 nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
 259                        AR934X_SRIF_DPLL1_NINT_MASK;
 260                 nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
 261                 ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
 262                           AR934X_SRIF_DPLL1_REFDIV_MASK;
 263                 frac = 1 << 18;
 264         } else {
 265                 pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
 266                 out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
 267                           AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
 268                 ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
 269                            AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
 270                 nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
 271                        AR934X_PLL_DDR_CONFIG_NINT_MASK;
 272                 nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
 273                         AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
 274                 frac = 1 << 10;
 275         }
 276
 277         ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
 278                                       nfrac, frac, out_div);
 279
 280         clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
 281
 282         postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
 283                   AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
 284
 285         if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)
 286                 cpu_rate = ref_rate;
 287         else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
 288                 cpu_rate = cpu_pll / (postdiv + 1);
 289         else
 290                 cpu_rate = ddr_pll / (postdiv + 1);
 291
 292         postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &
 293                   AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK;
 294
 295         if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS)
 296                 ddr_rate = ref_rate;
 297         else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)
 298                 ddr_rate = ddr_pll / (postdiv + 1);
 299         else
 300                 ddr_rate = cpu_pll / (postdiv + 1);
 301
 302         postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &
 303                   AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK;
 304
 305         if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS)
 306                 ahb_rate = ref_rate;
 307         else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
 308                 ahb_rate = ddr_pll / (postdiv + 1);
 309         else
 310                 ahb_rate = cpu_pll / (postdiv + 1);
 311
 312         ath79_add_sys_clkdev("ref", ref_rate);
 313         clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
 314         clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
 315         clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
 316
 317         clk_add_alias("wdt", NULL, "ref", NULL);
 318         clk_add_alias("uart", NULL, "ref", NULL);
 319
 320         iounmap(dpll_base);
 321 }
 322
 323 static void __init qca955x_clocks_init(void)
 324 {
 325         unsigned long ref_rate;
 326         unsigned long cpu_rate;
 327         unsigned long ddr_rate;
 328         unsigned long ahb_rate;
 329         u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
 330         u32 cpu_pll, ddr_pll;
 331         u32 bootstrap;
 332
 333         bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
 334         if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40)
 335                 ref_rate = 40 * 1000 * 1000;
 336         else
 337                 ref_rate = 25 * 1000 * 1000;
 338
 339         pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
 340         out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
 341                   QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
 342         ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
 343                   QCA955X_PLL_CPU_CONFIG_REFDIV_MASK;
 344         nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) &
 345                QCA955X_PLL_CPU_CONFIG_NINT_MASK;
 346         frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
 347                QCA955X_PLL_CPU_CONFIG_NFRAC_MASK;
 348
 349         cpu_pll = nint * ref_rate / ref_div;
 350         cpu_pll += frac * ref_rate / (ref_div * (1 << 6));
 351         cpu_pll /= (1 << out_div);
 352
 353         pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
 354         out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
 355                   QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
 356         ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
 357                   QCA955X_PLL_DDR_CONFIG_REFDIV_MASK;
 358         nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) &
 359                QCA955X_PLL_DDR_CONFIG_NINT_MASK;
 360         frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
 361                QCA955X_PLL_DDR_CONFIG_NFRAC_MASK;
 362
 363         ddr_pll = nint * ref_rate / ref_div;
 364         ddr_pll += frac * ref_rate / (ref_div * (1 << 10));
 365         ddr_pll /= (1 << out_div);
 366
 367         clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);
 368
 369         postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
 370                   QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
 371
 372         if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
 373                 cpu_rate = ref_rate;
 374         else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
 375                 cpu_rate = ddr_pll / (postdiv + 1);
 376         else
 377                 cpu_rate = cpu_pll / (postdiv + 1);
 378
 379         postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
 380                   QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
 381
 382         if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
 383                 ddr_rate = ref_rate;
 384         else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
 385                 ddr_rate = cpu_pll / (postdiv + 1);
 386         else
 387                 ddr_rate = ddr_pll / (postdiv + 1);
 388
 389         postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
 390                   QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
 391
 392         if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
 393                 ahb_rate = ref_rate;
 394         else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
 395                 ahb_rate = ddr_pll / (postdiv + 1);
 396         else
 397                 ahb_rate = cpu_pll / (postdiv + 1);
 398
 399         ath79_add_sys_clkdev("ref", ref_rate);
 400         clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
 401         clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
 402         clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
 403
 404         clk_add_alias("wdt", NULL, "ref", NULL);
 405         clk_add_alias("uart", NULL, "ref", NULL);
 406 }
 407
 408 void __init ath79_clocks_init(void)
 409 {
 410         if (soc_is_ar71xx())
 411                 ar71xx_clocks_init();
 412         else if (soc_is_ar724x() || soc_is_ar913x())
 413                 ar724x_clocks_init();
 414         else if (soc_is_ar933x())
 415                 ar933x_clocks_init();
 416         else if (soc_is_ar934x())
 417                 ar934x_clocks_init();
 418         else if (soc_is_qca955x())
 419                 qca955x_clocks_init();
 420         else
 421                 BUG();
 422
 423         of_clk_init(NULL);
 424 }
 425
 426 unsigned long __init
 427 ath79_get_sys_clk_rate(const char *id)
 428 {
 429         struct clk *clk;
 430         unsigned long rate;
 431
 432         clk = clk_get(NULL, id);
 433         if (IS_ERR(clk))
 434                 panic("unable to get %s clock, err=%d", id, (int) PTR_ERR(clk));
 435
 436         rate = clk_get_rate(clk);
 437         clk_put(clk);
 438
 439         return rate;
 440 }
 441
 442 #ifdef CONFIG_OF
 443 static void __init ath79_clocks_init_dt(struct device_node *np)
 444 {
 445         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 446 }
 447
 448 CLK_OF_DECLARE(ar7100, "qca,ar7100-pll", ath79_clocks_init_dt);
 449 CLK_OF_DECLARE(ar7240, "qca,ar7240-pll", ath79_clocks_init_dt);
 450 CLK_OF_DECLARE(ar9130, "qca,ar9130-pll", ath79_clocks_init_dt);
 451 CLK_OF_DECLARE(ar9330, "qca,ar9330-pll", ath79_clocks_init_dt);
 452 CLK_OF_DECLARE(ar9340, "qca,ar9340-pll", ath79_clocks_init_dt);
 453 CLK_OF_DECLARE(ar9550, "qca,qca9550-pll", ath79_clocks_init_dt);
 454 #endif