4 compatible = "brcm,bcm7420";
10 mips-hpt-frequency = <93750000>;
13 compatible = "brcm,bmips5000";
19 compatible = "brcm,bmips5000";
31 compatible = "mti,cpu-interrupt-controller";
34 #interrupt-cells = <1>;
39 compatible = "fixed-clock";
41 clock-frequency = <81000000>;
49 compatible = "simple-bus";
50 ranges = <0 0x10000000 0x01000000>;
52 periph_intc: periph_intc@441400 {
53 compatible = "brcm,bcm7038-l1-intc";
54 reg = <0x441400 0x30>, <0x441600 0x30>;
57 #interrupt-cells = <1>;
59 interrupt-parent = <&cpu_intc>;
60 interrupts = <2>, <3>;
63 sun_l2_intc: sun_l2_intc@401800 {
64 compatible = "brcm,l2-intc";
65 reg = <0x401800 0x30>;
67 #interrupt-cells = <1>;
68 interrupt-parent = <&periph_intc>;
73 compatible = "brcm,bcm7400-gisb-arb";
74 reg = <0x400000 0xdc>;
76 interrupt-parent = <&sun_l2_intc>;
77 interrupts = <0>, <2>;
78 brcm,gisb-arb-master-mask = <0x3ff>;
79 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pci_0",
80 "pcie_0", "bsp_0", "rdc_0",
81 "rptd_0", "avd_0", "avd_1",
85 upg_irq0_intc: upg_irq0_intc@406780 {
86 compatible = "brcm,bcm7120-l2-intc";
89 brcm,int-map-mask = <0x44>, <0x1f000000>;
90 brcm,int-fwd-mask = <0x70000>;
93 #interrupt-cells = <1>;
95 interrupt-parent = <&periph_intc>;
96 interrupts = <18>, <19>;
97 interrupt-names = "upg_main", "upg_bsc";
100 sun_top_ctrl: syscon@404000 {
101 compatible = "brcm,bcm7420-sun-top-ctrl", "syscon";
102 reg = <0x404000 0x60c>;
107 compatible = "brcm,bcm7038-reboot";
108 syscon = <&sun_top_ctrl 0x8 0x14>;
111 uart0: serial@406b00 {
112 compatible = "ns16550a";
113 reg = <0x406b00 0x20>;
114 reg-io-width = <0x4>;
116 interrupt-parent = <&periph_intc>;
118 clocks = <&uart_clk>;
122 uart1: serial@406b40 {
123 compatible = "ns16550a";
124 reg = <0x406b40 0x20>;
125 reg-io-width = <0x4>;
127 interrupt-parent = <&periph_intc>;
129 clocks = <&uart_clk>;
133 uart2: serial@406b80 {
134 compatible = "ns16550a";
135 reg = <0x406b80 0x20>;
136 reg-io-width = <0x4>;
138 interrupt-parent = <&periph_intc>;
140 clocks = <&uart_clk>;
145 clock-frequency = <390000>;
146 compatible = "brcm,brcmstb-i2c";
147 interrupt-parent = <&upg_irq0_intc>;
148 reg = <0x406200 0x58>;
150 interrupt-names = "upg_bsca";
155 clock-frequency = <390000>;
156 compatible = "brcm,brcmstb-i2c";
157 interrupt-parent = <&upg_irq0_intc>;
158 reg = <0x406280 0x58>;
160 interrupt-names = "upg_bscb";
165 clock-frequency = <390000>;
166 compatible = "brcm,brcmstb-i2c";
167 interrupt-parent = <&upg_irq0_intc>;
168 reg = <0x406300 0x58>;
170 interrupt-names = "upg_bscc";
175 clock-frequency = <390000>;
176 compatible = "brcm,brcmstb-i2c";
177 interrupt-parent = <&upg_irq0_intc>;
178 reg = <0x406380 0x58>;
180 interrupt-names = "upg_bscd";
185 clock-frequency = <390000>;
186 compatible = "brcm,brcmstb-i2c";
187 interrupt-parent = <&upg_irq0_intc>;
188 reg = <0x406800 0x58>;
190 interrupt-names = "upg_bsce";
194 enet0: ethernet@468000 {
195 phy-mode = "internal";
196 phy-handle = <&phy1>;
197 mac-address = [ 00 10 18 36 23 1a ];
198 compatible = "brcm,genet-v1";
199 #address-cells = <0x1>;
201 reg = <0x468000 0x3c8c>;
202 interrupts = <69>, <79>;
203 interrupt-parent = <&periph_intc>;
207 compatible = "brcm,genet-mdio-v1";
208 #address-cells = <0x1>;
212 phy1: ethernet-phy@1 {
215 compatible = "brcm,65nm-ephy",
216 "ethernet-phy-ieee802.3-c22";
222 compatible = "brcm,bcm7420-ehci", "generic-ehci";
223 reg = <0x488300 0x100>;
224 interrupt-parent = <&periph_intc>;
230 compatible = "brcm,bcm7420-ohci", "generic-ohci";
231 reg = <0x488400 0x100>;
234 interrupt-parent = <&periph_intc>;
240 compatible = "brcm,bcm7420-ehci", "generic-ehci";
241 reg = <0x488500 0x100>;
242 interrupt-parent = <&periph_intc>;
248 compatible = "brcm,bcm7420-ohci", "generic-ohci";
249 reg = <0x488600 0x100>;
252 interrupt-parent = <&periph_intc>;