4 compatible = "brcm,bcm7425";
10 mips-hpt-frequency = <163125000>;
13 compatible = "brcm,bmips5000";
19 compatible = "brcm,bmips5000";
31 compatible = "mti,cpu-interrupt-controller";
34 #interrupt-cells = <1>;
39 compatible = "fixed-clock";
41 clock-frequency = <81000000>;
49 compatible = "simple-bus";
50 ranges = <0 0x10000000 0x01000000>;
52 periph_intc: periph_intc@41a400 {
53 compatible = "brcm,bcm7038-l1-intc";
54 reg = <0x41a400 0x30>, <0x41a600 0x30>;
57 #interrupt-cells = <1>;
59 interrupt-parent = <&cpu_intc>;
60 interrupts = <2>, <3>;
63 sun_l2_intc: sun_l2_intc@403000 {
64 compatible = "brcm,l2-intc";
65 reg = <0x403000 0x30>;
67 #interrupt-cells = <1>;
68 interrupt-parent = <&periph_intc>;
73 compatible = "brcm,bcm7400-gisb-arb";
74 reg = <0x400000 0xdc>;
76 interrupt-parent = <&sun_l2_intc>;
77 interrupts = <0>, <2>;
78 brcm,gisb-arb-master-mask = <0x177b>;
79 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pcie_0",
86 upg_irq0_intc: upg_irq0_intc@406780 {
87 compatible = "brcm,bcm7120-l2-intc";
90 brcm,int-map-mask = <0x44>, <0x7000000>;
91 brcm,int-fwd-mask = <0x70000>;
94 #interrupt-cells = <1>;
96 interrupt-parent = <&periph_intc>;
97 interrupts = <55>, <53>;
98 interrupt-names = "upg_main", "upg_bsc";
101 upg_aon_irq0_intc: upg_aon_irq0_intc@409480 {
102 compatible = "brcm,bcm7120-l2-intc";
103 reg = <0x409480 0x8>;
105 brcm,int-map-mask = <0x40>, <0x18000000>, <0x100000>;
106 brcm,int-fwd-mask = <0>;
109 interrupt-controller;
110 #interrupt-cells = <1>;
112 interrupt-parent = <&periph_intc>;
113 interrupts = <56>, <54>, <59>;
114 interrupt-names = "upg_main_aon", "upg_bsc_aon",
118 sun_top_ctrl: syscon@404000 {
119 compatible = "brcm,bcm7425-sun-top-ctrl", "syscon";
120 reg = <0x404000 0x51c>;
125 compatible = "brcm,brcmstb-reboot";
126 syscon = <&sun_top_ctrl 0x304 0x308>;
129 uart0: serial@406b00 {
130 compatible = "ns16550a";
131 reg = <0x406b00 0x20>;
132 reg-io-width = <0x4>;
134 interrupt-parent = <&periph_intc>;
136 clocks = <&uart_clk>;
140 uart1: serial@406b40 {
141 compatible = "ns16550a";
142 reg = <0x406b40 0x20>;
143 reg-io-width = <0x4>;
145 interrupt-parent = <&periph_intc>;
147 clocks = <&uart_clk>;
151 uart2: serial@406b80 {
152 compatible = "ns16550a";
153 reg = <0x406b80 0x20>;
154 reg-io-width = <0x4>;
156 interrupt-parent = <&periph_intc>;
158 clocks = <&uart_clk>;
163 clock-frequency = <390000>;
164 compatible = "brcm,brcmstb-i2c";
165 interrupt-parent = <&upg_aon_irq0_intc>;
166 reg = <0x409180 0x58>;
168 interrupt-names = "upg_bsca";
173 clock-frequency = <390000>;
174 compatible = "brcm,brcmstb-i2c";
175 interrupt-parent = <&upg_aon_irq0_intc>;
176 reg = <0x409400 0x58>;
178 interrupt-names = "upg_bscb";
183 clock-frequency = <390000>;
184 compatible = "brcm,brcmstb-i2c";
185 interrupt-parent = <&upg_irq0_intc>;
186 reg = <0x406200 0x58>;
188 interrupt-names = "upg_bscc";
193 clock-frequency = <390000>;
194 compatible = "brcm,brcmstb-i2c";
195 interrupt-parent = <&upg_irq0_intc>;
196 reg = <0x406280 0x58>;
198 interrupt-names = "upg_bscd";
203 clock-frequency = <390000>;
204 compatible = "brcm,brcmstb-i2c";
205 interrupt-parent = <&upg_irq0_intc>;
206 reg = <0x406300 0x58>;
208 interrupt-names = "upg_bsce";
212 enet0: ethernet@b80000 {
213 phy-mode = "internal";
214 phy-handle = <&phy1>;
215 mac-address = [ 00 10 18 36 23 1a ];
216 compatible = "brcm,genet-v3";
217 #address-cells = <0x1>;
219 reg = <0xb80000 0x11c88>;
220 interrupts = <17>, <18>;
221 interrupt-parent = <&periph_intc>;
225 compatible = "brcm,genet-mdio-v3";
226 #address-cells = <0x1>;
230 phy1: ethernet-phy@1 {
233 compatible = "brcm,40nm-ephy",
234 "ethernet-phy-ieee802.3-c22";
240 compatible = "brcm,bcm7425-ehci", "generic-ehci";
241 reg = <0x480300 0x100>;
243 interrupt-parent = <&periph_intc>;
249 compatible = "brcm,bcm7425-ohci", "generic-ohci";
250 reg = <0x480400 0x100>;
253 interrupt-parent = <&periph_intc>;
259 compatible = "brcm,bcm7425-ehci", "generic-ehci";
260 reg = <0x480500 0x100>;
262 interrupt-parent = <&periph_intc>;
268 compatible = "brcm,bcm7425-ohci", "generic-ohci";
269 reg = <0x480600 0x100>;
272 interrupt-parent = <&periph_intc>;
278 compatible = "brcm,bcm7425-ehci", "generic-ehci";
279 reg = <0x490300 0x100>;
281 interrupt-parent = <&periph_intc>;
287 compatible = "brcm,bcm7425-ohci", "generic-ohci";
288 reg = <0x490400 0x100>;
291 interrupt-parent = <&periph_intc>;
297 compatible = "brcm,bcm7425-ehci", "generic-ehci";
298 reg = <0x490500 0x100>;
300 interrupt-parent = <&periph_intc>;
306 compatible = "brcm,bcm7425-ohci", "generic-ohci";
307 reg = <0x490600 0x100>;
310 interrupt-parent = <&periph_intc>;
316 compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
317 reg-names = "ahci", "top-ctrl";
318 reg = <0x181000 0xa9c>, <0x180020 0x1c>;
319 interrupt-parent = <&periph_intc>;
321 #address-cells = <1>;
336 sata_phy: sata-phy@180100 {
337 compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
338 reg = <0x180100 0x0eff>;
340 #address-cells = <1>;
344 sata_phy0: sata-phy@0 {
349 sata_phy1: sata-phy@1 {