4 compatible = "brcm,bcm7435";
10 mips-hpt-frequency = <175625000>;
13 compatible = "brcm,bmips5200";
19 compatible = "brcm,bmips5200";
25 compatible = "brcm,bmips5200";
31 compatible = "brcm,bmips5200";
41 cpu_intc: interrupt-controller {
43 compatible = "mti,cpu-interrupt-controller";
46 #interrupt-cells = <1>;
51 compatible = "fixed-clock";
53 clock-frequency = <81000000>;
57 compatible = "fixed-clock";
59 clock-frequency = <27000000>;
67 compatible = "simple-bus";
68 ranges = <0 0x10000000 0x01000000>;
70 periph_intc: interrupt-controller@41b500 {
71 compatible = "brcm,bcm7038-l1-intc";
72 reg = <0x41b500 0x40>, <0x41b600 0x40>,
73 <0x41b700 0x40>, <0x41b800 0x40>;
76 #interrupt-cells = <1>;
78 interrupt-parent = <&cpu_intc>;
79 interrupts = <2>, <3>, <2>, <3>;
82 sun_l2_intc: interrupt-controller@403000 {
83 compatible = "brcm,l2-intc";
84 reg = <0x403000 0x30>;
86 #interrupt-cells = <1>;
87 interrupt-parent = <&periph_intc>;
92 compatible = "brcm,bcm7435-gisb-arb";
93 reg = <0x400000 0xdc>;
95 interrupt-parent = <&sun_l2_intc>;
96 interrupts = <0>, <2>;
97 brcm,gisb-arb-master-mask = <0xf77f>;
98 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "webcpu_0",
107 upg_irq0_intc: interrupt-controller@406780 {
108 compatible = "brcm,bcm7120-l2-intc";
109 reg = <0x406780 0x8>;
111 brcm,int-map-mask = <0x44>, <0x7000000>;
112 brcm,int-fwd-mask = <0x70000>;
114 interrupt-controller;
115 #interrupt-cells = <1>;
117 interrupt-parent = <&periph_intc>;
118 interrupts = <60>, <58>;
119 interrupt-names = "upg_main", "upg_bsc";
122 upg_aon_irq0_intc: interrupt-controller@409480 {
123 compatible = "brcm,bcm7120-l2-intc";
124 reg = <0x409480 0x8>;
126 brcm,int-map-mask = <0x40>, <0x18000000>, <0x100000>;
127 brcm,int-fwd-mask = <0>;
130 interrupt-controller;
131 #interrupt-cells = <1>;
133 interrupt-parent = <&periph_intc>;
134 interrupts = <61>, <59>, <64>;
135 interrupt-names = "upg_main_aon", "upg_bsc_aon",
139 sun_top_ctrl: syscon@404000 {
140 compatible = "brcm,bcm7425-sun-top-ctrl", "syscon";
141 reg = <0x404000 0x51c>;
146 compatible = "brcm,brcmstb-reboot";
147 syscon = <&sun_top_ctrl 0x304 0x308>;
150 uart0: serial@406b00 {
151 compatible = "ns16550a";
152 reg = <0x406b00 0x20>;
153 reg-io-width = <0x4>;
155 interrupt-parent = <&periph_intc>;
157 clocks = <&uart_clk>;
161 uart1: serial@406b40 {
162 compatible = "ns16550a";
163 reg = <0x406b40 0x20>;
164 reg-io-width = <0x4>;
166 interrupt-parent = <&periph_intc>;
168 clocks = <&uart_clk>;
172 uart2: serial@406b80 {
173 compatible = "ns16550a";
174 reg = <0x406b80 0x20>;
175 reg-io-width = <0x4>;
177 interrupt-parent = <&periph_intc>;
179 clocks = <&uart_clk>;
184 clock-frequency = <390000>;
185 compatible = "brcm,brcmstb-i2c";
186 interrupt-parent = <&upg_irq0_intc>;
187 reg = <0x406300 0x58>;
189 interrupt-names = "upg_bsca";
194 clock-frequency = <390000>;
195 compatible = "brcm,brcmstb-i2c";
196 interrupt-parent = <&upg_aon_irq0_intc>;
197 reg = <0x409400 0x58>;
199 interrupt-names = "upg_bscb";
204 clock-frequency = <390000>;
205 compatible = "brcm,brcmstb-i2c";
206 interrupt-parent = <&upg_irq0_intc>;
207 reg = <0x406200 0x58>;
209 interrupt-names = "upg_bscc";
214 clock-frequency = <390000>;
215 compatible = "brcm,brcmstb-i2c";
216 interrupt-parent = <&upg_irq0_intc>;
217 reg = <0x406280 0x58>;
219 interrupt-names = "upg_bscd";
224 clock-frequency = <390000>;
225 compatible = "brcm,brcmstb-i2c";
226 interrupt-parent = <&upg_aon_irq0_intc>;
227 reg = <0x409180 0x58>;
229 interrupt-names = "upg_bsce";
234 compatible = "brcm,bcm7038-pwm";
235 reg = <0x406580 0x28>;
242 compatible = "brcm,bcm7038-pwm";
243 reg = <0x406800 0x28>;
249 aon_pm_l2_intc: interrupt-controller@408440 {
250 compatible = "brcm,l2-intc";
251 reg = <0x408440 0x30>;
252 interrupt-controller;
253 #interrupt-cells = <1>;
254 interrupt-parent = <&periph_intc>;
259 upg_gio: gpio@406700 {
260 compatible = "brcm,brcmstb-gpio";
261 reg = <0x406700 0x80>;
263 #interrupt-cells = <2>;
265 interrupt-controller;
266 interrupt-parent = <&upg_irq0_intc>;
268 brcm,gpio-bank-widths = <32 32 32 21>;
271 upg_gio_aon: gpio@4094c0 {
272 compatible = "brcm,brcmstb-gpio";
273 reg = <0x4094c0 0x40>;
275 #interrupt-cells = <2>;
277 interrupt-controller;
278 interrupt-parent = <&upg_aon_irq0_intc>;
280 interrupts-extended = <&upg_aon_irq0_intc 6>,
283 brcm,gpio-bank-widths = <18 4>;
286 enet0: ethernet@b80000 {
287 phy-mode = "internal";
288 phy-handle = <&phy1>;
289 mac-address = [ 00 10 18 36 23 1a ];
290 compatible = "brcm,genet-v3";
291 #address-cells = <0x1>;
293 reg = <0xb80000 0x11c88>;
294 interrupts = <17>, <18>;
295 interrupt-parent = <&periph_intc>;
299 compatible = "brcm,genet-mdio-v3";
300 #address-cells = <0x1>;
304 phy1: ethernet-phy@1 {
307 compatible = "brcm,40nm-ephy",
308 "ethernet-phy-ieee802.3-c22";
314 compatible = "brcm,bcm7435-ehci", "generic-ehci";
315 reg = <0x480300 0x100>;
317 interrupt-parent = <&periph_intc>;
323 compatible = "brcm,bcm7435-ohci", "generic-ohci";
324 reg = <0x480400 0x100>;
327 interrupt-parent = <&periph_intc>;
333 compatible = "brcm,bcm7435-ehci", "generic-ehci";
334 reg = <0x480500 0x100>;
336 interrupt-parent = <&periph_intc>;
342 compatible = "brcm,bcm7435-ohci", "generic-ohci";
343 reg = <0x480600 0x100>;
346 interrupt-parent = <&periph_intc>;
352 compatible = "brcm,bcm7435-ehci", "generic-ehci";
353 reg = <0x490300 0x100>;
355 interrupt-parent = <&periph_intc>;
361 compatible = "brcm,bcm7435-ohci", "generic-ohci";
362 reg = <0x490400 0x100>;
365 interrupt-parent = <&periph_intc>;
371 compatible = "brcm,bcm7435-ehci", "generic-ehci";
372 reg = <0x490500 0x100>;
374 interrupt-parent = <&periph_intc>;
380 compatible = "brcm,bcm7435-ohci", "generic-ohci";
381 reg = <0x490600 0x100>;
384 interrupt-parent = <&periph_intc>;
389 hif_l2_intc: interrupt-controller@41b000 {
390 compatible = "brcm,l2-intc";
391 reg = <0x41b000 0x30>;
392 interrupt-controller;
393 #interrupt-cells = <1>;
394 interrupt-parent = <&periph_intc>;
399 compatible = "brcm,brcmnand-v6.2", "brcm,brcmnand";
400 #address-cells = <1>;
402 reg-names = "nand", "flash-dma";
403 reg = <0x41c800 0x600>, <0x41d000 0x100>;
404 interrupt-parent = <&hif_l2_intc>;
405 interrupts = <24>, <4>;
410 compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
411 reg-names = "ahci", "top-ctrl";
412 reg = <0x181000 0xa9c>, <0x180020 0x1c>;
413 interrupt-parent = <&periph_intc>;
415 #address-cells = <1>;
430 sata_phy: sata-phy@180100 {
431 compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
432 reg = <0x180100 0x0eff>;
434 #address-cells = <1>;
438 sata_phy0: sata-phy@0 {
443 sata_phy1: sata-phy@1 {
449 sdhci0: sdhci@41a000 {
450 compatible = "brcm,bcm7425-sdhci";
451 reg = <0x41a000 0x100>;
452 interrupt-parent = <&periph_intc>;
459 sdhci1: sdhci@41a200 {
460 compatible = "brcm,bcm7425-sdhci";
461 reg = <0x41a200 0x100>;
462 interrupt-parent = <&periph_intc>;