arch/mips/boot/dts/mti/sead3.dts

   1 /dts-v1/;
   2
   3 /memreserve/ 0x00000000 0x00001000;     // reserved
   4 /memreserve/ 0x00001000 0x000ef000;     // ROM data
   5 /memreserve/ 0x000f0000 0x004cc000;     // reserved
   6
   7 #include <dt-bindings/interrupt-controller/mips-gic.h>
   8
   9 / {
  10         #address-cells = <1>;
  11         #size-cells = <1>;
  12         compatible = "mti,sead-3";
  13         model = "MIPS SEAD-3";
  14         interrupt-parent = <&gic>;
  15
  16         chosen {
  17                 stdout-path = "uart1:115200";
  18         };
  19
  20         aliases {
  21                 uart0 = &uart0;
  22                 uart1 = &uart1;
  23         };
  24
  25         cpus {
  26                 cpu@0 {
  27                         compatible = "mti,mips14KEc", "mti,mips14Kc";
  28                 };
  29         };
  30
  31         memory {
  32                 device_type = "memory";
  33                 reg = <0x0 0x08000000>;
  34         };
  35
  36         cpu_intc: interrupt-controller {
  37                 compatible = "mti,cpu-interrupt-controller";
  38
  39                 interrupt-controller;
  40                 #interrupt-cells = <1>;
  41         };
  42
  43         gic: interrupt-controller@1b1c0000 {
  44                 compatible = "mti,gic";
  45                 reg = <0x1b1c0000 0x20000>;
  46
  47                 interrupt-controller;
  48                 #interrupt-cells = <3>;
  49
  50                 /*
  51                  * Declare the interrupt-parent even though the mti,gic
  52                  * binding doesn't require it, such that the kernel can
  53                  * figure out that cpu_intc is the root interrupt
  54                  * controller & should be probed first.
  55                  */
  56                 interrupt-parent = <&cpu_intc>;
  57
  58                 timer {
  59                         compatible = "mti,gic-timer";
  60                         interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
  61                 };
  62         };
  63
  64         ehci@1b200000 {
  65                 compatible = "generic-ehci";
  66                 reg = <0x1b200000 0x1000>;
  67
  68                 interrupts = <0>; /* GIC 0 or CPU 6 */
  69
  70                 has-transaction-translator;
  71         };
  72
  73         flash@1c000000 {
  74                 compatible = "intel,28f128j3", "cfi-flash";
  75                 reg = <0x1c000000 0x2000000>;
  76                 #address-cells = <1>;
  77                 #size-cells = <1>;
  78                 bank-width = <4>;
  79
  80                 partitions {
  81                         compatible = "fixed-partitions";
  82                         #address-cells = <1>;
  83                         #size-cells = <1>;
  84
  85                         user-fs@0 {
  86                                 label = "User FS";
  87                                 reg = <0x0 0x1fc0000>;
  88                         };
  89
  90                         board-config@3e0000 {
  91                                 label = "Board Config";
  92                                 reg = <0x1fc0000 0x40000>;
  93                         };
  94                 };
  95         };
  96
  97         fpga_regs: system-controller@1f000000 {
  98                 compatible = "mti,sead3-fpga", "syscon", "simple-mfd";
  99                 reg = <0x1f000000 0x200>;
 100
 101                 reboot {
 102                         compatible = "syscon-reboot";
 103                         regmap = <&fpga_regs>;
 104                         offset = <0x50>;
 105                         mask = <0x4d>;
 106                 };
 107
 108                 poweroff {
 109                         compatible = "restart-poweroff";
 110                 };
 111         };
 112
 113         system-controller@1f000200 {
 114                 compatible = "mti,sead3-cpld", "syscon", "simple-mfd";
 115                 reg = <0x1f000200 0x300>;
 116
 117                 led@10.0 {
 118                         compatible = "register-bit-led";
 119                         offset = <0x10>;
 120                         mask = <0x1>;
 121                         label = "pled0";
 122                 };
 123                 led@10.1 {
 124                         compatible = "register-bit-led";
 125                         offset = <0x10>;
 126                         mask = <0x2>;
 127                         label = "pled1";
 128                 };
 129                 led@10.2 {
 130                         compatible = "register-bit-led";
 131                         offset = <0x10>;
 132                         mask = <0x4>;
 133                         label = "pled2";
 134                 };
 135                 led@10.3 {
 136                         compatible = "register-bit-led";
 137                         offset = <0x10>;
 138                         mask = <0x8>;
 139                         label = "pled3";
 140                 };
 141                 led@10.4 {
 142                         compatible = "register-bit-led";
 143                         offset = <0x10>;
 144                         mask = <0x10>;
 145                         label = "pled4";
 146                 };
 147                 led@10.5 {
 148                         compatible = "register-bit-led";
 149                         offset = <0x10>;
 150                         mask = <0x20>;
 151                         label = "pled5";
 152                 };
 153                 led@10.6 {
 154                         compatible = "register-bit-led";
 155                         offset = <0x10>;
 156                         mask = <0x40>;
 157                         label = "pled6";
 158                 };
 159                 led@10.7 {
 160                         compatible = "register-bit-led";
 161                         offset = <0x10>;
 162                         mask = <0x80>;
 163                         label = "pled7";
 164                 };
 165
 166                 led@18.0 {
 167                         compatible = "register-bit-led";
 168                         offset = <0x18>;
 169                         mask = <0x1>;
 170                         label = "fled0";
 171                 };
 172                 led@18.1 {
 173                         compatible = "register-bit-led";
 174                         offset = <0x18>;
 175                         mask = <0x2>;
 176                         label = "fled1";
 177                 };
 178                 led@18.2 {
 179                         compatible = "register-bit-led";
 180                         offset = <0x18>;
 181                         mask = <0x4>;
 182                         label = "fled2";
 183                 };
 184                 led@18.3 {
 185                         compatible = "register-bit-led";
 186                         offset = <0x18>;
 187                         mask = <0x8>;
 188                         label = "fled3";
 189                 };
 190                 led@18.4 {
 191                         compatible = "register-bit-led";
 192                         offset = <0x18>;
 193                         mask = <0x10>;
 194                         label = "fled4";
 195                 };
 196                 led@18.5 {
 197                         compatible = "register-bit-led";
 198                         offset = <0x18>;
 199                         mask = <0x20>;
 200                         label = "fled5";
 201                 };
 202                 led@18.6 {
 203                         compatible = "register-bit-led";
 204                         offset = <0x18>;
 205                         mask = <0x40>;
 206                         label = "fled6";
 207                 };
 208                 led@18.7 {
 209                         compatible = "register-bit-led";
 210                         offset = <0x18>;
 211                         mask = <0x80>;
 212                         label = "fled7";
 213                 };
 214
 215                 lcd@200 {
 216                         compatible = "mti,sead3-lcd";
 217                         offset = <0x200>;
 218                 };
 219         };
 220
 221         /* UART connected to FTDI & miniUSB socket */
 222         uart0: uart@1f000900 {
 223                 compatible = "ns16550a";
 224                 reg = <0x1f000900 0x20>;
 225                 reg-io-width = <4>;
 226                 reg-shift = <2>;
 227
 228                 clock-frequency = <14745600>;
 229
 230                 interrupts = <3>; /* GIC 3 or CPU 4 */
 231
 232                 no-loopback-test;
 233         };
 234
 235         /* UART connected to RS232 socket */
 236         uart1: uart@1f000800 {
 237                 compatible = "ns16550a";
 238                 reg = <0x1f000800 0x20>;
 239                 reg-io-width = <4>;
 240                 reg-shift = <2>;
 241
 242                 clock-frequency = <14745600>;
 243
 244                 interrupts = <2>; /* GIC 2 or CPU 4 */
 245
 246                 no-loopback-test;
 247         };
 248
 249         eth@1f010000 {
 250                 compatible = "smsc,lan9115";
 251                 reg = <0x1f010000 0x10000>;
 252                 reg-io-width = <4>;
 253
 254                 interrupts = <0>; /* GIC 0 or CPU 6 */
 255
 256                 phy-mode = "mii";
 257                 smsc,irq-push-pull;
 258                 smsc,save-mac-address;
 259         };
 260 };