2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2004-2016 Cavium, Inc.
9 #include <linux/of_address.h>
10 #include <linux/interrupt.h>
11 #include <linux/irqdomain.h>
12 #include <linux/bitops.h>
13 #include <linux/of_irq.h>
14 #include <linux/percpu.h>
15 #include <linux/slab.h>
16 #include <linux/irq.h>
17 #include <linux/smp.h>
20 #include <asm/octeon/octeon.h>
21 #include <asm/octeon/cvmx-ciu2-defs.h>
23 static DEFINE_PER_CPU(unsigned long, octeon_irq_ciu0_en_mirror);
24 static DEFINE_PER_CPU(unsigned long, octeon_irq_ciu1_en_mirror);
25 static DEFINE_PER_CPU(raw_spinlock_t, octeon_irq_ciu_spinlock);
27 struct octeon_irq_ciu_domain_data {
28 int num_sum; /* number of sum registers (2 or 3). */
31 static __read_mostly int octeon_irq_ciu_to_irq[8][64];
33 struct octeon_ciu_chip_data {
35 struct { /* only used for ciu3 */
39 struct { /* only used for ciu/ciu2 */
45 int current_cpu; /* Next CPU expected to take this irq */
48 struct octeon_core_chip_data {
49 struct mutex core_irq_mutex;
55 #define MIPS_CORE_IRQ_LINES 8
57 static struct octeon_core_chip_data octeon_irq_core_chip_data[MIPS_CORE_IRQ_LINES];
59 static int octeon_irq_set_ciu_mapping(int irq, int line, int bit, int gpio_line,
60 struct irq_chip *chip,
61 irq_flow_handler_t handler)
63 struct octeon_ciu_chip_data *cd;
65 cd = kzalloc(sizeof(*cd), GFP_KERNEL);
69 irq_set_chip_and_handler(irq, chip, handler);
73 cd->gpio_line = gpio_line;
75 irq_set_chip_data(irq, cd);
76 octeon_irq_ciu_to_irq[line][bit] = irq;
80 static void octeon_irq_free_cd(struct irq_domain *d, unsigned int irq)
82 struct irq_data *data = irq_get_irq_data(irq);
83 struct octeon_ciu_chip_data *cd = irq_data_get_irq_chip_data(data);
85 irq_set_chip_data(irq, NULL);
89 static int octeon_irq_force_ciu_mapping(struct irq_domain *domain,
90 int irq, int line, int bit)
92 return irq_domain_associate(domain, irq, line << 6 | bit);
95 static int octeon_coreid_for_cpu(int cpu)
98 return cpu_logical_map(cpu);
100 return cvmx_get_core_num();
104 static int octeon_cpu_for_coreid(int coreid)
107 return cpu_number_map(coreid);
109 return smp_processor_id();
113 static void octeon_irq_core_ack(struct irq_data *data)
115 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
116 unsigned int bit = cd->bit;
119 * We don't need to disable IRQs to make these atomic since
120 * they are already disabled earlier in the low level
123 clear_c0_status(0x100 << bit);
124 /* The two user interrupts must be cleared manually. */
126 clear_c0_cause(0x100 << bit);
129 static void octeon_irq_core_eoi(struct irq_data *data)
131 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
134 * We don't need to disable IRQs to make these atomic since
135 * they are already disabled earlier in the low level
138 set_c0_status(0x100 << cd->bit);
141 static void octeon_irq_core_set_enable_local(void *arg)
143 struct irq_data *data = arg;
144 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
145 unsigned int mask = 0x100 << cd->bit;
148 * Interrupts are already disabled, so these are atomic.
153 clear_c0_status(mask);
157 static void octeon_irq_core_disable(struct irq_data *data)
159 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
160 cd->desired_en = false;
163 static void octeon_irq_core_enable(struct irq_data *data)
165 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
166 cd->desired_en = true;
169 static void octeon_irq_core_bus_lock(struct irq_data *data)
171 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
173 mutex_lock(&cd->core_irq_mutex);
176 static void octeon_irq_core_bus_sync_unlock(struct irq_data *data)
178 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
180 if (cd->desired_en != cd->current_en) {
181 on_each_cpu(octeon_irq_core_set_enable_local, data, 1);
183 cd->current_en = cd->desired_en;
186 mutex_unlock(&cd->core_irq_mutex);
189 static struct irq_chip octeon_irq_chip_core = {
191 .irq_enable = octeon_irq_core_enable,
192 .irq_disable = octeon_irq_core_disable,
193 .irq_ack = octeon_irq_core_ack,
194 .irq_eoi = octeon_irq_core_eoi,
195 .irq_bus_lock = octeon_irq_core_bus_lock,
196 .irq_bus_sync_unlock = octeon_irq_core_bus_sync_unlock,
198 .irq_cpu_online = octeon_irq_core_eoi,
199 .irq_cpu_offline = octeon_irq_core_ack,
200 .flags = IRQCHIP_ONOFFLINE_ENABLED,
203 static void __init octeon_irq_init_core(void)
207 struct octeon_core_chip_data *cd;
209 for (i = 0; i < MIPS_CORE_IRQ_LINES; i++) {
210 cd = &octeon_irq_core_chip_data[i];
211 cd->current_en = false;
212 cd->desired_en = false;
214 mutex_init(&cd->core_irq_mutex);
216 irq = OCTEON_IRQ_SW0 + i;
217 irq_set_chip_data(irq, cd);
218 irq_set_chip_and_handler(irq, &octeon_irq_chip_core,
223 static int next_cpu_for_irq(struct irq_data *data)
228 struct cpumask *mask = irq_data_get_affinity_mask(data);
229 int weight = cpumask_weight(mask);
230 struct octeon_ciu_chip_data *cd = irq_data_get_irq_chip_data(data);
233 cpu = cd->current_cpu;
235 cpu = cpumask_next(cpu, mask);
236 if (cpu >= nr_cpu_ids) {
239 } else if (cpumask_test_cpu(cpu, cpu_online_mask)) {
243 } else if (weight == 1) {
244 cpu = cpumask_first(mask);
246 cpu = smp_processor_id();
248 cd->current_cpu = cpu;
251 return smp_processor_id();
255 static void octeon_irq_ciu_enable(struct irq_data *data)
257 int cpu = next_cpu_for_irq(data);
258 int coreid = octeon_coreid_for_cpu(cpu);
261 struct octeon_ciu_chip_data *cd;
262 raw_spinlock_t *lock = &per_cpu(octeon_irq_ciu_spinlock, cpu);
264 cd = irq_data_get_irq_chip_data(data);
266 raw_spin_lock_irqsave(lock, flags);
268 pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
269 __set_bit(cd->bit, pen);
271 * Must be visible to octeon_irq_ip{2,3}_ciu() before
275 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
277 pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
278 __set_bit(cd->bit, pen);
280 * Must be visible to octeon_irq_ip{2,3}_ciu() before
284 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
286 raw_spin_unlock_irqrestore(lock, flags);
289 static void octeon_irq_ciu_enable_local(struct irq_data *data)
293 struct octeon_ciu_chip_data *cd;
294 raw_spinlock_t *lock = this_cpu_ptr(&octeon_irq_ciu_spinlock);
296 cd = irq_data_get_irq_chip_data(data);
298 raw_spin_lock_irqsave(lock, flags);
300 pen = this_cpu_ptr(&octeon_irq_ciu0_en_mirror);
301 __set_bit(cd->bit, pen);
303 * Must be visible to octeon_irq_ip{2,3}_ciu() before
307 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen);
309 pen = this_cpu_ptr(&octeon_irq_ciu1_en_mirror);
310 __set_bit(cd->bit, pen);
312 * Must be visible to octeon_irq_ip{2,3}_ciu() before
316 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen);
318 raw_spin_unlock_irqrestore(lock, flags);
321 static void octeon_irq_ciu_disable_local(struct irq_data *data)
325 struct octeon_ciu_chip_data *cd;
326 raw_spinlock_t *lock = this_cpu_ptr(&octeon_irq_ciu_spinlock);
328 cd = irq_data_get_irq_chip_data(data);
330 raw_spin_lock_irqsave(lock, flags);
332 pen = this_cpu_ptr(&octeon_irq_ciu0_en_mirror);
333 __clear_bit(cd->bit, pen);
335 * Must be visible to octeon_irq_ip{2,3}_ciu() before
339 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen);
341 pen = this_cpu_ptr(&octeon_irq_ciu1_en_mirror);
342 __clear_bit(cd->bit, pen);
344 * Must be visible to octeon_irq_ip{2,3}_ciu() before
348 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen);
350 raw_spin_unlock_irqrestore(lock, flags);
353 static void octeon_irq_ciu_disable_all(struct irq_data *data)
358 struct octeon_ciu_chip_data *cd;
359 raw_spinlock_t *lock;
361 cd = irq_data_get_irq_chip_data(data);
363 for_each_online_cpu(cpu) {
364 int coreid = octeon_coreid_for_cpu(cpu);
365 lock = &per_cpu(octeon_irq_ciu_spinlock, cpu);
367 pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
369 pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
371 raw_spin_lock_irqsave(lock, flags);
372 __clear_bit(cd->bit, pen);
374 * Must be visible to octeon_irq_ip{2,3}_ciu() before
379 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
381 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
382 raw_spin_unlock_irqrestore(lock, flags);
386 static void octeon_irq_ciu_enable_all(struct irq_data *data)
391 struct octeon_ciu_chip_data *cd;
392 raw_spinlock_t *lock;
394 cd = irq_data_get_irq_chip_data(data);
396 for_each_online_cpu(cpu) {
397 int coreid = octeon_coreid_for_cpu(cpu);
398 lock = &per_cpu(octeon_irq_ciu_spinlock, cpu);
400 pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
402 pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
404 raw_spin_lock_irqsave(lock, flags);
405 __set_bit(cd->bit, pen);
407 * Must be visible to octeon_irq_ip{2,3}_ciu() before
412 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
414 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
415 raw_spin_unlock_irqrestore(lock, flags);
420 * Enable the irq on the next core in the affinity set for chips that
421 * have the EN*_W1{S,C} registers.
423 static void octeon_irq_ciu_enable_v2(struct irq_data *data)
426 int cpu = next_cpu_for_irq(data);
427 struct octeon_ciu_chip_data *cd;
429 cd = irq_data_get_irq_chip_data(data);
430 mask = 1ull << (cd->bit);
433 * Called under the desc lock, so these should never get out
437 int index = octeon_coreid_for_cpu(cpu) * 2;
438 set_bit(cd->bit, &per_cpu(octeon_irq_ciu0_en_mirror, cpu));
439 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
441 int index = octeon_coreid_for_cpu(cpu) * 2 + 1;
442 set_bit(cd->bit, &per_cpu(octeon_irq_ciu1_en_mirror, cpu));
443 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
448 * Enable the irq in the sum2 registers.
450 static void octeon_irq_ciu_enable_sum2(struct irq_data *data)
453 int cpu = next_cpu_for_irq(data);
454 int index = octeon_coreid_for_cpu(cpu);
455 struct octeon_ciu_chip_data *cd;
457 cd = irq_data_get_irq_chip_data(data);
458 mask = 1ull << (cd->bit);
460 cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1S(index), mask);
464 * Disable the irq in the sum2 registers.
466 static void octeon_irq_ciu_disable_local_sum2(struct irq_data *data)
469 int cpu = next_cpu_for_irq(data);
470 int index = octeon_coreid_for_cpu(cpu);
471 struct octeon_ciu_chip_data *cd;
473 cd = irq_data_get_irq_chip_data(data);
474 mask = 1ull << (cd->bit);
476 cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1C(index), mask);
479 static void octeon_irq_ciu_ack_sum2(struct irq_data *data)
482 int cpu = next_cpu_for_irq(data);
483 int index = octeon_coreid_for_cpu(cpu);
484 struct octeon_ciu_chip_data *cd;
486 cd = irq_data_get_irq_chip_data(data);
487 mask = 1ull << (cd->bit);
489 cvmx_write_csr(CVMX_CIU_SUM2_PPX_IP4(index), mask);
492 static void octeon_irq_ciu_disable_all_sum2(struct irq_data *data)
495 struct octeon_ciu_chip_data *cd;
498 cd = irq_data_get_irq_chip_data(data);
499 mask = 1ull << (cd->bit);
501 for_each_online_cpu(cpu) {
502 int coreid = octeon_coreid_for_cpu(cpu);
504 cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1C(coreid), mask);
509 * Enable the irq on the current CPU for chips that
510 * have the EN*_W1{S,C} registers.
512 static void octeon_irq_ciu_enable_local_v2(struct irq_data *data)
515 struct octeon_ciu_chip_data *cd;
517 cd = irq_data_get_irq_chip_data(data);
518 mask = 1ull << (cd->bit);
521 int index = cvmx_get_core_num() * 2;
522 set_bit(cd->bit, this_cpu_ptr(&octeon_irq_ciu0_en_mirror));
523 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
525 int index = cvmx_get_core_num() * 2 + 1;
526 set_bit(cd->bit, this_cpu_ptr(&octeon_irq_ciu1_en_mirror));
527 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
531 static void octeon_irq_ciu_disable_local_v2(struct irq_data *data)
534 struct octeon_ciu_chip_data *cd;
536 cd = irq_data_get_irq_chip_data(data);
537 mask = 1ull << (cd->bit);
540 int index = cvmx_get_core_num() * 2;
541 clear_bit(cd->bit, this_cpu_ptr(&octeon_irq_ciu0_en_mirror));
542 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
544 int index = cvmx_get_core_num() * 2 + 1;
545 clear_bit(cd->bit, this_cpu_ptr(&octeon_irq_ciu1_en_mirror));
546 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
551 * Write to the W1C bit in CVMX_CIU_INTX_SUM0 to clear the irq.
553 static void octeon_irq_ciu_ack(struct irq_data *data)
556 struct octeon_ciu_chip_data *cd;
558 cd = irq_data_get_irq_chip_data(data);
559 mask = 1ull << (cd->bit);
562 int index = cvmx_get_core_num() * 2;
563 cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask);
565 cvmx_write_csr(CVMX_CIU_INT_SUM1, mask);
570 * Disable the irq on the all cores for chips that have the EN*_W1{S,C}
573 static void octeon_irq_ciu_disable_all_v2(struct irq_data *data)
577 struct octeon_ciu_chip_data *cd;
579 cd = irq_data_get_irq_chip_data(data);
580 mask = 1ull << (cd->bit);
583 for_each_online_cpu(cpu) {
584 int index = octeon_coreid_for_cpu(cpu) * 2;
586 &per_cpu(octeon_irq_ciu0_en_mirror, cpu));
587 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
590 for_each_online_cpu(cpu) {
591 int index = octeon_coreid_for_cpu(cpu) * 2 + 1;
593 &per_cpu(octeon_irq_ciu1_en_mirror, cpu));
594 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
600 * Enable the irq on the all cores for chips that have the EN*_W1{S,C}
603 static void octeon_irq_ciu_enable_all_v2(struct irq_data *data)
607 struct octeon_ciu_chip_data *cd;
609 cd = irq_data_get_irq_chip_data(data);
610 mask = 1ull << (cd->bit);
613 for_each_online_cpu(cpu) {
614 int index = octeon_coreid_for_cpu(cpu) * 2;
616 &per_cpu(octeon_irq_ciu0_en_mirror, cpu));
617 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
620 for_each_online_cpu(cpu) {
621 int index = octeon_coreid_for_cpu(cpu) * 2 + 1;
623 &per_cpu(octeon_irq_ciu1_en_mirror, cpu));
624 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
629 static void octeon_irq_gpio_setup(struct irq_data *data)
631 union cvmx_gpio_bit_cfgx cfg;
632 struct octeon_ciu_chip_data *cd;
633 u32 t = irqd_get_trigger_type(data);
635 cd = irq_data_get_irq_chip_data(data);
639 cfg.s.int_type = (t & IRQ_TYPE_EDGE_BOTH) != 0;
640 cfg.s.rx_xor = (t & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) != 0;
642 /* 140 nS glitch filter*/
646 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd->gpio_line), cfg.u64);
649 static void octeon_irq_ciu_enable_gpio_v2(struct irq_data *data)
651 octeon_irq_gpio_setup(data);
652 octeon_irq_ciu_enable_v2(data);
655 static void octeon_irq_ciu_enable_gpio(struct irq_data *data)
657 octeon_irq_gpio_setup(data);
658 octeon_irq_ciu_enable(data);
661 static int octeon_irq_ciu_gpio_set_type(struct irq_data *data, unsigned int t)
663 irqd_set_trigger_type(data, t);
664 octeon_irq_gpio_setup(data);
666 if (irqd_get_trigger_type(data) & IRQ_TYPE_EDGE_BOTH)
667 irq_set_handler_locked(data, handle_edge_irq);
669 irq_set_handler_locked(data, handle_level_irq);
671 return IRQ_SET_MASK_OK;
674 static void octeon_irq_ciu_disable_gpio_v2(struct irq_data *data)
676 struct octeon_ciu_chip_data *cd;
678 cd = irq_data_get_irq_chip_data(data);
679 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd->gpio_line), 0);
681 octeon_irq_ciu_disable_all_v2(data);
684 static void octeon_irq_ciu_disable_gpio(struct irq_data *data)
686 struct octeon_ciu_chip_data *cd;
688 cd = irq_data_get_irq_chip_data(data);
689 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd->gpio_line), 0);
691 octeon_irq_ciu_disable_all(data);
694 static void octeon_irq_ciu_gpio_ack(struct irq_data *data)
696 struct octeon_ciu_chip_data *cd;
699 cd = irq_data_get_irq_chip_data(data);
700 mask = 1ull << (cd->gpio_line);
702 cvmx_write_csr(CVMX_GPIO_INT_CLR, mask);
707 static void octeon_irq_cpu_offline_ciu(struct irq_data *data)
709 int cpu = smp_processor_id();
710 cpumask_t new_affinity;
711 struct cpumask *mask = irq_data_get_affinity_mask(data);
713 if (!cpumask_test_cpu(cpu, mask))
716 if (cpumask_weight(mask) > 1) {
718 * It has multi CPU affinity, just remove this CPU
719 * from the affinity set.
721 cpumask_copy(&new_affinity, mask);
722 cpumask_clear_cpu(cpu, &new_affinity);
724 /* Otherwise, put it on lowest numbered online CPU. */
725 cpumask_clear(&new_affinity);
726 cpumask_set_cpu(cpumask_first(cpu_online_mask), &new_affinity);
728 irq_set_affinity_locked(data, &new_affinity, false);
731 static int octeon_irq_ciu_set_affinity(struct irq_data *data,
732 const struct cpumask *dest, bool force)
735 bool enable_one = !irqd_irq_disabled(data) && !irqd_irq_masked(data);
737 struct octeon_ciu_chip_data *cd;
739 raw_spinlock_t *lock;
741 cd = irq_data_get_irq_chip_data(data);
744 * For non-v2 CIU, we will allow only single CPU affinity.
745 * This removes the need to do locking in the .ack/.eoi
748 if (cpumask_weight(dest) != 1)
755 for_each_online_cpu(cpu) {
756 int coreid = octeon_coreid_for_cpu(cpu);
758 lock = &per_cpu(octeon_irq_ciu_spinlock, cpu);
759 raw_spin_lock_irqsave(lock, flags);
762 pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
764 pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
766 if (cpumask_test_cpu(cpu, dest) && enable_one) {
768 __set_bit(cd->bit, pen);
770 __clear_bit(cd->bit, pen);
773 * Must be visible to octeon_irq_ip{2,3}_ciu() before
779 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
781 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
783 raw_spin_unlock_irqrestore(lock, flags);
789 * Set affinity for the irq for chips that have the EN*_W1{S,C}
792 static int octeon_irq_ciu_set_affinity_v2(struct irq_data *data,
793 const struct cpumask *dest,
797 bool enable_one = !irqd_irq_disabled(data) && !irqd_irq_masked(data);
799 struct octeon_ciu_chip_data *cd;
804 cd = irq_data_get_irq_chip_data(data);
805 mask = 1ull << cd->bit;
808 for_each_online_cpu(cpu) {
809 unsigned long *pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
810 int index = octeon_coreid_for_cpu(cpu) * 2;
811 if (cpumask_test_cpu(cpu, dest) && enable_one) {
813 set_bit(cd->bit, pen);
814 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
816 clear_bit(cd->bit, pen);
817 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
821 for_each_online_cpu(cpu) {
822 unsigned long *pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
823 int index = octeon_coreid_for_cpu(cpu) * 2 + 1;
824 if (cpumask_test_cpu(cpu, dest) && enable_one) {
826 set_bit(cd->bit, pen);
827 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
829 clear_bit(cd->bit, pen);
830 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
837 static int octeon_irq_ciu_set_affinity_sum2(struct irq_data *data,
838 const struct cpumask *dest,
842 bool enable_one = !irqd_irq_disabled(data) && !irqd_irq_masked(data);
844 struct octeon_ciu_chip_data *cd;
849 cd = irq_data_get_irq_chip_data(data);
850 mask = 1ull << cd->bit;
852 for_each_online_cpu(cpu) {
853 int index = octeon_coreid_for_cpu(cpu);
855 if (cpumask_test_cpu(cpu, dest) && enable_one) {
857 cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1S(index), mask);
859 cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1C(index), mask);
867 * Newer octeon chips have support for lockless CIU operation.
869 static struct irq_chip octeon_irq_chip_ciu_v2 = {
871 .irq_enable = octeon_irq_ciu_enable_v2,
872 .irq_disable = octeon_irq_ciu_disable_all_v2,
873 .irq_mask = octeon_irq_ciu_disable_local_v2,
874 .irq_unmask = octeon_irq_ciu_enable_v2,
876 .irq_set_affinity = octeon_irq_ciu_set_affinity_v2,
877 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
881 static struct irq_chip octeon_irq_chip_ciu_v2_edge = {
883 .irq_enable = octeon_irq_ciu_enable_v2,
884 .irq_disable = octeon_irq_ciu_disable_all_v2,
885 .irq_ack = octeon_irq_ciu_ack,
886 .irq_mask = octeon_irq_ciu_disable_local_v2,
887 .irq_unmask = octeon_irq_ciu_enable_v2,
889 .irq_set_affinity = octeon_irq_ciu_set_affinity_v2,
890 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
895 * Newer octeon chips have support for lockless CIU operation.
897 static struct irq_chip octeon_irq_chip_ciu_sum2 = {
899 .irq_enable = octeon_irq_ciu_enable_sum2,
900 .irq_disable = octeon_irq_ciu_disable_all_sum2,
901 .irq_mask = octeon_irq_ciu_disable_local_sum2,
902 .irq_unmask = octeon_irq_ciu_enable_sum2,
904 .irq_set_affinity = octeon_irq_ciu_set_affinity_sum2,
905 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
909 static struct irq_chip octeon_irq_chip_ciu_sum2_edge = {
911 .irq_enable = octeon_irq_ciu_enable_sum2,
912 .irq_disable = octeon_irq_ciu_disable_all_sum2,
913 .irq_ack = octeon_irq_ciu_ack_sum2,
914 .irq_mask = octeon_irq_ciu_disable_local_sum2,
915 .irq_unmask = octeon_irq_ciu_enable_sum2,
917 .irq_set_affinity = octeon_irq_ciu_set_affinity_sum2,
918 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
922 static struct irq_chip octeon_irq_chip_ciu = {
924 .irq_enable = octeon_irq_ciu_enable,
925 .irq_disable = octeon_irq_ciu_disable_all,
926 .irq_mask = octeon_irq_ciu_disable_local,
927 .irq_unmask = octeon_irq_ciu_enable,
929 .irq_set_affinity = octeon_irq_ciu_set_affinity,
930 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
934 static struct irq_chip octeon_irq_chip_ciu_edge = {
936 .irq_enable = octeon_irq_ciu_enable,
937 .irq_disable = octeon_irq_ciu_disable_all,
938 .irq_ack = octeon_irq_ciu_ack,
939 .irq_mask = octeon_irq_ciu_disable_local,
940 .irq_unmask = octeon_irq_ciu_enable,
942 .irq_set_affinity = octeon_irq_ciu_set_affinity,
943 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
947 /* The mbox versions don't do any affinity or round-robin. */
948 static struct irq_chip octeon_irq_chip_ciu_mbox_v2 = {
950 .irq_enable = octeon_irq_ciu_enable_all_v2,
951 .irq_disable = octeon_irq_ciu_disable_all_v2,
952 .irq_ack = octeon_irq_ciu_disable_local_v2,
953 .irq_eoi = octeon_irq_ciu_enable_local_v2,
955 .irq_cpu_online = octeon_irq_ciu_enable_local_v2,
956 .irq_cpu_offline = octeon_irq_ciu_disable_local_v2,
957 .flags = IRQCHIP_ONOFFLINE_ENABLED,
960 static struct irq_chip octeon_irq_chip_ciu_mbox = {
962 .irq_enable = octeon_irq_ciu_enable_all,
963 .irq_disable = octeon_irq_ciu_disable_all,
964 .irq_ack = octeon_irq_ciu_disable_local,
965 .irq_eoi = octeon_irq_ciu_enable_local,
967 .irq_cpu_online = octeon_irq_ciu_enable_local,
968 .irq_cpu_offline = octeon_irq_ciu_disable_local,
969 .flags = IRQCHIP_ONOFFLINE_ENABLED,
972 static struct irq_chip octeon_irq_chip_ciu_gpio_v2 = {
974 .irq_enable = octeon_irq_ciu_enable_gpio_v2,
975 .irq_disable = octeon_irq_ciu_disable_gpio_v2,
976 .irq_ack = octeon_irq_ciu_gpio_ack,
977 .irq_mask = octeon_irq_ciu_disable_local_v2,
978 .irq_unmask = octeon_irq_ciu_enable_v2,
979 .irq_set_type = octeon_irq_ciu_gpio_set_type,
981 .irq_set_affinity = octeon_irq_ciu_set_affinity_v2,
982 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
984 .flags = IRQCHIP_SET_TYPE_MASKED,
987 static struct irq_chip octeon_irq_chip_ciu_gpio = {
989 .irq_enable = octeon_irq_ciu_enable_gpio,
990 .irq_disable = octeon_irq_ciu_disable_gpio,
991 .irq_mask = octeon_irq_ciu_disable_local,
992 .irq_unmask = octeon_irq_ciu_enable,
993 .irq_ack = octeon_irq_ciu_gpio_ack,
994 .irq_set_type = octeon_irq_ciu_gpio_set_type,
996 .irq_set_affinity = octeon_irq_ciu_set_affinity,
997 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
999 .flags = IRQCHIP_SET_TYPE_MASKED,
1003 * Watchdog interrupts are special. They are associated with a single
1004 * core, so we hardwire the affinity to that core.
1006 static void octeon_irq_ciu_wd_enable(struct irq_data *data)
1008 unsigned long flags;
1010 int coreid = data->irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
1011 int cpu = octeon_cpu_for_coreid(coreid);
1012 raw_spinlock_t *lock = &per_cpu(octeon_irq_ciu_spinlock, cpu);
1014 raw_spin_lock_irqsave(lock, flags);
1015 pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
1016 __set_bit(coreid, pen);
1018 * Must be visible to octeon_irq_ip{2,3}_ciu() before enabling
1022 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
1023 raw_spin_unlock_irqrestore(lock, flags);
1027 * Watchdog interrupts are special. They are associated with a single
1028 * core, so we hardwire the affinity to that core.
1030 static void octeon_irq_ciu1_wd_enable_v2(struct irq_data *data)
1032 int coreid = data->irq - OCTEON_IRQ_WDOG0;
1033 int cpu = octeon_cpu_for_coreid(coreid);
1035 set_bit(coreid, &per_cpu(octeon_irq_ciu1_en_mirror, cpu));
1036 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(coreid * 2 + 1), 1ull << coreid);
1040 static struct irq_chip octeon_irq_chip_ciu_wd_v2 = {
1042 .irq_enable = octeon_irq_ciu1_wd_enable_v2,
1043 .irq_disable = octeon_irq_ciu_disable_all_v2,
1044 .irq_mask = octeon_irq_ciu_disable_local_v2,
1045 .irq_unmask = octeon_irq_ciu_enable_local_v2,
1048 static struct irq_chip octeon_irq_chip_ciu_wd = {
1050 .irq_enable = octeon_irq_ciu_wd_enable,
1051 .irq_disable = octeon_irq_ciu_disable_all,
1052 .irq_mask = octeon_irq_ciu_disable_local,
1053 .irq_unmask = octeon_irq_ciu_enable_local,
1056 static bool octeon_irq_ciu_is_edge(unsigned int line, unsigned int bit)
1062 case 48 ... 49: /* GMX DRP */
1063 case 50: /* IPD_DRP */
1064 case 52 ... 55: /* Timers */
1071 else /* line == 1 */
1082 struct octeon_irq_gpio_domain_data {
1083 unsigned int base_hwirq;
1086 static int octeon_irq_gpio_xlat(struct irq_domain *d,
1087 struct device_node *node,
1089 unsigned int intsize,
1090 unsigned long *out_hwirq,
1091 unsigned int *out_type)
1095 unsigned int trigger;
1097 if (irq_domain_get_of_node(d) != node)
1107 trigger = intspec[1];
1111 type = IRQ_TYPE_EDGE_RISING;
1114 type = IRQ_TYPE_EDGE_FALLING;
1117 type = IRQ_TYPE_LEVEL_HIGH;
1120 type = IRQ_TYPE_LEVEL_LOW;
1123 pr_err("Error: (%s) Invalid irq trigger specification: %x\n",
1126 type = IRQ_TYPE_LEVEL_LOW;
1135 static int octeon_irq_ciu_xlat(struct irq_domain *d,
1136 struct device_node *node,
1138 unsigned int intsize,
1139 unsigned long *out_hwirq,
1140 unsigned int *out_type)
1142 unsigned int ciu, bit;
1143 struct octeon_irq_ciu_domain_data *dd = d->host_data;
1148 if (ciu >= dd->num_sum || bit > 63)
1151 *out_hwirq = (ciu << 6) | bit;
1157 static struct irq_chip *octeon_irq_ciu_chip;
1158 static struct irq_chip *octeon_irq_ciu_chip_edge;
1159 static struct irq_chip *octeon_irq_gpio_chip;
1161 static int octeon_irq_ciu_map(struct irq_domain *d,
1162 unsigned int virq, irq_hw_number_t hw)
1165 unsigned int line = hw >> 6;
1166 unsigned int bit = hw & 63;
1167 struct octeon_irq_ciu_domain_data *dd = d->host_data;
1169 if (line >= dd->num_sum || octeon_irq_ciu_to_irq[line][bit] != 0)
1173 if (octeon_irq_ciu_is_edge(line, bit))
1174 rv = octeon_irq_set_ciu_mapping(virq, line, bit, 0,
1175 &octeon_irq_chip_ciu_sum2_edge,
1178 rv = octeon_irq_set_ciu_mapping(virq, line, bit, 0,
1179 &octeon_irq_chip_ciu_sum2,
1182 if (octeon_irq_ciu_is_edge(line, bit))
1183 rv = octeon_irq_set_ciu_mapping(virq, line, bit, 0,
1184 octeon_irq_ciu_chip_edge,
1187 rv = octeon_irq_set_ciu_mapping(virq, line, bit, 0,
1188 octeon_irq_ciu_chip,
1194 static int octeon_irq_gpio_map(struct irq_domain *d,
1195 unsigned int virq, irq_hw_number_t hw)
1197 struct octeon_irq_gpio_domain_data *gpiod = d->host_data;
1198 unsigned int line, bit;
1201 line = (hw + gpiod->base_hwirq) >> 6;
1202 bit = (hw + gpiod->base_hwirq) & 63;
1203 if (line > ARRAY_SIZE(octeon_irq_ciu_to_irq) ||
1204 octeon_irq_ciu_to_irq[line][bit] != 0)
1208 * Default to handle_level_irq. If the DT contains a different
1209 * trigger type, it will call the irq_set_type callback and
1210 * the handler gets updated.
1212 r = octeon_irq_set_ciu_mapping(virq, line, bit, hw,
1213 octeon_irq_gpio_chip, handle_level_irq);
1217 static struct irq_domain_ops octeon_irq_domain_ciu_ops = {
1218 .map = octeon_irq_ciu_map,
1219 .unmap = octeon_irq_free_cd,
1220 .xlate = octeon_irq_ciu_xlat,
1223 static struct irq_domain_ops octeon_irq_domain_gpio_ops = {
1224 .map = octeon_irq_gpio_map,
1225 .unmap = octeon_irq_free_cd,
1226 .xlate = octeon_irq_gpio_xlat,
1229 static void octeon_irq_ip2_ciu(void)
1231 const unsigned long core_id = cvmx_get_core_num();
1232 u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INTX_SUM0(core_id * 2));
1234 ciu_sum &= __this_cpu_read(octeon_irq_ciu0_en_mirror);
1235 if (likely(ciu_sum)) {
1236 int bit = fls64(ciu_sum) - 1;
1237 int irq = octeon_irq_ciu_to_irq[0][bit];
1241 spurious_interrupt();
1243 spurious_interrupt();
1247 static void octeon_irq_ip3_ciu(void)
1249 u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INT_SUM1);
1251 ciu_sum &= __this_cpu_read(octeon_irq_ciu1_en_mirror);
1252 if (likely(ciu_sum)) {
1253 int bit = fls64(ciu_sum) - 1;
1254 int irq = octeon_irq_ciu_to_irq[1][bit];
1258 spurious_interrupt();
1260 spurious_interrupt();
1264 static void octeon_irq_ip4_ciu(void)
1266 int coreid = cvmx_get_core_num();
1267 u64 ciu_sum = cvmx_read_csr(CVMX_CIU_SUM2_PPX_IP4(coreid));
1268 u64 ciu_en = cvmx_read_csr(CVMX_CIU_EN2_PPX_IP4(coreid));
1271 if (likely(ciu_sum)) {
1272 int bit = fls64(ciu_sum) - 1;
1273 int irq = octeon_irq_ciu_to_irq[2][bit];
1278 spurious_interrupt();
1280 spurious_interrupt();
1284 static bool octeon_irq_use_ip4;
1286 static void octeon_irq_local_enable_ip4(void *arg)
1288 set_c0_status(STATUSF_IP4);
1291 static void octeon_irq_ip4_mask(void)
1293 clear_c0_status(STATUSF_IP4);
1294 spurious_interrupt();
1297 static void (*octeon_irq_ip2)(void);
1298 static void (*octeon_irq_ip3)(void);
1299 static void (*octeon_irq_ip4)(void);
1301 void (*octeon_irq_setup_secondary)(void);
1303 void octeon_irq_set_ip4_handler(octeon_irq_ip4_handler_t h)
1306 octeon_irq_use_ip4 = true;
1307 on_each_cpu(octeon_irq_local_enable_ip4, NULL, 1);
1310 static void octeon_irq_percpu_enable(void)
1315 static void octeon_irq_init_ciu_percpu(void)
1317 int coreid = cvmx_get_core_num();
1320 __this_cpu_write(octeon_irq_ciu0_en_mirror, 0);
1321 __this_cpu_write(octeon_irq_ciu1_en_mirror, 0);
1323 raw_spin_lock_init(this_cpu_ptr(&octeon_irq_ciu_spinlock));
1325 * Disable All CIU Interrupts. The ones we need will be
1326 * enabled later. Read the SUM register so we know the write
1329 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), 0);
1330 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0);
1331 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0);
1332 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0);
1333 cvmx_read_csr(CVMX_CIU_INTX_SUM0((coreid * 2)));
1336 static void octeon_irq_init_ciu2_percpu(void)
1339 int coreid = cvmx_get_core_num();
1340 u64 base = CVMX_CIU2_EN_PPX_IP2_WRKQ(coreid);
1343 * Disable All CIU2 Interrupts. The ones we need will be
1344 * enabled later. Read the SUM register so we know the write
1347 * There are 9 registers and 3 IPX levels with strides 0x1000
1348 * and 0x200 respectivly. Use loops to clear them.
1350 for (regx = 0; regx <= 0x8000; regx += 0x1000) {
1351 for (ipx = 0; ipx <= 0x400; ipx += 0x200)
1352 cvmx_write_csr(base + regx + ipx, 0);
1355 cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(coreid));
1358 static void octeon_irq_setup_secondary_ciu(void)
1360 octeon_irq_init_ciu_percpu();
1361 octeon_irq_percpu_enable();
1363 /* Enable the CIU lines */
1364 set_c0_status(STATUSF_IP3 | STATUSF_IP2);
1365 if (octeon_irq_use_ip4)
1366 set_c0_status(STATUSF_IP4);
1368 clear_c0_status(STATUSF_IP4);
1371 static void octeon_irq_setup_secondary_ciu2(void)
1373 octeon_irq_init_ciu2_percpu();
1374 octeon_irq_percpu_enable();
1376 /* Enable the CIU lines */
1377 set_c0_status(STATUSF_IP3 | STATUSF_IP2);
1378 if (octeon_irq_use_ip4)
1379 set_c0_status(STATUSF_IP4);
1381 clear_c0_status(STATUSF_IP4);
1384 static int __init octeon_irq_init_ciu(
1385 struct device_node *ciu_node, struct device_node *parent)
1388 struct irq_chip *chip;
1389 struct irq_chip *chip_edge;
1390 struct irq_chip *chip_mbox;
1391 struct irq_chip *chip_wd;
1392 struct irq_domain *ciu_domain = NULL;
1393 struct octeon_irq_ciu_domain_data *dd;
1395 dd = kzalloc(sizeof(*dd), GFP_KERNEL);
1399 octeon_irq_init_ciu_percpu();
1400 octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu;
1402 octeon_irq_ip2 = octeon_irq_ip2_ciu;
1403 octeon_irq_ip3 = octeon_irq_ip3_ciu;
1404 if ((OCTEON_IS_OCTEON2() || OCTEON_IS_OCTEON3())
1405 && !OCTEON_IS_MODEL(OCTEON_CN63XX)) {
1406 octeon_irq_ip4 = octeon_irq_ip4_ciu;
1408 octeon_irq_use_ip4 = true;
1410 octeon_irq_ip4 = octeon_irq_ip4_mask;
1412 octeon_irq_use_ip4 = false;
1414 if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS2_X) ||
1415 OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) ||
1416 OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X) ||
1417 OCTEON_IS_OCTEON2() || OCTEON_IS_OCTEON3()) {
1418 chip = &octeon_irq_chip_ciu_v2;
1419 chip_edge = &octeon_irq_chip_ciu_v2_edge;
1420 chip_mbox = &octeon_irq_chip_ciu_mbox_v2;
1421 chip_wd = &octeon_irq_chip_ciu_wd_v2;
1422 octeon_irq_gpio_chip = &octeon_irq_chip_ciu_gpio_v2;
1424 chip = &octeon_irq_chip_ciu;
1425 chip_edge = &octeon_irq_chip_ciu_edge;
1426 chip_mbox = &octeon_irq_chip_ciu_mbox;
1427 chip_wd = &octeon_irq_chip_ciu_wd;
1428 octeon_irq_gpio_chip = &octeon_irq_chip_ciu_gpio;
1430 octeon_irq_ciu_chip = chip;
1431 octeon_irq_ciu_chip_edge = chip_edge;
1434 octeon_irq_init_core();
1436 ciu_domain = irq_domain_add_tree(
1437 ciu_node, &octeon_irq_domain_ciu_ops, dd);
1438 irq_set_default_host(ciu_domain);
1441 for (i = 0; i < 16; i++) {
1442 r = octeon_irq_force_ciu_mapping(
1443 ciu_domain, i + OCTEON_IRQ_WORKQ0, 0, i + 0);
1448 r = octeon_irq_set_ciu_mapping(
1449 OCTEON_IRQ_MBOX0, 0, 32, 0, chip_mbox, handle_percpu_irq);
1452 r = octeon_irq_set_ciu_mapping(
1453 OCTEON_IRQ_MBOX1, 0, 33, 0, chip_mbox, handle_percpu_irq);
1457 for (i = 0; i < 4; i++) {
1458 r = octeon_irq_force_ciu_mapping(
1459 ciu_domain, i + OCTEON_IRQ_PCI_INT0, 0, i + 36);
1463 for (i = 0; i < 4; i++) {
1464 r = octeon_irq_force_ciu_mapping(
1465 ciu_domain, i + OCTEON_IRQ_PCI_MSI0, 0, i + 40);
1470 r = octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_TWSI, 0, 45);
1474 r = octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_RML, 0, 46);
1478 for (i = 0; i < 4; i++) {
1479 r = octeon_irq_force_ciu_mapping(
1480 ciu_domain, i + OCTEON_IRQ_TIMER0, 0, i + 52);
1485 r = octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_USB0, 0, 56);
1489 r = octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_TWSI2, 0, 59);
1494 for (i = 0; i < 16; i++) {
1495 r = octeon_irq_set_ciu_mapping(
1496 i + OCTEON_IRQ_WDOG0, 1, i + 0, 0, chip_wd,
1502 r = octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_USB1, 1, 17);
1506 /* Enable the CIU lines */
1507 set_c0_status(STATUSF_IP3 | STATUSF_IP2);
1508 if (octeon_irq_use_ip4)
1509 set_c0_status(STATUSF_IP4);
1511 clear_c0_status(STATUSF_IP4);
1518 static int __init octeon_irq_init_gpio(
1519 struct device_node *gpio_node, struct device_node *parent)
1521 struct octeon_irq_gpio_domain_data *gpiod;
1522 u32 interrupt_cells;
1523 unsigned int base_hwirq;
1526 r = of_property_read_u32(parent, "#interrupt-cells", &interrupt_cells);
1530 if (interrupt_cells == 1) {
1533 r = of_property_read_u32_index(gpio_node, "interrupts", 0, &v);
1535 pr_warn("No \"interrupts\" property.\n");
1539 } else if (interrupt_cells == 2) {
1542 r = of_property_read_u32_index(gpio_node, "interrupts", 0, &v0);
1544 pr_warn("No \"interrupts\" property.\n");
1547 r = of_property_read_u32_index(gpio_node, "interrupts", 1, &v1);
1549 pr_warn("No \"interrupts\" property.\n");
1552 base_hwirq = (v0 << 6) | v1;
1554 pr_warn("Bad \"#interrupt-cells\" property: %u\n",
1559 gpiod = kzalloc(sizeof(*gpiod), GFP_KERNEL);
1561 /* gpio domain host_data is the base hwirq number. */
1562 gpiod->base_hwirq = base_hwirq;
1563 irq_domain_add_linear(
1564 gpio_node, 16, &octeon_irq_domain_gpio_ops, gpiod);
1566 pr_warn("Cannot allocate memory for GPIO irq_domain.\n");
1573 * Watchdog interrupts are special. They are associated with a single
1574 * core, so we hardwire the affinity to that core.
1576 static void octeon_irq_ciu2_wd_enable(struct irq_data *data)
1580 int coreid = data->irq - OCTEON_IRQ_WDOG0;
1581 struct octeon_ciu_chip_data *cd;
1583 cd = irq_data_get_irq_chip_data(data);
1584 mask = 1ull << (cd->bit);
1586 en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(coreid) +
1587 (0x1000ull * cd->line);
1588 cvmx_write_csr(en_addr, mask);
1592 static void octeon_irq_ciu2_enable(struct irq_data *data)
1596 int cpu = next_cpu_for_irq(data);
1597 int coreid = octeon_coreid_for_cpu(cpu);
1598 struct octeon_ciu_chip_data *cd;
1600 cd = irq_data_get_irq_chip_data(data);
1601 mask = 1ull << (cd->bit);
1603 en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(coreid) +
1604 (0x1000ull * cd->line);
1605 cvmx_write_csr(en_addr, mask);
1608 static void octeon_irq_ciu2_enable_local(struct irq_data *data)
1612 int coreid = cvmx_get_core_num();
1613 struct octeon_ciu_chip_data *cd;
1615 cd = irq_data_get_irq_chip_data(data);
1616 mask = 1ull << (cd->bit);
1618 en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(coreid) +
1619 (0x1000ull * cd->line);
1620 cvmx_write_csr(en_addr, mask);
1624 static void octeon_irq_ciu2_disable_local(struct irq_data *data)
1628 int coreid = cvmx_get_core_num();
1629 struct octeon_ciu_chip_data *cd;
1631 cd = irq_data_get_irq_chip_data(data);
1632 mask = 1ull << (cd->bit);
1634 en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(coreid) +
1635 (0x1000ull * cd->line);
1636 cvmx_write_csr(en_addr, mask);
1640 static void octeon_irq_ciu2_ack(struct irq_data *data)
1644 int coreid = cvmx_get_core_num();
1645 struct octeon_ciu_chip_data *cd;
1647 cd = irq_data_get_irq_chip_data(data);
1648 mask = 1ull << (cd->bit);
1650 en_addr = CVMX_CIU2_RAW_PPX_IP2_WRKQ(coreid) + (0x1000ull * cd->line);
1651 cvmx_write_csr(en_addr, mask);
1655 static void octeon_irq_ciu2_disable_all(struct irq_data *data)
1659 struct octeon_ciu_chip_data *cd;
1661 cd = irq_data_get_irq_chip_data(data);
1662 mask = 1ull << (cd->bit);
1664 for_each_online_cpu(cpu) {
1665 u64 en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(
1666 octeon_coreid_for_cpu(cpu)) + (0x1000ull * cd->line);
1667 cvmx_write_csr(en_addr, mask);
1671 static void octeon_irq_ciu2_mbox_enable_all(struct irq_data *data)
1676 mask = 1ull << (data->irq - OCTEON_IRQ_MBOX0);
1678 for_each_online_cpu(cpu) {
1679 u64 en_addr = CVMX_CIU2_EN_PPX_IP3_MBOX_W1S(
1680 octeon_coreid_for_cpu(cpu));
1681 cvmx_write_csr(en_addr, mask);
1685 static void octeon_irq_ciu2_mbox_disable_all(struct irq_data *data)
1690 mask = 1ull << (data->irq - OCTEON_IRQ_MBOX0);
1692 for_each_online_cpu(cpu) {
1693 u64 en_addr = CVMX_CIU2_EN_PPX_IP3_MBOX_W1C(
1694 octeon_coreid_for_cpu(cpu));
1695 cvmx_write_csr(en_addr, mask);
1699 static void octeon_irq_ciu2_mbox_enable_local(struct irq_data *data)
1703 int coreid = cvmx_get_core_num();
1705 mask = 1ull << (data->irq - OCTEON_IRQ_MBOX0);
1706 en_addr = CVMX_CIU2_EN_PPX_IP3_MBOX_W1S(coreid);
1707 cvmx_write_csr(en_addr, mask);
1710 static void octeon_irq_ciu2_mbox_disable_local(struct irq_data *data)
1714 int coreid = cvmx_get_core_num();
1716 mask = 1ull << (data->irq - OCTEON_IRQ_MBOX0);
1717 en_addr = CVMX_CIU2_EN_PPX_IP3_MBOX_W1C(coreid);
1718 cvmx_write_csr(en_addr, mask);
1722 static int octeon_irq_ciu2_set_affinity(struct irq_data *data,
1723 const struct cpumask *dest, bool force)
1726 bool enable_one = !irqd_irq_disabled(data) && !irqd_irq_masked(data);
1728 struct octeon_ciu_chip_data *cd;
1733 cd = irq_data_get_irq_chip_data(data);
1734 mask = 1ull << cd->bit;
1736 for_each_online_cpu(cpu) {
1738 if (cpumask_test_cpu(cpu, dest) && enable_one) {
1740 en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(
1741 octeon_coreid_for_cpu(cpu)) +
1742 (0x1000ull * cd->line);
1744 en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(
1745 octeon_coreid_for_cpu(cpu)) +
1746 (0x1000ull * cd->line);
1748 cvmx_write_csr(en_addr, mask);
1755 static void octeon_irq_ciu2_enable_gpio(struct irq_data *data)
1757 octeon_irq_gpio_setup(data);
1758 octeon_irq_ciu2_enable(data);
1761 static void octeon_irq_ciu2_disable_gpio(struct irq_data *data)
1763 struct octeon_ciu_chip_data *cd;
1765 cd = irq_data_get_irq_chip_data(data);
1767 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd->gpio_line), 0);
1769 octeon_irq_ciu2_disable_all(data);
1772 static struct irq_chip octeon_irq_chip_ciu2 = {
1774 .irq_enable = octeon_irq_ciu2_enable,
1775 .irq_disable = octeon_irq_ciu2_disable_all,
1776 .irq_mask = octeon_irq_ciu2_disable_local,
1777 .irq_unmask = octeon_irq_ciu2_enable,
1779 .irq_set_affinity = octeon_irq_ciu2_set_affinity,
1780 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
1784 static struct irq_chip octeon_irq_chip_ciu2_edge = {
1786 .irq_enable = octeon_irq_ciu2_enable,
1787 .irq_disable = octeon_irq_ciu2_disable_all,
1788 .irq_ack = octeon_irq_ciu2_ack,
1789 .irq_mask = octeon_irq_ciu2_disable_local,
1790 .irq_unmask = octeon_irq_ciu2_enable,
1792 .irq_set_affinity = octeon_irq_ciu2_set_affinity,
1793 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
1797 static struct irq_chip octeon_irq_chip_ciu2_mbox = {
1799 .irq_enable = octeon_irq_ciu2_mbox_enable_all,
1800 .irq_disable = octeon_irq_ciu2_mbox_disable_all,
1801 .irq_ack = octeon_irq_ciu2_mbox_disable_local,
1802 .irq_eoi = octeon_irq_ciu2_mbox_enable_local,
1804 .irq_cpu_online = octeon_irq_ciu2_mbox_enable_local,
1805 .irq_cpu_offline = octeon_irq_ciu2_mbox_disable_local,
1806 .flags = IRQCHIP_ONOFFLINE_ENABLED,
1809 static struct irq_chip octeon_irq_chip_ciu2_wd = {
1811 .irq_enable = octeon_irq_ciu2_wd_enable,
1812 .irq_disable = octeon_irq_ciu2_disable_all,
1813 .irq_mask = octeon_irq_ciu2_disable_local,
1814 .irq_unmask = octeon_irq_ciu2_enable_local,
1817 static struct irq_chip octeon_irq_chip_ciu2_gpio = {
1819 .irq_enable = octeon_irq_ciu2_enable_gpio,
1820 .irq_disable = octeon_irq_ciu2_disable_gpio,
1821 .irq_ack = octeon_irq_ciu_gpio_ack,
1822 .irq_mask = octeon_irq_ciu2_disable_local,
1823 .irq_unmask = octeon_irq_ciu2_enable,
1824 .irq_set_type = octeon_irq_ciu_gpio_set_type,
1826 .irq_set_affinity = octeon_irq_ciu2_set_affinity,
1827 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
1829 .flags = IRQCHIP_SET_TYPE_MASKED,
1832 static int octeon_irq_ciu2_xlat(struct irq_domain *d,
1833 struct device_node *node,
1835 unsigned int intsize,
1836 unsigned long *out_hwirq,
1837 unsigned int *out_type)
1839 unsigned int ciu, bit;
1844 *out_hwirq = (ciu << 6) | bit;
1850 static bool octeon_irq_ciu2_is_edge(unsigned int line, unsigned int bit)
1854 if (line == 3) /* MIO */
1856 case 2: /* IPD_DRP */
1857 case 8 ... 11: /* Timers */
1864 else if (line == 6) /* PKT */
1866 case 52 ... 53: /* ILK_DRP */
1867 case 8 ... 12: /* GMX_DRP */
1876 static int octeon_irq_ciu2_map(struct irq_domain *d,
1877 unsigned int virq, irq_hw_number_t hw)
1879 unsigned int line = hw >> 6;
1880 unsigned int bit = hw & 63;
1883 * Don't map irq if it is reserved for GPIO.
1884 * (Line 7 are the GPIO lines.)
1889 if (line > 7 || octeon_irq_ciu_to_irq[line][bit] != 0)
1892 if (octeon_irq_ciu2_is_edge(line, bit))
1893 octeon_irq_set_ciu_mapping(virq, line, bit, 0,
1894 &octeon_irq_chip_ciu2_edge,
1897 octeon_irq_set_ciu_mapping(virq, line, bit, 0,
1898 &octeon_irq_chip_ciu2,
1904 static struct irq_domain_ops octeon_irq_domain_ciu2_ops = {
1905 .map = octeon_irq_ciu2_map,
1906 .unmap = octeon_irq_free_cd,
1907 .xlate = octeon_irq_ciu2_xlat,
1910 static void octeon_irq_ciu2(void)
1915 u64 src_reg, src, sum;
1916 const unsigned long core_id = cvmx_get_core_num();
1918 sum = cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(core_id)) & 0xfful;
1923 line = fls64(sum) - 1;
1924 src_reg = CVMX_CIU2_SRC_PPX_IP2_WRKQ(core_id) + (0x1000 * line);
1925 src = cvmx_read_csr(src_reg);
1930 bit = fls64(src) - 1;
1931 irq = octeon_irq_ciu_to_irq[line][bit];
1939 spurious_interrupt();
1941 /* CN68XX pass 1.x has an errata that accessing the ACK registers
1942 can stop interrupts from propagating */
1943 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
1944 cvmx_read_csr(CVMX_CIU2_INTR_CIU_READY);
1946 cvmx_read_csr(CVMX_CIU2_ACK_PPX_IP2(core_id));
1950 static void octeon_irq_ciu2_mbox(void)
1954 const unsigned long core_id = cvmx_get_core_num();
1955 u64 sum = cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP3(core_id)) >> 60;
1960 line = fls64(sum) - 1;
1962 do_IRQ(OCTEON_IRQ_MBOX0 + line);
1966 spurious_interrupt();
1968 /* CN68XX pass 1.x has an errata that accessing the ACK registers
1969 can stop interrupts from propagating */
1970 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
1971 cvmx_read_csr(CVMX_CIU2_INTR_CIU_READY);
1973 cvmx_read_csr(CVMX_CIU2_ACK_PPX_IP3(core_id));
1977 static int __init octeon_irq_init_ciu2(
1978 struct device_node *ciu_node, struct device_node *parent)
1981 struct irq_domain *ciu_domain = NULL;
1983 octeon_irq_init_ciu2_percpu();
1984 octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu2;
1986 octeon_irq_gpio_chip = &octeon_irq_chip_ciu2_gpio;
1987 octeon_irq_ip2 = octeon_irq_ciu2;
1988 octeon_irq_ip3 = octeon_irq_ciu2_mbox;
1989 octeon_irq_ip4 = octeon_irq_ip4_mask;
1992 octeon_irq_init_core();
1994 ciu_domain = irq_domain_add_tree(
1995 ciu_node, &octeon_irq_domain_ciu2_ops, NULL);
1996 irq_set_default_host(ciu_domain);
1999 for (i = 0; i < 64; i++) {
2000 r = octeon_irq_force_ciu_mapping(
2001 ciu_domain, i + OCTEON_IRQ_WORKQ0, 0, i);
2006 for (i = 0; i < 32; i++) {
2007 r = octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WDOG0, 1, i, 0,
2008 &octeon_irq_chip_ciu2_wd, handle_level_irq);
2013 for (i = 0; i < 4; i++) {
2014 r = octeon_irq_force_ciu_mapping(
2015 ciu_domain, i + OCTEON_IRQ_TIMER0, 3, i + 8);
2020 r = octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_USB0, 3, 44);
2024 for (i = 0; i < 4; i++) {
2025 r = octeon_irq_force_ciu_mapping(
2026 ciu_domain, i + OCTEON_IRQ_PCI_INT0, 4, i);
2031 for (i = 0; i < 4; i++) {
2032 r = octeon_irq_force_ciu_mapping(
2033 ciu_domain, i + OCTEON_IRQ_PCI_MSI0, 4, i + 8);
2038 irq_set_chip_and_handler(OCTEON_IRQ_MBOX0, &octeon_irq_chip_ciu2_mbox, handle_percpu_irq);
2039 irq_set_chip_and_handler(OCTEON_IRQ_MBOX1, &octeon_irq_chip_ciu2_mbox, handle_percpu_irq);
2040 irq_set_chip_and_handler(OCTEON_IRQ_MBOX2, &octeon_irq_chip_ciu2_mbox, handle_percpu_irq);
2041 irq_set_chip_and_handler(OCTEON_IRQ_MBOX3, &octeon_irq_chip_ciu2_mbox, handle_percpu_irq);
2043 /* Enable the CIU lines */
2044 set_c0_status(STATUSF_IP3 | STATUSF_IP2);
2045 clear_c0_status(STATUSF_IP4);
2051 struct octeon_irq_cib_host_data {
2052 raw_spinlock_t lock;
2058 struct octeon_irq_cib_chip_data {
2059 struct octeon_irq_cib_host_data *host_data;
2063 static void octeon_irq_cib_enable(struct irq_data *data)
2065 unsigned long flags;
2067 struct octeon_irq_cib_chip_data *cd = irq_data_get_irq_chip_data(data);
2068 struct octeon_irq_cib_host_data *host_data = cd->host_data;
2070 raw_spin_lock_irqsave(&host_data->lock, flags);
2071 en = cvmx_read_csr(host_data->en_reg);
2072 en |= 1ull << cd->bit;
2073 cvmx_write_csr(host_data->en_reg, en);
2074 raw_spin_unlock_irqrestore(&host_data->lock, flags);
2077 static void octeon_irq_cib_disable(struct irq_data *data)
2079 unsigned long flags;
2081 struct octeon_irq_cib_chip_data *cd = irq_data_get_irq_chip_data(data);
2082 struct octeon_irq_cib_host_data *host_data = cd->host_data;
2084 raw_spin_lock_irqsave(&host_data->lock, flags);
2085 en = cvmx_read_csr(host_data->en_reg);
2086 en &= ~(1ull << cd->bit);
2087 cvmx_write_csr(host_data->en_reg, en);
2088 raw_spin_unlock_irqrestore(&host_data->lock, flags);
2091 static int octeon_irq_cib_set_type(struct irq_data *data, unsigned int t)
2093 irqd_set_trigger_type(data, t);
2094 return IRQ_SET_MASK_OK;
2097 static struct irq_chip octeon_irq_chip_cib = {
2099 .irq_enable = octeon_irq_cib_enable,
2100 .irq_disable = octeon_irq_cib_disable,
2101 .irq_mask = octeon_irq_cib_disable,
2102 .irq_unmask = octeon_irq_cib_enable,
2103 .irq_set_type = octeon_irq_cib_set_type,
2106 static int octeon_irq_cib_xlat(struct irq_domain *d,
2107 struct device_node *node,
2109 unsigned int intsize,
2110 unsigned long *out_hwirq,
2111 unsigned int *out_type)
2113 unsigned int type = 0;
2119 case 0: /* unofficial value, but we might as well let it work. */
2120 case 4: /* official value for level triggering. */
2121 *out_type = IRQ_TYPE_LEVEL_HIGH;
2123 case 1: /* official value for edge triggering. */
2124 *out_type = IRQ_TYPE_EDGE_RISING;
2126 default: /* Nothing else is acceptable. */
2130 *out_hwirq = intspec[0];
2135 static int octeon_irq_cib_map(struct irq_domain *d,
2136 unsigned int virq, irq_hw_number_t hw)
2138 struct octeon_irq_cib_host_data *host_data = d->host_data;
2139 struct octeon_irq_cib_chip_data *cd;
2141 if (hw >= host_data->max_bits) {
2142 pr_err("ERROR: %s mapping %u is to big!\n",
2143 irq_domain_get_of_node(d)->name, (unsigned)hw);
2147 cd = kzalloc(sizeof(*cd), GFP_KERNEL);
2148 cd->host_data = host_data;
2151 irq_set_chip_and_handler(virq, &octeon_irq_chip_cib,
2153 irq_set_chip_data(virq, cd);
2157 static struct irq_domain_ops octeon_irq_domain_cib_ops = {
2158 .map = octeon_irq_cib_map,
2159 .unmap = octeon_irq_free_cd,
2160 .xlate = octeon_irq_cib_xlat,
2163 /* Chain to real handler. */
2164 static irqreturn_t octeon_irq_cib_handler(int my_irq, void *data)
2171 struct irq_domain *cib_domain = data;
2172 struct octeon_irq_cib_host_data *host_data = cib_domain->host_data;
2174 en = cvmx_read_csr(host_data->en_reg);
2175 raw = cvmx_read_csr(host_data->raw_reg);
2179 for (i = 0; i < host_data->max_bits; i++) {
2180 if ((bits & 1ull << i) == 0)
2182 irq = irq_find_mapping(cib_domain, i);
2184 unsigned long flags;
2186 pr_err("ERROR: CIB bit %d@%llx IRQ unhandled, disabling\n",
2187 i, host_data->raw_reg);
2188 raw_spin_lock_irqsave(&host_data->lock, flags);
2189 en = cvmx_read_csr(host_data->en_reg);
2191 cvmx_write_csr(host_data->en_reg, en);
2192 cvmx_write_csr(host_data->raw_reg, 1ull << i);
2193 raw_spin_unlock_irqrestore(&host_data->lock, flags);
2195 struct irq_desc *desc = irq_to_desc(irq);
2196 struct irq_data *irq_data = irq_desc_get_irq_data(desc);
2197 /* If edge, acknowledge the bit we will be sending. */
2198 if (irqd_get_trigger_type(irq_data) &
2200 cvmx_write_csr(host_data->raw_reg, 1ull << i);
2201 generic_handle_irq_desc(desc);
2208 static int __init octeon_irq_init_cib(struct device_node *ciu_node,
2209 struct device_node *parent)
2213 struct octeon_irq_cib_host_data *host_data;
2216 struct irq_domain *cib_domain;
2218 parent_irq = irq_of_parse_and_map(ciu_node, 0);
2220 pr_err("ERROR: Couldn't acquire parent_irq for %s\n.",
2225 host_data = kzalloc(sizeof(*host_data), GFP_KERNEL);
2226 raw_spin_lock_init(&host_data->lock);
2228 addr = of_get_address(ciu_node, 0, NULL, NULL);
2230 pr_err("ERROR: Couldn't acquire reg(0) %s\n.", ciu_node->name);
2233 host_data->raw_reg = (u64)phys_to_virt(
2234 of_translate_address(ciu_node, addr));
2236 addr = of_get_address(ciu_node, 1, NULL, NULL);
2238 pr_err("ERROR: Couldn't acquire reg(1) %s\n.", ciu_node->name);
2241 host_data->en_reg = (u64)phys_to_virt(
2242 of_translate_address(ciu_node, addr));
2244 r = of_property_read_u32(ciu_node, "cavium,max-bits", &val);
2246 pr_err("ERROR: Couldn't read cavium,max-bits from %s\n.",
2250 host_data->max_bits = val;
2252 cib_domain = irq_domain_add_linear(ciu_node, host_data->max_bits,
2253 &octeon_irq_domain_cib_ops,
2256 pr_err("ERROR: Couldn't irq_domain_add_linear()\n.");
2260 cvmx_write_csr(host_data->en_reg, 0); /* disable all IRQs */
2261 cvmx_write_csr(host_data->raw_reg, ~0); /* ack any outstanding */
2263 r = request_irq(parent_irq, octeon_irq_cib_handler,
2264 IRQF_NO_THREAD, "cib", cib_domain);
2266 pr_err("request_irq cib failed %d\n", r);
2269 pr_info("CIB interrupt controller probed: %llx %d\n",
2270 host_data->raw_reg, host_data->max_bits);
2274 static struct of_device_id ciu_types[] __initdata = {
2275 {.compatible = "cavium,octeon-3860-ciu", .data = octeon_irq_init_ciu},
2276 {.compatible = "cavium,octeon-3860-gpio", .data = octeon_irq_init_gpio},
2277 {.compatible = "cavium,octeon-6880-ciu2", .data = octeon_irq_init_ciu2},
2278 {.compatible = "cavium,octeon-7130-cib", .data = octeon_irq_init_cib},
2282 void __init arch_init_irq(void)
2285 /* Set the default affinity to the boot cpu. */
2286 cpumask_clear(irq_default_affinity);
2287 cpumask_set_cpu(smp_processor_id(), irq_default_affinity);
2289 of_irq_init(ciu_types);
2292 asmlinkage void plat_irq_dispatch(void)
2294 unsigned long cop0_cause;
2295 unsigned long cop0_status;
2298 cop0_cause = read_c0_cause();
2299 cop0_status = read_c0_status();
2300 cop0_cause &= cop0_status;
2301 cop0_cause &= ST0_IM;
2303 if (cop0_cause & STATUSF_IP2)
2305 else if (cop0_cause & STATUSF_IP3)
2307 else if (cop0_cause & STATUSF_IP4)
2309 else if (cop0_cause)
2310 do_IRQ(fls(cop0_cause) - 9 + MIPS_CPU_IRQ_BASE);
2316 #ifdef CONFIG_HOTPLUG_CPU
2318 void octeon_fixup_irqs(void)
2323 #endif /* CONFIG_HOTPLUG_CPU */