2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2003 Ralf Baechle
8 #ifndef _ASM_ASMMACRO_H
9 #define _ASM_ASMMACRO_H
11 #include <asm/hazards.h>
12 #include <asm/asm-offsets.h>
16 #include <asm/asmmacro-32.h>
19 #include <asm/asmmacro-64.h>
22 #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
23 .macro local_irq_enable reg=t0
28 .macro local_irq_disable reg=t0
33 .macro local_irq_enable reg=t0
40 .macro local_irq_disable reg=t0
42 lw \reg, TI_PRE_COUNT($28)
44 sw \reg, TI_PRE_COUNT($28)
52 lw \reg, TI_PRE_COUNT($28)
54 sw \reg, TI_PRE_COUNT($28)
57 #endif /* CONFIG_CPU_MIPSR2 */
59 .macro fpu_save_16even thread tmp=t0
63 sdc1 $f0, THREAD_FPR0(\thread)
64 sdc1 $f2, THREAD_FPR2(\thread)
65 sdc1 $f4, THREAD_FPR4(\thread)
66 sdc1 $f6, THREAD_FPR6(\thread)
67 sdc1 $f8, THREAD_FPR8(\thread)
68 sdc1 $f10, THREAD_FPR10(\thread)
69 sdc1 $f12, THREAD_FPR12(\thread)
70 sdc1 $f14, THREAD_FPR14(\thread)
71 sdc1 $f16, THREAD_FPR16(\thread)
72 sdc1 $f18, THREAD_FPR18(\thread)
73 sdc1 $f20, THREAD_FPR20(\thread)
74 sdc1 $f22, THREAD_FPR22(\thread)
75 sdc1 $f24, THREAD_FPR24(\thread)
76 sdc1 $f26, THREAD_FPR26(\thread)
77 sdc1 $f28, THREAD_FPR28(\thread)
78 sdc1 $f30, THREAD_FPR30(\thread)
79 sw \tmp, THREAD_FCR31(\thread)
83 .macro fpu_save_16odd thread
87 sdc1 $f1, THREAD_FPR1(\thread)
88 sdc1 $f3, THREAD_FPR3(\thread)
89 sdc1 $f5, THREAD_FPR5(\thread)
90 sdc1 $f7, THREAD_FPR7(\thread)
91 sdc1 $f9, THREAD_FPR9(\thread)
92 sdc1 $f11, THREAD_FPR11(\thread)
93 sdc1 $f13, THREAD_FPR13(\thread)
94 sdc1 $f15, THREAD_FPR15(\thread)
95 sdc1 $f17, THREAD_FPR17(\thread)
96 sdc1 $f19, THREAD_FPR19(\thread)
97 sdc1 $f21, THREAD_FPR21(\thread)
98 sdc1 $f23, THREAD_FPR23(\thread)
99 sdc1 $f25, THREAD_FPR25(\thread)
100 sdc1 $f27, THREAD_FPR27(\thread)
101 sdc1 $f29, THREAD_FPR29(\thread)
102 sdc1 $f31, THREAD_FPR31(\thread)
106 .macro fpu_save_double thread status tmp
107 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
108 defined(CONFIG_CPU_MIPS32_R6)
111 fpu_save_16odd \thread
114 fpu_save_16even \thread \tmp
117 .macro fpu_restore_16even thread tmp=t0
120 lw \tmp, THREAD_FCR31(\thread)
121 ldc1 $f0, THREAD_FPR0(\thread)
122 ldc1 $f2, THREAD_FPR2(\thread)
123 ldc1 $f4, THREAD_FPR4(\thread)
124 ldc1 $f6, THREAD_FPR6(\thread)
125 ldc1 $f8, THREAD_FPR8(\thread)
126 ldc1 $f10, THREAD_FPR10(\thread)
127 ldc1 $f12, THREAD_FPR12(\thread)
128 ldc1 $f14, THREAD_FPR14(\thread)
129 ldc1 $f16, THREAD_FPR16(\thread)
130 ldc1 $f18, THREAD_FPR18(\thread)
131 ldc1 $f20, THREAD_FPR20(\thread)
132 ldc1 $f22, THREAD_FPR22(\thread)
133 ldc1 $f24, THREAD_FPR24(\thread)
134 ldc1 $f26, THREAD_FPR26(\thread)
135 ldc1 $f28, THREAD_FPR28(\thread)
136 ldc1 $f30, THREAD_FPR30(\thread)
140 .macro fpu_restore_16odd thread
144 ldc1 $f1, THREAD_FPR1(\thread)
145 ldc1 $f3, THREAD_FPR3(\thread)
146 ldc1 $f5, THREAD_FPR5(\thread)
147 ldc1 $f7, THREAD_FPR7(\thread)
148 ldc1 $f9, THREAD_FPR9(\thread)
149 ldc1 $f11, THREAD_FPR11(\thread)
150 ldc1 $f13, THREAD_FPR13(\thread)
151 ldc1 $f15, THREAD_FPR15(\thread)
152 ldc1 $f17, THREAD_FPR17(\thread)
153 ldc1 $f19, THREAD_FPR19(\thread)
154 ldc1 $f21, THREAD_FPR21(\thread)
155 ldc1 $f23, THREAD_FPR23(\thread)
156 ldc1 $f25, THREAD_FPR25(\thread)
157 ldc1 $f27, THREAD_FPR27(\thread)
158 ldc1 $f29, THREAD_FPR29(\thread)
159 ldc1 $f31, THREAD_FPR31(\thread)
163 .macro fpu_restore_double thread status tmp
164 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
165 defined(CONFIG_CPU_MIPS32_R6)
167 bgez \tmp, 10f # 16 register mode?
169 fpu_restore_16odd \thread
172 fpu_restore_16even \thread \tmp
175 #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
176 .macro _EXT rd, rs, p, s
179 #else /* !CONFIG_CPU_MIPSR2 || !CONFIG_CPU_MIPSR6 */
180 .macro _EXT rd, rs, p, s
182 andi \rd, \rd, (1 << \s) - 1
184 #endif /* !CONFIG_CPU_MIPSR2 || !CONFIG_CPU_MIPSR6 */
187 * Temporary until all gas have MT ASE support
190 .word 0x41600bc1 | (\reg << 16)
194 .word 0x41600be1 | (\reg << 16)
198 .word 0x41600001 | (\reg << 16)
202 .word 0x41600021 | (\reg << 16)
205 .macro MFTR rt=0, rd=0, u=0, sel=0
206 .word 0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
209 .macro MTTR rt=0, rd=0, u=0, sel=0
210 .word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
213 #ifdef TOOLCHAIN_SUPPORTS_MSA
214 /* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
217 .macro _cfcmsa rd, cs
226 .macro _ctcmsa cd, rs
235 .macro ld_b wd, off, base
240 ld.b $w\wd, \off(\base)
244 .macro ld_h wd, off, base
249 ld.h $w\wd, \off(\base)
253 .macro ld_w wd, off, base
258 ld.w $w\wd, \off(\base)
262 .macro ld_d wd, off, base
267 ld.d $w\wd, \off(\base)
271 .macro st_b wd, off, base
276 st.b $w\wd, \off(\base)
280 .macro st_h wd, off, base
285 st.h $w\wd, \off(\base)
289 .macro st_w wd, off, base
294 st.w $w\wd, \off(\base)
298 .macro st_d wd, off, base
303 st.d $w\wd, \off(\base)
307 .macro copy_s_w ws, n
312 copy_s.w $1, $w\ws[\n]
316 .macro copy_s_d ws, n
321 copy_s.d $1, $w\ws[\n]
325 .macro insert_w wd, n
330 insert.w $w\wd[\n], $1
334 .macro insert_d wd, n
339 insert.d $w\wd[\n], $1
344 #ifdef CONFIG_CPU_MICROMIPS
345 #define CFC_MSA_INSN 0x587e0056
346 #define CTC_MSA_INSN 0x583e0816
347 #define LDB_MSA_INSN 0x58000807
348 #define LDH_MSA_INSN 0x58000817
349 #define LDW_MSA_INSN 0x58000827
350 #define LDD_MSA_INSN 0x58000837
351 #define STB_MSA_INSN 0x5800080f
352 #define STH_MSA_INSN 0x5800081f
353 #define STW_MSA_INSN 0x5800082f
354 #define STD_MSA_INSN 0x5800083f
355 #define COPY_SW_MSA_INSN 0x58b00056
356 #define COPY_SD_MSA_INSN 0x58b80056
357 #define INSERT_W_MSA_INSN 0x59300816
358 #define INSERT_D_MSA_INSN 0x59380816
360 #define CFC_MSA_INSN 0x787e0059
361 #define CTC_MSA_INSN 0x783e0819
362 #define LDB_MSA_INSN 0x78000820
363 #define LDH_MSA_INSN 0x78000821
364 #define LDW_MSA_INSN 0x78000822
365 #define LDD_MSA_INSN 0x78000823
366 #define STB_MSA_INSN 0x78000824
367 #define STH_MSA_INSN 0x78000825
368 #define STW_MSA_INSN 0x78000826
369 #define STD_MSA_INSN 0x78000827
370 #define COPY_SW_MSA_INSN 0x78b00059
371 #define COPY_SD_MSA_INSN 0x78b80059
372 #define INSERT_W_MSA_INSN 0x79300819
373 #define INSERT_D_MSA_INSN 0x79380819
377 * Temporary until all toolchains in use include MSA support.
379 .macro _cfcmsa rd, cs
384 .word CFC_MSA_INSN | (\cs << 11)
389 .macro _ctcmsa cd, rs
394 .word CTC_MSA_INSN | (\cd << 6)
398 .macro ld_b wd, off, base
402 PTR_ADDU $1, \base, \off
403 .word LDB_MSA_INSN | (\wd << 6)
407 .macro ld_h wd, off, base
411 PTR_ADDU $1, \base, \off
412 .word LDH_MSA_INSN | (\wd << 6)
416 .macro ld_w wd, off, base
420 PTR_ADDU $1, \base, \off
421 .word LDW_MSA_INSN | (\wd << 6)
425 .macro ld_d wd, off, base
429 PTR_ADDU $1, \base, \off
430 .word LDD_MSA_INSN | (\wd << 6)
434 .macro st_b wd, off, base
438 PTR_ADDU $1, \base, \off
439 .word STB_MSA_INSN | (\wd << 6)
443 .macro st_h wd, off, base
447 PTR_ADDU $1, \base, \off
448 .word STH_MSA_INSN | (\wd << 6)
452 .macro st_w wd, off, base
456 PTR_ADDU $1, \base, \off
457 .word STW_MSA_INSN | (\wd << 6)
461 .macro st_d wd, off, base
465 PTR_ADDU $1, \base, \off
466 .word STD_MSA_INSN | (\wd << 6)
470 .macro copy_s_w ws, n
475 .word COPY_SW_MSA_INSN | (\n << 16) | (\ws << 11)
479 .macro copy_s_d ws, n
484 .word COPY_SD_MSA_INSN | (\n << 16) | (\ws << 11)
488 .macro insert_w wd, n
492 .word INSERT_W_MSA_INSN | (\n << 16) | (\wd << 6)
496 .macro insert_d wd, n
500 .word INSERT_D_MSA_INSN | (\n << 16) | (\wd << 6)
505 #ifdef TOOLCHAIN_SUPPORTS_MSA
506 #define FPR_BASE_OFFS THREAD_FPR0
509 #define FPR_BASE_OFFS 0
510 #define FPR_BASE \thread
513 .macro msa_save_all thread
516 #ifdef TOOLCHAIN_SUPPORTS_MSA
517 PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS
519 st_d 0, THREAD_FPR0 - FPR_BASE_OFFS, FPR_BASE
520 st_d 1, THREAD_FPR1 - FPR_BASE_OFFS, FPR_BASE
521 st_d 2, THREAD_FPR2 - FPR_BASE_OFFS, FPR_BASE
522 st_d 3, THREAD_FPR3 - FPR_BASE_OFFS, FPR_BASE
523 st_d 4, THREAD_FPR4 - FPR_BASE_OFFS, FPR_BASE
524 st_d 5, THREAD_FPR5 - FPR_BASE_OFFS, FPR_BASE
525 st_d 6, THREAD_FPR6 - FPR_BASE_OFFS, FPR_BASE
526 st_d 7, THREAD_FPR7 - FPR_BASE_OFFS, FPR_BASE
527 st_d 8, THREAD_FPR8 - FPR_BASE_OFFS, FPR_BASE
528 st_d 9, THREAD_FPR9 - FPR_BASE_OFFS, FPR_BASE
529 st_d 10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE
530 st_d 11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE
531 st_d 12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE
532 st_d 13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE
533 st_d 14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE
534 st_d 15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE
535 st_d 16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE
536 st_d 17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE
537 st_d 18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE
538 st_d 19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE
539 st_d 20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE
540 st_d 21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE
541 st_d 22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE
542 st_d 23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE
543 st_d 24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE
544 st_d 25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE
545 st_d 26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE
546 st_d 27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE
547 st_d 28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE
548 st_d 29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE
549 st_d 30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE
550 st_d 31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE
553 sw $1, THREAD_MSA_CSR(\thread)
557 .macro msa_restore_all thread
561 lw $1, THREAD_MSA_CSR(\thread)
563 #ifdef TOOLCHAIN_SUPPORTS_MSA
564 PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS
566 ld_d 0, THREAD_FPR0 - FPR_BASE_OFFS, FPR_BASE
567 ld_d 1, THREAD_FPR1 - FPR_BASE_OFFS, FPR_BASE
568 ld_d 2, THREAD_FPR2 - FPR_BASE_OFFS, FPR_BASE
569 ld_d 3, THREAD_FPR3 - FPR_BASE_OFFS, FPR_BASE
570 ld_d 4, THREAD_FPR4 - FPR_BASE_OFFS, FPR_BASE
571 ld_d 5, THREAD_FPR5 - FPR_BASE_OFFS, FPR_BASE
572 ld_d 6, THREAD_FPR6 - FPR_BASE_OFFS, FPR_BASE
573 ld_d 7, THREAD_FPR7 - FPR_BASE_OFFS, FPR_BASE
574 ld_d 8, THREAD_FPR8 - FPR_BASE_OFFS, FPR_BASE
575 ld_d 9, THREAD_FPR9 - FPR_BASE_OFFS, FPR_BASE
576 ld_d 10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE
577 ld_d 11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE
578 ld_d 12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE
579 ld_d 13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE
580 ld_d 14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE
581 ld_d 15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE
582 ld_d 16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE
583 ld_d 17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE
584 ld_d 18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE
585 ld_d 19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE
586 ld_d 20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE
587 ld_d 21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE
588 ld_d 22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE
589 ld_d 23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE
590 ld_d 24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE
591 ld_d 25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE
592 ld_d 26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE
593 ld_d 27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE
594 ld_d 28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE
595 ld_d 29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE
596 ld_d 30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE
597 ld_d 31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE
604 .macro msa_init_upper wd
613 .macro msa_init_all_upper
653 #endif /* _ASM_ASMMACRO_H */