arch/mips/include/asm/kvm_host.h

   1 /*
   2 * This file is subject to the terms and conditions of the GNU General Public
   3 * License.  See the file "COPYING" in the main directory of this archive
   4 * for more details.
   5 *
   6 * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
   7 * Authors: Sanjay Lal <sanjayl@kymasys.com>
   8 */
   9
  10 #ifndef __MIPS_KVM_HOST_H__
  11 #define __MIPS_KVM_HOST_H__
  12
  13 #include <linux/mutex.h>
  14 #include <linux/hrtimer.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/types.h>
  17 #include <linux/kvm.h>
  18 #include <linux/kvm_types.h>
  19 #include <linux/threads.h>
  20 #include <linux/spinlock.h>
  21
  22 /* MIPS KVM register ids */
  23 #define MIPS_CP0_32(_R, _S)                                     \
  24         (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S)))
  25
  26 #define MIPS_CP0_64(_R, _S)                                     \
  27         (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S)))
  28
  29 #define KVM_REG_MIPS_CP0_INDEX          MIPS_CP0_32(0, 0)
  30 #define KVM_REG_MIPS_CP0_ENTRYLO0       MIPS_CP0_64(2, 0)
  31 #define KVM_REG_MIPS_CP0_ENTRYLO1       MIPS_CP0_64(3, 0)
  32 #define KVM_REG_MIPS_CP0_CONTEXT        MIPS_CP0_64(4, 0)
  33 #define KVM_REG_MIPS_CP0_USERLOCAL      MIPS_CP0_64(4, 2)
  34 #define KVM_REG_MIPS_CP0_PAGEMASK       MIPS_CP0_32(5, 0)
  35 #define KVM_REG_MIPS_CP0_PAGEGRAIN      MIPS_CP0_32(5, 1)
  36 #define KVM_REG_MIPS_CP0_WIRED          MIPS_CP0_32(6, 0)
  37 #define KVM_REG_MIPS_CP0_HWRENA         MIPS_CP0_32(7, 0)
  38 #define KVM_REG_MIPS_CP0_BADVADDR       MIPS_CP0_64(8, 0)
  39 #define KVM_REG_MIPS_CP0_COUNT          MIPS_CP0_32(9, 0)
  40 #define KVM_REG_MIPS_CP0_ENTRYHI        MIPS_CP0_64(10, 0)
  41 #define KVM_REG_MIPS_CP0_COMPARE        MIPS_CP0_32(11, 0)
  42 #define KVM_REG_MIPS_CP0_STATUS         MIPS_CP0_32(12, 0)
  43 #define KVM_REG_MIPS_CP0_CAUSE          MIPS_CP0_32(13, 0)
  44 #define KVM_REG_MIPS_CP0_EPC            MIPS_CP0_64(14, 0)
  45 #define KVM_REG_MIPS_CP0_PRID           MIPS_CP0_32(15, 0)
  46 #define KVM_REG_MIPS_CP0_EBASE          MIPS_CP0_64(15, 1)
  47 #define KVM_REG_MIPS_CP0_CONFIG         MIPS_CP0_32(16, 0)
  48 #define KVM_REG_MIPS_CP0_CONFIG1        MIPS_CP0_32(16, 1)
  49 #define KVM_REG_MIPS_CP0_CONFIG2        MIPS_CP0_32(16, 2)
  50 #define KVM_REG_MIPS_CP0_CONFIG3        MIPS_CP0_32(16, 3)
  51 #define KVM_REG_MIPS_CP0_CONFIG4        MIPS_CP0_32(16, 4)
  52 #define KVM_REG_MIPS_CP0_CONFIG5        MIPS_CP0_32(16, 5)
  53 #define KVM_REG_MIPS_CP0_CONFIG7        MIPS_CP0_32(16, 7)
  54 #define KVM_REG_MIPS_CP0_XCONTEXT       MIPS_CP0_64(20, 0)
  55 #define KVM_REG_MIPS_CP0_ERROREPC       MIPS_CP0_64(30, 0)
  56
  57
  58 #define KVM_MAX_VCPUS           1
  59 #define KVM_USER_MEM_SLOTS      8
  60 /* memory slots that does not exposed to userspace */
  61 #define KVM_PRIVATE_MEM_SLOTS   0
  62
  63 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
  64 #define KVM_HALT_POLL_NS_DEFAULT 500000
  65
  66
  67
  68 /* Special address that contains the comm page, used for reducing # of traps */
  69 #define KVM_GUEST_COMMPAGE_ADDR         0x0
  70
  71 #define KVM_GUEST_KERNEL_MODE(vcpu)     ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \
  72                                         ((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0))
  73
  74 #define KVM_GUEST_KUSEG                 0x00000000UL
  75 #define KVM_GUEST_KSEG0                 0x40000000UL
  76 #define KVM_GUEST_KSEG23                0x60000000UL
  77 #define KVM_GUEST_KSEGX(a)              ((_ACAST32_(a)) & 0x60000000)
  78 #define KVM_GUEST_CPHYSADDR(a)          ((_ACAST32_(a)) & 0x1fffffff)
  79
  80 #define KVM_GUEST_CKSEG0ADDR(a)         (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
  81 #define KVM_GUEST_CKSEG1ADDR(a)         (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
  82 #define KVM_GUEST_CKSEG23ADDR(a)        (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
  83
  84 /*
  85  * Map an address to a certain kernel segment
  86  */
  87 #define KVM_GUEST_KSEG0ADDR(a)          (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
  88 #define KVM_GUEST_KSEG1ADDR(a)          (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
  89 #define KVM_GUEST_KSEG23ADDR(a)         (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
  90
  91 #define KVM_INVALID_PAGE                0xdeadbeef
  92 #define KVM_INVALID_INST                0xdeadbeef
  93 #define KVM_INVALID_ADDR                0xdeadbeef
  94
  95 extern atomic_t kvm_mips_instance;
  96 extern kvm_pfn_t (*kvm_mips_gfn_to_pfn)(struct kvm *kvm, gfn_t gfn);
  97 extern void (*kvm_mips_release_pfn_clean)(kvm_pfn_t pfn);
  98 extern bool (*kvm_mips_is_error_pfn)(kvm_pfn_t pfn);
  99
 100 struct kvm_vm_stat {
 101         u32 remote_tlb_flush;
 102 };
 103
 104 struct kvm_vcpu_stat {
 105         u32 wait_exits;
 106         u32 cache_exits;
 107         u32 signal_exits;
 108         u32 int_exits;
 109         u32 cop_unusable_exits;
 110         u32 tlbmod_exits;
 111         u32 tlbmiss_ld_exits;
 112         u32 tlbmiss_st_exits;
 113         u32 addrerr_st_exits;
 114         u32 addrerr_ld_exits;
 115         u32 syscall_exits;
 116         u32 resvd_inst_exits;
 117         u32 break_inst_exits;
 118         u32 trap_inst_exits;
 119         u32 msa_fpe_exits;
 120         u32 fpe_exits;
 121         u32 msa_disabled_exits;
 122         u32 flush_dcache_exits;
 123         u32 halt_successful_poll;
 124         u32 halt_attempted_poll;
 125         u32 halt_poll_invalid;
 126         u32 halt_wakeup;
 127 };
 128
 129 enum kvm_mips_exit_types {
 130         WAIT_EXITS,
 131         CACHE_EXITS,
 132         SIGNAL_EXITS,
 133         INT_EXITS,
 134         COP_UNUSABLE_EXITS,
 135         TLBMOD_EXITS,
 136         TLBMISS_LD_EXITS,
 137         TLBMISS_ST_EXITS,
 138         ADDRERR_ST_EXITS,
 139         ADDRERR_LD_EXITS,
 140         SYSCALL_EXITS,
 141         RESVD_INST_EXITS,
 142         BREAK_INST_EXITS,
 143         TRAP_INST_EXITS,
 144         MSA_FPE_EXITS,
 145         FPE_EXITS,
 146         MSA_DISABLED_EXITS,
 147         FLUSH_DCACHE_EXITS,
 148         MAX_KVM_MIPS_EXIT_TYPES
 149 };
 150
 151 struct kvm_arch_memory_slot {
 152 };
 153
 154 struct kvm_arch {
 155         /* Guest GVA->HPA page table */
 156         unsigned long *guest_pmap;
 157         unsigned long guest_pmap_npages;
 158
 159         /* Wired host TLB used for the commpage */
 160         int commpage_tlb;
 161 };
 162
 163 #define N_MIPS_COPROC_REGS      32
 164 #define N_MIPS_COPROC_SEL       8
 165
 166 struct mips_coproc {
 167         unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
 168 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
 169         unsigned long stat[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
 170 #endif
 171 };
 172
 173 /*
 174  * Coprocessor 0 register names
 175  */
 176 #define MIPS_CP0_TLB_INDEX      0
 177 #define MIPS_CP0_TLB_RANDOM     1
 178 #define MIPS_CP0_TLB_LOW        2
 179 #define MIPS_CP0_TLB_LO0        2
 180 #define MIPS_CP0_TLB_LO1        3
 181 #define MIPS_CP0_TLB_CONTEXT    4
 182 #define MIPS_CP0_TLB_PG_MASK    5
 183 #define MIPS_CP0_TLB_WIRED      6
 184 #define MIPS_CP0_HWRENA         7
 185 #define MIPS_CP0_BAD_VADDR      8
 186 #define MIPS_CP0_COUNT          9
 187 #define MIPS_CP0_TLB_HI         10
 188 #define MIPS_CP0_COMPARE        11
 189 #define MIPS_CP0_STATUS         12
 190 #define MIPS_CP0_CAUSE          13
 191 #define MIPS_CP0_EXC_PC         14
 192 #define MIPS_CP0_PRID           15
 193 #define MIPS_CP0_CONFIG         16
 194 #define MIPS_CP0_LLADDR         17
 195 #define MIPS_CP0_WATCH_LO       18
 196 #define MIPS_CP0_WATCH_HI       19
 197 #define MIPS_CP0_TLB_XCONTEXT   20
 198 #define MIPS_CP0_ECC            26
 199 #define MIPS_CP0_CACHE_ERR      27
 200 #define MIPS_CP0_TAG_LO         28
 201 #define MIPS_CP0_TAG_HI         29
 202 #define MIPS_CP0_ERROR_PC       30
 203 #define MIPS_CP0_DEBUG          23
 204 #define MIPS_CP0_DEPC           24
 205 #define MIPS_CP0_PERFCNT        25
 206 #define MIPS_CP0_ERRCTL         26
 207 #define MIPS_CP0_DATA_LO        28
 208 #define MIPS_CP0_DATA_HI        29
 209 #define MIPS_CP0_DESAVE         31
 210
 211 #define MIPS_CP0_CONFIG_SEL     0
 212 #define MIPS_CP0_CONFIG1_SEL    1
 213 #define MIPS_CP0_CONFIG2_SEL    2
 214 #define MIPS_CP0_CONFIG3_SEL    3
 215 #define MIPS_CP0_CONFIG4_SEL    4
 216 #define MIPS_CP0_CONFIG5_SEL    5
 217
 218 /* Config0 register bits */
 219 #define CP0C0_M                 31
 220 #define CP0C0_K23               28
 221 #define CP0C0_KU                25
 222 #define CP0C0_MDU               20
 223 #define CP0C0_MM                17
 224 #define CP0C0_BM                16
 225 #define CP0C0_BE                15
 226 #define CP0C0_AT                13
 227 #define CP0C0_AR                10
 228 #define CP0C0_MT                7
 229 #define CP0C0_VI                3
 230 #define CP0C0_K0                0
 231
 232 /* Config1 register bits */
 233 #define CP0C1_M                 31
 234 #define CP0C1_MMU               25
 235 #define CP0C1_IS                22
 236 #define CP0C1_IL                19
 237 #define CP0C1_IA                16
 238 #define CP0C1_DS                13
 239 #define CP0C1_DL                10
 240 #define CP0C1_DA                7
 241 #define CP0C1_C2                6
 242 #define CP0C1_MD                5
 243 #define CP0C1_PC                4
 244 #define CP0C1_WR                3
 245 #define CP0C1_CA                2
 246 #define CP0C1_EP                1
 247 #define CP0C1_FP                0
 248
 249 /* Config2 Register bits */
 250 #define CP0C2_M                 31
 251 #define CP0C2_TU                28
 252 #define CP0C2_TS                24
 253 #define CP0C2_TL                20
 254 #define CP0C2_TA                16
 255 #define CP0C2_SU                12
 256 #define CP0C2_SS                8
 257 #define CP0C2_SL                4
 258 #define CP0C2_SA                0
 259
 260 /* Config3 Register bits */
 261 #define CP0C3_M                 31
 262 #define CP0C3_ISA_ON_EXC        16
 263 #define CP0C3_ULRI              13
 264 #define CP0C3_DSPP              10
 265 #define CP0C3_LPA               7
 266 #define CP0C3_VEIC              6
 267 #define CP0C3_VInt              5
 268 #define CP0C3_SP                4
 269 #define CP0C3_MT                2
 270 #define CP0C3_SM                1
 271 #define CP0C3_TL                0
 272
 273 /* MMU types, the first four entries have the same layout as the
 274    CP0C0_MT field.  */
 275 enum mips_mmu_types {
 276         MMU_TYPE_NONE,
 277         MMU_TYPE_R4000,
 278         MMU_TYPE_RESERVED,
 279         MMU_TYPE_FMT,
 280         MMU_TYPE_R3000,
 281         MMU_TYPE_R6000,
 282         MMU_TYPE_R8000
 283 };
 284
 285 /* Resume Flags */
 286 #define RESUME_FLAG_DR          (1<<0)  /* Reload guest nonvolatile state? */
 287 #define RESUME_FLAG_HOST        (1<<1)  /* Resume host? */
 288
 289 #define RESUME_GUEST            0
 290 #define RESUME_GUEST_DR         RESUME_FLAG_DR
 291 #define RESUME_HOST             RESUME_FLAG_HOST
 292
 293 enum emulation_result {
 294         EMULATE_DONE,           /* no further processing */
 295         EMULATE_DO_MMIO,        /* kvm_run filled with MMIO request */
 296         EMULATE_FAIL,           /* can't emulate this instruction */
 297         EMULATE_WAIT,           /* WAIT instruction */
 298         EMULATE_PRIV_FAIL,
 299 };
 300
 301 #define MIPS3_PG_G      0x00000001 /* Global; ignore ASID if in lo0 & lo1 */
 302 #define MIPS3_PG_V      0x00000002 /* Valid */
 303 #define MIPS3_PG_NV     0x00000000
 304 #define MIPS3_PG_D      0x00000004 /* Dirty */
 305
 306 #define mips3_paddr_to_tlbpfn(x) \
 307         (((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
 308 #define mips3_tlbpfn_to_paddr(x) \
 309         ((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
 310
 311 #define MIPS3_PG_SHIFT          6
 312 #define MIPS3_PG_FRAME          0x3fffffc0
 313
 314 #define VPN2_MASK               0xffffe000
 315 #define KVM_ENTRYHI_ASID        MIPS_ENTRYHI_ASID
 316 #define TLB_IS_GLOBAL(x)        (((x).tlb_lo0 & MIPS3_PG_G) &&          \
 317                                  ((x).tlb_lo1 & MIPS3_PG_G))
 318 #define TLB_VPN2(x)             ((x).tlb_hi & VPN2_MASK)
 319 #define TLB_ASID(x)             ((x).tlb_hi & KVM_ENTRYHI_ASID)
 320 #define TLB_IS_VALID(x, va)     (((va) & (1 << PAGE_SHIFT))             \
 321                                  ? ((x).tlb_lo1 & MIPS3_PG_V)           \
 322                                  : ((x).tlb_lo0 & MIPS3_PG_V))
 323 #define TLB_HI_VPN2_HIT(x, y)   ((TLB_VPN2(x) & ~(x).tlb_mask) ==       \
 324                                  ((y) & VPN2_MASK & ~(x).tlb_mask))
 325 #define TLB_HI_ASID_HIT(x, y)   (TLB_IS_GLOBAL(x) ||                    \
 326                                  TLB_ASID(x) == ((y) & KVM_ENTRYHI_ASID))
 327
 328 struct kvm_mips_tlb {
 329         long tlb_mask;
 330         long tlb_hi;
 331         long tlb_lo0;
 332         long tlb_lo1;
 333 };
 334
 335 #define KVM_MIPS_FPU_FPU        0x1
 336 #define KVM_MIPS_FPU_MSA        0x2
 337
 338 #define KVM_MIPS_GUEST_TLB_SIZE 64
 339 struct kvm_vcpu_arch {
 340         void *host_ebase, *guest_ebase;
 341         unsigned long host_stack;
 342         unsigned long host_gp;
 343
 344         /* Host CP0 registers used when handling exits from guest */
 345         unsigned long host_cp0_badvaddr;
 346         unsigned long host_cp0_cause;
 347         unsigned long host_cp0_epc;
 348         unsigned long host_cp0_entryhi;
 349         uint32_t guest_inst;
 350
 351         /* GPRS */
 352         unsigned long gprs[32];
 353         unsigned long hi;
 354         unsigned long lo;
 355         unsigned long pc;
 356
 357         /* FPU State */
 358         struct mips_fpu_struct fpu;
 359         /* Which FPU state is loaded (KVM_MIPS_FPU_*) */
 360         unsigned int fpu_inuse;
 361
 362         /* COP0 State */
 363         struct mips_coproc *cop0;
 364
 365         /* Host KSEG0 address of the EI/DI offset */
 366         void *kseg0_commpage;
 367
 368         u32 io_gpr;             /* GPR used as IO source/target */
 369
 370         struct hrtimer comparecount_timer;
 371         /* Count timer control KVM register */
 372         uint32_t count_ctl;
 373         /* Count bias from the raw time */
 374         uint32_t count_bias;
 375         /* Frequency of timer in Hz */
 376         uint32_t count_hz;
 377         /* Dynamic nanosecond bias (multiple of count_period) to avoid overflow */
 378         s64 count_dyn_bias;
 379         /* Resume time */
 380         ktime_t count_resume;
 381         /* Period of timer tick in ns */
 382         u64 count_period;
 383
 384         /* Bitmask of exceptions that are pending */
 385         unsigned long pending_exceptions;
 386
 387         /* Bitmask of pending exceptions to be cleared */
 388         unsigned long pending_exceptions_clr;
 389
 390         unsigned long pending_load_cause;
 391
 392         /* Save/Restore the entryhi register when are are preempted/scheduled back in */
 393         unsigned long preempt_entryhi;
 394
 395         /* S/W Based TLB for guest */
 396         struct kvm_mips_tlb guest_tlb[KVM_MIPS_GUEST_TLB_SIZE];
 397
 398         /* Cached guest kernel/user ASIDs */
 399         uint32_t guest_user_asid[NR_CPUS];
 400         uint32_t guest_kernel_asid[NR_CPUS];
 401         struct mm_struct guest_kernel_mm, guest_user_mm;
 402
 403         int last_sched_cpu;
 404
 405         /* WAIT executed */
 406         int wait;
 407
 408         u8 fpu_enabled;
 409         u8 msa_enabled;
 410 };
 411
 412
 413 #define kvm_read_c0_guest_index(cop0)           (cop0->reg[MIPS_CP0_TLB_INDEX][0])
 414 #define kvm_write_c0_guest_index(cop0, val)     (cop0->reg[MIPS_CP0_TLB_INDEX][0] = val)
 415 #define kvm_read_c0_guest_entrylo0(cop0)        (cop0->reg[MIPS_CP0_TLB_LO0][0])
 416 #define kvm_read_c0_guest_entrylo1(cop0)        (cop0->reg[MIPS_CP0_TLB_LO1][0])
 417 #define kvm_read_c0_guest_context(cop0)         (cop0->reg[MIPS_CP0_TLB_CONTEXT][0])
 418 #define kvm_write_c0_guest_context(cop0, val)   (cop0->reg[MIPS_CP0_TLB_CONTEXT][0] = (val))
 419 #define kvm_read_c0_guest_userlocal(cop0)       (cop0->reg[MIPS_CP0_TLB_CONTEXT][2])
 420 #define kvm_write_c0_guest_userlocal(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2] = (val))
 421 #define kvm_read_c0_guest_pagemask(cop0)        (cop0->reg[MIPS_CP0_TLB_PG_MASK][0])
 422 #define kvm_write_c0_guest_pagemask(cop0, val)  (cop0->reg[MIPS_CP0_TLB_PG_MASK][0] = (val))
 423 #define kvm_read_c0_guest_wired(cop0)           (cop0->reg[MIPS_CP0_TLB_WIRED][0])
 424 #define kvm_write_c0_guest_wired(cop0, val)     (cop0->reg[MIPS_CP0_TLB_WIRED][0] = (val))
 425 #define kvm_read_c0_guest_hwrena(cop0)          (cop0->reg[MIPS_CP0_HWRENA][0])
 426 #define kvm_write_c0_guest_hwrena(cop0, val)    (cop0->reg[MIPS_CP0_HWRENA][0] = (val))
 427 #define kvm_read_c0_guest_badvaddr(cop0)        (cop0->reg[MIPS_CP0_BAD_VADDR][0])
 428 #define kvm_write_c0_guest_badvaddr(cop0, val)  (cop0->reg[MIPS_CP0_BAD_VADDR][0] = (val))
 429 #define kvm_read_c0_guest_count(cop0)           (cop0->reg[MIPS_CP0_COUNT][0])
 430 #define kvm_write_c0_guest_count(cop0, val)     (cop0->reg[MIPS_CP0_COUNT][0] = (val))
 431 #define kvm_read_c0_guest_entryhi(cop0)         (cop0->reg[MIPS_CP0_TLB_HI][0])
 432 #define kvm_write_c0_guest_entryhi(cop0, val)   (cop0->reg[MIPS_CP0_TLB_HI][0] = (val))
 433 #define kvm_read_c0_guest_compare(cop0)         (cop0->reg[MIPS_CP0_COMPARE][0])
 434 #define kvm_write_c0_guest_compare(cop0, val)   (cop0->reg[MIPS_CP0_COMPARE][0] = (val))
 435 #define kvm_read_c0_guest_status(cop0)          (cop0->reg[MIPS_CP0_STATUS][0])
 436 #define kvm_write_c0_guest_status(cop0, val)    (cop0->reg[MIPS_CP0_STATUS][0] = (val))
 437 #define kvm_read_c0_guest_intctl(cop0)          (cop0->reg[MIPS_CP0_STATUS][1])
 438 #define kvm_write_c0_guest_intctl(cop0, val)    (cop0->reg[MIPS_CP0_STATUS][1] = (val))
 439 #define kvm_read_c0_guest_cause(cop0)           (cop0->reg[MIPS_CP0_CAUSE][0])
 440 #define kvm_write_c0_guest_cause(cop0, val)     (cop0->reg[MIPS_CP0_CAUSE][0] = (val))
 441 #define kvm_read_c0_guest_epc(cop0)             (cop0->reg[MIPS_CP0_EXC_PC][0])
 442 #define kvm_write_c0_guest_epc(cop0, val)       (cop0->reg[MIPS_CP0_EXC_PC][0] = (val))
 443 #define kvm_read_c0_guest_prid(cop0)            (cop0->reg[MIPS_CP0_PRID][0])
 444 #define kvm_write_c0_guest_prid(cop0, val)      (cop0->reg[MIPS_CP0_PRID][0] = (val))
 445 #define kvm_read_c0_guest_ebase(cop0)           (cop0->reg[MIPS_CP0_PRID][1])
 446 #define kvm_write_c0_guest_ebase(cop0, val)     (cop0->reg[MIPS_CP0_PRID][1] = (val))
 447 #define kvm_read_c0_guest_config(cop0)          (cop0->reg[MIPS_CP0_CONFIG][0])
 448 #define kvm_read_c0_guest_config1(cop0)         (cop0->reg[MIPS_CP0_CONFIG][1])
 449 #define kvm_read_c0_guest_config2(cop0)         (cop0->reg[MIPS_CP0_CONFIG][2])
 450 #define kvm_read_c0_guest_config3(cop0)         (cop0->reg[MIPS_CP0_CONFIG][3])
 451 #define kvm_read_c0_guest_config4(cop0)         (cop0->reg[MIPS_CP0_CONFIG][4])
 452 #define kvm_read_c0_guest_config5(cop0)         (cop0->reg[MIPS_CP0_CONFIG][5])
 453 #define kvm_read_c0_guest_config7(cop0)         (cop0->reg[MIPS_CP0_CONFIG][7])
 454 #define kvm_write_c0_guest_config(cop0, val)    (cop0->reg[MIPS_CP0_CONFIG][0] = (val))
 455 #define kvm_write_c0_guest_config1(cop0, val)   (cop0->reg[MIPS_CP0_CONFIG][1] = (val))
 456 #define kvm_write_c0_guest_config2(cop0, val)   (cop0->reg[MIPS_CP0_CONFIG][2] = (val))
 457 #define kvm_write_c0_guest_config3(cop0, val)   (cop0->reg[MIPS_CP0_CONFIG][3] = (val))
 458 #define kvm_write_c0_guest_config4(cop0, val)   (cop0->reg[MIPS_CP0_CONFIG][4] = (val))
 459 #define kvm_write_c0_guest_config5(cop0, val)   (cop0->reg[MIPS_CP0_CONFIG][5] = (val))
 460 #define kvm_write_c0_guest_config7(cop0, val)   (cop0->reg[MIPS_CP0_CONFIG][7] = (val))
 461 #define kvm_read_c0_guest_errorepc(cop0)        (cop0->reg[MIPS_CP0_ERROR_PC][0])
 462 #define kvm_write_c0_guest_errorepc(cop0, val)  (cop0->reg[MIPS_CP0_ERROR_PC][0] = (val))
 463
 464 /*
 465  * Some of the guest registers may be modified asynchronously (e.g. from a
 466  * hrtimer callback in hard irq context) and therefore need stronger atomicity
 467  * guarantees than other registers.
 468  */
 469
 470 static inline void _kvm_atomic_set_c0_guest_reg(unsigned long *reg,
 471                                                 unsigned long val)
 472 {
 473         unsigned long temp;
 474         do {
 475                 __asm__ __volatile__(
 476                 "       .set    mips3                           \n"
 477                 "       " __LL "%0, %1                          \n"
 478                 "       or      %0, %2                          \n"
 479                 "       " __SC  "%0, %1                         \n"
 480                 "       .set    mips0                           \n"
 481                 : "=&r" (temp), "+m" (*reg)
 482                 : "r" (val));
 483         } while (unlikely(!temp));
 484 }
 485
 486 static inline void _kvm_atomic_clear_c0_guest_reg(unsigned long *reg,
 487                                                   unsigned long val)
 488 {
 489         unsigned long temp;
 490         do {
 491                 __asm__ __volatile__(
 492                 "       .set    mips3                           \n"
 493                 "       " __LL "%0, %1                          \n"
 494                 "       and     %0, %2                          \n"
 495                 "       " __SC  "%0, %1                         \n"
 496                 "       .set    mips0                           \n"
 497                 : "=&r" (temp), "+m" (*reg)
 498                 : "r" (~val));
 499         } while (unlikely(!temp));
 500 }
 501
 502 static inline void _kvm_atomic_change_c0_guest_reg(unsigned long *reg,
 503                                                    unsigned long change,
 504                                                    unsigned long val)
 505 {
 506         unsigned long temp;
 507         do {
 508                 __asm__ __volatile__(
 509                 "       .set    mips3                           \n"
 510                 "       " __LL "%0, %1                          \n"
 511                 "       and     %0, %2                          \n"
 512                 "       or      %0, %3                          \n"
 513                 "       " __SC  "%0, %1                         \n"
 514                 "       .set    mips0                           \n"
 515                 : "=&r" (temp), "+m" (*reg)
 516                 : "r" (~change), "r" (val & change));
 517         } while (unlikely(!temp));
 518 }
 519
 520 #define kvm_set_c0_guest_status(cop0, val)      (cop0->reg[MIPS_CP0_STATUS][0] |= (val))
 521 #define kvm_clear_c0_guest_status(cop0, val)    (cop0->reg[MIPS_CP0_STATUS][0] &= ~(val))
 522
 523 /* Cause can be modified asynchronously from hardirq hrtimer callback */
 524 #define kvm_set_c0_guest_cause(cop0, val)                               \
 525         _kvm_atomic_set_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)
 526 #define kvm_clear_c0_guest_cause(cop0, val)                             \
 527         _kvm_atomic_clear_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)
 528 #define kvm_change_c0_guest_cause(cop0, change, val)                    \
 529         _kvm_atomic_change_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0],  \
 530                                         change, val)
 531
 532 #define kvm_set_c0_guest_ebase(cop0, val)       (cop0->reg[MIPS_CP0_PRID][1] |= (val))
 533 #define kvm_clear_c0_guest_ebase(cop0, val)     (cop0->reg[MIPS_CP0_PRID][1] &= ~(val))
 534 #define kvm_change_c0_guest_ebase(cop0, change, val)                    \
 535 {                                                                       \
 536         kvm_clear_c0_guest_ebase(cop0, change);                         \
 537         kvm_set_c0_guest_ebase(cop0, ((val) & (change)));               \
 538 }
 539
 540 /* Helpers */
 541
 542 static inline bool kvm_mips_guest_can_have_fpu(struct kvm_vcpu_arch *vcpu)
 543 {
 544         return (!__builtin_constant_p(cpu_has_fpu) || cpu_has_fpu) &&
 545                 vcpu->fpu_enabled;
 546 }
 547
 548 static inline bool kvm_mips_guest_has_fpu(struct kvm_vcpu_arch *vcpu)
 549 {
 550         return kvm_mips_guest_can_have_fpu(vcpu) &&
 551                 kvm_read_c0_guest_config1(vcpu->cop0) & MIPS_CONF1_FP;
 552 }
 553
 554 static inline bool kvm_mips_guest_can_have_msa(struct kvm_vcpu_arch *vcpu)
 555 {
 556         return (!__builtin_constant_p(cpu_has_msa) || cpu_has_msa) &&
 557                 vcpu->msa_enabled;
 558 }
 559
 560 static inline bool kvm_mips_guest_has_msa(struct kvm_vcpu_arch *vcpu)
 561 {
 562         return kvm_mips_guest_can_have_msa(vcpu) &&
 563                 kvm_read_c0_guest_config3(vcpu->cop0) & MIPS_CONF3_MSA;
 564 }
 565
 566 struct kvm_mips_callbacks {
 567         int (*handle_cop_unusable)(struct kvm_vcpu *vcpu);
 568         int (*handle_tlb_mod)(struct kvm_vcpu *vcpu);
 569         int (*handle_tlb_ld_miss)(struct kvm_vcpu *vcpu);
 570         int (*handle_tlb_st_miss)(struct kvm_vcpu *vcpu);
 571         int (*handle_addr_err_st)(struct kvm_vcpu *vcpu);
 572         int (*handle_addr_err_ld)(struct kvm_vcpu *vcpu);
 573         int (*handle_syscall)(struct kvm_vcpu *vcpu);
 574         int (*handle_res_inst)(struct kvm_vcpu *vcpu);
 575         int (*handle_break)(struct kvm_vcpu *vcpu);
 576         int (*handle_trap)(struct kvm_vcpu *vcpu);
 577         int (*handle_msa_fpe)(struct kvm_vcpu *vcpu);
 578         int (*handle_fpe)(struct kvm_vcpu *vcpu);
 579         int (*handle_msa_disabled)(struct kvm_vcpu *vcpu);
 580         int (*vm_init)(struct kvm *kvm);
 581         int (*vcpu_init)(struct kvm_vcpu *vcpu);
 582         int (*vcpu_setup)(struct kvm_vcpu *vcpu);
 583         gpa_t (*gva_to_gpa)(gva_t gva);
 584         void (*queue_timer_int)(struct kvm_vcpu *vcpu);
 585         void (*dequeue_timer_int)(struct kvm_vcpu *vcpu);
 586         void (*queue_io_int)(struct kvm_vcpu *vcpu,
 587                              struct kvm_mips_interrupt *irq);
 588         void (*dequeue_io_int)(struct kvm_vcpu *vcpu,
 589                                struct kvm_mips_interrupt *irq);
 590         int (*irq_deliver)(struct kvm_vcpu *vcpu, unsigned int priority,
 591                            uint32_t cause);
 592         int (*irq_clear)(struct kvm_vcpu *vcpu, unsigned int priority,
 593                          uint32_t cause);
 594         int (*get_one_reg)(struct kvm_vcpu *vcpu,
 595                            const struct kvm_one_reg *reg, s64 *v);
 596         int (*set_one_reg)(struct kvm_vcpu *vcpu,
 597                            const struct kvm_one_reg *reg, s64 v);
 598         int (*vcpu_get_regs)(struct kvm_vcpu *vcpu);
 599         int (*vcpu_set_regs)(struct kvm_vcpu *vcpu);
 600 };
 601 extern struct kvm_mips_callbacks *kvm_mips_callbacks;
 602 int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks);
 603
 604 /* Debug: dump vcpu state */
 605 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu);
 606
 607 /* Trampoline ASM routine to start running in "Guest" context */
 608 extern int __kvm_mips_vcpu_run(struct kvm_run *run, struct kvm_vcpu *vcpu);
 609
 610 /* FPU/MSA context management */
 611 void __kvm_save_fpu(struct kvm_vcpu_arch *vcpu);
 612 void __kvm_restore_fpu(struct kvm_vcpu_arch *vcpu);
 613 void __kvm_restore_fcsr(struct kvm_vcpu_arch *vcpu);
 614 void __kvm_save_msa(struct kvm_vcpu_arch *vcpu);
 615 void __kvm_restore_msa(struct kvm_vcpu_arch *vcpu);
 616 void __kvm_restore_msa_upper(struct kvm_vcpu_arch *vcpu);
 617 void __kvm_restore_msacsr(struct kvm_vcpu_arch *vcpu);
 618 void kvm_own_fpu(struct kvm_vcpu *vcpu);
 619 void kvm_own_msa(struct kvm_vcpu *vcpu);
 620 void kvm_drop_fpu(struct kvm_vcpu *vcpu);
 621 void kvm_lose_fpu(struct kvm_vcpu *vcpu);
 622
 623 /* TLB handling */
 624 uint32_t kvm_get_kernel_asid(struct kvm_vcpu *vcpu);
 625
 626 uint32_t kvm_get_user_asid(struct kvm_vcpu *vcpu);
 627
 628 uint32_t kvm_get_commpage_asid (struct kvm_vcpu *vcpu);
 629
 630 extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr,
 631                                            struct kvm_vcpu *vcpu);
 632
 633 extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr,
 634                                               struct kvm_vcpu *vcpu);
 635
 636 extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu,
 637                                                 struct kvm_mips_tlb *tlb,
 638                                                 unsigned long *hpa0,
 639                                                 unsigned long *hpa1);
 640
 641 extern enum emulation_result kvm_mips_handle_tlbmiss(unsigned long cause,
 642                                                      uint32_t *opc,
 643                                                      struct kvm_run *run,
 644                                                      struct kvm_vcpu *vcpu);
 645
 646 extern enum emulation_result kvm_mips_handle_tlbmod(unsigned long cause,
 647                                                     uint32_t *opc,
 648                                                     struct kvm_run *run,
 649                                                     struct kvm_vcpu *vcpu);
 650
 651 extern void kvm_mips_dump_host_tlbs(void);
 652 extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu);
 653 extern void kvm_mips_flush_host_tlb(int skip_kseg0);
 654 extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi);
 655
 656 extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu,
 657                                      unsigned long entryhi);
 658 extern int kvm_mips_host_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long vaddr);
 659 extern unsigned long kvm_mips_translate_guest_kseg0_to_hpa(struct kvm_vcpu *vcpu,
 660                                                    unsigned long gva);
 661 extern void kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu,
 662                                     struct kvm_vcpu *vcpu);
 663 extern void kvm_local_flush_tlb_all(void);
 664 extern void kvm_mips_alloc_new_mmu_context(struct kvm_vcpu *vcpu);
 665 extern void kvm_mips_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
 666 extern void kvm_mips_vcpu_put(struct kvm_vcpu *vcpu);
 667
 668 /* Emulation */
 669 uint32_t kvm_get_inst(uint32_t *opc, struct kvm_vcpu *vcpu);
 670 enum emulation_result update_pc(struct kvm_vcpu *vcpu, uint32_t cause);
 671
 672 extern enum emulation_result kvm_mips_emulate_inst(unsigned long cause,
 673                                                    uint32_t *opc,
 674                                                    struct kvm_run *run,
 675                                                    struct kvm_vcpu *vcpu);
 676
 677 extern enum emulation_result kvm_mips_emulate_syscall(unsigned long cause,
 678                                                       uint32_t *opc,
 679                                                       struct kvm_run *run,
 680                                                       struct kvm_vcpu *vcpu);
 681
 682 extern enum emulation_result kvm_mips_emulate_tlbmiss_ld(unsigned long cause,
 683                                                          uint32_t *opc,
 684                                                          struct kvm_run *run,
 685                                                          struct kvm_vcpu *vcpu);
 686
 687 extern enum emulation_result kvm_mips_emulate_tlbinv_ld(unsigned long cause,
 688                                                         uint32_t *opc,
 689                                                         struct kvm_run *run,
 690                                                         struct kvm_vcpu *vcpu);
 691
 692 extern enum emulation_result kvm_mips_emulate_tlbmiss_st(unsigned long cause,
 693                                                          uint32_t *opc,
 694                                                          struct kvm_run *run,
 695                                                          struct kvm_vcpu *vcpu);
 696
 697 extern enum emulation_result kvm_mips_emulate_tlbinv_st(unsigned long cause,
 698                                                         uint32_t *opc,
 699                                                         struct kvm_run *run,
 700                                                         struct kvm_vcpu *vcpu);
 701
 702 extern enum emulation_result kvm_mips_emulate_tlbmod(unsigned long cause,
 703                                                      uint32_t *opc,
 704                                                      struct kvm_run *run,
 705                                                      struct kvm_vcpu *vcpu);
 706
 707 extern enum emulation_result kvm_mips_emulate_fpu_exc(unsigned long cause,
 708                                                       uint32_t *opc,
 709                                                       struct kvm_run *run,
 710                                                       struct kvm_vcpu *vcpu);
 711
 712 extern enum emulation_result kvm_mips_handle_ri(unsigned long cause,
 713                                                 uint32_t *opc,
 714                                                 struct kvm_run *run,
 715                                                 struct kvm_vcpu *vcpu);
 716
 717 extern enum emulation_result kvm_mips_emulate_ri_exc(unsigned long cause,
 718                                                      uint32_t *opc,
 719                                                      struct kvm_run *run,
 720                                                      struct kvm_vcpu *vcpu);
 721
 722 extern enum emulation_result kvm_mips_emulate_bp_exc(unsigned long cause,
 723                                                      uint32_t *opc,
 724                                                      struct kvm_run *run,
 725                                                      struct kvm_vcpu *vcpu);
 726
 727 extern enum emulation_result kvm_mips_emulate_trap_exc(unsigned long cause,
 728                                                        uint32_t *opc,
 729                                                        struct kvm_run *run,
 730                                                        struct kvm_vcpu *vcpu);
 731
 732 extern enum emulation_result kvm_mips_emulate_msafpe_exc(unsigned long cause,
 733                                                          uint32_t *opc,
 734                                                          struct kvm_run *run,
 735                                                          struct kvm_vcpu *vcpu);
 736
 737 extern enum emulation_result kvm_mips_emulate_fpe_exc(unsigned long cause,
 738                                                       uint32_t *opc,
 739                                                       struct kvm_run *run,
 740                                                       struct kvm_vcpu *vcpu);
 741
 742 extern enum emulation_result kvm_mips_emulate_msadis_exc(unsigned long cause,
 743                                                          uint32_t *opc,
 744                                                          struct kvm_run *run,
 745                                                          struct kvm_vcpu *vcpu);
 746
 747 extern enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu,
 748                                                          struct kvm_run *run);
 749
 750 uint32_t kvm_mips_read_count(struct kvm_vcpu *vcpu);
 751 void kvm_mips_write_count(struct kvm_vcpu *vcpu, uint32_t count);
 752 void kvm_mips_write_compare(struct kvm_vcpu *vcpu, uint32_t compare, bool ack);
 753 void kvm_mips_init_count(struct kvm_vcpu *vcpu);
 754 int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl);
 755 int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume);
 756 int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz);
 757 void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu);
 758 void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu);
 759 enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu);
 760
 761 enum emulation_result kvm_mips_check_privilege(unsigned long cause,
 762                                                uint32_t *opc,
 763                                                struct kvm_run *run,
 764                                                struct kvm_vcpu *vcpu);
 765
 766 enum emulation_result kvm_mips_emulate_cache(uint32_t inst,
 767                                              uint32_t *opc,
 768                                              uint32_t cause,
 769                                              struct kvm_run *run,
 770                                              struct kvm_vcpu *vcpu);
 771 enum emulation_result kvm_mips_emulate_CP0(uint32_t inst,
 772                                            uint32_t *opc,
 773                                            uint32_t cause,
 774                                            struct kvm_run *run,
 775                                            struct kvm_vcpu *vcpu);
 776 enum emulation_result kvm_mips_emulate_store(uint32_t inst,
 777                                              uint32_t cause,
 778                                              struct kvm_run *run,
 779                                              struct kvm_vcpu *vcpu);
 780 enum emulation_result kvm_mips_emulate_load(uint32_t inst,
 781                                             uint32_t cause,
 782                                             struct kvm_run *run,
 783                                             struct kvm_vcpu *vcpu);
 784
 785 unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu);
 786 unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu *vcpu);
 787 unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu);
 788 unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu);
 789
 790 /* Dynamic binary translation */
 791 extern int kvm_mips_trans_cache_index(uint32_t inst, uint32_t *opc,
 792                                       struct kvm_vcpu *vcpu);
 793 extern int kvm_mips_trans_cache_va(uint32_t inst, uint32_t *opc,
 794                                    struct kvm_vcpu *vcpu);
 795 extern int kvm_mips_trans_mfc0(uint32_t inst, uint32_t *opc,
 796                                struct kvm_vcpu *vcpu);
 797 extern int kvm_mips_trans_mtc0(uint32_t inst, uint32_t *opc,
 798                                struct kvm_vcpu *vcpu);
 799
 800 /* Misc */
 801 extern void kvm_mips_dump_stats(struct kvm_vcpu *vcpu);
 802 extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm);
 803
 804 static inline void kvm_arch_hardware_disable(void) {}
 805 static inline void kvm_arch_hardware_unsetup(void) {}
 806 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
 807 static inline void kvm_arch_free_memslot(struct kvm *kvm,
 808                 struct kvm_memory_slot *free, struct kvm_memory_slot *dont) {}
 809 static inline void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots) {}
 810 static inline void kvm_arch_flush_shadow_all(struct kvm *kvm) {}
 811 static inline void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
 812                 struct kvm_memory_slot *slot) {}
 813 static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {}
 814 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
 815 static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) {}
 816 static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) {}
 817 static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {}
 818
 819 #endif /* __MIPS_KVM_HOST_H__ */