arch/mips/include/asm/mipsregs.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
   7  * Copyright (C) 2000 Silicon Graphics, Inc.
   8  * Modified for further R[236]000 support by Paul M. Antoine, 1996.
   9  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  10  * Copyright (C) 2000, 07 MIPS Technologies, Inc.
  11  * Copyright (C) 2003, 2004  Maciej W. Rozycki
  12  */
  13 #ifndef _ASM_MIPSREGS_H
  14 #define _ASM_MIPSREGS_H
  15
  16 #include <linux/linkage.h>
  17 #include <linux/types.h>
  18 #include <asm/hazards.h>
  19 #include <asm/war.h>
  20
  21 /*
  22  * The following macros are especially useful for __asm__
  23  * inline assembler.
  24  */
  25 #ifndef __STR
  26 #define __STR(x) #x
  27 #endif
  28 #ifndef STR
  29 #define STR(x) __STR(x)
  30 #endif
  31
  32 /*
  33  *  Configure language
  34  */
  35 #ifdef __ASSEMBLY__
  36 #define _ULCAST_
  37 #else
  38 #define _ULCAST_ (unsigned long)
  39 #endif
  40
  41 /*
  42  * Coprocessor 0 register names
  43  */
  44 #define CP0_INDEX $0
  45 #define CP0_RANDOM $1
  46 #define CP0_ENTRYLO0 $2
  47 #define CP0_ENTRYLO1 $3
  48 #define CP0_CONF $3
  49 #define CP0_CONTEXT $4
  50 #define CP0_PAGEMASK $5
  51 #define CP0_SEGCTL0 $5, 2
  52 #define CP0_SEGCTL1 $5, 3
  53 #define CP0_SEGCTL2 $5, 4
  54 #define CP0_WIRED $6
  55 #define CP0_INFO $7
  56 #define CP0_HWRENA $7, 0
  57 #define CP0_BADVADDR $8
  58 #define CP0_BADINSTR $8, 1
  59 #define CP0_COUNT $9
  60 #define CP0_ENTRYHI $10
  61 #define CP0_GUESTCTL1 $10, 4
  62 #define CP0_GUESTCTL2 $10, 5
  63 #define CP0_GUESTCTL3 $10, 6
  64 #define CP0_COMPARE $11
  65 #define CP0_GUESTCTL0EXT $11, 4
  66 #define CP0_STATUS $12
  67 #define CP0_GUESTCTL0 $12, 6
  68 #define CP0_GTOFFSET $12, 7
  69 #define CP0_CAUSE $13
  70 #define CP0_EPC $14
  71 #define CP0_PRID $15
  72 #define CP0_EBASE $15, 1
  73 #define CP0_CMGCRBASE $15, 3
  74 #define CP0_CONFIG $16
  75 #define CP0_CONFIG3 $16, 3
  76 #define CP0_CONFIG5 $16, 5
  77 #define CP0_LLADDR $17
  78 #define CP0_WATCHLO $18
  79 #define CP0_WATCHHI $19
  80 #define CP0_XCONTEXT $20
  81 #define CP0_FRAMEMASK $21
  82 #define CP0_DIAGNOSTIC $22
  83 #define CP0_DEBUG $23
  84 #define CP0_DEPC $24
  85 #define CP0_PERFORMANCE $25
  86 #define CP0_ECC $26
  87 #define CP0_CACHEERR $27
  88 #define CP0_TAGLO $28
  89 #define CP0_TAGHI $29
  90 #define CP0_ERROREPC $30
  91 #define CP0_DESAVE $31
  92
  93 /*
  94  * R4640/R4650 cp0 register names.  These registers are listed
  95  * here only for completeness; without MMU these CPUs are not useable
  96  * by Linux.  A future ELKS port might take make Linux run on them
  97  * though ...
  98  */
  99 #define CP0_IBASE $0
 100 #define CP0_IBOUND $1
 101 #define CP0_DBASE $2
 102 #define CP0_DBOUND $3
 103 #define CP0_CALG $17
 104 #define CP0_IWATCH $18
 105 #define CP0_DWATCH $19
 106
 107 /*
 108  * Coprocessor 0 Set 1 register names
 109  */
 110 #define CP0_S1_DERRADDR0  $26
 111 #define CP0_S1_DERRADDR1  $27
 112 #define CP0_S1_INTCONTROL $20
 113
 114 /*
 115  * Coprocessor 0 Set 2 register names
 116  */
 117 #define CP0_S2_SRSCTL     $12   /* MIPSR2 */
 118
 119 /*
 120  * Coprocessor 0 Set 3 register names
 121  */
 122 #define CP0_S3_SRSMAP     $12   /* MIPSR2 */
 123
 124 /*
 125  *  TX39 Series
 126  */
 127 #define CP0_TX39_CACHE  $7
 128
 129
 130 /* Generic EntryLo bit definitions */
 131 #define ENTRYLO_G               (_ULCAST_(1) << 0)
 132 #define ENTRYLO_V               (_ULCAST_(1) << 1)
 133 #define ENTRYLO_D               (_ULCAST_(1) << 2)
 134 #define ENTRYLO_C_SHIFT         3
 135 #define ENTRYLO_C               (_ULCAST_(7) << ENTRYLO_C_SHIFT)
 136
 137 /* R3000 EntryLo bit definitions */
 138 #define R3K_ENTRYLO_G           (_ULCAST_(1) << 8)
 139 #define R3K_ENTRYLO_V           (_ULCAST_(1) << 9)
 140 #define R3K_ENTRYLO_D           (_ULCAST_(1) << 10)
 141 #define R3K_ENTRYLO_N           (_ULCAST_(1) << 11)
 142
 143 /* MIPS32/64 EntryLo bit definitions */
 144 #define MIPS_ENTRYLO_PFN_SHIFT  6
 145 #define MIPS_ENTRYLO_XI         (_ULCAST_(1) << (BITS_PER_LONG - 2))
 146 #define MIPS_ENTRYLO_RI         (_ULCAST_(1) << (BITS_PER_LONG - 1))
 147
 148 /*
 149  * Values for PageMask register
 150  */
 151 #ifdef CONFIG_CPU_VR41XX
 152
 153 /* Why doesn't stupidity hurt ... */
 154
 155 #define PM_1K           0x00000000
 156 #define PM_4K           0x00001800
 157 #define PM_16K          0x00007800
 158 #define PM_64K          0x0001f800
 159 #define PM_256K         0x0007f800
 160
 161 #else
 162
 163 #define PM_4K           0x00000000
 164 #define PM_8K           0x00002000
 165 #define PM_16K          0x00006000
 166 #define PM_32K          0x0000e000
 167 #define PM_64K          0x0001e000
 168 #define PM_128K         0x0003e000
 169 #define PM_256K         0x0007e000
 170 #define PM_512K         0x000fe000
 171 #define PM_1M           0x001fe000
 172 #define PM_2M           0x003fe000
 173 #define PM_4M           0x007fe000
 174 #define PM_8M           0x00ffe000
 175 #define PM_16M          0x01ffe000
 176 #define PM_32M          0x03ffe000
 177 #define PM_64M          0x07ffe000
 178 #define PM_256M         0x1fffe000
 179 #define PM_1G           0x7fffe000
 180
 181 #endif
 182
 183 /*
 184  * Default page size for a given kernel configuration
 185  */
 186 #ifdef CONFIG_PAGE_SIZE_4KB
 187 #define PM_DEFAULT_MASK PM_4K
 188 #elif defined(CONFIG_PAGE_SIZE_8KB)
 189 #define PM_DEFAULT_MASK PM_8K
 190 #elif defined(CONFIG_PAGE_SIZE_16KB)
 191 #define PM_DEFAULT_MASK PM_16K
 192 #elif defined(CONFIG_PAGE_SIZE_32KB)
 193 #define PM_DEFAULT_MASK PM_32K
 194 #elif defined(CONFIG_PAGE_SIZE_64KB)
 195 #define PM_DEFAULT_MASK PM_64K
 196 #else
 197 #error Bad page size configuration!
 198 #endif
 199
 200 /*
 201  * Default huge tlb size for a given kernel configuration
 202  */
 203 #ifdef CONFIG_PAGE_SIZE_4KB
 204 #define PM_HUGE_MASK    PM_1M
 205 #elif defined(CONFIG_PAGE_SIZE_8KB)
 206 #define PM_HUGE_MASK    PM_4M
 207 #elif defined(CONFIG_PAGE_SIZE_16KB)
 208 #define PM_HUGE_MASK    PM_16M
 209 #elif defined(CONFIG_PAGE_SIZE_32KB)
 210 #define PM_HUGE_MASK    PM_64M
 211 #elif defined(CONFIG_PAGE_SIZE_64KB)
 212 #define PM_HUGE_MASK    PM_256M
 213 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
 214 #error Bad page size configuration for hugetlbfs!
 215 #endif
 216
 217 /*
 218  * Values used for computation of new tlb entries
 219  */
 220 #define PL_4K           12
 221 #define PL_16K          14
 222 #define PL_64K          16
 223 #define PL_256K         18
 224 #define PL_1M           20
 225 #define PL_4M           22
 226 #define PL_16M          24
 227 #define PL_64M          26
 228 #define PL_256M         28
 229
 230 /*
 231  * PageGrain bits
 232  */
 233 #define PG_RIE          (_ULCAST_(1) <<  31)
 234 #define PG_XIE          (_ULCAST_(1) <<  30)
 235 #define PG_ELPA         (_ULCAST_(1) <<  29)
 236 #define PG_ESP          (_ULCAST_(1) <<  28)
 237 #define PG_IEC          (_ULCAST_(1) <<  27)
 238
 239 /* MIPS32/64 EntryHI bit definitions */
 240 #define MIPS_ENTRYHI_EHINV      (_ULCAST_(1) << 10)
 241 #define MIPS_ENTRYHI_ASIDX      (_ULCAST_(0x3) << 8)
 242 #define MIPS_ENTRYHI_ASID       (_ULCAST_(0xff) << 0)
 243
 244 /*
 245  * R4x00 interrupt enable / cause bits
 246  */
 247 #define IE_SW0          (_ULCAST_(1) <<  8)
 248 #define IE_SW1          (_ULCAST_(1) <<  9)
 249 #define IE_IRQ0         (_ULCAST_(1) << 10)
 250 #define IE_IRQ1         (_ULCAST_(1) << 11)
 251 #define IE_IRQ2         (_ULCAST_(1) << 12)
 252 #define IE_IRQ3         (_ULCAST_(1) << 13)
 253 #define IE_IRQ4         (_ULCAST_(1) << 14)
 254 #define IE_IRQ5         (_ULCAST_(1) << 15)
 255
 256 /*
 257  * R4x00 interrupt cause bits
 258  */
 259 #define C_SW0           (_ULCAST_(1) <<  8)
 260 #define C_SW1           (_ULCAST_(1) <<  9)
 261 #define C_IRQ0          (_ULCAST_(1) << 10)
 262 #define C_IRQ1          (_ULCAST_(1) << 11)
 263 #define C_IRQ2          (_ULCAST_(1) << 12)
 264 #define C_IRQ3          (_ULCAST_(1) << 13)
 265 #define C_IRQ4          (_ULCAST_(1) << 14)
 266 #define C_IRQ5          (_ULCAST_(1) << 15)
 267
 268 /*
 269  * Bitfields in the R4xx0 cp0 status register
 270  */
 271 #define ST0_IE                  0x00000001
 272 #define ST0_EXL                 0x00000002
 273 #define ST0_ERL                 0x00000004
 274 #define ST0_KSU                 0x00000018
 275 #  define KSU_USER              0x00000010
 276 #  define KSU_SUPERVISOR        0x00000008
 277 #  define KSU_KERNEL            0x00000000
 278 #define ST0_UX                  0x00000020
 279 #define ST0_SX                  0x00000040
 280 #define ST0_KX                  0x00000080
 281 #define ST0_DE                  0x00010000
 282 #define ST0_CE                  0x00020000
 283
 284 /*
 285  * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
 286  * cacheops in userspace.  This bit exists only on RM7000 and RM9000
 287  * processors.
 288  */
 289 #define ST0_CO                  0x08000000
 290
 291 /*
 292  * Bitfields in the R[23]000 cp0 status register.
 293  */
 294 #define ST0_IEC                 0x00000001
 295 #define ST0_KUC                 0x00000002
 296 #define ST0_IEP                 0x00000004
 297 #define ST0_KUP                 0x00000008
 298 #define ST0_IEO                 0x00000010
 299 #define ST0_KUO                 0x00000020
 300 /* bits 6 & 7 are reserved on R[23]000 */
 301 #define ST0_ISC                 0x00010000
 302 #define ST0_SWC                 0x00020000
 303 #define ST0_CM                  0x00080000
 304
 305 /*
 306  * Bits specific to the R4640/R4650
 307  */
 308 #define ST0_UM                  (_ULCAST_(1) <<  4)
 309 #define ST0_IL                  (_ULCAST_(1) << 23)
 310 #define ST0_DL                  (_ULCAST_(1) << 24)
 311
 312 /*
 313  * Enable the MIPS MDMX and DSP ASEs
 314  */
 315 #define ST0_MX                  0x01000000
 316
 317 /*
 318  * Status register bits available in all MIPS CPUs.
 319  */
 320 #define ST0_IM                  0x0000ff00
 321 #define  STATUSB_IP0            8
 322 #define  STATUSF_IP0            (_ULCAST_(1) <<  8)
 323 #define  STATUSB_IP1            9
 324 #define  STATUSF_IP1            (_ULCAST_(1) <<  9)
 325 #define  STATUSB_IP2            10
 326 #define  STATUSF_IP2            (_ULCAST_(1) << 10)
 327 #define  STATUSB_IP3            11
 328 #define  STATUSF_IP3            (_ULCAST_(1) << 11)
 329 #define  STATUSB_IP4            12
 330 #define  STATUSF_IP4            (_ULCAST_(1) << 12)
 331 #define  STATUSB_IP5            13
 332 #define  STATUSF_IP5            (_ULCAST_(1) << 13)
 333 #define  STATUSB_IP6            14
 334 #define  STATUSF_IP6            (_ULCAST_(1) << 14)
 335 #define  STATUSB_IP7            15
 336 #define  STATUSF_IP7            (_ULCAST_(1) << 15)
 337 #define  STATUSB_IP8            0
 338 #define  STATUSF_IP8            (_ULCAST_(1) <<  0)
 339 #define  STATUSB_IP9            1
 340 #define  STATUSF_IP9            (_ULCAST_(1) <<  1)
 341 #define  STATUSB_IP10           2
 342 #define  STATUSF_IP10           (_ULCAST_(1) <<  2)
 343 #define  STATUSB_IP11           3
 344 #define  STATUSF_IP11           (_ULCAST_(1) <<  3)
 345 #define  STATUSB_IP12           4
 346 #define  STATUSF_IP12           (_ULCAST_(1) <<  4)
 347 #define  STATUSB_IP13           5
 348 #define  STATUSF_IP13           (_ULCAST_(1) <<  5)
 349 #define  STATUSB_IP14           6
 350 #define  STATUSF_IP14           (_ULCAST_(1) <<  6)
 351 #define  STATUSB_IP15           7
 352 #define  STATUSF_IP15           (_ULCAST_(1) <<  7)
 353 #define ST0_CH                  0x00040000
 354 #define ST0_NMI                 0x00080000
 355 #define ST0_SR                  0x00100000
 356 #define ST0_TS                  0x00200000
 357 #define ST0_BEV                 0x00400000
 358 #define ST0_RE                  0x02000000
 359 #define ST0_FR                  0x04000000
 360 #define ST0_CU                  0xf0000000
 361 #define ST0_CU0                 0x10000000
 362 #define ST0_CU1                 0x20000000
 363 #define ST0_CU2                 0x40000000
 364 #define ST0_CU3                 0x80000000
 365 #define ST0_XX                  0x80000000      /* MIPS IV naming */
 366
 367 /*
 368  * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
 369  */
 370 #define INTCTLB_IPFDC           23
 371 #define INTCTLF_IPFDC           (_ULCAST_(7) << INTCTLB_IPFDC)
 372 #define INTCTLB_IPPCI           26
 373 #define INTCTLF_IPPCI           (_ULCAST_(7) << INTCTLB_IPPCI)
 374 #define INTCTLB_IPTI            29
 375 #define INTCTLF_IPTI            (_ULCAST_(7) << INTCTLB_IPTI)
 376
 377 /*
 378  * Bitfields and bit numbers in the coprocessor 0 cause register.
 379  *
 380  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
 381  */
 382 #define CAUSEB_EXCCODE          2
 383 #define CAUSEF_EXCCODE          (_ULCAST_(31)  <<  2)
 384 #define CAUSEB_IP               8
 385 #define CAUSEF_IP               (_ULCAST_(255) <<  8)
 386 #define  CAUSEB_IP0             8
 387 #define  CAUSEF_IP0             (_ULCAST_(1)   <<  8)
 388 #define  CAUSEB_IP1             9
 389 #define  CAUSEF_IP1             (_ULCAST_(1)   <<  9)
 390 #define  CAUSEB_IP2             10
 391 #define  CAUSEF_IP2             (_ULCAST_(1)   << 10)
 392 #define  CAUSEB_IP3             11
 393 #define  CAUSEF_IP3             (_ULCAST_(1)   << 11)
 394 #define  CAUSEB_IP4             12
 395 #define  CAUSEF_IP4             (_ULCAST_(1)   << 12)
 396 #define  CAUSEB_IP5             13
 397 #define  CAUSEF_IP5             (_ULCAST_(1)   << 13)
 398 #define  CAUSEB_IP6             14
 399 #define  CAUSEF_IP6             (_ULCAST_(1)   << 14)
 400 #define  CAUSEB_IP7             15
 401 #define  CAUSEF_IP7             (_ULCAST_(1)   << 15)
 402 #define CAUSEB_FDCI             21
 403 #define CAUSEF_FDCI             (_ULCAST_(1)   << 21)
 404 #define CAUSEB_WP               22
 405 #define CAUSEF_WP               (_ULCAST_(1)   << 22)
 406 #define CAUSEB_IV               23
 407 #define CAUSEF_IV               (_ULCAST_(1)   << 23)
 408 #define CAUSEB_PCI              26
 409 #define CAUSEF_PCI              (_ULCAST_(1)   << 26)
 410 #define CAUSEB_DC               27
 411 #define CAUSEF_DC               (_ULCAST_(1)   << 27)
 412 #define CAUSEB_CE               28
 413 #define CAUSEF_CE               (_ULCAST_(3)   << 28)
 414 #define CAUSEB_TI               30
 415 #define CAUSEF_TI               (_ULCAST_(1)   << 30)
 416 #define CAUSEB_BD               31
 417 #define CAUSEF_BD               (_ULCAST_(1)   << 31)
 418
 419 /*
 420  * Cause.ExcCode trap codes.
 421  */
 422 #define EXCCODE_INT             0       /* Interrupt pending */
 423 #define EXCCODE_MOD             1       /* TLB modified fault */
 424 #define EXCCODE_TLBL            2       /* TLB miss on load or ifetch */
 425 #define EXCCODE_TLBS            3       /* TLB miss on a store */
 426 #define EXCCODE_ADEL            4       /* Address error on a load or ifetch */
 427 #define EXCCODE_ADES            5       /* Address error on a store */
 428 #define EXCCODE_IBE             6       /* Bus error on an ifetch */
 429 #define EXCCODE_DBE             7       /* Bus error on a load or store */
 430 #define EXCCODE_SYS             8       /* System call */
 431 #define EXCCODE_BP              9       /* Breakpoint */
 432 #define EXCCODE_RI              10      /* Reserved instruction exception */
 433 #define EXCCODE_CPU             11      /* Coprocessor unusable */
 434 #define EXCCODE_OV              12      /* Arithmetic overflow */
 435 #define EXCCODE_TR              13      /* Trap instruction */
 436 #define EXCCODE_MSAFPE          14      /* MSA floating point exception */
 437 #define EXCCODE_FPE             15      /* Floating point exception */
 438 #define EXCCODE_TLBRI           19      /* TLB Read-Inhibit exception */
 439 #define EXCCODE_TLBXI           20      /* TLB Execution-Inhibit exception */
 440 #define EXCCODE_MSADIS          21      /* MSA disabled exception */
 441 #define EXCCODE_MDMX            22      /* MDMX unusable exception */
 442 #define EXCCODE_WATCH           23      /* Watch address reference */
 443 #define EXCCODE_MCHECK          24      /* Machine check */
 444 #define EXCCODE_THREAD          25      /* Thread exceptions (MT) */
 445 #define EXCCODE_DSPDIS          26      /* DSP disabled exception */
 446 #define EXCCODE_GE              27      /* Virtualized guest exception (VZ) */
 447
 448 /* Implementation specific trap codes used by MIPS cores */
 449 #define MIPS_EXCCODE_TLBPAR     16      /* TLB parity error exception */
 450
 451 /*
 452  * Bits in the coprocessor 0 config register.
 453  */
 454 /* Generic bits.  */
 455 #define CONF_CM_CACHABLE_NO_WA          0
 456 #define CONF_CM_CACHABLE_WA             1
 457 #define CONF_CM_UNCACHED                2
 458 #define CONF_CM_CACHABLE_NONCOHERENT    3
 459 #define CONF_CM_CACHABLE_CE             4
 460 #define CONF_CM_CACHABLE_COW            5
 461 #define CONF_CM_CACHABLE_CUW            6
 462 #define CONF_CM_CACHABLE_ACCELERATED    7
 463 #define CONF_CM_CMASK                   7
 464 #define CONF_BE                 (_ULCAST_(1) << 15)
 465
 466 /* Bits common to various processors.  */
 467 #define CONF_CU                 (_ULCAST_(1) <<  3)
 468 #define CONF_DB                 (_ULCAST_(1) <<  4)
 469 #define CONF_IB                 (_ULCAST_(1) <<  5)
 470 #define CONF_DC                 (_ULCAST_(7) <<  6)
 471 #define CONF_IC                 (_ULCAST_(7) <<  9)
 472 #define CONF_EB                 (_ULCAST_(1) << 13)
 473 #define CONF_EM                 (_ULCAST_(1) << 14)
 474 #define CONF_SM                 (_ULCAST_(1) << 16)
 475 #define CONF_SC                 (_ULCAST_(1) << 17)
 476 #define CONF_EW                 (_ULCAST_(3) << 18)
 477 #define CONF_EP                 (_ULCAST_(15)<< 24)
 478 #define CONF_EC                 (_ULCAST_(7) << 28)
 479 #define CONF_CM                 (_ULCAST_(1) << 31)
 480
 481 /* Bits specific to the R4xx0.  */
 482 #define R4K_CONF_SW             (_ULCAST_(1) << 20)
 483 #define R4K_CONF_SS             (_ULCAST_(1) << 21)
 484 #define R4K_CONF_SB             (_ULCAST_(3) << 22)
 485
 486 /* Bits specific to the R5000.  */
 487 #define R5K_CONF_SE             (_ULCAST_(1) << 12)
 488 #define R5K_CONF_SS             (_ULCAST_(3) << 20)
 489
 490 /* Bits specific to the RM7000.  */
 491 #define RM7K_CONF_SE            (_ULCAST_(1) <<  3)
 492 #define RM7K_CONF_TE            (_ULCAST_(1) << 12)
 493 #define RM7K_CONF_CLK           (_ULCAST_(1) << 16)
 494 #define RM7K_CONF_TC            (_ULCAST_(1) << 17)
 495 #define RM7K_CONF_SI            (_ULCAST_(3) << 20)
 496 #define RM7K_CONF_SC            (_ULCAST_(1) << 31)
 497
 498 /* Bits specific to the R10000.  */
 499 #define R10K_CONF_DN            (_ULCAST_(3) <<  3)
 500 #define R10K_CONF_CT            (_ULCAST_(1) <<  5)
 501 #define R10K_CONF_PE            (_ULCAST_(1) <<  6)
 502 #define R10K_CONF_PM            (_ULCAST_(3) <<  7)
 503 #define R10K_CONF_EC            (_ULCAST_(15)<<  9)
 504 #define R10K_CONF_SB            (_ULCAST_(1) << 13)
 505 #define R10K_CONF_SK            (_ULCAST_(1) << 14)
 506 #define R10K_CONF_SS            (_ULCAST_(7) << 16)
 507 #define R10K_CONF_SC            (_ULCAST_(7) << 19)
 508 #define R10K_CONF_DC            (_ULCAST_(7) << 26)
 509 #define R10K_CONF_IC            (_ULCAST_(7) << 29)
 510
 511 /* Bits specific to the VR41xx.  */
 512 #define VR41_CONF_CS            (_ULCAST_(1) << 12)
 513 #define VR41_CONF_P4K           (_ULCAST_(1) << 13)
 514 #define VR41_CONF_BP            (_ULCAST_(1) << 16)
 515 #define VR41_CONF_M16           (_ULCAST_(1) << 20)
 516 #define VR41_CONF_AD            (_ULCAST_(1) << 23)
 517
 518 /* Bits specific to the R30xx.  */
 519 #define R30XX_CONF_FDM          (_ULCAST_(1) << 19)
 520 #define R30XX_CONF_REV          (_ULCAST_(1) << 22)
 521 #define R30XX_CONF_AC           (_ULCAST_(1) << 23)
 522 #define R30XX_CONF_RF           (_ULCAST_(1) << 24)
 523 #define R30XX_CONF_HALT         (_ULCAST_(1) << 25)
 524 #define R30XX_CONF_FPINT        (_ULCAST_(7) << 26)
 525 #define R30XX_CONF_DBR          (_ULCAST_(1) << 29)
 526 #define R30XX_CONF_SB           (_ULCAST_(1) << 30)
 527 #define R30XX_CONF_LOCK         (_ULCAST_(1) << 31)
 528
 529 /* Bits specific to the TX49.  */
 530 #define TX49_CONF_DC            (_ULCAST_(1) << 16)
 531 #define TX49_CONF_IC            (_ULCAST_(1) << 17)  /* conflict with CONF_SC */
 532 #define TX49_CONF_HALT          (_ULCAST_(1) << 18)
 533 #define TX49_CONF_CWFON         (_ULCAST_(1) << 27)
 534
 535 /* Bits specific to the MIPS32/64 PRA.  */
 536 #define MIPS_CONF_MT            (_ULCAST_(7) <<  7)
 537 #define MIPS_CONF_MT_TLB        (_ULCAST_(1) <<  7)
 538 #define MIPS_CONF_MT_FTLB       (_ULCAST_(4) <<  7)
 539 #define MIPS_CONF_AR            (_ULCAST_(7) << 10)
 540 #define MIPS_CONF_AT            (_ULCAST_(3) << 13)
 541 #define MIPS_CONF_M             (_ULCAST_(1) << 31)
 542
 543 /*
 544  * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
 545  */
 546 #define MIPS_CONF1_FP           (_ULCAST_(1) <<  0)
 547 #define MIPS_CONF1_EP           (_ULCAST_(1) <<  1)
 548 #define MIPS_CONF1_CA           (_ULCAST_(1) <<  2)
 549 #define MIPS_CONF1_WR           (_ULCAST_(1) <<  3)
 550 #define MIPS_CONF1_PC           (_ULCAST_(1) <<  4)
 551 #define MIPS_CONF1_MD           (_ULCAST_(1) <<  5)
 552 #define MIPS_CONF1_C2           (_ULCAST_(1) <<  6)
 553 #define MIPS_CONF1_DA_SHF       7
 554 #define MIPS_CONF1_DA_SZ        3
 555 #define MIPS_CONF1_DA           (_ULCAST_(7) <<  7)
 556 #define MIPS_CONF1_DL_SHF       10
 557 #define MIPS_CONF1_DL_SZ        3
 558 #define MIPS_CONF1_DL           (_ULCAST_(7) << 10)
 559 #define MIPS_CONF1_DS_SHF       13
 560 #define MIPS_CONF1_DS_SZ        3
 561 #define MIPS_CONF1_DS           (_ULCAST_(7) << 13)
 562 #define MIPS_CONF1_IA_SHF       16
 563 #define MIPS_CONF1_IA_SZ        3
 564 #define MIPS_CONF1_IA           (_ULCAST_(7) << 16)
 565 #define MIPS_CONF1_IL_SHF       19
 566 #define MIPS_CONF1_IL_SZ        3
 567 #define MIPS_CONF1_IL           (_ULCAST_(7) << 19)
 568 #define MIPS_CONF1_IS_SHF       22
 569 #define MIPS_CONF1_IS_SZ        3
 570 #define MIPS_CONF1_IS           (_ULCAST_(7) << 22)
 571 #define MIPS_CONF1_TLBS_SHIFT   (25)
 572 #define MIPS_CONF1_TLBS_SIZE    (6)
 573 #define MIPS_CONF1_TLBS         (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
 574
 575 #define MIPS_CONF2_SA           (_ULCAST_(15)<<  0)
 576 #define MIPS_CONF2_SL           (_ULCAST_(15)<<  4)
 577 #define MIPS_CONF2_SS           (_ULCAST_(15)<<  8)
 578 #define MIPS_CONF2_SU           (_ULCAST_(15)<< 12)
 579 #define MIPS_CONF2_TA           (_ULCAST_(15)<< 16)
 580 #define MIPS_CONF2_TL           (_ULCAST_(15)<< 20)
 581 #define MIPS_CONF2_TS           (_ULCAST_(15)<< 24)
 582 #define MIPS_CONF2_TU           (_ULCAST_(7) << 28)
 583
 584 #define MIPS_CONF3_TL           (_ULCAST_(1) <<  0)
 585 #define MIPS_CONF3_SM           (_ULCAST_(1) <<  1)
 586 #define MIPS_CONF3_MT           (_ULCAST_(1) <<  2)
 587 #define MIPS_CONF3_CDMM         (_ULCAST_(1) <<  3)
 588 #define MIPS_CONF3_SP           (_ULCAST_(1) <<  4)
 589 #define MIPS_CONF3_VINT         (_ULCAST_(1) <<  5)
 590 #define MIPS_CONF3_VEIC         (_ULCAST_(1) <<  6)
 591 #define MIPS_CONF3_LPA          (_ULCAST_(1) <<  7)
 592 #define MIPS_CONF3_ITL          (_ULCAST_(1) <<  8)
 593 #define MIPS_CONF3_CTXTC        (_ULCAST_(1) <<  9)
 594 #define MIPS_CONF3_DSP          (_ULCAST_(1) << 10)
 595 #define MIPS_CONF3_DSP2P        (_ULCAST_(1) << 11)
 596 #define MIPS_CONF3_RXI          (_ULCAST_(1) << 12)
 597 #define MIPS_CONF3_ULRI         (_ULCAST_(1) << 13)
 598 #define MIPS_CONF3_ISA          (_ULCAST_(3) << 14)
 599 #define MIPS_CONF3_ISA_OE       (_ULCAST_(1) << 16)
 600 #define MIPS_CONF3_MCU          (_ULCAST_(1) << 17)
 601 #define MIPS_CONF3_MMAR         (_ULCAST_(7) << 18)
 602 #define MIPS_CONF3_IPLW         (_ULCAST_(3) << 21)
 603 #define MIPS_CONF3_VZ           (_ULCAST_(1) << 23)
 604 #define MIPS_CONF3_PW           (_ULCAST_(1) << 24)
 605 #define MIPS_CONF3_SC           (_ULCAST_(1) << 25)
 606 #define MIPS_CONF3_BI           (_ULCAST_(1) << 26)
 607 #define MIPS_CONF3_BP           (_ULCAST_(1) << 27)
 608 #define MIPS_CONF3_MSA          (_ULCAST_(1) << 28)
 609 #define MIPS_CONF3_CMGCR        (_ULCAST_(1) << 29)
 610 #define MIPS_CONF3_BPG          (_ULCAST_(1) << 30)
 611
 612 #define MIPS_CONF4_MMUSIZEEXT_SHIFT     (0)
 613 #define MIPS_CONF4_MMUSIZEEXT   (_ULCAST_(255) << 0)
 614 #define MIPS_CONF4_FTLBSETS_SHIFT       (0)
 615 #define MIPS_CONF4_FTLBSETS     (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
 616 #define MIPS_CONF4_FTLBWAYS_SHIFT       (4)
 617 #define MIPS_CONF4_FTLBWAYS     (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
 618 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT   (8)
 619 /* bits 10:8 in FTLB-only configurations */
 620 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 621 /* bits 12:8 in VTLB-FTLB only configurations */
 622 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 623 #define MIPS_CONF4_MMUEXTDEF    (_ULCAST_(3) << 14)
 624 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
 625 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT        (_ULCAST_(2) << 14)
 626 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT        (_ULCAST_(3) << 14)
 627 #define MIPS_CONF4_KSCREXIST_SHIFT      (16)
 628 #define MIPS_CONF4_KSCREXIST    (_ULCAST_(255) << MIPS_CONF4_KSCREXIST_SHIFT)
 629 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT    (24)
 630 #define MIPS_CONF4_VTLBSIZEEXT  (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
 631 #define MIPS_CONF4_AE           (_ULCAST_(1) << 28)
 632 #define MIPS_CONF4_IE           (_ULCAST_(3) << 29)
 633 #define MIPS_CONF4_TLBINV       (_ULCAST_(2) << 29)
 634
 635 #define MIPS_CONF5_NF           (_ULCAST_(1) << 0)
 636 #define MIPS_CONF5_UFR          (_ULCAST_(1) << 2)
 637 #define MIPS_CONF5_MRP          (_ULCAST_(1) << 3)
 638 #define MIPS_CONF5_LLB          (_ULCAST_(1) << 4)
 639 #define MIPS_CONF5_MVH          (_ULCAST_(1) << 5)
 640 #define MIPS_CONF5_VP           (_ULCAST_(1) << 7)
 641 #define MIPS_CONF5_FRE          (_ULCAST_(1) << 8)
 642 #define MIPS_CONF5_UFE          (_ULCAST_(1) << 9)
 643 #define MIPS_CONF5_MSAEN        (_ULCAST_(1) << 27)
 644 #define MIPS_CONF5_EVA          (_ULCAST_(1) << 28)
 645 #define MIPS_CONF5_CV           (_ULCAST_(1) << 29)
 646 #define MIPS_CONF5_K            (_ULCAST_(1) << 30)
 647
 648 #define MIPS_CONF6_SYND         (_ULCAST_(1) << 13)
 649 /* proAptiv FTLB on/off bit */
 650 #define MIPS_CONF6_FTLBEN       (_ULCAST_(1) << 15)
 651 /* Loongson-3 FTLB on/off bit */
 652 #define MIPS_CONF6_FTLBDIS      (_ULCAST_(1) << 22)
 653 /* FTLB probability bits */
 654 #define MIPS_CONF6_FTLBP_SHIFT  (16)
 655
 656 #define MIPS_CONF7_WII          (_ULCAST_(1) << 31)
 657
 658 #define MIPS_CONF7_RPS          (_ULCAST_(1) << 2)
 659
 660 #define MIPS_CONF7_IAR          (_ULCAST_(1) << 10)
 661 #define MIPS_CONF7_AR           (_ULCAST_(1) << 16)
 662 /* FTLB probability bits for R6 */
 663 #define MIPS_CONF7_FTLBP_SHIFT  (18)
 664
 665 /* WatchLo* register definitions */
 666 #define MIPS_WATCHLO_IRW        (_ULCAST_(0x7) << 0)
 667
 668 /* WatchHi* register definitions */
 669 #define MIPS_WATCHHI_M          (_ULCAST_(1) << 31)
 670 #define MIPS_WATCHHI_G          (_ULCAST_(1) << 30)
 671 #define MIPS_WATCHHI_WM         (_ULCAST_(0x3) << 28)
 672 #define MIPS_WATCHHI_WM_R_RVA   (_ULCAST_(0) << 28)
 673 #define MIPS_WATCHHI_WM_R_GPA   (_ULCAST_(1) << 28)
 674 #define MIPS_WATCHHI_WM_G_GVA   (_ULCAST_(2) << 28)
 675 #define MIPS_WATCHHI_EAS        (_ULCAST_(0x3) << 24)
 676 #define MIPS_WATCHHI_ASID       (_ULCAST_(0xff) << 16)
 677 #define MIPS_WATCHHI_MASK       (_ULCAST_(0x1ff) << 3)
 678 #define MIPS_WATCHHI_I          (_ULCAST_(1) << 2)
 679 #define MIPS_WATCHHI_R          (_ULCAST_(1) << 1)
 680 #define MIPS_WATCHHI_W          (_ULCAST_(1) << 0)
 681 #define MIPS_WATCHHI_IRW        (_ULCAST_(0x7) << 0)
 682
 683 /* MAAR bit definitions */
 684 #define MIPS_MAAR_ADDR          ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
 685 #define MIPS_MAAR_ADDR_SHIFT    12
 686 #define MIPS_MAAR_S             (_ULCAST_(1) << 1)
 687 #define MIPS_MAAR_V             (_ULCAST_(1) << 0)
 688
 689 /* EBase bit definitions */
 690 #define MIPS_EBASE_CPUNUM_SHIFT 0
 691 #define MIPS_EBASE_CPUNUM       (_ULCAST_(0x3ff) << 0)
 692 #define MIPS_EBASE_WG_SHIFT     11
 693 #define MIPS_EBASE_WG           (_ULCAST_(1) << 11)
 694 #define MIPS_EBASE_BASE_SHIFT   12
 695 #define MIPS_EBASE_BASE         (~_ULCAST_((1 << MIPS_EBASE_BASE_SHIFT) - 1))
 696
 697 /* CMGCRBase bit definitions */
 698 #define MIPS_CMGCRB_BASE        11
 699 #define MIPS_CMGCRF_BASE        (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
 700
 701 /*
 702  * Bits in the MIPS32 Memory Segmentation registers.
 703  */
 704 #define MIPS_SEGCFG_PA_SHIFT    9
 705 #define MIPS_SEGCFG_PA          (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
 706 #define MIPS_SEGCFG_AM_SHIFT    4
 707 #define MIPS_SEGCFG_AM          (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
 708 #define MIPS_SEGCFG_EU_SHIFT    3
 709 #define MIPS_SEGCFG_EU          (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
 710 #define MIPS_SEGCFG_C_SHIFT     0
 711 #define MIPS_SEGCFG_C           (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
 712
 713 #define MIPS_SEGCFG_UUSK        _ULCAST_(7)
 714 #define MIPS_SEGCFG_USK         _ULCAST_(5)
 715 #define MIPS_SEGCFG_MUSUK       _ULCAST_(4)
 716 #define MIPS_SEGCFG_MUSK        _ULCAST_(3)
 717 #define MIPS_SEGCFG_MSK         _ULCAST_(2)
 718 #define MIPS_SEGCFG_MK          _ULCAST_(1)
 719 #define MIPS_SEGCFG_UK          _ULCAST_(0)
 720
 721 #define MIPS_PWFIELD_GDI_SHIFT  24
 722 #define MIPS_PWFIELD_GDI_MASK   0x3f000000
 723 #define MIPS_PWFIELD_UDI_SHIFT  18
 724 #define MIPS_PWFIELD_UDI_MASK   0x00fc0000
 725 #define MIPS_PWFIELD_MDI_SHIFT  12
 726 #define MIPS_PWFIELD_MDI_MASK   0x0003f000
 727 #define MIPS_PWFIELD_PTI_SHIFT  6
 728 #define MIPS_PWFIELD_PTI_MASK   0x00000fc0
 729 #define MIPS_PWFIELD_PTEI_SHIFT 0
 730 #define MIPS_PWFIELD_PTEI_MASK  0x0000003f
 731
 732 #define MIPS_PWSIZE_GDW_SHIFT   24
 733 #define MIPS_PWSIZE_GDW_MASK    0x3f000000
 734 #define MIPS_PWSIZE_UDW_SHIFT   18
 735 #define MIPS_PWSIZE_UDW_MASK    0x00fc0000
 736 #define MIPS_PWSIZE_MDW_SHIFT   12
 737 #define MIPS_PWSIZE_MDW_MASK    0x0003f000
 738 #define MIPS_PWSIZE_PTW_SHIFT   6
 739 #define MIPS_PWSIZE_PTW_MASK    0x00000fc0
 740 #define MIPS_PWSIZE_PTEW_SHIFT  0
 741 #define MIPS_PWSIZE_PTEW_MASK   0x0000003f
 742
 743 #define MIPS_PWCTL_PWEN_SHIFT   31
 744 #define MIPS_PWCTL_PWEN_MASK    0x80000000
 745 #define MIPS_PWCTL_DPH_SHIFT    7
 746 #define MIPS_PWCTL_DPH_MASK     0x00000080
 747 #define MIPS_PWCTL_HUGEPG_SHIFT 6
 748 #define MIPS_PWCTL_HUGEPG_MASK  0x00000060
 749 #define MIPS_PWCTL_PSN_SHIFT    0
 750 #define MIPS_PWCTL_PSN_MASK     0x0000003f
 751
 752 /* GuestCtl0 fields */
 753 #define MIPS_GCTL0_GM_SHIFT     31
 754 #define MIPS_GCTL0_GM           (_ULCAST_(1) << MIPS_GCTL0_GM_SHIFT)
 755 #define MIPS_GCTL0_RI_SHIFT     30
 756 #define MIPS_GCTL0_RI           (_ULCAST_(1) << MIPS_GCTL0_RI_SHIFT)
 757 #define MIPS_GCTL0_MC_SHIFT     29
 758 #define MIPS_GCTL0_MC           (_ULCAST_(1) << MIPS_GCTL0_MC_SHIFT)
 759 #define MIPS_GCTL0_CP0_SHIFT    28
 760 #define MIPS_GCTL0_CP0          (_ULCAST_(1) << MIPS_GCTL0_CP0_SHIFT)
 761 #define MIPS_GCTL0_AT_SHIFT     26
 762 #define MIPS_GCTL0_AT           (_ULCAST_(0x3) << MIPS_GCTL0_AT_SHIFT)
 763 #define MIPS_GCTL0_GT_SHIFT     25
 764 #define MIPS_GCTL0_GT           (_ULCAST_(1) << MIPS_GCTL0_GT_SHIFT)
 765 #define MIPS_GCTL0_CG_SHIFT     24
 766 #define MIPS_GCTL0_CG           (_ULCAST_(1) << MIPS_GCTL0_CG_SHIFT)
 767 #define MIPS_GCTL0_CF_SHIFT     23
 768 #define MIPS_GCTL0_CF           (_ULCAST_(1) << MIPS_GCTL0_CF_SHIFT)
 769 #define MIPS_GCTL0_G1_SHIFT     22
 770 #define MIPS_GCTL0_G1           (_ULCAST_(1) << MIPS_GCTL0_G1_SHIFT)
 771 #define MIPS_GCTL0_G0E_SHIFT    19
 772 #define MIPS_GCTL0_G0E          (_ULCAST_(1) << MIPS_GCTL0_G0E_SHIFT)
 773 #define MIPS_GCTL0_PT_SHIFT     18
 774 #define MIPS_GCTL0_PT           (_ULCAST_(1) << MIPS_GCTL0_PT_SHIFT)
 775 #define MIPS_GCTL0_RAD_SHIFT    9
 776 #define MIPS_GCTL0_RAD          (_ULCAST_(1) << MIPS_GCTL0_RAD_SHIFT)
 777 #define MIPS_GCTL0_DRG_SHIFT    8
 778 #define MIPS_GCTL0_DRG          (_ULCAST_(1) << MIPS_GCTL0_DRG_SHIFT)
 779 #define MIPS_GCTL0_G2_SHIFT     7
 780 #define MIPS_GCTL0_G2           (_ULCAST_(1) << MIPS_GCTL0_G2_SHIFT)
 781 #define MIPS_GCTL0_GEXC_SHIFT   2
 782 #define MIPS_GCTL0_GEXC         (_ULCAST_(0x1f) << MIPS_GCTL0_GEXC_SHIFT)
 783 #define MIPS_GCTL0_SFC2_SHIFT   1
 784 #define MIPS_GCTL0_SFC2         (_ULCAST_(1) << MIPS_GCTL0_SFC2_SHIFT)
 785 #define MIPS_GCTL0_SFC1_SHIFT   0
 786 #define MIPS_GCTL0_SFC1         (_ULCAST_(1) << MIPS_GCTL0_SFC1_SHIFT)
 787
 788 /* GuestCtl0.AT Guest address translation control */
 789 #define MIPS_GCTL0_AT_ROOT      1  /* Guest MMU under Root control */
 790 #define MIPS_GCTL0_AT_GUEST     3  /* Guest MMU under Guest control */
 791
 792 /* GuestCtl0.GExcCode Hypervisor exception cause codes */
 793 #define MIPS_GCTL0_GEXC_GPSI    0  /* Guest Privileged Sensitive Instruction */
 794 #define MIPS_GCTL0_GEXC_GSFC    1  /* Guest Software Field Change */
 795 #define MIPS_GCTL0_GEXC_HC      2  /* Hypercall */
 796 #define MIPS_GCTL0_GEXC_GRR     3  /* Guest Reserved Instruction Redirect */
 797 #define MIPS_GCTL0_GEXC_GVA     8  /* Guest Virtual Address available */
 798 #define MIPS_GCTL0_GEXC_GHFC    9  /* Guest Hardware Field Change */
 799 #define MIPS_GCTL0_GEXC_GPA     10 /* Guest Physical Address available */
 800
 801 /* GuestCtl0Ext fields */
 802 #define MIPS_GCTL0EXT_RPW_SHIFT 8
 803 #define MIPS_GCTL0EXT_RPW       (_ULCAST_(0x3) << MIPS_GCTL0EXT_RPW_SHIFT)
 804 #define MIPS_GCTL0EXT_NCC_SHIFT 6
 805 #define MIPS_GCTL0EXT_NCC       (_ULCAST_(0x3) << MIPS_GCTL0EXT_NCC_SHIFT)
 806 #define MIPS_GCTL0EXT_CGI_SHIFT 4
 807 #define MIPS_GCTL0EXT_CGI       (_ULCAST_(1) << MIPS_GCTL0EXT_CGI_SHIFT)
 808 #define MIPS_GCTL0EXT_FCD_SHIFT 3
 809 #define MIPS_GCTL0EXT_FCD       (_ULCAST_(1) << MIPS_GCTL0EXT_FCD_SHIFT)
 810 #define MIPS_GCTL0EXT_OG_SHIFT  2
 811 #define MIPS_GCTL0EXT_OG        (_ULCAST_(1) << MIPS_GCTL0EXT_OG_SHIFT)
 812 #define MIPS_GCTL0EXT_BG_SHIFT  1
 813 #define MIPS_GCTL0EXT_BG        (_ULCAST_(1) << MIPS_GCTL0EXT_BG_SHIFT)
 814 #define MIPS_GCTL0EXT_MG_SHIFT  0
 815 #define MIPS_GCTL0EXT_MG        (_ULCAST_(1) << MIPS_GCTL0EXT_MG_SHIFT)
 816
 817 /* GuestCtl0Ext.RPW Root page walk configuration */
 818 #define MIPS_GCTL0EXT_RPW_BOTH  0  /* Root PW for GPA->RPA and RVA->RPA */
 819 #define MIPS_GCTL0EXT_RPW_GPA   2  /* Root PW for GPA->RPA */
 820 #define MIPS_GCTL0EXT_RPW_RVA   3  /* Root PW for RVA->RPA */
 821
 822 /* GuestCtl0Ext.NCC Nested cache coherency attributes */
 823 #define MIPS_GCTL0EXT_NCC_IND   0  /* Guest CCA independent of Root CCA */
 824 #define MIPS_GCTL0EXT_NCC_MOD   1  /* Guest CCA modified by Root CCA */
 825
 826 /* GuestCtl1 fields */
 827 #define MIPS_GCTL1_ID_SHIFT     0
 828 #define MIPS_GCTL1_ID_WIDTH     8
 829 #define MIPS_GCTL1_ID           (_ULCAST_(0xff) << MIPS_GCTL1_ID_SHIFT)
 830 #define MIPS_GCTL1_RID_SHIFT    16
 831 #define MIPS_GCTL1_RID_WIDTH    8
 832 #define MIPS_GCTL1_RID          (_ULCAST_(0xff) << MIPS_GCTL1_RID_SHIFT)
 833 #define MIPS_GCTL1_EID_SHIFT    24
 834 #define MIPS_GCTL1_EID_WIDTH    8
 835 #define MIPS_GCTL1_EID          (_ULCAST_(0xff) << MIPS_GCTL1_EID_SHIFT)
 836
 837 /* GuestID reserved for root context */
 838 #define MIPS_GCTL1_ROOT_GUESTID 0
 839
 840 /* CDMMBase register bit definitions */
 841 #define MIPS_CDMMBASE_SIZE_SHIFT 0
 842 #define MIPS_CDMMBASE_SIZE      (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
 843 #define MIPS_CDMMBASE_CI        (_ULCAST_(1) << 9)
 844 #define MIPS_CDMMBASE_EN        (_ULCAST_(1) << 10)
 845 #define MIPS_CDMMBASE_ADDR_SHIFT 11
 846 #define MIPS_CDMMBASE_ADDR_START 15
 847
 848 /*
 849  * Bitfields in the TX39 family CP0 Configuration Register 3
 850  */
 851 #define TX39_CONF_ICS_SHIFT     19
 852 #define TX39_CONF_ICS_MASK      0x00380000
 853 #define TX39_CONF_ICS_1KB       0x00000000
 854 #define TX39_CONF_ICS_2KB       0x00080000
 855 #define TX39_CONF_ICS_4KB       0x00100000
 856 #define TX39_CONF_ICS_8KB       0x00180000
 857 #define TX39_CONF_ICS_16KB      0x00200000
 858
 859 #define TX39_CONF_DCS_SHIFT     16
 860 #define TX39_CONF_DCS_MASK      0x00070000
 861 #define TX39_CONF_DCS_1KB       0x00000000
 862 #define TX39_CONF_DCS_2KB       0x00010000
 863 #define TX39_CONF_DCS_4KB       0x00020000
 864 #define TX39_CONF_DCS_8KB       0x00030000
 865 #define TX39_CONF_DCS_16KB      0x00040000
 866
 867 #define TX39_CONF_CWFON         0x00004000
 868 #define TX39_CONF_WBON          0x00002000
 869 #define TX39_CONF_RF_SHIFT      10
 870 #define TX39_CONF_RF_MASK       0x00000c00
 871 #define TX39_CONF_DOZE          0x00000200
 872 #define TX39_CONF_HALT          0x00000100
 873 #define TX39_CONF_LOCK          0x00000080
 874 #define TX39_CONF_ICE           0x00000020
 875 #define TX39_CONF_DCE           0x00000010
 876 #define TX39_CONF_IRSIZE_SHIFT  2
 877 #define TX39_CONF_IRSIZE_MASK   0x0000000c
 878 #define TX39_CONF_DRSIZE_SHIFT  0
 879 #define TX39_CONF_DRSIZE_MASK   0x00000003
 880
 881 /*
 882  * Interesting Bits in the R10K CP0 Branch Diagnostic Register
 883  */
 884 /* Disable Branch Target Address Cache */
 885 #define R10K_DIAG_D_BTAC        (_ULCAST_(1) << 27)
 886 /* Enable Branch Prediction Global History */
 887 #define R10K_DIAG_E_GHIST       (_ULCAST_(1) << 26)
 888 /* Disable Branch Return Cache */
 889 #define R10K_DIAG_D_BRC         (_ULCAST_(1) << 22)
 890
 891 /* Flush ITLB */
 892 #define LOONGSON_DIAG_ITLB      (_ULCAST_(1) << 2)
 893 /* Flush DTLB */
 894 #define LOONGSON_DIAG_DTLB      (_ULCAST_(1) << 3)
 895 /* Flush VTLB */
 896 #define LOONGSON_DIAG_VTLB      (_ULCAST_(1) << 12)
 897 /* Flush FTLB */
 898 #define LOONGSON_DIAG_FTLB      (_ULCAST_(1) << 13)
 899
 900 /*
 901  * Coprocessor 1 (FPU) register names
 902  */
 903 #define CP1_REVISION    $0
 904 #define CP1_UFR         $1
 905 #define CP1_UNFR        $4
 906 #define CP1_FCCR        $25
 907 #define CP1_FEXR        $26
 908 #define CP1_FENR        $28
 909 #define CP1_STATUS      $31
 910
 911
 912 /*
 913  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
 914  */
 915 #define MIPS_FPIR_S             (_ULCAST_(1) << 16)
 916 #define MIPS_FPIR_D             (_ULCAST_(1) << 17)
 917 #define MIPS_FPIR_PS            (_ULCAST_(1) << 18)
 918 #define MIPS_FPIR_3D            (_ULCAST_(1) << 19)
 919 #define MIPS_FPIR_W             (_ULCAST_(1) << 20)
 920 #define MIPS_FPIR_L             (_ULCAST_(1) << 21)
 921 #define MIPS_FPIR_F64           (_ULCAST_(1) << 22)
 922 #define MIPS_FPIR_HAS2008       (_ULCAST_(1) << 23)
 923 #define MIPS_FPIR_UFRP          (_ULCAST_(1) << 28)
 924 #define MIPS_FPIR_FREP          (_ULCAST_(1) << 29)
 925
 926 /*
 927  * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
 928  */
 929 #define MIPS_FCCR_CONDX_S       0
 930 #define MIPS_FCCR_CONDX         (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
 931 #define MIPS_FCCR_COND0_S       0
 932 #define MIPS_FCCR_COND0         (_ULCAST_(1) << MIPS_FCCR_COND0_S)
 933 #define MIPS_FCCR_COND1_S       1
 934 #define MIPS_FCCR_COND1         (_ULCAST_(1) << MIPS_FCCR_COND1_S)
 935 #define MIPS_FCCR_COND2_S       2
 936 #define MIPS_FCCR_COND2         (_ULCAST_(1) << MIPS_FCCR_COND2_S)
 937 #define MIPS_FCCR_COND3_S       3
 938 #define MIPS_FCCR_COND3         (_ULCAST_(1) << MIPS_FCCR_COND3_S)
 939 #define MIPS_FCCR_COND4_S       4
 940 #define MIPS_FCCR_COND4         (_ULCAST_(1) << MIPS_FCCR_COND4_S)
 941 #define MIPS_FCCR_COND5_S       5
 942 #define MIPS_FCCR_COND5         (_ULCAST_(1) << MIPS_FCCR_COND5_S)
 943 #define MIPS_FCCR_COND6_S       6
 944 #define MIPS_FCCR_COND6         (_ULCAST_(1) << MIPS_FCCR_COND6_S)
 945 #define MIPS_FCCR_COND7_S       7
 946 #define MIPS_FCCR_COND7         (_ULCAST_(1) << MIPS_FCCR_COND7_S)
 947
 948 /*
 949  * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
 950  */
 951 #define MIPS_FENR_FS_S          2
 952 #define MIPS_FENR_FS            (_ULCAST_(1) << MIPS_FENR_FS_S)
 953
 954 /*
 955  * FPU Status Register Values
 956  */
 957 #define FPU_CSR_COND_S  23                                      /* $fcc0 */
 958 #define FPU_CSR_COND    (_ULCAST_(1) << FPU_CSR_COND_S)
 959
 960 #define FPU_CSR_FS_S    24              /* flush denormalised results to 0 */
 961 #define FPU_CSR_FS      (_ULCAST_(1) << FPU_CSR_FS_S)
 962
 963 #define FPU_CSR_CONDX_S 25                                      /* $fcc[7:1] */
 964 #define FPU_CSR_CONDX   (_ULCAST_(127) << FPU_CSR_CONDX_S)
 965 #define FPU_CSR_COND1_S 25                                      /* $fcc1 */
 966 #define FPU_CSR_COND1   (_ULCAST_(1) << FPU_CSR_COND1_S)
 967 #define FPU_CSR_COND2_S 26                                      /* $fcc2 */
 968 #define FPU_CSR_COND2   (_ULCAST_(1) << FPU_CSR_COND2_S)
 969 #define FPU_CSR_COND3_S 27                                      /* $fcc3 */
 970 #define FPU_CSR_COND3   (_ULCAST_(1) << FPU_CSR_COND3_S)
 971 #define FPU_CSR_COND4_S 28                                      /* $fcc4 */
 972 #define FPU_CSR_COND4   (_ULCAST_(1) << FPU_CSR_COND4_S)
 973 #define FPU_CSR_COND5_S 29                                      /* $fcc5 */
 974 #define FPU_CSR_COND5   (_ULCAST_(1) << FPU_CSR_COND5_S)
 975 #define FPU_CSR_COND6_S 30                                      /* $fcc6 */
 976 #define FPU_CSR_COND6   (_ULCAST_(1) << FPU_CSR_COND6_S)
 977 #define FPU_CSR_COND7_S 31                                      /* $fcc7 */
 978 #define FPU_CSR_COND7   (_ULCAST_(1) << FPU_CSR_COND7_S)
 979
 980 /*
 981  * Bits 22:20 of the FPU Status Register will be read as 0,
 982  * and should be written as zero.
 983  */
 984 #define FPU_CSR_RSVD    (_ULCAST_(7) << 20)
 985
 986 #define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
 987 #define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
 988
 989 /*
 990  * X the exception cause indicator
 991  * E the exception enable
 992  * S the sticky/flag bit
 993 */
 994 #define FPU_CSR_ALL_X   0x0003f000
 995 #define FPU_CSR_UNI_X   0x00020000
 996 #define FPU_CSR_INV_X   0x00010000
 997 #define FPU_CSR_DIV_X   0x00008000
 998 #define FPU_CSR_OVF_X   0x00004000
 999 #define FPU_CSR_UDF_X   0x00002000
1000 #define FPU_CSR_INE_X   0x00001000
1001
1002 #define FPU_CSR_ALL_E   0x00000f80
1003 #define FPU_CSR_INV_E   0x00000800
1004 #define FPU_CSR_DIV_E   0x00000400
1005 #define FPU_CSR_OVF_E   0x00000200
1006 #define FPU_CSR_UDF_E   0x00000100
1007 #define FPU_CSR_INE_E   0x00000080
1008
1009 #define FPU_CSR_ALL_S   0x0000007c
1010 #define FPU_CSR_INV_S   0x00000040
1011 #define FPU_CSR_DIV_S   0x00000020
1012 #define FPU_CSR_OVF_S   0x00000010
1013 #define FPU_CSR_UDF_S   0x00000008
1014 #define FPU_CSR_INE_S   0x00000004
1015
1016 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
1017 #define FPU_CSR_RM      0x00000003
1018 #define FPU_CSR_RN      0x0     /* nearest */
1019 #define FPU_CSR_RZ      0x1     /* towards zero */
1020 #define FPU_CSR_RU      0x2     /* towards +Infinity */
1021 #define FPU_CSR_RD      0x3     /* towards -Infinity */
1022
1023
1024 #ifndef __ASSEMBLY__
1025
1026 /*
1027  * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
1028  */
1029 #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
1030     defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
1031 #define get_isa16_mode(x)               ((x) & 0x1)
1032 #define msk_isa16_mode(x)               ((x) & ~0x1)
1033 #define set_isa16_mode(x)               do { (x) |= 0x1; } while(0)
1034 #else
1035 #define get_isa16_mode(x)               0
1036 #define msk_isa16_mode(x)               (x)
1037 #define set_isa16_mode(x)               do { } while(0)
1038 #endif
1039
1040 /*
1041  * microMIPS instructions can be 16-bit or 32-bit in length. This
1042  * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
1043  */
1044 static inline int mm_insn_16bit(u16 insn)
1045 {
1046         u16 opcode = (insn >> 10) & 0x7;
1047
1048         return (opcode >= 1 && opcode <= 3) ? 1 : 0;
1049 }
1050
1051 /*
1052  * Helper macros for generating raw instruction encodings in inline asm.
1053  */
1054 #ifdef CONFIG_CPU_MICROMIPS
1055 #define _ASM_INSN16_IF_MM(_enc)                 \
1056         ".insn\n\t"                             \
1057         ".hword (" #_enc ")\n\t"
1058 #define _ASM_INSN32_IF_MM(_enc)                 \
1059         ".insn\n\t"                             \
1060         ".hword ((" #_enc ") >> 16)\n\t"        \
1061         ".hword ((" #_enc ") & 0xffff)\n\t"
1062 #else
1063 #define _ASM_INSN_IF_MIPS(_enc)                 \
1064         ".insn\n\t"                             \
1065         ".word (" #_enc ")\n\t"
1066 #endif
1067
1068 #ifndef _ASM_INSN16_IF_MM
1069 #define _ASM_INSN16_IF_MM(_enc)
1070 #endif
1071 #ifndef _ASM_INSN32_IF_MM
1072 #define _ASM_INSN32_IF_MM(_enc)
1073 #endif
1074 #ifndef _ASM_INSN_IF_MIPS
1075 #define _ASM_INSN_IF_MIPS(_enc)
1076 #endif
1077
1078 /*
1079  * TLB Invalidate Flush
1080  */
1081 static inline void tlbinvf(void)
1082 {
1083         __asm__ __volatile__(
1084                 ".set push\n\t"
1085                 ".set noreorder\n\t"
1086                 "# tlbinvf\n\t"
1087                 _ASM_INSN_IF_MIPS(0x42000004)
1088                 _ASM_INSN32_IF_MM(0x0000537c)
1089                 ".set pop");
1090 }
1091
1092
1093 /*
1094  * Functions to access the R10000 performance counters.  These are basically
1095  * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
1096  * performance counter number encoded into bits 1 ... 5 of the instruction.
1097  * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
1098  * disassembler these will look like an access to sel 0 or 1.
1099  */
1100 #define read_r10k_perf_cntr(counter)                            \
1101 ({                                                              \
1102         unsigned int __res;                                     \
1103         __asm__ __volatile__(                                   \
1104         "mfpc\t%0, %1"                                          \
1105         : "=r" (__res)                                          \
1106         : "i" (counter));                                       \
1107                                                                 \
1108         __res;                                                  \
1109 })
1110
1111 #define write_r10k_perf_cntr(counter,val)                       \
1112 do {                                                            \
1113         __asm__ __volatile__(                                   \
1114         "mtpc\t%0, %1"                                          \
1115         :                                                       \
1116         : "r" (val), "i" (counter));                            \
1117 } while (0)
1118
1119 #define read_r10k_perf_event(counter)                           \
1120 ({                                                              \
1121         unsigned int __res;                                     \
1122         __asm__ __volatile__(                                   \
1123         "mfps\t%0, %1"                                          \
1124         : "=r" (__res)                                          \
1125         : "i" (counter));                                       \
1126                                                                 \
1127         __res;                                                  \
1128 })
1129
1130 #define write_r10k_perf_cntl(counter,val)                       \
1131 do {                                                            \
1132         __asm__ __volatile__(                                   \
1133         "mtps\t%0, %1"                                          \
1134         :                                                       \
1135         : "r" (val), "i" (counter));                            \
1136 } while (0)
1137
1138
1139 /*
1140  * Macros to access the system control coprocessor
1141  */
1142
1143 #define __read_32bit_c0_register(source, sel)                           \
1144 ({ unsigned int __res;                                                  \
1145         if (sel == 0)                                                   \
1146                 __asm__ __volatile__(                                   \
1147                         "mfc0\t%0, " #source "\n\t"                     \
1148                         : "=r" (__res));                                \
1149         else                                                            \
1150                 __asm__ __volatile__(                                   \
1151                         ".set\tmips32\n\t"                              \
1152                         "mfc0\t%0, " #source ", " #sel "\n\t"           \
1153                         ".set\tmips0\n\t"                               \
1154                         : "=r" (__res));                                \
1155         __res;                                                          \
1156 })
1157
1158 #define __read_64bit_c0_register(source, sel)                           \
1159 ({ unsigned long long __res;                                            \
1160         if (sizeof(unsigned long) == 4)                                 \
1161                 __res = __read_64bit_c0_split(source, sel);             \
1162         else if (sel == 0)                                              \
1163                 __asm__ __volatile__(                                   \
1164                         ".set\tmips3\n\t"                               \
1165                         "dmfc0\t%0, " #source "\n\t"                    \
1166                         ".set\tmips0"                                   \
1167                         : "=r" (__res));                                \
1168         else                                                            \
1169                 __asm__ __volatile__(                                   \
1170                         ".set\tmips64\n\t"                              \
1171                         "dmfc0\t%0, " #source ", " #sel "\n\t"          \
1172                         ".set\tmips0"                                   \
1173                         : "=r" (__res));                                \
1174         __res;                                                          \
1175 })
1176
1177 #define __write_32bit_c0_register(register, sel, value)                 \
1178 do {                                                                    \
1179         if (sel == 0)                                                   \
1180                 __asm__ __volatile__(                                   \
1181                         "mtc0\t%z0, " #register "\n\t"                  \
1182                         : : "Jr" ((unsigned int)(value)));              \
1183         else                                                            \
1184                 __asm__ __volatile__(                                   \
1185                         ".set\tmips32\n\t"                              \
1186                         "mtc0\t%z0, " #register ", " #sel "\n\t"        \
1187                         ".set\tmips0"                                   \
1188                         : : "Jr" ((unsigned int)(value)));              \
1189 } while (0)
1190
1191 #define __write_64bit_c0_register(register, sel, value)                 \
1192 do {                                                                    \
1193         if (sizeof(unsigned long) == 4)                                 \
1194                 __write_64bit_c0_split(register, sel, value);           \
1195         else if (sel == 0)                                              \
1196                 __asm__ __volatile__(                                   \
1197                         ".set\tmips3\n\t"                               \
1198                         "dmtc0\t%z0, " #register "\n\t"                 \
1199                         ".set\tmips0"                                   \
1200                         : : "Jr" (value));                              \
1201         else                                                            \
1202                 __asm__ __volatile__(                                   \
1203                         ".set\tmips64\n\t"                              \
1204                         "dmtc0\t%z0, " #register ", " #sel "\n\t"       \
1205                         ".set\tmips0"                                   \
1206                         : : "Jr" (value));                              \
1207 } while (0)
1208
1209 #define __read_ulong_c0_register(reg, sel)                              \
1210         ((sizeof(unsigned long) == 4) ?                                 \
1211         (unsigned long) __read_32bit_c0_register(reg, sel) :            \
1212         (unsigned long) __read_64bit_c0_register(reg, sel))
1213
1214 #define __write_ulong_c0_register(reg, sel, val)                        \
1215 do {                                                                    \
1216         if (sizeof(unsigned long) == 4)                                 \
1217                 __write_32bit_c0_register(reg, sel, val);               \
1218         else                                                            \
1219                 __write_64bit_c0_register(reg, sel, val);               \
1220 } while (0)
1221
1222 /*
1223  * On RM7000/RM9000 these are uses to access cop0 set 1 registers
1224  */
1225 #define __read_32bit_c0_ctrl_register(source)                           \
1226 ({ unsigned int __res;                                                  \
1227         __asm__ __volatile__(                                           \
1228                 "cfc0\t%0, " #source "\n\t"                             \
1229                 : "=r" (__res));                                        \
1230         __res;                                                          \
1231 })
1232
1233 #define __write_32bit_c0_ctrl_register(register, value)                 \
1234 do {                                                                    \
1235         __asm__ __volatile__(                                           \
1236                 "ctc0\t%z0, " #register "\n\t"                          \
1237                 : : "Jr" ((unsigned int)(value)));                      \
1238 } while (0)
1239
1240 /*
1241  * These versions are only needed for systems with more than 38 bits of
1242  * physical address space running the 32-bit kernel.  That's none atm :-)
1243  */
1244 #define __read_64bit_c0_split(source, sel)                              \
1245 ({                                                                      \
1246         unsigned long long __val;                                       \
1247         unsigned long __flags;                                          \
1248                                                                         \
1249         local_irq_save(__flags);                                        \
1250         if (sel == 0)                                                   \
1251                 __asm__ __volatile__(                                   \
1252                         ".set\tmips64\n\t"                              \
1253                         "dmfc0\t%M0, " #source "\n\t"                   \
1254                         "dsll\t%L0, %M0, 32\n\t"                        \
1255                         "dsra\t%M0, %M0, 32\n\t"                        \
1256                         "dsra\t%L0, %L0, 32\n\t"                        \
1257                         ".set\tmips0"                                   \
1258                         : "=r" (__val));                                \
1259         else                                                            \
1260                 __asm__ __volatile__(                                   \
1261                         ".set\tmips64\n\t"                              \
1262                         "dmfc0\t%M0, " #source ", " #sel "\n\t"         \
1263                         "dsll\t%L0, %M0, 32\n\t"                        \
1264                         "dsra\t%M0, %M0, 32\n\t"                        \
1265                         "dsra\t%L0, %L0, 32\n\t"                        \
1266                         ".set\tmips0"                                   \
1267                         : "=r" (__val));                                \
1268         local_irq_restore(__flags);                                     \
1269                                                                         \
1270         __val;                                                          \
1271 })
1272
1273 #define __write_64bit_c0_split(source, sel, val)                        \
1274 do {                                                                    \
1275         unsigned long __flags;                                          \
1276                                                                         \
1277         local_irq_save(__flags);                                        \
1278         if (sel == 0)                                                   \
1279                 __asm__ __volatile__(                                   \
1280                         ".set\tmips64\n\t"                              \
1281                         "dsll\t%L0, %L0, 32\n\t"                        \
1282                         "dsrl\t%L0, %L0, 32\n\t"                        \
1283                         "dsll\t%M0, %M0, 32\n\t"                        \
1284                         "or\t%L0, %L0, %M0\n\t"                         \
1285                         "dmtc0\t%L0, " #source "\n\t"                   \
1286                         ".set\tmips0"                                   \
1287                         : : "r" (val));                                 \
1288         else                                                            \
1289                 __asm__ __volatile__(                                   \
1290                         ".set\tmips64\n\t"                              \
1291                         "dsll\t%L0, %L0, 32\n\t"                        \
1292                         "dsrl\t%L0, %L0, 32\n\t"                        \
1293                         "dsll\t%M0, %M0, 32\n\t"                        \
1294                         "or\t%L0, %L0, %M0\n\t"                         \
1295                         "dmtc0\t%L0, " #source ", " #sel "\n\t"         \
1296                         ".set\tmips0"                                   \
1297                         : : "r" (val));                                 \
1298         local_irq_restore(__flags);                                     \
1299 } while (0)
1300
1301 #define __readx_32bit_c0_register(source)                               \
1302 ({                                                                      \
1303         unsigned int __res;                                             \
1304                                                                         \
1305         __asm__ __volatile__(                                           \
1306         "       .set    push                                    \n"     \
1307         "       .set    noat                                    \n"     \
1308         "       .set    mips32r2                                \n"     \
1309         "       # mfhc0 $1, %1                                  \n"     \
1310         _ASM_INSN_IF_MIPS(0x40410000 | ((%1 & 0x1f) << 11))             \
1311         _ASM_INSN32_IF_MM(0x002000f4 | ((%1 & 0x1f) << 16))             \
1312         "       move    %0, $1                                  \n"     \
1313         "       .set    pop                                     \n"     \
1314         : "=r" (__res)                                                  \
1315         : "i" (source));                                                \
1316         __res;                                                          \
1317 })
1318
1319 #define __writex_32bit_c0_register(register, value)                     \
1320 do {                                                                    \
1321         __asm__ __volatile__(                                           \
1322         "       .set    push                                    \n"     \
1323         "       .set    noat                                    \n"     \
1324         "       .set    mips32r2                                \n"     \
1325         "       move    $1, %0                                  \n"     \
1326         "       # mthc0 $1, %1                                  \n"     \
1327         _ASM_INSN_IF_MIPS(0x40c10000 | ((%1 & 0x1f) << 11))             \
1328         _ASM_INSN32_IF_MM(0x002002f4 | ((%1 & 0x1f) << 16))             \
1329         "       .set    pop                                     \n"     \
1330         :                                                               \
1331         : "r" (value), "i" (register));                                 \
1332 } while (0)
1333
1334 #define read_c0_index()         __read_32bit_c0_register($0, 0)
1335 #define write_c0_index(val)     __write_32bit_c0_register($0, 0, val)
1336
1337 #define read_c0_random()        __read_32bit_c0_register($1, 0)
1338 #define write_c0_random(val)    __write_32bit_c0_register($1, 0, val)
1339
1340 #define read_c0_entrylo0()      __read_ulong_c0_register($2, 0)
1341 #define write_c0_entrylo0(val)  __write_ulong_c0_register($2, 0, val)
1342
1343 #define readx_c0_entrylo0()     __readx_32bit_c0_register(2)
1344 #define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val)
1345
1346 #define read_c0_entrylo1()      __read_ulong_c0_register($3, 0)
1347 #define write_c0_entrylo1(val)  __write_ulong_c0_register($3, 0, val)
1348
1349 #define readx_c0_entrylo1()     __readx_32bit_c0_register(3)
1350 #define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val)
1351
1352 #define read_c0_conf()          __read_32bit_c0_register($3, 0)
1353 #define write_c0_conf(val)      __write_32bit_c0_register($3, 0, val)
1354
1355 #define read_c0_context()       __read_ulong_c0_register($4, 0)
1356 #define write_c0_context(val)   __write_ulong_c0_register($4, 0, val)
1357
1358 #define read_c0_contextconfig()         __read_32bit_c0_register($4, 1)
1359 #define write_c0_contextconfig(val)     __write_32bit_c0_register($4, 1, val)
1360
1361 #define read_c0_userlocal()     __read_ulong_c0_register($4, 2)
1362 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1363
1364 #define read_c0_xcontextconfig()        __read_ulong_c0_register($4, 3)
1365 #define write_c0_xcontextconfig(val)    __write_ulong_c0_register($4, 3, val)
1366
1367 #define read_c0_pagemask()      __read_32bit_c0_register($5, 0)
1368 #define write_c0_pagemask(val)  __write_32bit_c0_register($5, 0, val)
1369
1370 #define read_c0_pagegrain()     __read_32bit_c0_register($5, 1)
1371 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1372
1373 #define read_c0_wired()         __read_32bit_c0_register($6, 0)
1374 #define write_c0_wired(val)     __write_32bit_c0_register($6, 0, val)
1375
1376 #define read_c0_info()          __read_32bit_c0_register($7, 0)
1377
1378 #define read_c0_cache()         __read_32bit_c0_register($7, 0) /* TX39xx */
1379 #define write_c0_cache(val)     __write_32bit_c0_register($7, 0, val)
1380
1381 #define read_c0_badvaddr()      __read_ulong_c0_register($8, 0)
1382 #define write_c0_badvaddr(val)  __write_ulong_c0_register($8, 0, val)
1383
1384 #define read_c0_badinstr()      __read_32bit_c0_register($8, 1)
1385 #define read_c0_badinstrp()     __read_32bit_c0_register($8, 2)
1386
1387 #define read_c0_count()         __read_32bit_c0_register($9, 0)
1388 #define write_c0_count(val)     __write_32bit_c0_register($9, 0, val)
1389
1390 #define read_c0_count2()        __read_32bit_c0_register($9, 6) /* pnx8550 */
1391 #define write_c0_count2(val)    __write_32bit_c0_register($9, 6, val)
1392
1393 #define read_c0_count3()        __read_32bit_c0_register($9, 7) /* pnx8550 */
1394 #define write_c0_count3(val)    __write_32bit_c0_register($9, 7, val)
1395
1396 #define read_c0_entryhi()       __read_ulong_c0_register($10, 0)
1397 #define write_c0_entryhi(val)   __write_ulong_c0_register($10, 0, val)
1398
1399 #define read_c0_guestctl1()     __read_32bit_c0_register($10, 4)
1400 #define write_c0_guestctl1(val) __write_32bit_c0_register($10, 4, val)
1401
1402 #define read_c0_guestctl2()     __read_32bit_c0_register($10, 5)
1403 #define write_c0_guestctl2(val) __write_32bit_c0_register($10, 5, val)
1404
1405 #define read_c0_guestctl3()     __read_32bit_c0_register($10, 6)
1406 #define write_c0_guestctl3(val) __write_32bit_c0_register($10, 6, val)
1407
1408 #define read_c0_compare()       __read_32bit_c0_register($11, 0)
1409 #define write_c0_compare(val)   __write_32bit_c0_register($11, 0, val)
1410
1411 #define read_c0_guestctl0ext()  __read_32bit_c0_register($11, 4)
1412 #define write_c0_guestctl0ext(val) __write_32bit_c0_register($11, 4, val)
1413
1414 #define read_c0_compare2()      __read_32bit_c0_register($11, 6) /* pnx8550 */
1415 #define write_c0_compare2(val)  __write_32bit_c0_register($11, 6, val)
1416
1417 #define read_c0_compare3()      __read_32bit_c0_register($11, 7) /* pnx8550 */
1418 #define write_c0_compare3(val)  __write_32bit_c0_register($11, 7, val)
1419
1420 #define read_c0_status()        __read_32bit_c0_register($12, 0)
1421
1422 #define write_c0_status(val)    __write_32bit_c0_register($12, 0, val)
1423
1424 #define read_c0_guestctl0()     __read_32bit_c0_register($12, 6)
1425 #define write_c0_guestctl0(val) __write_32bit_c0_register($12, 6, val)
1426
1427 #define read_c0_gtoffset()      __read_32bit_c0_register($12, 7)
1428 #define write_c0_gtoffset(val)  __write_32bit_c0_register($12, 7, val)
1429
1430 #define read_c0_cause()         __read_32bit_c0_register($13, 0)
1431 #define write_c0_cause(val)     __write_32bit_c0_register($13, 0, val)
1432
1433 #define read_c0_epc()           __read_ulong_c0_register($14, 0)
1434 #define write_c0_epc(val)       __write_ulong_c0_register($14, 0, val)
1435
1436 #define read_c0_prid()          __read_32bit_c0_register($15, 0)
1437
1438 #define read_c0_cmgcrbase()     __read_ulong_c0_register($15, 3)
1439
1440 #define read_c0_config()        __read_32bit_c0_register($16, 0)
1441 #define read_c0_config1()       __read_32bit_c0_register($16, 1)
1442 #define read_c0_config2()       __read_32bit_c0_register($16, 2)
1443 #define read_c0_config3()       __read_32bit_c0_register($16, 3)
1444 #define read_c0_config4()       __read_32bit_c0_register($16, 4)
1445 #define read_c0_config5()       __read_32bit_c0_register($16, 5)
1446 #define read_c0_config6()       __read_32bit_c0_register($16, 6)
1447 #define read_c0_config7()       __read_32bit_c0_register($16, 7)
1448 #define write_c0_config(val)    __write_32bit_c0_register($16, 0, val)
1449 #define write_c0_config1(val)   __write_32bit_c0_register($16, 1, val)
1450 #define write_c0_config2(val)   __write_32bit_c0_register($16, 2, val)
1451 #define write_c0_config3(val)   __write_32bit_c0_register($16, 3, val)
1452 #define write_c0_config4(val)   __write_32bit_c0_register($16, 4, val)
1453 #define write_c0_config5(val)   __write_32bit_c0_register($16, 5, val)
1454 #define write_c0_config6(val)   __write_32bit_c0_register($16, 6, val)
1455 #define write_c0_config7(val)   __write_32bit_c0_register($16, 7, val)
1456
1457 #define read_c0_lladdr()        __read_ulong_c0_register($17, 0)
1458 #define write_c0_lladdr(val)    __write_ulong_c0_register($17, 0, val)
1459 #define read_c0_maar()          __read_ulong_c0_register($17, 1)
1460 #define write_c0_maar(val)      __write_ulong_c0_register($17, 1, val)
1461 #define read_c0_maari()         __read_32bit_c0_register($17, 2)
1462 #define write_c0_maari(val)     __write_32bit_c0_register($17, 2, val)
1463
1464 /*
1465  * The WatchLo register.  There may be up to 8 of them.
1466  */
1467 #define read_c0_watchlo0()      __read_ulong_c0_register($18, 0)
1468 #define read_c0_watchlo1()      __read_ulong_c0_register($18, 1)
1469 #define read_c0_watchlo2()      __read_ulong_c0_register($18, 2)
1470 #define read_c0_watchlo3()      __read_ulong_c0_register($18, 3)
1471 #define read_c0_watchlo4()      __read_ulong_c0_register($18, 4)
1472 #define read_c0_watchlo5()      __read_ulong_c0_register($18, 5)
1473 #define read_c0_watchlo6()      __read_ulong_c0_register($18, 6)
1474 #define read_c0_watchlo7()      __read_ulong_c0_register($18, 7)
1475 #define write_c0_watchlo0(val)  __write_ulong_c0_register($18, 0, val)
1476 #define write_c0_watchlo1(val)  __write_ulong_c0_register($18, 1, val)
1477 #define write_c0_watchlo2(val)  __write_ulong_c0_register($18, 2, val)
1478 #define write_c0_watchlo3(val)  __write_ulong_c0_register($18, 3, val)
1479 #define write_c0_watchlo4(val)  __write_ulong_c0_register($18, 4, val)
1480 #define write_c0_watchlo5(val)  __write_ulong_c0_register($18, 5, val)
1481 #define write_c0_watchlo6(val)  __write_ulong_c0_register($18, 6, val)
1482 #define write_c0_watchlo7(val)  __write_ulong_c0_register($18, 7, val)
1483
1484 /*
1485  * The WatchHi register.  There may be up to 8 of them.
1486  */
1487 #define read_c0_watchhi0()      __read_32bit_c0_register($19, 0)
1488 #define read_c0_watchhi1()      __read_32bit_c0_register($19, 1)
1489 #define read_c0_watchhi2()      __read_32bit_c0_register($19, 2)
1490 #define read_c0_watchhi3()      __read_32bit_c0_register($19, 3)
1491 #define read_c0_watchhi4()      __read_32bit_c0_register($19, 4)
1492 #define read_c0_watchhi5()      __read_32bit_c0_register($19, 5)
1493 #define read_c0_watchhi6()      __read_32bit_c0_register($19, 6)
1494 #define read_c0_watchhi7()      __read_32bit_c0_register($19, 7)
1495
1496 #define write_c0_watchhi0(val)  __write_32bit_c0_register($19, 0, val)
1497 #define write_c0_watchhi1(val)  __write_32bit_c0_register($19, 1, val)
1498 #define write_c0_watchhi2(val)  __write_32bit_c0_register($19, 2, val)
1499 #define write_c0_watchhi3(val)  __write_32bit_c0_register($19, 3, val)
1500 #define write_c0_watchhi4(val)  __write_32bit_c0_register($19, 4, val)
1501 #define write_c0_watchhi5(val)  __write_32bit_c0_register($19, 5, val)
1502 #define write_c0_watchhi6(val)  __write_32bit_c0_register($19, 6, val)
1503 #define write_c0_watchhi7(val)  __write_32bit_c0_register($19, 7, val)
1504
1505 #define read_c0_xcontext()      __read_ulong_c0_register($20, 0)
1506 #define write_c0_xcontext(val)  __write_ulong_c0_register($20, 0, val)
1507
1508 #define read_c0_intcontrol()    __read_32bit_c0_ctrl_register($20)
1509 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1510
1511 #define read_c0_framemask()     __read_32bit_c0_register($21, 0)
1512 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1513
1514 #define read_c0_diag()          __read_32bit_c0_register($22, 0)
1515 #define write_c0_diag(val)      __write_32bit_c0_register($22, 0, val)
1516
1517 /* R10K CP0 Branch Diagnostic register is 64bits wide */
1518 #define read_c0_r10k_diag()     __read_64bit_c0_register($22, 0)
1519 #define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
1520
1521 #define read_c0_diag1()         __read_32bit_c0_register($22, 1)
1522 #define write_c0_diag1(val)     __write_32bit_c0_register($22, 1, val)
1523
1524 #define read_c0_diag2()         __read_32bit_c0_register($22, 2)
1525 #define write_c0_diag2(val)     __write_32bit_c0_register($22, 2, val)
1526
1527 #define read_c0_diag3()         __read_32bit_c0_register($22, 3)
1528 #define write_c0_diag3(val)     __write_32bit_c0_register($22, 3, val)
1529
1530 #define read_c0_diag4()         __read_32bit_c0_register($22, 4)
1531 #define write_c0_diag4(val)     __write_32bit_c0_register($22, 4, val)
1532
1533 #define read_c0_diag5()         __read_32bit_c0_register($22, 5)
1534 #define write_c0_diag5(val)     __write_32bit_c0_register($22, 5, val)
1535
1536 #define read_c0_debug()         __read_32bit_c0_register($23, 0)
1537 #define write_c0_debug(val)     __write_32bit_c0_register($23, 0, val)
1538
1539 #define read_c0_depc()          __read_ulong_c0_register($24, 0)
1540 #define write_c0_depc(val)      __write_ulong_c0_register($24, 0, val)
1541
1542 /*
1543  * MIPS32 / MIPS64 performance counters
1544  */
1545 #define read_c0_perfctrl0()     __read_32bit_c0_register($25, 0)
1546 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1547 #define read_c0_perfcntr0()     __read_32bit_c0_register($25, 1)
1548 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1549 #define read_c0_perfcntr0_64()  __read_64bit_c0_register($25, 1)
1550 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1551 #define read_c0_perfctrl1()     __read_32bit_c0_register($25, 2)
1552 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1553 #define read_c0_perfcntr1()     __read_32bit_c0_register($25, 3)
1554 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1555 #define read_c0_perfcntr1_64()  __read_64bit_c0_register($25, 3)
1556 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1557 #define read_c0_perfctrl2()     __read_32bit_c0_register($25, 4)
1558 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1559 #define read_c0_perfcntr2()     __read_32bit_c0_register($25, 5)
1560 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1561 #define read_c0_perfcntr2_64()  __read_64bit_c0_register($25, 5)
1562 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1563 #define read_c0_perfctrl3()     __read_32bit_c0_register($25, 6)
1564 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1565 #define read_c0_perfcntr3()     __read_32bit_c0_register($25, 7)
1566 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1567 #define read_c0_perfcntr3_64()  __read_64bit_c0_register($25, 7)
1568 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1569
1570 #define read_c0_ecc()           __read_32bit_c0_register($26, 0)
1571 #define write_c0_ecc(val)       __write_32bit_c0_register($26, 0, val)
1572
1573 #define read_c0_derraddr0()     __read_ulong_c0_register($26, 1)
1574 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1575
1576 #define read_c0_cacheerr()      __read_32bit_c0_register($27, 0)
1577
1578 #define read_c0_derraddr1()     __read_ulong_c0_register($27, 1)
1579 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1580
1581 #define read_c0_taglo()         __read_32bit_c0_register($28, 0)
1582 #define write_c0_taglo(val)     __write_32bit_c0_register($28, 0, val)
1583
1584 #define read_c0_dtaglo()        __read_32bit_c0_register($28, 2)
1585 #define write_c0_dtaglo(val)    __write_32bit_c0_register($28, 2, val)
1586
1587 #define read_c0_ddatalo()       __read_32bit_c0_register($28, 3)
1588 #define write_c0_ddatalo(val)   __write_32bit_c0_register($28, 3, val)
1589
1590 #define read_c0_staglo()        __read_32bit_c0_register($28, 4)
1591 #define write_c0_staglo(val)    __write_32bit_c0_register($28, 4, val)
1592
1593 #define read_c0_taghi()         __read_32bit_c0_register($29, 0)
1594 #define write_c0_taghi(val)     __write_32bit_c0_register($29, 0, val)
1595
1596 #define read_c0_errorepc()      __read_ulong_c0_register($30, 0)
1597 #define write_c0_errorepc(val)  __write_ulong_c0_register($30, 0, val)
1598
1599 /* MIPSR2 */
1600 #define read_c0_hwrena()        __read_32bit_c0_register($7, 0)
1601 #define write_c0_hwrena(val)    __write_32bit_c0_register($7, 0, val)
1602
1603 #define read_c0_intctl()        __read_32bit_c0_register($12, 1)
1604 #define write_c0_intctl(val)    __write_32bit_c0_register($12, 1, val)
1605
1606 #define read_c0_srsctl()        __read_32bit_c0_register($12, 2)
1607 #define write_c0_srsctl(val)    __write_32bit_c0_register($12, 2, val)
1608
1609 #define read_c0_srsmap()        __read_32bit_c0_register($12, 3)
1610 #define write_c0_srsmap(val)    __write_32bit_c0_register($12, 3, val)
1611
1612 #define read_c0_ebase()         __read_32bit_c0_register($15, 1)
1613 #define write_c0_ebase(val)     __write_32bit_c0_register($15, 1, val)
1614
1615 #define read_c0_ebase_64()      __read_64bit_c0_register($15, 1)
1616 #define write_c0_ebase_64(val)  __write_64bit_c0_register($15, 1, val)
1617
1618 #define read_c0_cdmmbase()      __read_ulong_c0_register($15, 2)
1619 #define write_c0_cdmmbase(val)  __write_ulong_c0_register($15, 2, val)
1620
1621 /* MIPSR3 */
1622 #define read_c0_segctl0()       __read_32bit_c0_register($5, 2)
1623 #define write_c0_segctl0(val)   __write_32bit_c0_register($5, 2, val)
1624
1625 #define read_c0_segctl1()       __read_32bit_c0_register($5, 3)
1626 #define write_c0_segctl1(val)   __write_32bit_c0_register($5, 3, val)
1627
1628 #define read_c0_segctl2()       __read_32bit_c0_register($5, 4)
1629 #define write_c0_segctl2(val)   __write_32bit_c0_register($5, 4, val)
1630
1631 /* Hardware Page Table Walker */
1632 #define read_c0_pwbase()        __read_ulong_c0_register($5, 5)
1633 #define write_c0_pwbase(val)    __write_ulong_c0_register($5, 5, val)
1634
1635 #define read_c0_pwfield()       __read_ulong_c0_register($5, 6)
1636 #define write_c0_pwfield(val)   __write_ulong_c0_register($5, 6, val)
1637
1638 #define read_c0_pwsize()        __read_ulong_c0_register($5, 7)
1639 #define write_c0_pwsize(val)    __write_ulong_c0_register($5, 7, val)
1640
1641 #define read_c0_pwctl()         __read_32bit_c0_register($6, 6)
1642 #define write_c0_pwctl(val)     __write_32bit_c0_register($6, 6, val)
1643
1644 #define read_c0_pgd()           __read_64bit_c0_register($9, 7)
1645 #define write_c0_pgd(val)       __write_64bit_c0_register($9, 7, val)
1646
1647 #define read_c0_kpgd()          __read_64bit_c0_register($31, 7)
1648 #define write_c0_kpgd(val)      __write_64bit_c0_register($31, 7, val)
1649
1650 /* Cavium OCTEON (cnMIPS) */
1651 #define read_c0_cvmcount()      __read_ulong_c0_register($9, 6)
1652 #define write_c0_cvmcount(val)  __write_ulong_c0_register($9, 6, val)
1653
1654 #define read_c0_cvmctl()        __read_64bit_c0_register($9, 7)
1655 #define write_c0_cvmctl(val)    __write_64bit_c0_register($9, 7, val)
1656
1657 #define read_c0_cvmmemctl()     __read_64bit_c0_register($11, 7)
1658 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1659 /*
1660  * The cacheerr registers are not standardized.  On OCTEON, they are
1661  * 64 bits wide.
1662  */
1663 #define read_octeon_c0_icacheerr()      __read_64bit_c0_register($27, 0)
1664 #define write_octeon_c0_icacheerr(val)  __write_64bit_c0_register($27, 0, val)
1665
1666 #define read_octeon_c0_dcacheerr()      __read_64bit_c0_register($27, 1)
1667 #define write_octeon_c0_dcacheerr(val)  __write_64bit_c0_register($27, 1, val)
1668
1669 /* BMIPS3300 */
1670 #define read_c0_brcm_config_0()         __read_32bit_c0_register($22, 0)
1671 #define write_c0_brcm_config_0(val)     __write_32bit_c0_register($22, 0, val)
1672
1673 #define read_c0_brcm_bus_pll()          __read_32bit_c0_register($22, 4)
1674 #define write_c0_brcm_bus_pll(val)      __write_32bit_c0_register($22, 4, val)
1675
1676 #define read_c0_brcm_reset()            __read_32bit_c0_register($22, 5)
1677 #define write_c0_brcm_reset(val)        __write_32bit_c0_register($22, 5, val)
1678
1679 /* BMIPS43xx */
1680 #define read_c0_brcm_cmt_intr()         __read_32bit_c0_register($22, 1)
1681 #define write_c0_brcm_cmt_intr(val)     __write_32bit_c0_register($22, 1, val)
1682
1683 #define read_c0_brcm_cmt_ctrl()         __read_32bit_c0_register($22, 2)
1684 #define write_c0_brcm_cmt_ctrl(val)     __write_32bit_c0_register($22, 2, val)
1685
1686 #define read_c0_brcm_cmt_local()        __read_32bit_c0_register($22, 3)
1687 #define write_c0_brcm_cmt_local(val)    __write_32bit_c0_register($22, 3, val)
1688
1689 #define read_c0_brcm_config_1()         __read_32bit_c0_register($22, 5)
1690 #define write_c0_brcm_config_1(val)     __write_32bit_c0_register($22, 5, val)
1691
1692 #define read_c0_brcm_cbr()              __read_32bit_c0_register($22, 6)
1693 #define write_c0_brcm_cbr(val)          __write_32bit_c0_register($22, 6, val)
1694
1695 /* BMIPS5000 */
1696 #define read_c0_brcm_config()           __read_32bit_c0_register($22, 0)
1697 #define write_c0_brcm_config(val)       __write_32bit_c0_register($22, 0, val)
1698
1699 #define read_c0_brcm_mode()             __read_32bit_c0_register($22, 1)
1700 #define write_c0_brcm_mode(val)         __write_32bit_c0_register($22, 1, val)
1701
1702 #define read_c0_brcm_action()           __read_32bit_c0_register($22, 2)
1703 #define write_c0_brcm_action(val)       __write_32bit_c0_register($22, 2, val)
1704
1705 #define read_c0_brcm_edsp()             __read_32bit_c0_register($22, 3)
1706 #define write_c0_brcm_edsp(val)         __write_32bit_c0_register($22, 3, val)
1707
1708 #define read_c0_brcm_bootvec()          __read_32bit_c0_register($22, 4)
1709 #define write_c0_brcm_bootvec(val)      __write_32bit_c0_register($22, 4, val)
1710
1711 #define read_c0_brcm_sleepcount()       __read_32bit_c0_register($22, 7)
1712 #define write_c0_brcm_sleepcount(val)   __write_32bit_c0_register($22, 7, val)
1713
1714 /*
1715  * Macros to access the guest system control coprocessor
1716  */
1717
1718 #ifdef TOOLCHAIN_SUPPORTS_VIRT
1719
1720 #define __read_32bit_gc0_register(source, sel)                          \
1721 ({ int __res;                                                           \
1722         __asm__ __volatile__(                                           \
1723                 ".set\tpush\n\t"                                        \
1724                 ".set\tmips32r2\n\t"                                    \
1725                 ".set\tvirt\n\t"                                        \
1726                 "mfgc0\t%0, $%1, %2\n\t"                                \
1727                 ".set\tpop"                                             \
1728                 : "=r" (__res)                                          \
1729                 : "i" (source), "i" (sel));                             \
1730         __res;                                                          \
1731 })
1732
1733 #define __read_64bit_gc0_register(source, sel)                          \
1734 ({ unsigned long long __res;                                            \
1735         __asm__ __volatile__(                                           \
1736                 ".set\tpush\n\t"                                        \
1737                 ".set\tmips64r2\n\t"                                    \
1738                 ".set\tvirt\n\t"                                        \
1739                 "dmfgc0\t%0, $%1, %2\n\t"                       \
1740                 ".set\tpop"                                             \
1741                 : "=r" (__res)                                          \
1742                 : "i" (source), "i" (sel));                             \
1743         __res;                                                          \
1744 })
1745
1746 #define __write_32bit_gc0_register(register, sel, value)                \
1747 do {                                                                    \
1748         __asm__ __volatile__(                                           \
1749                 ".set\tpush\n\t"                                        \
1750                 ".set\tmips32r2\n\t"                                    \
1751                 ".set\tvirt\n\t"                                        \
1752                 "mtgc0\t%z0, $%1, %2\n\t"                               \
1753                 ".set\tpop"                                             \
1754                 : : "Jr" ((unsigned int)(value)),                       \
1755                     "i" (register), "i" (sel));                         \
1756 } while (0)
1757
1758 #define __write_64bit_gc0_register(register, sel, value)                \
1759 do {                                                                    \
1760         __asm__ __volatile__(                                           \
1761                 ".set\tpush\n\t"                                        \
1762                 ".set\tmips64r2\n\t"                                    \
1763                 ".set\tvirt\n\t"                                        \
1764                 "dmtgc0\t%z0, $%1, %2\n\t"                              \
1765                 ".set\tpop"                                             \
1766                 : : "Jr" (value),                                       \
1767                     "i" (register), "i" (sel));                         \
1768 } while (0)
1769
1770 #else   /* TOOLCHAIN_SUPPORTS_VIRT */
1771
1772 #define __read_32bit_gc0_register(source, sel)                          \
1773 ({ int __res;                                                           \
1774         __asm__ __volatile__(                                           \
1775                 ".set\tpush\n\t"                                        \
1776                 ".set\tnoat\n\t"                                        \
1777                 "# mfgc0\t$1, $%1, %2\n\t"                              \
1778                 _ASM_INSN_IF_MIPS(0x40610000 | %1 << 11 | %2)           \
1779                 _ASM_INSN32_IF_MM(0x002004fc | %1 << 16 | %2 << 11)     \
1780                 "move\t%0, $1\n\t"                                      \
1781                 ".set\tpop"                                             \
1782                 : "=r" (__res)                                          \
1783                 : "i" (source), "i" (sel));                             \
1784         __res;                                                          \
1785 })
1786
1787 #define __read_64bit_gc0_register(source, sel)                          \
1788 ({ unsigned long long __res;                                            \
1789         __asm__ __volatile__(                                           \
1790                 ".set\tpush\n\t"                                        \
1791                 ".set\tnoat\n\t"                                        \
1792                 "# dmfgc0\t$1, $%1, %2\n\t"                             \
1793                 _ASM_INSN_IF_MIPS(0x40610100 | %1 << 11 | %2)           \
1794                 _ASM_INSN32_IF_MM(0x582004fc | %1 << 16 | %2 << 11)     \
1795                 "move\t%0, $1\n\t"                                      \
1796                 ".set\tpop"                                             \
1797                 : "=r" (__res)                                          \
1798                 : "i" (source), "i" (sel));                             \
1799         __res;                                                          \
1800 })
1801
1802 #define __write_32bit_gc0_register(register, sel, value)                \
1803 do {                                                                    \
1804         __asm__ __volatile__(                                           \
1805                 ".set\tpush\n\t"                                        \
1806                 ".set\tnoat\n\t"                                        \
1807                 "move\t$1, %z0\n\t"                                     \
1808                 "# mtgc0\t$1, $%1, %2\n\t"                              \
1809                 _ASM_INSN_IF_MIPS(0x40610200 | %1 << 11 | %2)           \
1810                 _ASM_INSN32_IF_MM(0x002006fc | %1 << 16 | %2 << 11)     \
1811                 ".set\tpop"                                             \
1812                 : : "Jr" ((unsigned int)(value)),                       \
1813                     "i" (register), "i" (sel));                         \
1814 } while (0)
1815
1816 #define __write_64bit_gc0_register(register, sel, value)                \
1817 do {                                                                    \
1818         __asm__ __volatile__(                                           \
1819                 ".set\tpush\n\t"                                        \
1820                 ".set\tnoat\n\t"                                        \
1821                 "move\t$1, %z0\n\t"                                     \
1822                 "# dmtgc0\t$1, $%1, %2\n\t"                             \
1823                 _ASM_INSN_IF_MIPS(0x40610300 | %1 << 11 | %2)           \
1824                 _ASM_INSN32_IF_MM(0x582006fc | %1 << 16 | %2 << 11)     \
1825                 ".set\tpop"                                             \
1826                 : : "Jr" (value),                                       \
1827                     "i" (register), "i" (sel));                         \
1828 } while (0)
1829
1830 #endif  /* !TOOLCHAIN_SUPPORTS_VIRT */
1831
1832 #define __read_ulong_gc0_register(reg, sel)                             \
1833         ((sizeof(unsigned long) == 4) ?                                 \
1834         (unsigned long) __read_32bit_gc0_register(reg, sel) :           \
1835         (unsigned long) __read_64bit_gc0_register(reg, sel))
1836
1837 #define __write_ulong_gc0_register(reg, sel, val)                       \
1838 do {                                                                    \
1839         if (sizeof(unsigned long) == 4)                                 \
1840                 __write_32bit_gc0_register(reg, sel, val);              \
1841         else                                                            \
1842                 __write_64bit_gc0_register(reg, sel, val);              \
1843 } while (0)
1844
1845 #define read_gc0_index()                __read_32bit_gc0_register(0, 0)
1846 #define write_gc0_index(val)            __write_32bit_gc0_register(0, 0, val)
1847
1848 #define read_gc0_entrylo0()             __read_ulong_gc0_register(2, 0)
1849 #define write_gc0_entrylo0(val)         __write_ulong_gc0_register(2, 0, val)
1850
1851 #define read_gc0_entrylo1()             __read_ulong_gc0_register(3, 0)
1852 #define write_gc0_entrylo1(val)         __write_ulong_gc0_register(3, 0, val)
1853
1854 #define read_gc0_context()              __read_ulong_gc0_register(4, 0)
1855 #define write_gc0_context(val)          __write_ulong_gc0_register(4, 0, val)
1856
1857 #define read_gc0_contextconfig()        __read_32bit_gc0_register(4, 1)
1858 #define write_gc0_contextconfig(val)    __write_32bit_gc0_register(4, 1, val)
1859
1860 #define read_gc0_userlocal()            __read_ulong_gc0_register(4, 2)
1861 #define write_gc0_userlocal(val)        __write_ulong_gc0_register(4, 2, val)
1862
1863 #define read_gc0_xcontextconfig()       __read_ulong_gc0_register(4, 3)
1864 #define write_gc0_xcontextconfig(val)   __write_ulong_gc0_register(4, 3, val)
1865
1866 #define read_gc0_pagemask()             __read_32bit_gc0_register(5, 0)
1867 #define write_gc0_pagemask(val)         __write_32bit_gc0_register(5, 0, val)
1868
1869 #define read_gc0_pagegrain()            __read_32bit_gc0_register(5, 1)
1870 #define write_gc0_pagegrain(val)        __write_32bit_gc0_register(5, 1, val)
1871
1872 #define read_gc0_segctl0()              __read_ulong_gc0_register(5, 2)
1873 #define write_gc0_segctl0(val)          __write_ulong_gc0_register(5, 2, val)
1874
1875 #define read_gc0_segctl1()              __read_ulong_gc0_register(5, 3)
1876 #define write_gc0_segctl1(val)          __write_ulong_gc0_register(5, 3, val)
1877
1878 #define read_gc0_segctl2()              __read_ulong_gc0_register(5, 4)
1879 #define write_gc0_segctl2(val)          __write_ulong_gc0_register(5, 4, val)
1880
1881 #define read_gc0_pwbase()               __read_ulong_gc0_register(5, 5)
1882 #define write_gc0_pwbase(val)           __write_ulong_gc0_register(5, 5, val)
1883
1884 #define read_gc0_pwfield()              __read_ulong_gc0_register(5, 6)
1885 #define write_gc0_pwfield(val)          __write_ulong_gc0_register(5, 6, val)
1886
1887 #define read_gc0_pwsize()               __read_ulong_gc0_register(5, 7)
1888 #define write_gc0_pwsize(val)           __write_ulong_gc0_register(5, 7, val)
1889
1890 #define read_gc0_wired()                __read_32bit_gc0_register(6, 0)
1891 #define write_gc0_wired(val)            __write_32bit_gc0_register(6, 0, val)
1892
1893 #define read_gc0_pwctl()                __read_32bit_gc0_register(6, 6)
1894 #define write_gc0_pwctl(val)            __write_32bit_gc0_register(6, 6, val)
1895
1896 #define read_gc0_hwrena()               __read_32bit_gc0_register(7, 0)
1897 #define write_gc0_hwrena(val)           __write_32bit_gc0_register(7, 0, val)
1898
1899 #define read_gc0_badvaddr()             __read_ulong_gc0_register(8, 0)
1900 #define write_gc0_badvaddr(val)         __write_ulong_gc0_register(8, 0, val)
1901
1902 #define read_gc0_badinstr()             __read_32bit_gc0_register(8, 1)
1903 #define write_gc0_badinstr(val)         __write_32bit_gc0_register(8, 1, val)
1904
1905 #define read_gc0_badinstrp()            __read_32bit_gc0_register(8, 2)
1906 #define write_gc0_badinstrp(val)        __write_32bit_gc0_register(8, 2, val)
1907
1908 #define read_gc0_count()                __read_32bit_gc0_register(9, 0)
1909
1910 #define read_gc0_entryhi()              __read_ulong_gc0_register(10, 0)
1911 #define write_gc0_entryhi(val)          __write_ulong_gc0_register(10, 0, val)
1912
1913 #define read_gc0_compare()              __read_32bit_gc0_register(11, 0)
1914 #define write_gc0_compare(val)          __write_32bit_gc0_register(11, 0, val)
1915
1916 #define read_gc0_status()               __read_32bit_gc0_register(12, 0)
1917 #define write_gc0_status(val)           __write_32bit_gc0_register(12, 0, val)
1918
1919 #define read_gc0_intctl()               __read_32bit_gc0_register(12, 1)
1920 #define write_gc0_intctl(val)           __write_32bit_gc0_register(12, 1, val)
1921
1922 #define read_gc0_cause()                __read_32bit_gc0_register(13, 0)
1923 #define write_gc0_cause(val)            __write_32bit_gc0_register(13, 0, val)
1924
1925 #define read_gc0_epc()                  __read_ulong_gc0_register(14, 0)
1926 #define write_gc0_epc(val)              __write_ulong_gc0_register(14, 0, val)
1927
1928 #define read_gc0_ebase()                __read_32bit_gc0_register(15, 1)
1929 #define write_gc0_ebase(val)            __write_32bit_gc0_register(15, 1, val)
1930
1931 #define read_gc0_ebase_64()             __read_64bit_gc0_register(15, 1)
1932 #define write_gc0_ebase_64(val)         __write_64bit_gc0_register(15, 1, val)
1933
1934 #define read_gc0_config()               __read_32bit_gc0_register(16, 0)
1935 #define read_gc0_config1()              __read_32bit_gc0_register(16, 1)
1936 #define read_gc0_config2()              __read_32bit_gc0_register(16, 2)
1937 #define read_gc0_config3()              __read_32bit_gc0_register(16, 3)
1938 #define read_gc0_config4()              __read_32bit_gc0_register(16, 4)
1939 #define read_gc0_config5()              __read_32bit_gc0_register(16, 5)
1940 #define read_gc0_config6()              __read_32bit_gc0_register(16, 6)
1941 #define read_gc0_config7()              __read_32bit_gc0_register(16, 7)
1942 #define write_gc0_config(val)           __write_32bit_gc0_register(16, 0, val)
1943 #define write_gc0_config1(val)          __write_32bit_gc0_register(16, 1, val)
1944 #define write_gc0_config2(val)          __write_32bit_gc0_register(16, 2, val)
1945 #define write_gc0_config3(val)          __write_32bit_gc0_register(16, 3, val)
1946 #define write_gc0_config4(val)          __write_32bit_gc0_register(16, 4, val)
1947 #define write_gc0_config5(val)          __write_32bit_gc0_register(16, 5, val)
1948 #define write_gc0_config6(val)          __write_32bit_gc0_register(16, 6, val)
1949 #define write_gc0_config7(val)          __write_32bit_gc0_register(16, 7, val)
1950
1951 #define read_gc0_watchlo0()             __read_ulong_gc0_register(18, 0)
1952 #define read_gc0_watchlo1()             __read_ulong_gc0_register(18, 1)
1953 #define read_gc0_watchlo2()             __read_ulong_gc0_register(18, 2)
1954 #define read_gc0_watchlo3()             __read_ulong_gc0_register(18, 3)
1955 #define read_gc0_watchlo4()             __read_ulong_gc0_register(18, 4)
1956 #define read_gc0_watchlo5()             __read_ulong_gc0_register(18, 5)
1957 #define read_gc0_watchlo6()             __read_ulong_gc0_register(18, 6)
1958 #define read_gc0_watchlo7()             __read_ulong_gc0_register(18, 7)
1959 #define write_gc0_watchlo0(val)         __write_ulong_gc0_register(18, 0, val)
1960 #define write_gc0_watchlo1(val)         __write_ulong_gc0_register(18, 1, val)
1961 #define write_gc0_watchlo2(val)         __write_ulong_gc0_register(18, 2, val)
1962 #define write_gc0_watchlo3(val)         __write_ulong_gc0_register(18, 3, val)
1963 #define write_gc0_watchlo4(val)         __write_ulong_gc0_register(18, 4, val)
1964 #define write_gc0_watchlo5(val)         __write_ulong_gc0_register(18, 5, val)
1965 #define write_gc0_watchlo6(val)         __write_ulong_gc0_register(18, 6, val)
1966 #define write_gc0_watchlo7(val)         __write_ulong_gc0_register(18, 7, val)
1967
1968 #define read_gc0_watchhi0()             __read_32bit_gc0_register(19, 0)
1969 #define read_gc0_watchhi1()             __read_32bit_gc0_register(19, 1)
1970 #define read_gc0_watchhi2()             __read_32bit_gc0_register(19, 2)
1971 #define read_gc0_watchhi3()             __read_32bit_gc0_register(19, 3)
1972 #define read_gc0_watchhi4()             __read_32bit_gc0_register(19, 4)
1973 #define read_gc0_watchhi5()             __read_32bit_gc0_register(19, 5)
1974 #define read_gc0_watchhi6()             __read_32bit_gc0_register(19, 6)
1975 #define read_gc0_watchhi7()             __read_32bit_gc0_register(19, 7)
1976 #define write_gc0_watchhi0(val)         __write_32bit_gc0_register(19, 0, val)
1977 #define write_gc0_watchhi1(val)         __write_32bit_gc0_register(19, 1, val)
1978 #define write_gc0_watchhi2(val)         __write_32bit_gc0_register(19, 2, val)
1979 #define write_gc0_watchhi3(val)         __write_32bit_gc0_register(19, 3, val)
1980 #define write_gc0_watchhi4(val)         __write_32bit_gc0_register(19, 4, val)
1981 #define write_gc0_watchhi5(val)         __write_32bit_gc0_register(19, 5, val)
1982 #define write_gc0_watchhi6(val)         __write_32bit_gc0_register(19, 6, val)
1983 #define write_gc0_watchhi7(val)         __write_32bit_gc0_register(19, 7, val)
1984
1985 #define read_gc0_xcontext()             __read_ulong_gc0_register(20, 0)
1986 #define write_gc0_xcontext(val)         __write_ulong_gc0_register(20, 0, val)
1987
1988 #define read_gc0_perfctrl0()            __read_32bit_gc0_register(25, 0)
1989 #define write_gc0_perfctrl0(val)        __write_32bit_gc0_register(25, 0, val)
1990 #define read_gc0_perfcntr0()            __read_32bit_gc0_register(25, 1)
1991 #define write_gc0_perfcntr0(val)        __write_32bit_gc0_register(25, 1, val)
1992 #define read_gc0_perfcntr0_64()         __read_64bit_gc0_register(25, 1)
1993 #define write_gc0_perfcntr0_64(val)     __write_64bit_gc0_register(25, 1, val)
1994 #define read_gc0_perfctrl1()            __read_32bit_gc0_register(25, 2)
1995 #define write_gc0_perfctrl1(val)        __write_32bit_gc0_register(25, 2, val)
1996 #define read_gc0_perfcntr1()            __read_32bit_gc0_register(25, 3)
1997 #define write_gc0_perfcntr1(val)        __write_32bit_gc0_register(25, 3, val)
1998 #define read_gc0_perfcntr1_64()         __read_64bit_gc0_register(25, 3)
1999 #define write_gc0_perfcntr1_64(val)     __write_64bit_gc0_register(25, 3, val)
2000 #define read_gc0_perfctrl2()            __read_32bit_gc0_register(25, 4)
2001 #define write_gc0_perfctrl2(val)        __write_32bit_gc0_register(25, 4, val)
2002 #define read_gc0_perfcntr2()            __read_32bit_gc0_register(25, 5)
2003 #define write_gc0_perfcntr2(val)        __write_32bit_gc0_register(25, 5, val)
2004 #define read_gc0_perfcntr2_64()         __read_64bit_gc0_register(25, 5)
2005 #define write_gc0_perfcntr2_64(val)     __write_64bit_gc0_register(25, 5, val)
2006 #define read_gc0_perfctrl3()            __read_32bit_gc0_register(25, 6)
2007 #define write_gc0_perfctrl3(val)        __write_32bit_gc0_register(25, 6, val)
2008 #define read_gc0_perfcntr3()            __read_32bit_gc0_register(25, 7)
2009 #define write_gc0_perfcntr3(val)        __write_32bit_gc0_register(25, 7, val)
2010 #define read_gc0_perfcntr3_64()         __read_64bit_gc0_register(25, 7)
2011 #define write_gc0_perfcntr3_64(val)     __write_64bit_gc0_register(25, 7, val)
2012
2013 #define read_gc0_errorepc()             __read_ulong_gc0_register(30, 0)
2014 #define write_gc0_errorepc(val)         __write_ulong_gc0_register(30, 0, val)
2015
2016 #define read_gc0_kscratch1()            __read_ulong_gc0_register(31, 2)
2017 #define read_gc0_kscratch2()            __read_ulong_gc0_register(31, 3)
2018 #define read_gc0_kscratch3()            __read_ulong_gc0_register(31, 4)
2019 #define read_gc0_kscratch4()            __read_ulong_gc0_register(31, 5)
2020 #define read_gc0_kscratch5()            __read_ulong_gc0_register(31, 6)
2021 #define read_gc0_kscratch6()            __read_ulong_gc0_register(31, 7)
2022 #define write_gc0_kscratch1(val)        __write_ulong_gc0_register(31, 2, val)
2023 #define write_gc0_kscratch2(val)        __write_ulong_gc0_register(31, 3, val)
2024 #define write_gc0_kscratch3(val)        __write_ulong_gc0_register(31, 4, val)
2025 #define write_gc0_kscratch4(val)        __write_ulong_gc0_register(31, 5, val)
2026 #define write_gc0_kscratch5(val)        __write_ulong_gc0_register(31, 6, val)
2027 #define write_gc0_kscratch6(val)        __write_ulong_gc0_register(31, 7, val)
2028
2029 /*
2030  * Macros to access the floating point coprocessor control registers
2031  */
2032 #define _read_32bit_cp1_register(source, gas_hardfloat)                 \
2033 ({                                                                      \
2034         unsigned int __res;                                             \
2035                                                                         \
2036         __asm__ __volatile__(                                           \
2037         "       .set    push                                    \n"     \
2038         "       .set    reorder                                 \n"     \
2039         "       # gas fails to assemble cfc1 for some archs,    \n"     \
2040         "       # like Octeon.                                  \n"     \
2041         "       .set    mips1                                   \n"     \
2042         "       "STR(gas_hardfloat)"                            \n"     \
2043         "       cfc1    %0,"STR(source)"                        \n"     \
2044         "       .set    pop                                     \n"     \
2045         : "=r" (__res));                                                \
2046         __res;                                                          \
2047 })
2048
2049 #define _write_32bit_cp1_register(dest, val, gas_hardfloat)             \
2050 do {                                                                    \
2051         __asm__ __volatile__(                                           \
2052         "       .set    push                                    \n"     \
2053         "       .set    reorder                                 \n"     \
2054         "       "STR(gas_hardfloat)"                            \n"     \
2055         "       ctc1    %0,"STR(dest)"                          \n"     \
2056         "       .set    pop                                     \n"     \
2057         : : "r" (val));                                                 \
2058 } while (0)
2059
2060 #ifdef GAS_HAS_SET_HARDFLOAT
2061 #define read_32bit_cp1_register(source)                                 \
2062         _read_32bit_cp1_register(source, .set hardfloat)
2063 #define write_32bit_cp1_register(dest, val)                             \
2064         _write_32bit_cp1_register(dest, val, .set hardfloat)
2065 #else
2066 #define read_32bit_cp1_register(source)                                 \
2067         _read_32bit_cp1_register(source, )
2068 #define write_32bit_cp1_register(dest, val)                             \
2069         _write_32bit_cp1_register(dest, val, )
2070 #endif
2071
2072 #ifdef HAVE_AS_DSP
2073 #define rddsp(mask)                                                     \
2074 ({                                                                      \
2075         unsigned int __dspctl;                                          \
2076                                                                         \
2077         __asm__ __volatile__(                                           \
2078         "       .set push                                       \n"     \
2079         "       .set dsp                                        \n"     \
2080         "       rddsp   %0, %x1                                 \n"     \
2081         "       .set pop                                        \n"     \
2082         : "=r" (__dspctl)                                               \
2083         : "i" (mask));                                                  \
2084         __dspctl;                                                       \
2085 })
2086
2087 #define wrdsp(val, mask)                                                \
2088 do {                                                                    \
2089         __asm__ __volatile__(                                           \
2090         "       .set push                                       \n"     \
2091         "       .set dsp                                        \n"     \
2092         "       wrdsp   %0, %x1                                 \n"     \
2093         "       .set pop                                        \n"     \
2094         :                                                               \
2095         : "r" (val), "i" (mask));                                       \
2096 } while (0)
2097
2098 #define mflo0()                                                         \
2099 ({                                                                      \
2100         long mflo0;                                                     \
2101         __asm__(                                                        \
2102         "       .set push                                       \n"     \
2103         "       .set dsp                                        \n"     \
2104         "       mflo %0, $ac0                                   \n"     \
2105         "       .set pop                                        \n"     \
2106         : "=r" (mflo0));                                                \
2107         mflo0;                                                          \
2108 })
2109
2110 #define mflo1()                                                         \
2111 ({                                                                      \
2112         long mflo1;                                                     \
2113         __asm__(                                                        \
2114         "       .set push                                       \n"     \
2115         "       .set dsp                                        \n"     \
2116         "       mflo %0, $ac1                                   \n"     \
2117         "       .set pop                                        \n"     \
2118         : "=r" (mflo1));                                                \
2119         mflo1;                                                          \
2120 })
2121
2122 #define mflo2()                                                         \
2123 ({                                                                      \
2124         long mflo2;                                                     \
2125         __asm__(                                                        \
2126         "       .set push                                       \n"     \
2127         "       .set dsp                                        \n"     \
2128         "       mflo %0, $ac2                                   \n"     \
2129         "       .set pop                                        \n"     \
2130         : "=r" (mflo2));                                                \
2131         mflo2;                                                          \
2132 })
2133
2134 #define mflo3()                                                         \
2135 ({                                                                      \
2136         long mflo3;                                                     \
2137         __asm__(                                                        \
2138         "       .set push                                       \n"     \
2139         "       .set dsp                                        \n"     \
2140         "       mflo %0, $ac3                                   \n"     \
2141         "       .set pop                                        \n"     \
2142         : "=r" (mflo3));                                                \
2143         mflo3;                                                          \
2144 })
2145
2146 #define mfhi0()                                                         \
2147 ({                                                                      \
2148         long mfhi0;                                                     \
2149         __asm__(                                                        \
2150         "       .set push                                       \n"     \
2151         "       .set dsp                                        \n"     \
2152         "       mfhi %0, $ac0                                   \n"     \
2153         "       .set pop                                        \n"     \
2154         : "=r" (mfhi0));                                                \
2155         mfhi0;                                                          \
2156 })
2157
2158 #define mfhi1()                                                         \
2159 ({                                                                      \
2160         long mfhi1;                                                     \
2161         __asm__(                                                        \
2162         "       .set push                                       \n"     \
2163         "       .set dsp                                        \n"     \
2164         "       mfhi %0, $ac1                                   \n"     \
2165         "       .set pop                                        \n"     \
2166         : "=r" (mfhi1));                                                \
2167         mfhi1;                                                          \
2168 })
2169
2170 #define mfhi2()                                                         \
2171 ({                                                                      \
2172         long mfhi2;                                                     \
2173         __asm__(                                                        \
2174         "       .set push                                       \n"     \
2175         "       .set dsp                                        \n"     \
2176         "       mfhi %0, $ac2                                   \n"     \
2177         "       .set pop                                        \n"     \
2178         : "=r" (mfhi2));                                                \
2179         mfhi2;                                                          \
2180 })
2181
2182 #define mfhi3()                                                         \
2183 ({                                                                      \
2184         long mfhi3;                                                     \
2185         __asm__(                                                        \
2186         "       .set push                                       \n"     \
2187         "       .set dsp                                        \n"     \
2188         "       mfhi %0, $ac3                                   \n"     \
2189         "       .set pop                                        \n"     \
2190         : "=r" (mfhi3));                                                \
2191         mfhi3;                                                          \
2192 })
2193
2194
2195 #define mtlo0(x)                                                        \
2196 ({                                                                      \
2197         __asm__(                                                        \
2198         "       .set push                                       \n"     \
2199         "       .set dsp                                        \n"     \
2200         "       mtlo %0, $ac0                                   \n"     \
2201         "       .set pop                                        \n"     \
2202         :                                                               \
2203         : "r" (x));                                                     \
2204 })
2205
2206 #define mtlo1(x)                                                        \
2207 ({                                                                      \
2208         __asm__(                                                        \
2209         "       .set push                                       \n"     \
2210         "       .set dsp                                        \n"     \
2211         "       mtlo %0, $ac1                                   \n"     \
2212         "       .set pop                                        \n"     \
2213         :                                                               \
2214         : "r" (x));                                                     \
2215 })
2216
2217 #define mtlo2(x)                                                        \
2218 ({                                                                      \
2219         __asm__(                                                        \
2220         "       .set push                                       \n"     \
2221         "       .set dsp                                        \n"     \
2222         "       mtlo %0, $ac2                                   \n"     \
2223         "       .set pop                                        \n"     \
2224         :                                                               \
2225         : "r" (x));                                                     \
2226 })
2227
2228 #define mtlo3(x)                                                        \
2229 ({                                                                      \
2230         __asm__(                                                        \
2231         "       .set push                                       \n"     \
2232         "       .set dsp                                        \n"     \
2233         "       mtlo %0, $ac3                                   \n"     \
2234         "       .set pop                                        \n"     \
2235         :                                                               \
2236         : "r" (x));                                                     \
2237 })
2238
2239 #define mthi0(x)                                                        \
2240 ({                                                                      \
2241         __asm__(                                                        \
2242         "       .set push                                       \n"     \
2243         "       .set dsp                                        \n"     \
2244         "       mthi %0, $ac0                                   \n"     \
2245         "       .set pop                                        \n"     \
2246         :                                                               \
2247         : "r" (x));                                                     \
2248 })
2249
2250 #define mthi1(x)                                                        \
2251 ({                                                                      \
2252         __asm__(                                                        \
2253         "       .set push                                       \n"     \
2254         "       .set dsp                                        \n"     \
2255         "       mthi %0, $ac1                                   \n"     \
2256         "       .set pop                                        \n"     \
2257         :                                                               \
2258         : "r" (x));                                                     \
2259 })
2260
2261 #define mthi2(x)                                                        \
2262 ({                                                                      \
2263         __asm__(                                                        \
2264         "       .set push                                       \n"     \
2265         "       .set dsp                                        \n"     \
2266         "       mthi %0, $ac2                                   \n"     \
2267         "       .set pop                                        \n"     \
2268         :                                                               \
2269         : "r" (x));                                                     \
2270 })
2271
2272 #define mthi3(x)                                                        \
2273 ({                                                                      \
2274         __asm__(                                                        \
2275         "       .set push                                       \n"     \
2276         "       .set dsp                                        \n"     \
2277         "       mthi %0, $ac3                                   \n"     \
2278         "       .set pop                                        \n"     \
2279         :                                                               \
2280         : "r" (x));                                                     \
2281 })
2282
2283 #else
2284
2285 #ifdef CONFIG_CPU_MICROMIPS
2286 #define rddsp(mask)                                                     \
2287 ({                                                                      \
2288         unsigned int __res;                                             \
2289                                                                         \
2290         __asm__ __volatile__(                                           \
2291         "       .set    push                                    \n"     \
2292         "       .set    noat                                    \n"     \
2293         "       # rddsp $1, %x1                                 \n"     \
2294         "       .hword  ((0x0020067c | (%x1 << 14)) >> 16)      \n"     \
2295         "       .hword  ((0x0020067c | (%x1 << 14)) & 0xffff)   \n"     \
2296         "       move    %0, $1                                  \n"     \
2297         "       .set    pop                                     \n"     \
2298         : "=r" (__res)                                                  \
2299         : "i" (mask));                                                  \
2300         __res;                                                          \
2301 })
2302
2303 #define wrdsp(val, mask)                                                \
2304 do {                                                                    \
2305         __asm__ __volatile__(                                           \
2306         "       .set    push                                    \n"     \
2307         "       .set    noat                                    \n"     \
2308         "       move    $1, %0                                  \n"     \
2309         "       # wrdsp $1, %x1                                 \n"     \
2310         "       .hword  ((0x0020167c | (%x1 << 14)) >> 16)      \n"     \
2311         "       .hword  ((0x0020167c | (%x1 << 14)) & 0xffff)   \n"     \
2312         "       .set    pop                                     \n"     \
2313         :                                                               \
2314         : "r" (val), "i" (mask));                                       \
2315 } while (0)
2316
2317 #define _umips_dsp_mfxxx(ins)                                           \
2318 ({                                                                      \
2319         unsigned long __treg;                                           \
2320                                                                         \
2321         __asm__ __volatile__(                                           \
2322         "       .set    push                                    \n"     \
2323         "       .set    noat                                    \n"     \
2324         "       .hword  0x0001                                  \n"     \
2325         "       .hword  %x1                                     \n"     \
2326         "       move    %0, $1                                  \n"     \
2327         "       .set    pop                                     \n"     \
2328         : "=r" (__treg)                                                 \
2329         : "i" (ins));                                                   \
2330         __treg;                                                         \
2331 })
2332
2333 #define _umips_dsp_mtxxx(val, ins)                                      \
2334 do {                                                                    \
2335         __asm__ __volatile__(                                           \
2336         "       .set    push                                    \n"     \
2337         "       .set    noat                                    \n"     \
2338         "       move    $1, %0                                  \n"     \
2339         "       .hword  0x0001                                  \n"     \
2340         "       .hword  %x1                                     \n"     \
2341         "       .set    pop                                     \n"     \
2342         :                                                               \
2343         : "r" (val), "i" (ins));                                        \
2344 } while (0)
2345
2346 #define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c)
2347 #define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)
2348
2349 #define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
2350 #define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
2351
2352 #define mflo0() _umips_dsp_mflo(0)
2353 #define mflo1() _umips_dsp_mflo(1)
2354 #define mflo2() _umips_dsp_mflo(2)
2355 #define mflo3() _umips_dsp_mflo(3)
2356
2357 #define mfhi0() _umips_dsp_mfhi(0)
2358 #define mfhi1() _umips_dsp_mfhi(1)
2359 #define mfhi2() _umips_dsp_mfhi(2)
2360 #define mfhi3() _umips_dsp_mfhi(3)
2361
2362 #define mtlo0(x) _umips_dsp_mtlo(x, 0)
2363 #define mtlo1(x) _umips_dsp_mtlo(x, 1)
2364 #define mtlo2(x) _umips_dsp_mtlo(x, 2)
2365 #define mtlo3(x) _umips_dsp_mtlo(x, 3)
2366
2367 #define mthi0(x) _umips_dsp_mthi(x, 0)
2368 #define mthi1(x) _umips_dsp_mthi(x, 1)
2369 #define mthi2(x) _umips_dsp_mthi(x, 2)
2370 #define mthi3(x) _umips_dsp_mthi(x, 3)
2371
2372 #else  /* !CONFIG_CPU_MICROMIPS */
2373 #define rddsp(mask)                                                     \
2374 ({                                                                      \
2375         unsigned int __res;                                             \
2376                                                                         \
2377         __asm__ __volatile__(                                           \
2378         "       .set    push                            \n"             \
2379         "       .set    noat                            \n"             \
2380         "       # rddsp $1, %x1                         \n"             \
2381         "       .word   0x7c000cb8 | (%x1 << 16)        \n"             \
2382         "       move    %0, $1                          \n"             \
2383         "       .set    pop                             \n"             \
2384         : "=r" (__res)                                                  \
2385         : "i" (mask));                                                  \
2386         __res;                                                          \
2387 })
2388
2389 #define wrdsp(val, mask)                                                \
2390 do {                                                                    \
2391         __asm__ __volatile__(                                           \
2392         "       .set    push                                    \n"     \
2393         "       .set    noat                                    \n"     \
2394         "       move    $1, %0                                  \n"     \
2395         "       # wrdsp $1, %x1                                 \n"     \
2396         "       .word   0x7c2004f8 | (%x1 << 11)                \n"     \
2397         "       .set    pop                                     \n"     \
2398         :                                                               \
2399         : "r" (val), "i" (mask));                                       \
2400 } while (0)
2401
2402 #define _dsp_mfxxx(ins)                                                 \
2403 ({                                                                      \
2404         unsigned long __treg;                                           \
2405                                                                         \
2406         __asm__ __volatile__(                                           \
2407         "       .set    push                                    \n"     \
2408         "       .set    noat                                    \n"     \
2409         "       .word   (0x00000810 | %1)                       \n"     \
2410         "       move    %0, $1                                  \n"     \
2411         "       .set    pop                                     \n"     \
2412         : "=r" (__treg)                                                 \
2413         : "i" (ins));                                                   \
2414         __treg;                                                         \
2415 })
2416
2417 #define _dsp_mtxxx(val, ins)                                            \
2418 do {                                                                    \
2419         __asm__ __volatile__(                                           \
2420         "       .set    push                                    \n"     \
2421         "       .set    noat                                    \n"     \
2422         "       move    $1, %0                                  \n"     \
2423         "       .word   (0x00200011 | %1)                       \n"     \
2424         "       .set    pop                                     \n"     \
2425         :                                                               \
2426         : "r" (val), "i" (ins));                                        \
2427 } while (0)
2428
2429 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
2430 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
2431
2432 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
2433 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
2434
2435 #define mflo0() _dsp_mflo(0)
2436 #define mflo1() _dsp_mflo(1)
2437 #define mflo2() _dsp_mflo(2)
2438 #define mflo3() _dsp_mflo(3)
2439
2440 #define mfhi0() _dsp_mfhi(0)
2441 #define mfhi1() _dsp_mfhi(1)
2442 #define mfhi2() _dsp_mfhi(2)
2443 #define mfhi3() _dsp_mfhi(3)
2444
2445 #define mtlo0(x) _dsp_mtlo(x, 0)
2446 #define mtlo1(x) _dsp_mtlo(x, 1)
2447 #define mtlo2(x) _dsp_mtlo(x, 2)
2448 #define mtlo3(x) _dsp_mtlo(x, 3)
2449
2450 #define mthi0(x) _dsp_mthi(x, 0)
2451 #define mthi1(x) _dsp_mthi(x, 1)
2452 #define mthi2(x) _dsp_mthi(x, 2)
2453 #define mthi3(x) _dsp_mthi(x, 3)
2454
2455 #endif /* CONFIG_CPU_MICROMIPS */
2456 #endif
2457
2458 /*
2459  * TLB operations.
2460  *
2461  * It is responsibility of the caller to take care of any TLB hazards.
2462  */
2463 static inline void tlb_probe(void)
2464 {
2465         __asm__ __volatile__(
2466                 ".set noreorder\n\t"
2467                 "tlbp\n\t"
2468                 ".set reorder");
2469 }
2470
2471 static inline void tlb_read(void)
2472 {
2473 #if MIPS34K_MISSED_ITLB_WAR
2474         int res = 0;
2475
2476         __asm__ __volatile__(
2477         "       .set    push                                    \n"
2478         "       .set    noreorder                               \n"
2479         "       .set    noat                                    \n"
2480         "       .set    mips32r2                                \n"
2481         "       .word   0x41610001              # dvpe $1       \n"
2482         "       move    %0, $1                                  \n"
2483         "       ehb                                             \n"
2484         "       .set    pop                                     \n"
2485         : "=r" (res));
2486
2487         instruction_hazard();
2488 #endif
2489
2490         __asm__ __volatile__(
2491                 ".set noreorder\n\t"
2492                 "tlbr\n\t"
2493                 ".set reorder");
2494
2495 #if MIPS34K_MISSED_ITLB_WAR
2496         if ((res & _ULCAST_(1)))
2497                 __asm__ __volatile__(
2498                 "       .set    push                            \n"
2499                 "       .set    noreorder                       \n"
2500                 "       .set    noat                            \n"
2501                 "       .set    mips32r2                        \n"
2502                 "       .word   0x41600021      # evpe          \n"
2503                 "       ehb                                     \n"
2504                 "       .set    pop                             \n");
2505 #endif
2506 }
2507
2508 static inline void tlb_write_indexed(void)
2509 {
2510         __asm__ __volatile__(
2511                 ".set noreorder\n\t"
2512                 "tlbwi\n\t"
2513                 ".set reorder");
2514 }
2515
2516 static inline void tlb_write_random(void)
2517 {
2518         __asm__ __volatile__(
2519                 ".set noreorder\n\t"
2520                 "tlbwr\n\t"
2521                 ".set reorder");
2522 }
2523
2524 #ifdef TOOLCHAIN_SUPPORTS_VIRT
2525
2526 /*
2527  * Guest TLB operations.
2528  *
2529  * It is responsibility of the caller to take care of any TLB hazards.
2530  */
2531 static inline void guest_tlb_probe(void)
2532 {
2533         __asm__ __volatile__(
2534                 ".set push\n\t"
2535                 ".set noreorder\n\t"
2536                 ".set virt\n\t"
2537                 "tlbgp\n\t"
2538                 ".set pop");
2539 }
2540
2541 static inline void guest_tlb_read(void)
2542 {
2543         __asm__ __volatile__(
2544                 ".set push\n\t"
2545                 ".set noreorder\n\t"
2546                 ".set virt\n\t"
2547                 "tlbgr\n\t"
2548                 ".set pop");
2549 }
2550
2551 static inline void guest_tlb_write_indexed(void)
2552 {
2553         __asm__ __volatile__(
2554                 ".set push\n\t"
2555                 ".set noreorder\n\t"
2556                 ".set virt\n\t"
2557                 "tlbgwi\n\t"
2558                 ".set pop");
2559 }
2560
2561 static inline void guest_tlb_write_random(void)
2562 {
2563         __asm__ __volatile__(
2564                 ".set push\n\t"
2565                 ".set noreorder\n\t"
2566                 ".set virt\n\t"
2567                 "tlbgwr\n\t"
2568                 ".set pop");
2569 }
2570
2571 /*
2572  * Guest TLB Invalidate Flush
2573  */
2574 static inline void guest_tlbinvf(void)
2575 {
2576         __asm__ __volatile__(
2577                 ".set push\n\t"
2578                 ".set noreorder\n\t"
2579                 ".set virt\n\t"
2580                 "tlbginvf\n\t"
2581                 ".set pop");
2582 }
2583
2584 #else   /* TOOLCHAIN_SUPPORTS_VIRT */
2585
2586 /*
2587  * Guest TLB operations.
2588  *
2589  * It is responsibility of the caller to take care of any TLB hazards.
2590  */
2591 static inline void guest_tlb_probe(void)
2592 {
2593         __asm__ __volatile__(
2594                 "# tlbgp\n\t"
2595                 _ASM_INSN_IF_MIPS(0x42000010)
2596                 _ASM_INSN32_IF_MM(0x0000017c));
2597 }
2598
2599 static inline void guest_tlb_read(void)
2600 {
2601         __asm__ __volatile__(
2602                 "# tlbgr\n\t"
2603                 _ASM_INSN_IF_MIPS(0x42000009)
2604                 _ASM_INSN32_IF_MM(0x0000117c));
2605 }
2606
2607 static inline void guest_tlb_write_indexed(void)
2608 {
2609         __asm__ __volatile__(
2610                 "# tlbgwi\n\t"
2611                 _ASM_INSN_IF_MIPS(0x4200000a)
2612                 _ASM_INSN32_IF_MM(0x0000217c));
2613 }
2614
2615 static inline void guest_tlb_write_random(void)
2616 {
2617         __asm__ __volatile__(
2618                 "# tlbgwr\n\t"
2619                 _ASM_INSN_IF_MIPS(0x4200000e)
2620                 _ASM_INSN32_IF_MM(0x0000317c));
2621 }
2622
2623 /*
2624  * Guest TLB Invalidate Flush
2625  */
2626 static inline void guest_tlbinvf(void)
2627 {
2628         __asm__ __volatile__(
2629                 "# tlbginvf\n\t"
2630                 _ASM_INSN_IF_MIPS(0x4200000c)
2631                 _ASM_INSN32_IF_MM(0x0000517c));
2632 }
2633
2634 #endif  /* !TOOLCHAIN_SUPPORTS_VIRT */
2635
2636 /*
2637  * Manipulate bits in a register.
2638  */
2639 #define __BUILD_SET_COMMON(name)                                \
2640 static inline unsigned int                                      \
2641 set_##name(unsigned int set)                                    \
2642 {                                                               \
2643         unsigned int res, new;                                  \
2644                                                                 \
2645         res = read_##name();                                    \
2646         new = res | set;                                        \
2647         write_##name(new);                                      \
2648                                                                 \
2649         return res;                                             \
2650 }                                                               \
2651                                                                 \
2652 static inline unsigned int                                      \
2653 clear_##name(unsigned int clear)                                \
2654 {                                                               \
2655         unsigned int res, new;                                  \
2656                                                                 \
2657         res = read_##name();                                    \
2658         new = res & ~clear;                                     \
2659         write_##name(new);                                      \
2660                                                                 \
2661         return res;                                             \
2662 }                                                               \
2663                                                                 \
2664 static inline unsigned int                                      \
2665 change_##name(unsigned int change, unsigned int val)            \
2666 {                                                               \
2667         unsigned int res, new;                                  \
2668                                                                 \
2669         res = read_##name();                                    \
2670         new = res & ~change;                                    \
2671         new |= (val & change);                                  \
2672         write_##name(new);                                      \
2673                                                                 \
2674         return res;                                             \
2675 }
2676
2677 /*
2678  * Manipulate bits in a c0 register.
2679  */
2680 #define __BUILD_SET_C0(name)    __BUILD_SET_COMMON(c0_##name)
2681
2682 __BUILD_SET_C0(status)
2683 __BUILD_SET_C0(cause)
2684 __BUILD_SET_C0(config)
2685 __BUILD_SET_C0(config5)
2686 __BUILD_SET_C0(intcontrol)
2687 __BUILD_SET_C0(intctl)
2688 __BUILD_SET_C0(srsmap)
2689 __BUILD_SET_C0(pagegrain)
2690 __BUILD_SET_C0(guestctl0)
2691 __BUILD_SET_C0(guestctl0ext)
2692 __BUILD_SET_C0(guestctl1)
2693 __BUILD_SET_C0(guestctl2)
2694 __BUILD_SET_C0(guestctl3)
2695 __BUILD_SET_C0(brcm_config_0)
2696 __BUILD_SET_C0(brcm_bus_pll)
2697 __BUILD_SET_C0(brcm_reset)
2698 __BUILD_SET_C0(brcm_cmt_intr)
2699 __BUILD_SET_C0(brcm_cmt_ctrl)
2700 __BUILD_SET_C0(brcm_config)
2701 __BUILD_SET_C0(brcm_mode)
2702
2703 /*
2704  * Manipulate bits in a guest c0 register.
2705  */
2706 #define __BUILD_SET_GC0(name)   __BUILD_SET_COMMON(gc0_##name)
2707
2708 __BUILD_SET_GC0(status)
2709 __BUILD_SET_GC0(cause)
2710 __BUILD_SET_GC0(ebase)
2711
2712 /*
2713  * Return low 10 bits of ebase.
2714  * Note that under KVM (MIPSVZ) this returns vcpu id.
2715  */
2716 static inline unsigned int get_ebase_cpunum(void)
2717 {
2718         return read_c0_ebase() & MIPS_EBASE_CPUNUM;
2719 }
2720
2721 #endif /* !__ASSEMBLY__ */
2722
2723 #endif /* _ASM_MIPSREGS_H */