arch/mips/include/asm/mipsregs.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
   7  * Copyright (C) 2000 Silicon Graphics, Inc.
   8  * Modified for further R[236]000 support by Paul M. Antoine, 1996.
   9  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  10  * Copyright (C) 2000, 07 MIPS Technologies, Inc.
  11  * Copyright (C) 2003, 2004  Maciej W. Rozycki
  12  */
  13 #ifndef _ASM_MIPSREGS_H
  14 #define _ASM_MIPSREGS_H
  15
  16 #include <linux/linkage.h>
  17 #include <linux/types.h>
  18 #include <asm/hazards.h>
  19 #include <asm/war.h>
  20
  21 /*
  22  * The following macros are especially useful for __asm__
  23  * inline assembler.
  24  */
  25 #ifndef __STR
  26 #define __STR(x) #x
  27 #endif
  28 #ifndef STR
  29 #define STR(x) __STR(x)
  30 #endif
  31
  32 /*
  33  *  Configure language
  34  */
  35 #ifdef __ASSEMBLY__
  36 #define _ULCAST_
  37 #else
  38 #define _ULCAST_ (unsigned long)
  39 #endif
  40
  41 /*
  42  * Coprocessor 0 register names
  43  */
  44 #define CP0_INDEX $0
  45 #define CP0_RANDOM $1
  46 #define CP0_ENTRYLO0 $2
  47 #define CP0_ENTRYLO1 $3
  48 #define CP0_CONF $3
  49 #define CP0_CONTEXT $4
  50 #define CP0_PAGEMASK $5
  51 #define CP0_WIRED $6
  52 #define CP0_INFO $7
  53 #define CP0_HWRENA $7, 0
  54 #define CP0_BADVADDR $8
  55 #define CP0_BADINSTR $8, 1
  56 #define CP0_COUNT $9
  57 #define CP0_ENTRYHI $10
  58 #define CP0_COMPARE $11
  59 #define CP0_STATUS $12
  60 #define CP0_CAUSE $13
  61 #define CP0_EPC $14
  62 #define CP0_PRID $15
  63 #define CP0_EBASE $15, 1
  64 #define CP0_CMGCRBASE $15, 3
  65 #define CP0_CONFIG $16
  66 #define CP0_CONFIG3 $16, 3
  67 #define CP0_CONFIG5 $16, 5
  68 #define CP0_LLADDR $17
  69 #define CP0_WATCHLO $18
  70 #define CP0_WATCHHI $19
  71 #define CP0_XCONTEXT $20
  72 #define CP0_FRAMEMASK $21
  73 #define CP0_DIAGNOSTIC $22
  74 #define CP0_DEBUG $23
  75 #define CP0_DEPC $24
  76 #define CP0_PERFORMANCE $25
  77 #define CP0_ECC $26
  78 #define CP0_CACHEERR $27
  79 #define CP0_TAGLO $28
  80 #define CP0_TAGHI $29
  81 #define CP0_ERROREPC $30
  82 #define CP0_DESAVE $31
  83
  84 /*
  85  * R4640/R4650 cp0 register names.  These registers are listed
  86  * here only for completeness; without MMU these CPUs are not useable
  87  * by Linux.  A future ELKS port might take make Linux run on them
  88  * though ...
  89  */
  90 #define CP0_IBASE $0
  91 #define CP0_IBOUND $1
  92 #define CP0_DBASE $2
  93 #define CP0_DBOUND $3
  94 #define CP0_CALG $17
  95 #define CP0_IWATCH $18
  96 #define CP0_DWATCH $19
  97
  98 /*
  99  * Coprocessor 0 Set 1 register names
 100  */
 101 #define CP0_S1_DERRADDR0  $26
 102 #define CP0_S1_DERRADDR1  $27
 103 #define CP0_S1_INTCONTROL $20
 104
 105 /*
 106  * Coprocessor 0 Set 2 register names
 107  */
 108 #define CP0_S2_SRSCTL     $12   /* MIPSR2 */
 109
 110 /*
 111  * Coprocessor 0 Set 3 register names
 112  */
 113 #define CP0_S3_SRSMAP     $12   /* MIPSR2 */
 114
 115 /*
 116  *  TX39 Series
 117  */
 118 #define CP0_TX39_CACHE  $7
 119
 120
 121 /* Generic EntryLo bit definitions */
 122 #define ENTRYLO_G               (_ULCAST_(1) << 0)
 123 #define ENTRYLO_V               (_ULCAST_(1) << 1)
 124 #define ENTRYLO_D               (_ULCAST_(1) << 2)
 125 #define ENTRYLO_C_SHIFT         3
 126 #define ENTRYLO_C               (_ULCAST_(7) << ENTRYLO_C_SHIFT)
 127
 128 /* R3000 EntryLo bit definitions */
 129 #define R3K_ENTRYLO_G           (_ULCAST_(1) << 8)
 130 #define R3K_ENTRYLO_V           (_ULCAST_(1) << 9)
 131 #define R3K_ENTRYLO_D           (_ULCAST_(1) << 10)
 132 #define R3K_ENTRYLO_N           (_ULCAST_(1) << 11)
 133
 134 /* MIPS32/64 EntryLo bit definitions */
 135 #define MIPS_ENTRYLO_PFN_SHIFT  6
 136 #define MIPS_ENTRYLO_XI         (_ULCAST_(1) << (BITS_PER_LONG - 2))
 137 #define MIPS_ENTRYLO_RI         (_ULCAST_(1) << (BITS_PER_LONG - 1))
 138
 139 /*
 140  * Values for PageMask register
 141  */
 142 #ifdef CONFIG_CPU_VR41XX
 143
 144 /* Why doesn't stupidity hurt ... */
 145
 146 #define PM_1K           0x00000000
 147 #define PM_4K           0x00001800
 148 #define PM_16K          0x00007800
 149 #define PM_64K          0x0001f800
 150 #define PM_256K         0x0007f800
 151
 152 #else
 153
 154 #define PM_4K           0x00000000
 155 #define PM_8K           0x00002000
 156 #define PM_16K          0x00006000
 157 #define PM_32K          0x0000e000
 158 #define PM_64K          0x0001e000
 159 #define PM_128K         0x0003e000
 160 #define PM_256K         0x0007e000
 161 #define PM_512K         0x000fe000
 162 #define PM_1M           0x001fe000
 163 #define PM_2M           0x003fe000
 164 #define PM_4M           0x007fe000
 165 #define PM_8M           0x00ffe000
 166 #define PM_16M          0x01ffe000
 167 #define PM_32M          0x03ffe000
 168 #define PM_64M          0x07ffe000
 169 #define PM_256M         0x1fffe000
 170 #define PM_1G           0x7fffe000
 171
 172 #endif
 173
 174 /*
 175  * Default page size for a given kernel configuration
 176  */
 177 #ifdef CONFIG_PAGE_SIZE_4KB
 178 #define PM_DEFAULT_MASK PM_4K
 179 #elif defined(CONFIG_PAGE_SIZE_8KB)
 180 #define PM_DEFAULT_MASK PM_8K
 181 #elif defined(CONFIG_PAGE_SIZE_16KB)
 182 #define PM_DEFAULT_MASK PM_16K
 183 #elif defined(CONFIG_PAGE_SIZE_32KB)
 184 #define PM_DEFAULT_MASK PM_32K
 185 #elif defined(CONFIG_PAGE_SIZE_64KB)
 186 #define PM_DEFAULT_MASK PM_64K
 187 #else
 188 #error Bad page size configuration!
 189 #endif
 190
 191 /*
 192  * Default huge tlb size for a given kernel configuration
 193  */
 194 #ifdef CONFIG_PAGE_SIZE_4KB
 195 #define PM_HUGE_MASK    PM_1M
 196 #elif defined(CONFIG_PAGE_SIZE_8KB)
 197 #define PM_HUGE_MASK    PM_4M
 198 #elif defined(CONFIG_PAGE_SIZE_16KB)
 199 #define PM_HUGE_MASK    PM_16M
 200 #elif defined(CONFIG_PAGE_SIZE_32KB)
 201 #define PM_HUGE_MASK    PM_64M
 202 #elif defined(CONFIG_PAGE_SIZE_64KB)
 203 #define PM_HUGE_MASK    PM_256M
 204 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
 205 #error Bad page size configuration for hugetlbfs!
 206 #endif
 207
 208 /*
 209  * Values used for computation of new tlb entries
 210  */
 211 #define PL_4K           12
 212 #define PL_16K          14
 213 #define PL_64K          16
 214 #define PL_256K         18
 215 #define PL_1M           20
 216 #define PL_4M           22
 217 #define PL_16M          24
 218 #define PL_64M          26
 219 #define PL_256M         28
 220
 221 /*
 222  * PageGrain bits
 223  */
 224 #define PG_RIE          (_ULCAST_(1) <<  31)
 225 #define PG_XIE          (_ULCAST_(1) <<  30)
 226 #define PG_ELPA         (_ULCAST_(1) <<  29)
 227 #define PG_ESP          (_ULCAST_(1) <<  28)
 228 #define PG_IEC          (_ULCAST_(1) <<  27)
 229
 230 /* MIPS32/64 EntryHI bit definitions */
 231 #define MIPS_ENTRYHI_EHINV      (_ULCAST_(1) << 10)
 232 #define MIPS_ENTRYHI_ASIDX      (_ULCAST_(0x3) << 8)
 233 #define MIPS_ENTRYHI_ASID       (_ULCAST_(0xff) << 0)
 234
 235 /*
 236  * R4x00 interrupt enable / cause bits
 237  */
 238 #define IE_SW0          (_ULCAST_(1) <<  8)
 239 #define IE_SW1          (_ULCAST_(1) <<  9)
 240 #define IE_IRQ0         (_ULCAST_(1) << 10)
 241 #define IE_IRQ1         (_ULCAST_(1) << 11)
 242 #define IE_IRQ2         (_ULCAST_(1) << 12)
 243 #define IE_IRQ3         (_ULCAST_(1) << 13)
 244 #define IE_IRQ4         (_ULCAST_(1) << 14)
 245 #define IE_IRQ5         (_ULCAST_(1) << 15)
 246
 247 /*
 248  * R4x00 interrupt cause bits
 249  */
 250 #define C_SW0           (_ULCAST_(1) <<  8)
 251 #define C_SW1           (_ULCAST_(1) <<  9)
 252 #define C_IRQ0          (_ULCAST_(1) << 10)
 253 #define C_IRQ1          (_ULCAST_(1) << 11)
 254 #define C_IRQ2          (_ULCAST_(1) << 12)
 255 #define C_IRQ3          (_ULCAST_(1) << 13)
 256 #define C_IRQ4          (_ULCAST_(1) << 14)
 257 #define C_IRQ5          (_ULCAST_(1) << 15)
 258
 259 /*
 260  * Bitfields in the R4xx0 cp0 status register
 261  */
 262 #define ST0_IE                  0x00000001
 263 #define ST0_EXL                 0x00000002
 264 #define ST0_ERL                 0x00000004
 265 #define ST0_KSU                 0x00000018
 266 #  define KSU_USER              0x00000010
 267 #  define KSU_SUPERVISOR        0x00000008
 268 #  define KSU_KERNEL            0x00000000
 269 #define ST0_UX                  0x00000020
 270 #define ST0_SX                  0x00000040
 271 #define ST0_KX                  0x00000080
 272 #define ST0_DE                  0x00010000
 273 #define ST0_CE                  0x00020000
 274
 275 /*
 276  * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
 277  * cacheops in userspace.  This bit exists only on RM7000 and RM9000
 278  * processors.
 279  */
 280 #define ST0_CO                  0x08000000
 281
 282 /*
 283  * Bitfields in the R[23]000 cp0 status register.
 284  */
 285 #define ST0_IEC                 0x00000001
 286 #define ST0_KUC                 0x00000002
 287 #define ST0_IEP                 0x00000004
 288 #define ST0_KUP                 0x00000008
 289 #define ST0_IEO                 0x00000010
 290 #define ST0_KUO                 0x00000020
 291 /* bits 6 & 7 are reserved on R[23]000 */
 292 #define ST0_ISC                 0x00010000
 293 #define ST0_SWC                 0x00020000
 294 #define ST0_CM                  0x00080000
 295
 296 /*
 297  * Bits specific to the R4640/R4650
 298  */
 299 #define ST0_UM                  (_ULCAST_(1) <<  4)
 300 #define ST0_IL                  (_ULCAST_(1) << 23)
 301 #define ST0_DL                  (_ULCAST_(1) << 24)
 302
 303 /*
 304  * Enable the MIPS MDMX and DSP ASEs
 305  */
 306 #define ST0_MX                  0x01000000
 307
 308 /*
 309  * Status register bits available in all MIPS CPUs.
 310  */
 311 #define ST0_IM                  0x0000ff00
 312 #define  STATUSB_IP0            8
 313 #define  STATUSF_IP0            (_ULCAST_(1) <<  8)
 314 #define  STATUSB_IP1            9
 315 #define  STATUSF_IP1            (_ULCAST_(1) <<  9)
 316 #define  STATUSB_IP2            10
 317 #define  STATUSF_IP2            (_ULCAST_(1) << 10)
 318 #define  STATUSB_IP3            11
 319 #define  STATUSF_IP3            (_ULCAST_(1) << 11)
 320 #define  STATUSB_IP4            12
 321 #define  STATUSF_IP4            (_ULCAST_(1) << 12)
 322 #define  STATUSB_IP5            13
 323 #define  STATUSF_IP5            (_ULCAST_(1) << 13)
 324 #define  STATUSB_IP6            14
 325 #define  STATUSF_IP6            (_ULCAST_(1) << 14)
 326 #define  STATUSB_IP7            15
 327 #define  STATUSF_IP7            (_ULCAST_(1) << 15)
 328 #define  STATUSB_IP8            0
 329 #define  STATUSF_IP8            (_ULCAST_(1) <<  0)
 330 #define  STATUSB_IP9            1
 331 #define  STATUSF_IP9            (_ULCAST_(1) <<  1)
 332 #define  STATUSB_IP10           2
 333 #define  STATUSF_IP10           (_ULCAST_(1) <<  2)
 334 #define  STATUSB_IP11           3
 335 #define  STATUSF_IP11           (_ULCAST_(1) <<  3)
 336 #define  STATUSB_IP12           4
 337 #define  STATUSF_IP12           (_ULCAST_(1) <<  4)
 338 #define  STATUSB_IP13           5
 339 #define  STATUSF_IP13           (_ULCAST_(1) <<  5)
 340 #define  STATUSB_IP14           6
 341 #define  STATUSF_IP14           (_ULCAST_(1) <<  6)
 342 #define  STATUSB_IP15           7
 343 #define  STATUSF_IP15           (_ULCAST_(1) <<  7)
 344 #define ST0_CH                  0x00040000
 345 #define ST0_NMI                 0x00080000
 346 #define ST0_SR                  0x00100000
 347 #define ST0_TS                  0x00200000
 348 #define ST0_BEV                 0x00400000
 349 #define ST0_RE                  0x02000000
 350 #define ST0_FR                  0x04000000
 351 #define ST0_CU                  0xf0000000
 352 #define ST0_CU0                 0x10000000
 353 #define ST0_CU1                 0x20000000
 354 #define ST0_CU2                 0x40000000
 355 #define ST0_CU3                 0x80000000
 356 #define ST0_XX                  0x80000000      /* MIPS IV naming */
 357
 358 /*
 359  * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
 360  */
 361 #define INTCTLB_IPFDC           23
 362 #define INTCTLF_IPFDC           (_ULCAST_(7) << INTCTLB_IPFDC)
 363 #define INTCTLB_IPPCI           26
 364 #define INTCTLF_IPPCI           (_ULCAST_(7) << INTCTLB_IPPCI)
 365 #define INTCTLB_IPTI            29
 366 #define INTCTLF_IPTI            (_ULCAST_(7) << INTCTLB_IPTI)
 367
 368 /*
 369  * Bitfields and bit numbers in the coprocessor 0 cause register.
 370  *
 371  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
 372  */
 373 #define CAUSEB_EXCCODE          2
 374 #define CAUSEF_EXCCODE          (_ULCAST_(31)  <<  2)
 375 #define CAUSEB_IP               8
 376 #define CAUSEF_IP               (_ULCAST_(255) <<  8)
 377 #define  CAUSEB_IP0             8
 378 #define  CAUSEF_IP0             (_ULCAST_(1)   <<  8)
 379 #define  CAUSEB_IP1             9
 380 #define  CAUSEF_IP1             (_ULCAST_(1)   <<  9)
 381 #define  CAUSEB_IP2             10
 382 #define  CAUSEF_IP2             (_ULCAST_(1)   << 10)
 383 #define  CAUSEB_IP3             11
 384 #define  CAUSEF_IP3             (_ULCAST_(1)   << 11)
 385 #define  CAUSEB_IP4             12
 386 #define  CAUSEF_IP4             (_ULCAST_(1)   << 12)
 387 #define  CAUSEB_IP5             13
 388 #define  CAUSEF_IP5             (_ULCAST_(1)   << 13)
 389 #define  CAUSEB_IP6             14
 390 #define  CAUSEF_IP6             (_ULCAST_(1)   << 14)
 391 #define  CAUSEB_IP7             15
 392 #define  CAUSEF_IP7             (_ULCAST_(1)   << 15)
 393 #define CAUSEB_FDCI             21
 394 #define CAUSEF_FDCI             (_ULCAST_(1)   << 21)
 395 #define CAUSEB_WP               22
 396 #define CAUSEF_WP               (_ULCAST_(1)   << 22)
 397 #define CAUSEB_IV               23
 398 #define CAUSEF_IV               (_ULCAST_(1)   << 23)
 399 #define CAUSEB_PCI              26
 400 #define CAUSEF_PCI              (_ULCAST_(1)   << 26)
 401 #define CAUSEB_DC               27
 402 #define CAUSEF_DC               (_ULCAST_(1)   << 27)
 403 #define CAUSEB_CE               28
 404 #define CAUSEF_CE               (_ULCAST_(3)   << 28)
 405 #define CAUSEB_TI               30
 406 #define CAUSEF_TI               (_ULCAST_(1)   << 30)
 407 #define CAUSEB_BD               31
 408 #define CAUSEF_BD               (_ULCAST_(1)   << 31)
 409
 410 /*
 411  * Cause.ExcCode trap codes.
 412  */
 413 #define EXCCODE_INT             0       /* Interrupt pending */
 414 #define EXCCODE_MOD             1       /* TLB modified fault */
 415 #define EXCCODE_TLBL            2       /* TLB miss on load or ifetch */
 416 #define EXCCODE_TLBS            3       /* TLB miss on a store */
 417 #define EXCCODE_ADEL            4       /* Address error on a load or ifetch */
 418 #define EXCCODE_ADES            5       /* Address error on a store */
 419 #define EXCCODE_IBE             6       /* Bus error on an ifetch */
 420 #define EXCCODE_DBE             7       /* Bus error on a load or store */
 421 #define EXCCODE_SYS             8       /* System call */
 422 #define EXCCODE_BP              9       /* Breakpoint */
 423 #define EXCCODE_RI              10      /* Reserved instruction exception */
 424 #define EXCCODE_CPU             11      /* Coprocessor unusable */
 425 #define EXCCODE_OV              12      /* Arithmetic overflow */
 426 #define EXCCODE_TR              13      /* Trap instruction */
 427 #define EXCCODE_MSAFPE          14      /* MSA floating point exception */
 428 #define EXCCODE_FPE             15      /* Floating point exception */
 429 #define EXCCODE_TLBRI           19      /* TLB Read-Inhibit exception */
 430 #define EXCCODE_TLBXI           20      /* TLB Execution-Inhibit exception */
 431 #define EXCCODE_MSADIS          21      /* MSA disabled exception */
 432 #define EXCCODE_MDMX            22      /* MDMX unusable exception */
 433 #define EXCCODE_WATCH           23      /* Watch address reference */
 434 #define EXCCODE_MCHECK          24      /* Machine check */
 435 #define EXCCODE_THREAD          25      /* Thread exceptions (MT) */
 436 #define EXCCODE_DSPDIS          26      /* DSP disabled exception */
 437 #define EXCCODE_GE              27      /* Virtualized guest exception (VZ) */
 438
 439 /* Implementation specific trap codes used by MIPS cores */
 440 #define MIPS_EXCCODE_TLBPAR     16      /* TLB parity error exception */
 441
 442 /*
 443  * Bits in the coprocessor 0 config register.
 444  */
 445 /* Generic bits.  */
 446 #define CONF_CM_CACHABLE_NO_WA          0
 447 #define CONF_CM_CACHABLE_WA             1
 448 #define CONF_CM_UNCACHED                2
 449 #define CONF_CM_CACHABLE_NONCOHERENT    3
 450 #define CONF_CM_CACHABLE_CE             4
 451 #define CONF_CM_CACHABLE_COW            5
 452 #define CONF_CM_CACHABLE_CUW            6
 453 #define CONF_CM_CACHABLE_ACCELERATED    7
 454 #define CONF_CM_CMASK                   7
 455 #define CONF_BE                 (_ULCAST_(1) << 15)
 456
 457 /* Bits common to various processors.  */
 458 #define CONF_CU                 (_ULCAST_(1) <<  3)
 459 #define CONF_DB                 (_ULCAST_(1) <<  4)
 460 #define CONF_IB                 (_ULCAST_(1) <<  5)
 461 #define CONF_DC                 (_ULCAST_(7) <<  6)
 462 #define CONF_IC                 (_ULCAST_(7) <<  9)
 463 #define CONF_EB                 (_ULCAST_(1) << 13)
 464 #define CONF_EM                 (_ULCAST_(1) << 14)
 465 #define CONF_SM                 (_ULCAST_(1) << 16)
 466 #define CONF_SC                 (_ULCAST_(1) << 17)
 467 #define CONF_EW                 (_ULCAST_(3) << 18)
 468 #define CONF_EP                 (_ULCAST_(15)<< 24)
 469 #define CONF_EC                 (_ULCAST_(7) << 28)
 470 #define CONF_CM                 (_ULCAST_(1) << 31)
 471
 472 /* Bits specific to the R4xx0.  */
 473 #define R4K_CONF_SW             (_ULCAST_(1) << 20)
 474 #define R4K_CONF_SS             (_ULCAST_(1) << 21)
 475 #define R4K_CONF_SB             (_ULCAST_(3) << 22)
 476
 477 /* Bits specific to the R5000.  */
 478 #define R5K_CONF_SE             (_ULCAST_(1) << 12)
 479 #define R5K_CONF_SS             (_ULCAST_(3) << 20)
 480
 481 /* Bits specific to the RM7000.  */
 482 #define RM7K_CONF_SE            (_ULCAST_(1) <<  3)
 483 #define RM7K_CONF_TE            (_ULCAST_(1) << 12)
 484 #define RM7K_CONF_CLK           (_ULCAST_(1) << 16)
 485 #define RM7K_CONF_TC            (_ULCAST_(1) << 17)
 486 #define RM7K_CONF_SI            (_ULCAST_(3) << 20)
 487 #define RM7K_CONF_SC            (_ULCAST_(1) << 31)
 488
 489 /* Bits specific to the R10000.  */
 490 #define R10K_CONF_DN            (_ULCAST_(3) <<  3)
 491 #define R10K_CONF_CT            (_ULCAST_(1) <<  5)
 492 #define R10K_CONF_PE            (_ULCAST_(1) <<  6)
 493 #define R10K_CONF_PM            (_ULCAST_(3) <<  7)
 494 #define R10K_CONF_EC            (_ULCAST_(15)<<  9)
 495 #define R10K_CONF_SB            (_ULCAST_(1) << 13)
 496 #define R10K_CONF_SK            (_ULCAST_(1) << 14)
 497 #define R10K_CONF_SS            (_ULCAST_(7) << 16)
 498 #define R10K_CONF_SC            (_ULCAST_(7) << 19)
 499 #define R10K_CONF_DC            (_ULCAST_(7) << 26)
 500 #define R10K_CONF_IC            (_ULCAST_(7) << 29)
 501
 502 /* Bits specific to the VR41xx.  */
 503 #define VR41_CONF_CS            (_ULCAST_(1) << 12)
 504 #define VR41_CONF_P4K           (_ULCAST_(1) << 13)
 505 #define VR41_CONF_BP            (_ULCAST_(1) << 16)
 506 #define VR41_CONF_M16           (_ULCAST_(1) << 20)
 507 #define VR41_CONF_AD            (_ULCAST_(1) << 23)
 508
 509 /* Bits specific to the R30xx.  */
 510 #define R30XX_CONF_FDM          (_ULCAST_(1) << 19)
 511 #define R30XX_CONF_REV          (_ULCAST_(1) << 22)
 512 #define R30XX_CONF_AC           (_ULCAST_(1) << 23)
 513 #define R30XX_CONF_RF           (_ULCAST_(1) << 24)
 514 #define R30XX_CONF_HALT         (_ULCAST_(1) << 25)
 515 #define R30XX_CONF_FPINT        (_ULCAST_(7) << 26)
 516 #define R30XX_CONF_DBR          (_ULCAST_(1) << 29)
 517 #define R30XX_CONF_SB           (_ULCAST_(1) << 30)
 518 #define R30XX_CONF_LOCK         (_ULCAST_(1) << 31)
 519
 520 /* Bits specific to the TX49.  */
 521 #define TX49_CONF_DC            (_ULCAST_(1) << 16)
 522 #define TX49_CONF_IC            (_ULCAST_(1) << 17)  /* conflict with CONF_SC */
 523 #define TX49_CONF_HALT          (_ULCAST_(1) << 18)
 524 #define TX49_CONF_CWFON         (_ULCAST_(1) << 27)
 525
 526 /* Bits specific to the MIPS32/64 PRA.  */
 527 #define MIPS_CONF_MT            (_ULCAST_(7) <<  7)
 528 #define MIPS_CONF_MT_TLB        (_ULCAST_(1) <<  7)
 529 #define MIPS_CONF_MT_FTLB       (_ULCAST_(4) <<  7)
 530 #define MIPS_CONF_AR            (_ULCAST_(7) << 10)
 531 #define MIPS_CONF_AT            (_ULCAST_(3) << 13)
 532 #define MIPS_CONF_M             (_ULCAST_(1) << 31)
 533
 534 /*
 535  * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
 536  */
 537 #define MIPS_CONF1_FP           (_ULCAST_(1) <<  0)
 538 #define MIPS_CONF1_EP           (_ULCAST_(1) <<  1)
 539 #define MIPS_CONF1_CA           (_ULCAST_(1) <<  2)
 540 #define MIPS_CONF1_WR           (_ULCAST_(1) <<  3)
 541 #define MIPS_CONF1_PC           (_ULCAST_(1) <<  4)
 542 #define MIPS_CONF1_MD           (_ULCAST_(1) <<  5)
 543 #define MIPS_CONF1_C2           (_ULCAST_(1) <<  6)
 544 #define MIPS_CONF1_DA_SHF       7
 545 #define MIPS_CONF1_DA_SZ        3
 546 #define MIPS_CONF1_DA           (_ULCAST_(7) <<  7)
 547 #define MIPS_CONF1_DL_SHF       10
 548 #define MIPS_CONF1_DL_SZ        3
 549 #define MIPS_CONF1_DL           (_ULCAST_(7) << 10)
 550 #define MIPS_CONF1_DS_SHF       13
 551 #define MIPS_CONF1_DS_SZ        3
 552 #define MIPS_CONF1_DS           (_ULCAST_(7) << 13)
 553 #define MIPS_CONF1_IA_SHF       16
 554 #define MIPS_CONF1_IA_SZ        3
 555 #define MIPS_CONF1_IA           (_ULCAST_(7) << 16)
 556 #define MIPS_CONF1_IL_SHF       19
 557 #define MIPS_CONF1_IL_SZ        3
 558 #define MIPS_CONF1_IL           (_ULCAST_(7) << 19)
 559 #define MIPS_CONF1_IS_SHF       22
 560 #define MIPS_CONF1_IS_SZ        3
 561 #define MIPS_CONF1_IS           (_ULCAST_(7) << 22)
 562 #define MIPS_CONF1_TLBS_SHIFT   (25)
 563 #define MIPS_CONF1_TLBS_SIZE    (6)
 564 #define MIPS_CONF1_TLBS         (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
 565
 566 #define MIPS_CONF2_SA           (_ULCAST_(15)<<  0)
 567 #define MIPS_CONF2_SL           (_ULCAST_(15)<<  4)
 568 #define MIPS_CONF2_SS           (_ULCAST_(15)<<  8)
 569 #define MIPS_CONF2_SU           (_ULCAST_(15)<< 12)
 570 #define MIPS_CONF2_TA           (_ULCAST_(15)<< 16)
 571 #define MIPS_CONF2_TL           (_ULCAST_(15)<< 20)
 572 #define MIPS_CONF2_TS           (_ULCAST_(15)<< 24)
 573 #define MIPS_CONF2_TU           (_ULCAST_(7) << 28)
 574
 575 #define MIPS_CONF3_TL           (_ULCAST_(1) <<  0)
 576 #define MIPS_CONF3_SM           (_ULCAST_(1) <<  1)
 577 #define MIPS_CONF3_MT           (_ULCAST_(1) <<  2)
 578 #define MIPS_CONF3_CDMM         (_ULCAST_(1) <<  3)
 579 #define MIPS_CONF3_SP           (_ULCAST_(1) <<  4)
 580 #define MIPS_CONF3_VINT         (_ULCAST_(1) <<  5)
 581 #define MIPS_CONF3_VEIC         (_ULCAST_(1) <<  6)
 582 #define MIPS_CONF3_LPA          (_ULCAST_(1) <<  7)
 583 #define MIPS_CONF3_ITL          (_ULCAST_(1) <<  8)
 584 #define MIPS_CONF3_CTXTC        (_ULCAST_(1) <<  9)
 585 #define MIPS_CONF3_DSP          (_ULCAST_(1) << 10)
 586 #define MIPS_CONF3_DSP2P        (_ULCAST_(1) << 11)
 587 #define MIPS_CONF3_RXI          (_ULCAST_(1) << 12)
 588 #define MIPS_CONF3_ULRI         (_ULCAST_(1) << 13)
 589 #define MIPS_CONF3_ISA          (_ULCAST_(3) << 14)
 590 #define MIPS_CONF3_ISA_OE       (_ULCAST_(1) << 16)
 591 #define MIPS_CONF3_MCU          (_ULCAST_(1) << 17)
 592 #define MIPS_CONF3_MMAR         (_ULCAST_(7) << 18)
 593 #define MIPS_CONF3_IPLW         (_ULCAST_(3) << 21)
 594 #define MIPS_CONF3_VZ           (_ULCAST_(1) << 23)
 595 #define MIPS_CONF3_PW           (_ULCAST_(1) << 24)
 596 #define MIPS_CONF3_SC           (_ULCAST_(1) << 25)
 597 #define MIPS_CONF3_BI           (_ULCAST_(1) << 26)
 598 #define MIPS_CONF3_BP           (_ULCAST_(1) << 27)
 599 #define MIPS_CONF3_MSA          (_ULCAST_(1) << 28)
 600 #define MIPS_CONF3_CMGCR        (_ULCAST_(1) << 29)
 601 #define MIPS_CONF3_BPG          (_ULCAST_(1) << 30)
 602
 603 #define MIPS_CONF4_MMUSIZEEXT_SHIFT     (0)
 604 #define MIPS_CONF4_MMUSIZEEXT   (_ULCAST_(255) << 0)
 605 #define MIPS_CONF4_FTLBSETS_SHIFT       (0)
 606 #define MIPS_CONF4_FTLBSETS     (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
 607 #define MIPS_CONF4_FTLBWAYS_SHIFT       (4)
 608 #define MIPS_CONF4_FTLBWAYS     (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
 609 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT   (8)
 610 /* bits 10:8 in FTLB-only configurations */
 611 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 612 /* bits 12:8 in VTLB-FTLB only configurations */
 613 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 614 #define MIPS_CONF4_MMUEXTDEF    (_ULCAST_(3) << 14)
 615 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
 616 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT        (_ULCAST_(2) << 14)
 617 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT        (_ULCAST_(3) << 14)
 618 #define MIPS_CONF4_KSCREXIST    (_ULCAST_(255) << 16)
 619 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT    (24)
 620 #define MIPS_CONF4_VTLBSIZEEXT  (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
 621 #define MIPS_CONF4_AE           (_ULCAST_(1) << 28)
 622 #define MIPS_CONF4_IE           (_ULCAST_(3) << 29)
 623 #define MIPS_CONF4_TLBINV       (_ULCAST_(2) << 29)
 624
 625 #define MIPS_CONF5_NF           (_ULCAST_(1) << 0)
 626 #define MIPS_CONF5_UFR          (_ULCAST_(1) << 2)
 627 #define MIPS_CONF5_MRP          (_ULCAST_(1) << 3)
 628 #define MIPS_CONF5_LLB          (_ULCAST_(1) << 4)
 629 #define MIPS_CONF5_MVH          (_ULCAST_(1) << 5)
 630 #define MIPS_CONF5_VP           (_ULCAST_(1) << 7)
 631 #define MIPS_CONF5_FRE          (_ULCAST_(1) << 8)
 632 #define MIPS_CONF5_UFE          (_ULCAST_(1) << 9)
 633 #define MIPS_CONF5_MSAEN        (_ULCAST_(1) << 27)
 634 #define MIPS_CONF5_EVA          (_ULCAST_(1) << 28)
 635 #define MIPS_CONF5_CV           (_ULCAST_(1) << 29)
 636 #define MIPS_CONF5_K            (_ULCAST_(1) << 30)
 637
 638 #define MIPS_CONF6_SYND         (_ULCAST_(1) << 13)
 639 /* proAptiv FTLB on/off bit */
 640 #define MIPS_CONF6_FTLBEN       (_ULCAST_(1) << 15)
 641 /* Loongson-3 FTLB on/off bit */
 642 #define MIPS_CONF6_FTLBDIS      (_ULCAST_(1) << 22)
 643 /* FTLB probability bits */
 644 #define MIPS_CONF6_FTLBP_SHIFT  (16)
 645
 646 #define MIPS_CONF7_WII          (_ULCAST_(1) << 31)
 647
 648 #define MIPS_CONF7_RPS          (_ULCAST_(1) << 2)
 649
 650 #define MIPS_CONF7_IAR          (_ULCAST_(1) << 10)
 651 #define MIPS_CONF7_AR           (_ULCAST_(1) << 16)
 652 /* FTLB probability bits for R6 */
 653 #define MIPS_CONF7_FTLBP_SHIFT  (18)
 654
 655 /* WatchLo* register definitions */
 656 #define MIPS_WATCHLO_IRW        (_ULCAST_(0x7) << 0)
 657
 658 /* WatchHi* register definitions */
 659 #define MIPS_WATCHHI_M          (_ULCAST_(1) << 31)
 660 #define MIPS_WATCHHI_G          (_ULCAST_(1) << 30)
 661 #define MIPS_WATCHHI_WM         (_ULCAST_(0x3) << 28)
 662 #define MIPS_WATCHHI_WM_R_RVA   (_ULCAST_(0) << 28)
 663 #define MIPS_WATCHHI_WM_R_GPA   (_ULCAST_(1) << 28)
 664 #define MIPS_WATCHHI_WM_G_GVA   (_ULCAST_(2) << 28)
 665 #define MIPS_WATCHHI_EAS        (_ULCAST_(0x3) << 24)
 666 #define MIPS_WATCHHI_ASID       (_ULCAST_(0xff) << 16)
 667 #define MIPS_WATCHHI_MASK       (_ULCAST_(0x1ff) << 3)
 668 #define MIPS_WATCHHI_I          (_ULCAST_(1) << 2)
 669 #define MIPS_WATCHHI_R          (_ULCAST_(1) << 1)
 670 #define MIPS_WATCHHI_W          (_ULCAST_(1) << 0)
 671 #define MIPS_WATCHHI_IRW        (_ULCAST_(0x7) << 0)
 672
 673 /* MAAR bit definitions */
 674 #define MIPS_MAAR_ADDR          ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
 675 #define MIPS_MAAR_ADDR_SHIFT    12
 676 #define MIPS_MAAR_S             (_ULCAST_(1) << 1)
 677 #define MIPS_MAAR_V             (_ULCAST_(1) << 0)
 678
 679 /* EBase bit definitions */
 680 #define MIPS_EBASE_CPUNUM_SHIFT 0
 681 #define MIPS_EBASE_CPUNUM       (_ULCAST_(0x3ff) << 0)
 682 #define MIPS_EBASE_WG_SHIFT     11
 683 #define MIPS_EBASE_WG           (_ULCAST_(1) << 11)
 684 #define MIPS_EBASE_BASE_SHIFT   12
 685 #define MIPS_EBASE_BASE         (~_ULCAST_((1 << MIPS_EBASE_BASE_SHIFT) - 1))
 686
 687 /* CMGCRBase bit definitions */
 688 #define MIPS_CMGCRB_BASE        11
 689 #define MIPS_CMGCRF_BASE        (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
 690
 691 /*
 692  * Bits in the MIPS32 Memory Segmentation registers.
 693  */
 694 #define MIPS_SEGCFG_PA_SHIFT    9
 695 #define MIPS_SEGCFG_PA          (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
 696 #define MIPS_SEGCFG_AM_SHIFT    4
 697 #define MIPS_SEGCFG_AM          (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
 698 #define MIPS_SEGCFG_EU_SHIFT    3
 699 #define MIPS_SEGCFG_EU          (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
 700 #define MIPS_SEGCFG_C_SHIFT     0
 701 #define MIPS_SEGCFG_C           (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
 702
 703 #define MIPS_SEGCFG_UUSK        _ULCAST_(7)
 704 #define MIPS_SEGCFG_USK         _ULCAST_(5)
 705 #define MIPS_SEGCFG_MUSUK       _ULCAST_(4)
 706 #define MIPS_SEGCFG_MUSK        _ULCAST_(3)
 707 #define MIPS_SEGCFG_MSK         _ULCAST_(2)
 708 #define MIPS_SEGCFG_MK          _ULCAST_(1)
 709 #define MIPS_SEGCFG_UK          _ULCAST_(0)
 710
 711 #define MIPS_PWFIELD_GDI_SHIFT  24
 712 #define MIPS_PWFIELD_GDI_MASK   0x3f000000
 713 #define MIPS_PWFIELD_UDI_SHIFT  18
 714 #define MIPS_PWFIELD_UDI_MASK   0x00fc0000
 715 #define MIPS_PWFIELD_MDI_SHIFT  12
 716 #define MIPS_PWFIELD_MDI_MASK   0x0003f000
 717 #define MIPS_PWFIELD_PTI_SHIFT  6
 718 #define MIPS_PWFIELD_PTI_MASK   0x00000fc0
 719 #define MIPS_PWFIELD_PTEI_SHIFT 0
 720 #define MIPS_PWFIELD_PTEI_MASK  0x0000003f
 721
 722 #define MIPS_PWSIZE_GDW_SHIFT   24
 723 #define MIPS_PWSIZE_GDW_MASK    0x3f000000
 724 #define MIPS_PWSIZE_UDW_SHIFT   18
 725 #define MIPS_PWSIZE_UDW_MASK    0x00fc0000
 726 #define MIPS_PWSIZE_MDW_SHIFT   12
 727 #define MIPS_PWSIZE_MDW_MASK    0x0003f000
 728 #define MIPS_PWSIZE_PTW_SHIFT   6
 729 #define MIPS_PWSIZE_PTW_MASK    0x00000fc0
 730 #define MIPS_PWSIZE_PTEW_SHIFT  0
 731 #define MIPS_PWSIZE_PTEW_MASK   0x0000003f
 732
 733 #define MIPS_PWCTL_PWEN_SHIFT   31
 734 #define MIPS_PWCTL_PWEN_MASK    0x80000000
 735 #define MIPS_PWCTL_DPH_SHIFT    7
 736 #define MIPS_PWCTL_DPH_MASK     0x00000080
 737 #define MIPS_PWCTL_HUGEPG_SHIFT 6
 738 #define MIPS_PWCTL_HUGEPG_MASK  0x00000060
 739 #define MIPS_PWCTL_PSN_SHIFT    0
 740 #define MIPS_PWCTL_PSN_MASK     0x0000003f
 741
 742 /* CDMMBase register bit definitions */
 743 #define MIPS_CDMMBASE_SIZE_SHIFT 0
 744 #define MIPS_CDMMBASE_SIZE      (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
 745 #define MIPS_CDMMBASE_CI        (_ULCAST_(1) << 9)
 746 #define MIPS_CDMMBASE_EN        (_ULCAST_(1) << 10)
 747 #define MIPS_CDMMBASE_ADDR_SHIFT 11
 748 #define MIPS_CDMMBASE_ADDR_START 15
 749
 750 /*
 751  * Bitfields in the TX39 family CP0 Configuration Register 3
 752  */
 753 #define TX39_CONF_ICS_SHIFT     19
 754 #define TX39_CONF_ICS_MASK      0x00380000
 755 #define TX39_CONF_ICS_1KB       0x00000000
 756 #define TX39_CONF_ICS_2KB       0x00080000
 757 #define TX39_CONF_ICS_4KB       0x00100000
 758 #define TX39_CONF_ICS_8KB       0x00180000
 759 #define TX39_CONF_ICS_16KB      0x00200000
 760
 761 #define TX39_CONF_DCS_SHIFT     16
 762 #define TX39_CONF_DCS_MASK      0x00070000
 763 #define TX39_CONF_DCS_1KB       0x00000000
 764 #define TX39_CONF_DCS_2KB       0x00010000
 765 #define TX39_CONF_DCS_4KB       0x00020000
 766 #define TX39_CONF_DCS_8KB       0x00030000
 767 #define TX39_CONF_DCS_16KB      0x00040000
 768
 769 #define TX39_CONF_CWFON         0x00004000
 770 #define TX39_CONF_WBON          0x00002000
 771 #define TX39_CONF_RF_SHIFT      10
 772 #define TX39_CONF_RF_MASK       0x00000c00
 773 #define TX39_CONF_DOZE          0x00000200
 774 #define TX39_CONF_HALT          0x00000100
 775 #define TX39_CONF_LOCK          0x00000080
 776 #define TX39_CONF_ICE           0x00000020
 777 #define TX39_CONF_DCE           0x00000010
 778 #define TX39_CONF_IRSIZE_SHIFT  2
 779 #define TX39_CONF_IRSIZE_MASK   0x0000000c
 780 #define TX39_CONF_DRSIZE_SHIFT  0
 781 #define TX39_CONF_DRSIZE_MASK   0x00000003
 782
 783 /*
 784  * Interesting Bits in the R10K CP0 Branch Diagnostic Register
 785  */
 786 /* Disable Branch Target Address Cache */
 787 #define R10K_DIAG_D_BTAC        (_ULCAST_(1) << 27)
 788 /* Enable Branch Prediction Global History */
 789 #define R10K_DIAG_E_GHIST       (_ULCAST_(1) << 26)
 790 /* Disable Branch Return Cache */
 791 #define R10K_DIAG_D_BRC         (_ULCAST_(1) << 22)
 792
 793 /* Flush ITLB */
 794 #define LOONGSON_DIAG_ITLB      (_ULCAST_(1) << 2)
 795 /* Flush DTLB */
 796 #define LOONGSON_DIAG_DTLB      (_ULCAST_(1) << 3)
 797 /* Flush VTLB */
 798 #define LOONGSON_DIAG_VTLB      (_ULCAST_(1) << 12)
 799 /* Flush FTLB */
 800 #define LOONGSON_DIAG_FTLB      (_ULCAST_(1) << 13)
 801
 802 /*
 803  * Coprocessor 1 (FPU) register names
 804  */
 805 #define CP1_REVISION    $0
 806 #define CP1_UFR         $1
 807 #define CP1_UNFR        $4
 808 #define CP1_FCCR        $25
 809 #define CP1_FEXR        $26
 810 #define CP1_FENR        $28
 811 #define CP1_STATUS      $31
 812
 813
 814 /*
 815  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
 816  */
 817 #define MIPS_FPIR_S             (_ULCAST_(1) << 16)
 818 #define MIPS_FPIR_D             (_ULCAST_(1) << 17)
 819 #define MIPS_FPIR_PS            (_ULCAST_(1) << 18)
 820 #define MIPS_FPIR_3D            (_ULCAST_(1) << 19)
 821 #define MIPS_FPIR_W             (_ULCAST_(1) << 20)
 822 #define MIPS_FPIR_L             (_ULCAST_(1) << 21)
 823 #define MIPS_FPIR_F64           (_ULCAST_(1) << 22)
 824 #define MIPS_FPIR_HAS2008       (_ULCAST_(1) << 23)
 825 #define MIPS_FPIR_UFRP          (_ULCAST_(1) << 28)
 826 #define MIPS_FPIR_FREP          (_ULCAST_(1) << 29)
 827
 828 /*
 829  * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
 830  */
 831 #define MIPS_FCCR_CONDX_S       0
 832 #define MIPS_FCCR_CONDX         (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
 833 #define MIPS_FCCR_COND0_S       0
 834 #define MIPS_FCCR_COND0         (_ULCAST_(1) << MIPS_FCCR_COND0_S)
 835 #define MIPS_FCCR_COND1_S       1
 836 #define MIPS_FCCR_COND1         (_ULCAST_(1) << MIPS_FCCR_COND1_S)
 837 #define MIPS_FCCR_COND2_S       2
 838 #define MIPS_FCCR_COND2         (_ULCAST_(1) << MIPS_FCCR_COND2_S)
 839 #define MIPS_FCCR_COND3_S       3
 840 #define MIPS_FCCR_COND3         (_ULCAST_(1) << MIPS_FCCR_COND3_S)
 841 #define MIPS_FCCR_COND4_S       4
 842 #define MIPS_FCCR_COND4         (_ULCAST_(1) << MIPS_FCCR_COND4_S)
 843 #define MIPS_FCCR_COND5_S       5
 844 #define MIPS_FCCR_COND5         (_ULCAST_(1) << MIPS_FCCR_COND5_S)
 845 #define MIPS_FCCR_COND6_S       6
 846 #define MIPS_FCCR_COND6         (_ULCAST_(1) << MIPS_FCCR_COND6_S)
 847 #define MIPS_FCCR_COND7_S       7
 848 #define MIPS_FCCR_COND7         (_ULCAST_(1) << MIPS_FCCR_COND7_S)
 849
 850 /*
 851  * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
 852  */
 853 #define MIPS_FENR_FS_S          2
 854 #define MIPS_FENR_FS            (_ULCAST_(1) << MIPS_FENR_FS_S)
 855
 856 /*
 857  * FPU Status Register Values
 858  */
 859 #define FPU_CSR_COND_S  23                                      /* $fcc0 */
 860 #define FPU_CSR_COND    (_ULCAST_(1) << FPU_CSR_COND_S)
 861
 862 #define FPU_CSR_FS_S    24              /* flush denormalised results to 0 */
 863 #define FPU_CSR_FS      (_ULCAST_(1) << FPU_CSR_FS_S)
 864
 865 #define FPU_CSR_CONDX_S 25                                      /* $fcc[7:1] */
 866 #define FPU_CSR_CONDX   (_ULCAST_(127) << FPU_CSR_CONDX_S)
 867 #define FPU_CSR_COND1_S 25                                      /* $fcc1 */
 868 #define FPU_CSR_COND1   (_ULCAST_(1) << FPU_CSR_COND1_S)
 869 #define FPU_CSR_COND2_S 26                                      /* $fcc2 */
 870 #define FPU_CSR_COND2   (_ULCAST_(1) << FPU_CSR_COND2_S)
 871 #define FPU_CSR_COND3_S 27                                      /* $fcc3 */
 872 #define FPU_CSR_COND3   (_ULCAST_(1) << FPU_CSR_COND3_S)
 873 #define FPU_CSR_COND4_S 28                                      /* $fcc4 */
 874 #define FPU_CSR_COND4   (_ULCAST_(1) << FPU_CSR_COND4_S)
 875 #define FPU_CSR_COND5_S 29                                      /* $fcc5 */
 876 #define FPU_CSR_COND5   (_ULCAST_(1) << FPU_CSR_COND5_S)
 877 #define FPU_CSR_COND6_S 30                                      /* $fcc6 */
 878 #define FPU_CSR_COND6   (_ULCAST_(1) << FPU_CSR_COND6_S)
 879 #define FPU_CSR_COND7_S 31                                      /* $fcc7 */
 880 #define FPU_CSR_COND7   (_ULCAST_(1) << FPU_CSR_COND7_S)
 881
 882 /*
 883  * Bits 22:20 of the FPU Status Register will be read as 0,
 884  * and should be written as zero.
 885  */
 886 #define FPU_CSR_RSVD    (_ULCAST_(7) << 20)
 887
 888 #define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
 889 #define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
 890
 891 /*
 892  * X the exception cause indicator
 893  * E the exception enable
 894  * S the sticky/flag bit
 895 */
 896 #define FPU_CSR_ALL_X   0x0003f000
 897 #define FPU_CSR_UNI_X   0x00020000
 898 #define FPU_CSR_INV_X   0x00010000
 899 #define FPU_CSR_DIV_X   0x00008000
 900 #define FPU_CSR_OVF_X   0x00004000
 901 #define FPU_CSR_UDF_X   0x00002000
 902 #define FPU_CSR_INE_X   0x00001000
 903
 904 #define FPU_CSR_ALL_E   0x00000f80
 905 #define FPU_CSR_INV_E   0x00000800
 906 #define FPU_CSR_DIV_E   0x00000400
 907 #define FPU_CSR_OVF_E   0x00000200
 908 #define FPU_CSR_UDF_E   0x00000100
 909 #define FPU_CSR_INE_E   0x00000080
 910
 911 #define FPU_CSR_ALL_S   0x0000007c
 912 #define FPU_CSR_INV_S   0x00000040
 913 #define FPU_CSR_DIV_S   0x00000020
 914 #define FPU_CSR_OVF_S   0x00000010
 915 #define FPU_CSR_UDF_S   0x00000008
 916 #define FPU_CSR_INE_S   0x00000004
 917
 918 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
 919 #define FPU_CSR_RM      0x00000003
 920 #define FPU_CSR_RN      0x0     /* nearest */
 921 #define FPU_CSR_RZ      0x1     /* towards zero */
 922 #define FPU_CSR_RU      0x2     /* towards +Infinity */
 923 #define FPU_CSR_RD      0x3     /* towards -Infinity */
 924
 925
 926 #ifndef __ASSEMBLY__
 927
 928 /*
 929  * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
 930  */
 931 #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
 932     defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
 933 #define get_isa16_mode(x)               ((x) & 0x1)
 934 #define msk_isa16_mode(x)               ((x) & ~0x1)
 935 #define set_isa16_mode(x)               do { (x) |= 0x1; } while(0)
 936 #else
 937 #define get_isa16_mode(x)               0
 938 #define msk_isa16_mode(x)               (x)
 939 #define set_isa16_mode(x)               do { } while(0)
 940 #endif
 941
 942 /*
 943  * microMIPS instructions can be 16-bit or 32-bit in length. This
 944  * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
 945  */
 946 static inline int mm_insn_16bit(u16 insn)
 947 {
 948         u16 opcode = (insn >> 10) & 0x7;
 949
 950         return (opcode >= 1 && opcode <= 3) ? 1 : 0;
 951 }
 952
 953 /*
 954  * TLB Invalidate Flush
 955  */
 956 static inline void tlbinvf(void)
 957 {
 958         __asm__ __volatile__(
 959                 ".set push\n\t"
 960                 ".set noreorder\n\t"
 961                 ".word 0x42000004\n\t" /* tlbinvf */
 962                 ".set pop");
 963 }
 964
 965
 966 /*
 967  * Functions to access the R10000 performance counters.  These are basically
 968  * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
 969  * performance counter number encoded into bits 1 ... 5 of the instruction.
 970  * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
 971  * disassembler these will look like an access to sel 0 or 1.
 972  */
 973 #define read_r10k_perf_cntr(counter)                            \
 974 ({                                                              \
 975         unsigned int __res;                                     \
 976         __asm__ __volatile__(                                   \
 977         "mfpc\t%0, %1"                                          \
 978         : "=r" (__res)                                          \
 979         : "i" (counter));                                       \
 980                                                                 \
 981         __res;                                                  \
 982 })
 983
 984 #define write_r10k_perf_cntr(counter,val)                       \
 985 do {                                                            \
 986         __asm__ __volatile__(                                   \
 987         "mtpc\t%0, %1"                                          \
 988         :                                                       \
 989         : "r" (val), "i" (counter));                            \
 990 } while (0)
 991
 992 #define read_r10k_perf_event(counter)                           \
 993 ({                                                              \
 994         unsigned int __res;                                     \
 995         __asm__ __volatile__(                                   \
 996         "mfps\t%0, %1"                                          \
 997         : "=r" (__res)                                          \
 998         : "i" (counter));                                       \
 999                                                                 \
1000         __res;                                                  \
1001 })
1002
1003 #define write_r10k_perf_cntl(counter,val)                       \
1004 do {                                                            \
1005         __asm__ __volatile__(                                   \
1006         "mtps\t%0, %1"                                          \
1007         :                                                       \
1008         : "r" (val), "i" (counter));                            \
1009 } while (0)
1010
1011
1012 /*
1013  * Macros to access the system control coprocessor
1014  */
1015
1016 #define __read_32bit_c0_register(source, sel)                           \
1017 ({ unsigned int __res;                                                  \
1018         if (sel == 0)                                                   \
1019                 __asm__ __volatile__(                                   \
1020                         "mfc0\t%0, " #source "\n\t"                     \
1021                         : "=r" (__res));                                \
1022         else                                                            \
1023                 __asm__ __volatile__(                                   \
1024                         ".set\tmips32\n\t"                              \
1025                         "mfc0\t%0, " #source ", " #sel "\n\t"           \
1026                         ".set\tmips0\n\t"                               \
1027                         : "=r" (__res));                                \
1028         __res;                                                          \
1029 })
1030
1031 #define __read_64bit_c0_register(source, sel)                           \
1032 ({ unsigned long long __res;                                            \
1033         if (sizeof(unsigned long) == 4)                                 \
1034                 __res = __read_64bit_c0_split(source, sel);             \
1035         else if (sel == 0)                                              \
1036                 __asm__ __volatile__(                                   \
1037                         ".set\tmips3\n\t"                               \
1038                         "dmfc0\t%0, " #source "\n\t"                    \
1039                         ".set\tmips0"                                   \
1040                         : "=r" (__res));                                \
1041         else                                                            \
1042                 __asm__ __volatile__(                                   \
1043                         ".set\tmips64\n\t"                              \
1044                         "dmfc0\t%0, " #source ", " #sel "\n\t"          \
1045                         ".set\tmips0"                                   \
1046                         : "=r" (__res));                                \
1047         __res;                                                          \
1048 })
1049
1050 #define __write_32bit_c0_register(register, sel, value)                 \
1051 do {                                                                    \
1052         if (sel == 0)                                                   \
1053                 __asm__ __volatile__(                                   \
1054                         "mtc0\t%z0, " #register "\n\t"                  \
1055                         : : "Jr" ((unsigned int)(value)));              \
1056         else                                                            \
1057                 __asm__ __volatile__(                                   \
1058                         ".set\tmips32\n\t"                              \
1059                         "mtc0\t%z0, " #register ", " #sel "\n\t"        \
1060                         ".set\tmips0"                                   \
1061                         : : "Jr" ((unsigned int)(value)));              \
1062 } while (0)
1063
1064 #define __write_64bit_c0_register(register, sel, value)                 \
1065 do {                                                                    \
1066         if (sizeof(unsigned long) == 4)                                 \
1067                 __write_64bit_c0_split(register, sel, value);           \
1068         else if (sel == 0)                                              \
1069                 __asm__ __volatile__(                                   \
1070                         ".set\tmips3\n\t"                               \
1071                         "dmtc0\t%z0, " #register "\n\t"                 \
1072                         ".set\tmips0"                                   \
1073                         : : "Jr" (value));                              \
1074         else                                                            \
1075                 __asm__ __volatile__(                                   \
1076                         ".set\tmips64\n\t"                              \
1077                         "dmtc0\t%z0, " #register ", " #sel "\n\t"       \
1078                         ".set\tmips0"                                   \
1079                         : : "Jr" (value));                              \
1080 } while (0)
1081
1082 #define __read_ulong_c0_register(reg, sel)                              \
1083         ((sizeof(unsigned long) == 4) ?                                 \
1084         (unsigned long) __read_32bit_c0_register(reg, sel) :            \
1085         (unsigned long) __read_64bit_c0_register(reg, sel))
1086
1087 #define __write_ulong_c0_register(reg, sel, val)                        \
1088 do {                                                                    \
1089         if (sizeof(unsigned long) == 4)                                 \
1090                 __write_32bit_c0_register(reg, sel, val);               \
1091         else                                                            \
1092                 __write_64bit_c0_register(reg, sel, val);               \
1093 } while (0)
1094
1095 /*
1096  * On RM7000/RM9000 these are uses to access cop0 set 1 registers
1097  */
1098 #define __read_32bit_c0_ctrl_register(source)                           \
1099 ({ unsigned int __res;                                                  \
1100         __asm__ __volatile__(                                           \
1101                 "cfc0\t%0, " #source "\n\t"                             \
1102                 : "=r" (__res));                                        \
1103         __res;                                                          \
1104 })
1105
1106 #define __write_32bit_c0_ctrl_register(register, value)                 \
1107 do {                                                                    \
1108         __asm__ __volatile__(                                           \
1109                 "ctc0\t%z0, " #register "\n\t"                          \
1110                 : : "Jr" ((unsigned int)(value)));                      \
1111 } while (0)
1112
1113 /*
1114  * These versions are only needed for systems with more than 38 bits of
1115  * physical address space running the 32-bit kernel.  That's none atm :-)
1116  */
1117 #define __read_64bit_c0_split(source, sel)                              \
1118 ({                                                                      \
1119         unsigned long long __val;                                       \
1120         unsigned long __flags;                                          \
1121                                                                         \
1122         local_irq_save(__flags);                                        \
1123         if (sel == 0)                                                   \
1124                 __asm__ __volatile__(                                   \
1125                         ".set\tmips64\n\t"                              \
1126                         "dmfc0\t%M0, " #source "\n\t"                   \
1127                         "dsll\t%L0, %M0, 32\n\t"                        \
1128                         "dsra\t%M0, %M0, 32\n\t"                        \
1129                         "dsra\t%L0, %L0, 32\n\t"                        \
1130                         ".set\tmips0"                                   \
1131                         : "=r" (__val));                                \
1132         else                                                            \
1133                 __asm__ __volatile__(                                   \
1134                         ".set\tmips64\n\t"                              \
1135                         "dmfc0\t%M0, " #source ", " #sel "\n\t"         \
1136                         "dsll\t%L0, %M0, 32\n\t"                        \
1137                         "dsra\t%M0, %M0, 32\n\t"                        \
1138                         "dsra\t%L0, %L0, 32\n\t"                        \
1139                         ".set\tmips0"                                   \
1140                         : "=r" (__val));                                \
1141         local_irq_restore(__flags);                                     \
1142                                                                         \
1143         __val;                                                          \
1144 })
1145
1146 #define __write_64bit_c0_split(source, sel, val)                        \
1147 do {                                                                    \
1148         unsigned long __flags;                                          \
1149                                                                         \
1150         local_irq_save(__flags);                                        \
1151         if (sel == 0)                                                   \
1152                 __asm__ __volatile__(                                   \
1153                         ".set\tmips64\n\t"                              \
1154                         "dsll\t%L0, %L0, 32\n\t"                        \
1155                         "dsrl\t%L0, %L0, 32\n\t"                        \
1156                         "dsll\t%M0, %M0, 32\n\t"                        \
1157                         "or\t%L0, %L0, %M0\n\t"                         \
1158                         "dmtc0\t%L0, " #source "\n\t"                   \
1159                         ".set\tmips0"                                   \
1160                         : : "r" (val));                                 \
1161         else                                                            \
1162                 __asm__ __volatile__(                                   \
1163                         ".set\tmips64\n\t"                              \
1164                         "dsll\t%L0, %L0, 32\n\t"                        \
1165                         "dsrl\t%L0, %L0, 32\n\t"                        \
1166                         "dsll\t%M0, %M0, 32\n\t"                        \
1167                         "or\t%L0, %L0, %M0\n\t"                         \
1168                         "dmtc0\t%L0, " #source ", " #sel "\n\t"         \
1169                         ".set\tmips0"                                   \
1170                         : : "r" (val));                                 \
1171         local_irq_restore(__flags);                                     \
1172 } while (0)
1173
1174 #define __readx_32bit_c0_register(source)                               \
1175 ({                                                                      \
1176         unsigned int __res;                                             \
1177                                                                         \
1178         __asm__ __volatile__(                                           \
1179         "       .set    push                                    \n"     \
1180         "       .set    noat                                    \n"     \
1181         "       .set    mips32r2                                \n"     \
1182         "       .insn                                           \n"     \
1183         "       # mfhc0 $1, %1                                  \n"     \
1184         "       .word   (0x40410000 | ((%1 & 0x1f) << 11))      \n"     \
1185         "       move    %0, $1                                  \n"     \
1186         "       .set    pop                                     \n"     \
1187         : "=r" (__res)                                                  \
1188         : "i" (source));                                                \
1189         __res;                                                          \
1190 })
1191
1192 #define __writex_32bit_c0_register(register, value)                     \
1193 do {                                                                    \
1194         __asm__ __volatile__(                                           \
1195         "       .set    push                                    \n"     \
1196         "       .set    noat                                    \n"     \
1197         "       .set    mips32r2                                \n"     \
1198         "       move    $1, %0                                  \n"     \
1199         "       # mthc0 $1, %1                                  \n"     \
1200         "       .insn                                           \n"     \
1201         "       .word   (0x40c10000 | ((%1 & 0x1f) << 11))      \n"     \
1202         "       .set    pop                                     \n"     \
1203         :                                                               \
1204         : "r" (value), "i" (register));                                 \
1205 } while (0)
1206
1207 #define read_c0_index()         __read_32bit_c0_register($0, 0)
1208 #define write_c0_index(val)     __write_32bit_c0_register($0, 0, val)
1209
1210 #define read_c0_random()        __read_32bit_c0_register($1, 0)
1211 #define write_c0_random(val)    __write_32bit_c0_register($1, 0, val)
1212
1213 #define read_c0_entrylo0()      __read_ulong_c0_register($2, 0)
1214 #define write_c0_entrylo0(val)  __write_ulong_c0_register($2, 0, val)
1215
1216 #define readx_c0_entrylo0()     __readx_32bit_c0_register(2)
1217 #define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val)
1218
1219 #define read_c0_entrylo1()      __read_ulong_c0_register($3, 0)
1220 #define write_c0_entrylo1(val)  __write_ulong_c0_register($3, 0, val)
1221
1222 #define readx_c0_entrylo1()     __readx_32bit_c0_register(3)
1223 #define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val)
1224
1225 #define read_c0_conf()          __read_32bit_c0_register($3, 0)
1226 #define write_c0_conf(val)      __write_32bit_c0_register($3, 0, val)
1227
1228 #define read_c0_context()       __read_ulong_c0_register($4, 0)
1229 #define write_c0_context(val)   __write_ulong_c0_register($4, 0, val)
1230
1231 #define read_c0_userlocal()     __read_ulong_c0_register($4, 2)
1232 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1233
1234 #define read_c0_pagemask()      __read_32bit_c0_register($5, 0)
1235 #define write_c0_pagemask(val)  __write_32bit_c0_register($5, 0, val)
1236
1237 #define read_c0_pagegrain()     __read_32bit_c0_register($5, 1)
1238 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1239
1240 #define read_c0_wired()         __read_32bit_c0_register($6, 0)
1241 #define write_c0_wired(val)     __write_32bit_c0_register($6, 0, val)
1242
1243 #define read_c0_info()          __read_32bit_c0_register($7, 0)
1244
1245 #define read_c0_cache()         __read_32bit_c0_register($7, 0) /* TX39xx */
1246 #define write_c0_cache(val)     __write_32bit_c0_register($7, 0, val)
1247
1248 #define read_c0_badvaddr()      __read_ulong_c0_register($8, 0)
1249 #define write_c0_badvaddr(val)  __write_ulong_c0_register($8, 0, val)
1250
1251 #define read_c0_count()         __read_32bit_c0_register($9, 0)
1252 #define write_c0_count(val)     __write_32bit_c0_register($9, 0, val)
1253
1254 #define read_c0_count2()        __read_32bit_c0_register($9, 6) /* pnx8550 */
1255 #define write_c0_count2(val)    __write_32bit_c0_register($9, 6, val)
1256
1257 #define read_c0_count3()        __read_32bit_c0_register($9, 7) /* pnx8550 */
1258 #define write_c0_count3(val)    __write_32bit_c0_register($9, 7, val)
1259
1260 #define read_c0_entryhi()       __read_ulong_c0_register($10, 0)
1261 #define write_c0_entryhi(val)   __write_ulong_c0_register($10, 0, val)
1262
1263 #define read_c0_compare()       __read_32bit_c0_register($11, 0)
1264 #define write_c0_compare(val)   __write_32bit_c0_register($11, 0, val)
1265
1266 #define read_c0_compare2()      __read_32bit_c0_register($11, 6) /* pnx8550 */
1267 #define write_c0_compare2(val)  __write_32bit_c0_register($11, 6, val)
1268
1269 #define read_c0_compare3()      __read_32bit_c0_register($11, 7) /* pnx8550 */
1270 #define write_c0_compare3(val)  __write_32bit_c0_register($11, 7, val)
1271
1272 #define read_c0_status()        __read_32bit_c0_register($12, 0)
1273
1274 #define write_c0_status(val)    __write_32bit_c0_register($12, 0, val)
1275
1276 #define read_c0_cause()         __read_32bit_c0_register($13, 0)
1277 #define write_c0_cause(val)     __write_32bit_c0_register($13, 0, val)
1278
1279 #define read_c0_epc()           __read_ulong_c0_register($14, 0)
1280 #define write_c0_epc(val)       __write_ulong_c0_register($14, 0, val)
1281
1282 #define read_c0_prid()          __read_32bit_c0_register($15, 0)
1283
1284 #define read_c0_cmgcrbase()     __read_ulong_c0_register($15, 3)
1285
1286 #define read_c0_config()        __read_32bit_c0_register($16, 0)
1287 #define read_c0_config1()       __read_32bit_c0_register($16, 1)
1288 #define read_c0_config2()       __read_32bit_c0_register($16, 2)
1289 #define read_c0_config3()       __read_32bit_c0_register($16, 3)
1290 #define read_c0_config4()       __read_32bit_c0_register($16, 4)
1291 #define read_c0_config5()       __read_32bit_c0_register($16, 5)
1292 #define read_c0_config6()       __read_32bit_c0_register($16, 6)
1293 #define read_c0_config7()       __read_32bit_c0_register($16, 7)
1294 #define write_c0_config(val)    __write_32bit_c0_register($16, 0, val)
1295 #define write_c0_config1(val)   __write_32bit_c0_register($16, 1, val)
1296 #define write_c0_config2(val)   __write_32bit_c0_register($16, 2, val)
1297 #define write_c0_config3(val)   __write_32bit_c0_register($16, 3, val)
1298 #define write_c0_config4(val)   __write_32bit_c0_register($16, 4, val)
1299 #define write_c0_config5(val)   __write_32bit_c0_register($16, 5, val)
1300 #define write_c0_config6(val)   __write_32bit_c0_register($16, 6, val)
1301 #define write_c0_config7(val)   __write_32bit_c0_register($16, 7, val)
1302
1303 #define read_c0_lladdr()        __read_ulong_c0_register($17, 0)
1304 #define write_c0_lladdr(val)    __write_ulong_c0_register($17, 0, val)
1305 #define read_c0_maar()          __read_ulong_c0_register($17, 1)
1306 #define write_c0_maar(val)      __write_ulong_c0_register($17, 1, val)
1307 #define read_c0_maari()         __read_32bit_c0_register($17, 2)
1308 #define write_c0_maari(val)     __write_32bit_c0_register($17, 2, val)
1309
1310 /*
1311  * The WatchLo register.  There may be up to 8 of them.
1312  */
1313 #define read_c0_watchlo0()      __read_ulong_c0_register($18, 0)
1314 #define read_c0_watchlo1()      __read_ulong_c0_register($18, 1)
1315 #define read_c0_watchlo2()      __read_ulong_c0_register($18, 2)
1316 #define read_c0_watchlo3()      __read_ulong_c0_register($18, 3)
1317 #define read_c0_watchlo4()      __read_ulong_c0_register($18, 4)
1318 #define read_c0_watchlo5()      __read_ulong_c0_register($18, 5)
1319 #define read_c0_watchlo6()      __read_ulong_c0_register($18, 6)
1320 #define read_c0_watchlo7()      __read_ulong_c0_register($18, 7)
1321 #define write_c0_watchlo0(val)  __write_ulong_c0_register($18, 0, val)
1322 #define write_c0_watchlo1(val)  __write_ulong_c0_register($18, 1, val)
1323 #define write_c0_watchlo2(val)  __write_ulong_c0_register($18, 2, val)
1324 #define write_c0_watchlo3(val)  __write_ulong_c0_register($18, 3, val)
1325 #define write_c0_watchlo4(val)  __write_ulong_c0_register($18, 4, val)
1326 #define write_c0_watchlo5(val)  __write_ulong_c0_register($18, 5, val)
1327 #define write_c0_watchlo6(val)  __write_ulong_c0_register($18, 6, val)
1328 #define write_c0_watchlo7(val)  __write_ulong_c0_register($18, 7, val)
1329
1330 /*
1331  * The WatchHi register.  There may be up to 8 of them.
1332  */
1333 #define read_c0_watchhi0()      __read_32bit_c0_register($19, 0)
1334 #define read_c0_watchhi1()      __read_32bit_c0_register($19, 1)
1335 #define read_c0_watchhi2()      __read_32bit_c0_register($19, 2)
1336 #define read_c0_watchhi3()      __read_32bit_c0_register($19, 3)
1337 #define read_c0_watchhi4()      __read_32bit_c0_register($19, 4)
1338 #define read_c0_watchhi5()      __read_32bit_c0_register($19, 5)
1339 #define read_c0_watchhi6()      __read_32bit_c0_register($19, 6)
1340 #define read_c0_watchhi7()      __read_32bit_c0_register($19, 7)
1341
1342 #define write_c0_watchhi0(val)  __write_32bit_c0_register($19, 0, val)
1343 #define write_c0_watchhi1(val)  __write_32bit_c0_register($19, 1, val)
1344 #define write_c0_watchhi2(val)  __write_32bit_c0_register($19, 2, val)
1345 #define write_c0_watchhi3(val)  __write_32bit_c0_register($19, 3, val)
1346 #define write_c0_watchhi4(val)  __write_32bit_c0_register($19, 4, val)
1347 #define write_c0_watchhi5(val)  __write_32bit_c0_register($19, 5, val)
1348 #define write_c0_watchhi6(val)  __write_32bit_c0_register($19, 6, val)
1349 #define write_c0_watchhi7(val)  __write_32bit_c0_register($19, 7, val)
1350
1351 #define read_c0_xcontext()      __read_ulong_c0_register($20, 0)
1352 #define write_c0_xcontext(val)  __write_ulong_c0_register($20, 0, val)
1353
1354 #define read_c0_intcontrol()    __read_32bit_c0_ctrl_register($20)
1355 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1356
1357 #define read_c0_framemask()     __read_32bit_c0_register($21, 0)
1358 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1359
1360 #define read_c0_diag()          __read_32bit_c0_register($22, 0)
1361 #define write_c0_diag(val)      __write_32bit_c0_register($22, 0, val)
1362
1363 /* R10K CP0 Branch Diagnostic register is 64bits wide */
1364 #define read_c0_r10k_diag()     __read_64bit_c0_register($22, 0)
1365 #define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
1366
1367 #define read_c0_diag1()         __read_32bit_c0_register($22, 1)
1368 #define write_c0_diag1(val)     __write_32bit_c0_register($22, 1, val)
1369
1370 #define read_c0_diag2()         __read_32bit_c0_register($22, 2)
1371 #define write_c0_diag2(val)     __write_32bit_c0_register($22, 2, val)
1372
1373 #define read_c0_diag3()         __read_32bit_c0_register($22, 3)
1374 #define write_c0_diag3(val)     __write_32bit_c0_register($22, 3, val)
1375
1376 #define read_c0_diag4()         __read_32bit_c0_register($22, 4)
1377 #define write_c0_diag4(val)     __write_32bit_c0_register($22, 4, val)
1378
1379 #define read_c0_diag5()         __read_32bit_c0_register($22, 5)
1380 #define write_c0_diag5(val)     __write_32bit_c0_register($22, 5, val)
1381
1382 #define read_c0_debug()         __read_32bit_c0_register($23, 0)
1383 #define write_c0_debug(val)     __write_32bit_c0_register($23, 0, val)
1384
1385 #define read_c0_depc()          __read_ulong_c0_register($24, 0)
1386 #define write_c0_depc(val)      __write_ulong_c0_register($24, 0, val)
1387
1388 /*
1389  * MIPS32 / MIPS64 performance counters
1390  */
1391 #define read_c0_perfctrl0()     __read_32bit_c0_register($25, 0)
1392 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1393 #define read_c0_perfcntr0()     __read_32bit_c0_register($25, 1)
1394 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1395 #define read_c0_perfcntr0_64()  __read_64bit_c0_register($25, 1)
1396 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1397 #define read_c0_perfctrl1()     __read_32bit_c0_register($25, 2)
1398 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1399 #define read_c0_perfcntr1()     __read_32bit_c0_register($25, 3)
1400 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1401 #define read_c0_perfcntr1_64()  __read_64bit_c0_register($25, 3)
1402 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1403 #define read_c0_perfctrl2()     __read_32bit_c0_register($25, 4)
1404 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1405 #define read_c0_perfcntr2()     __read_32bit_c0_register($25, 5)
1406 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1407 #define read_c0_perfcntr2_64()  __read_64bit_c0_register($25, 5)
1408 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1409 #define read_c0_perfctrl3()     __read_32bit_c0_register($25, 6)
1410 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1411 #define read_c0_perfcntr3()     __read_32bit_c0_register($25, 7)
1412 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1413 #define read_c0_perfcntr3_64()  __read_64bit_c0_register($25, 7)
1414 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1415
1416 #define read_c0_ecc()           __read_32bit_c0_register($26, 0)
1417 #define write_c0_ecc(val)       __write_32bit_c0_register($26, 0, val)
1418
1419 #define read_c0_derraddr0()     __read_ulong_c0_register($26, 1)
1420 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1421
1422 #define read_c0_cacheerr()      __read_32bit_c0_register($27, 0)
1423
1424 #define read_c0_derraddr1()     __read_ulong_c0_register($27, 1)
1425 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1426
1427 #define read_c0_taglo()         __read_32bit_c0_register($28, 0)
1428 #define write_c0_taglo(val)     __write_32bit_c0_register($28, 0, val)
1429
1430 #define read_c0_dtaglo()        __read_32bit_c0_register($28, 2)
1431 #define write_c0_dtaglo(val)    __write_32bit_c0_register($28, 2, val)
1432
1433 #define read_c0_ddatalo()       __read_32bit_c0_register($28, 3)
1434 #define write_c0_ddatalo(val)   __write_32bit_c0_register($28, 3, val)
1435
1436 #define read_c0_staglo()        __read_32bit_c0_register($28, 4)
1437 #define write_c0_staglo(val)    __write_32bit_c0_register($28, 4, val)
1438
1439 #define read_c0_taghi()         __read_32bit_c0_register($29, 0)
1440 #define write_c0_taghi(val)     __write_32bit_c0_register($29, 0, val)
1441
1442 #define read_c0_errorepc()      __read_ulong_c0_register($30, 0)
1443 #define write_c0_errorepc(val)  __write_ulong_c0_register($30, 0, val)
1444
1445 /* MIPSR2 */
1446 #define read_c0_hwrena()        __read_32bit_c0_register($7, 0)
1447 #define write_c0_hwrena(val)    __write_32bit_c0_register($7, 0, val)
1448
1449 #define read_c0_intctl()        __read_32bit_c0_register($12, 1)
1450 #define write_c0_intctl(val)    __write_32bit_c0_register($12, 1, val)
1451
1452 #define read_c0_srsctl()        __read_32bit_c0_register($12, 2)
1453 #define write_c0_srsctl(val)    __write_32bit_c0_register($12, 2, val)
1454
1455 #define read_c0_srsmap()        __read_32bit_c0_register($12, 3)
1456 #define write_c0_srsmap(val)    __write_32bit_c0_register($12, 3, val)
1457
1458 #define read_c0_ebase()         __read_32bit_c0_register($15, 1)
1459 #define write_c0_ebase(val)     __write_32bit_c0_register($15, 1, val)
1460
1461 #define read_c0_cdmmbase()      __read_ulong_c0_register($15, 2)
1462 #define write_c0_cdmmbase(val)  __write_ulong_c0_register($15, 2, val)
1463
1464 /* MIPSR3 */
1465 #define read_c0_segctl0()       __read_32bit_c0_register($5, 2)
1466 #define write_c0_segctl0(val)   __write_32bit_c0_register($5, 2, val)
1467
1468 #define read_c0_segctl1()       __read_32bit_c0_register($5, 3)
1469 #define write_c0_segctl1(val)   __write_32bit_c0_register($5, 3, val)
1470
1471 #define read_c0_segctl2()       __read_32bit_c0_register($5, 4)
1472 #define write_c0_segctl2(val)   __write_32bit_c0_register($5, 4, val)
1473
1474 /* Hardware Page Table Walker */
1475 #define read_c0_pwbase()        __read_ulong_c0_register($5, 5)
1476 #define write_c0_pwbase(val)    __write_ulong_c0_register($5, 5, val)
1477
1478 #define read_c0_pwfield()       __read_ulong_c0_register($5, 6)
1479 #define write_c0_pwfield(val)   __write_ulong_c0_register($5, 6, val)
1480
1481 #define read_c0_pwsize()        __read_ulong_c0_register($5, 7)
1482 #define write_c0_pwsize(val)    __write_ulong_c0_register($5, 7, val)
1483
1484 #define read_c0_pwctl()         __read_32bit_c0_register($6, 6)
1485 #define write_c0_pwctl(val)     __write_32bit_c0_register($6, 6, val)
1486
1487 #define read_c0_pgd()           __read_64bit_c0_register($9, 7)
1488 #define write_c0_pgd(val)       __write_64bit_c0_register($9, 7, val)
1489
1490 #define read_c0_kpgd()          __read_64bit_c0_register($31, 7)
1491 #define write_c0_kpgd(val)      __write_64bit_c0_register($31, 7, val)
1492
1493 /* Cavium OCTEON (cnMIPS) */
1494 #define read_c0_cvmcount()      __read_ulong_c0_register($9, 6)
1495 #define write_c0_cvmcount(val)  __write_ulong_c0_register($9, 6, val)
1496
1497 #define read_c0_cvmctl()        __read_64bit_c0_register($9, 7)
1498 #define write_c0_cvmctl(val)    __write_64bit_c0_register($9, 7, val)
1499
1500 #define read_c0_cvmmemctl()     __read_64bit_c0_register($11, 7)
1501 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1502 /*
1503  * The cacheerr registers are not standardized.  On OCTEON, they are
1504  * 64 bits wide.
1505  */
1506 #define read_octeon_c0_icacheerr()      __read_64bit_c0_register($27, 0)
1507 #define write_octeon_c0_icacheerr(val)  __write_64bit_c0_register($27, 0, val)
1508
1509 #define read_octeon_c0_dcacheerr()      __read_64bit_c0_register($27, 1)
1510 #define write_octeon_c0_dcacheerr(val)  __write_64bit_c0_register($27, 1, val)
1511
1512 /* BMIPS3300 */
1513 #define read_c0_brcm_config_0()         __read_32bit_c0_register($22, 0)
1514 #define write_c0_brcm_config_0(val)     __write_32bit_c0_register($22, 0, val)
1515
1516 #define read_c0_brcm_bus_pll()          __read_32bit_c0_register($22, 4)
1517 #define write_c0_brcm_bus_pll(val)      __write_32bit_c0_register($22, 4, val)
1518
1519 #define read_c0_brcm_reset()            __read_32bit_c0_register($22, 5)
1520 #define write_c0_brcm_reset(val)        __write_32bit_c0_register($22, 5, val)
1521
1522 /* BMIPS43xx */
1523 #define read_c0_brcm_cmt_intr()         __read_32bit_c0_register($22, 1)
1524 #define write_c0_brcm_cmt_intr(val)     __write_32bit_c0_register($22, 1, val)
1525
1526 #define read_c0_brcm_cmt_ctrl()         __read_32bit_c0_register($22, 2)
1527 #define write_c0_brcm_cmt_ctrl(val)     __write_32bit_c0_register($22, 2, val)
1528
1529 #define read_c0_brcm_cmt_local()        __read_32bit_c0_register($22, 3)
1530 #define write_c0_brcm_cmt_local(val)    __write_32bit_c0_register($22, 3, val)
1531
1532 #define read_c0_brcm_config_1()         __read_32bit_c0_register($22, 5)
1533 #define write_c0_brcm_config_1(val)     __write_32bit_c0_register($22, 5, val)
1534
1535 #define read_c0_brcm_cbr()              __read_32bit_c0_register($22, 6)
1536 #define write_c0_brcm_cbr(val)          __write_32bit_c0_register($22, 6, val)
1537
1538 /* BMIPS5000 */
1539 #define read_c0_brcm_config()           __read_32bit_c0_register($22, 0)
1540 #define write_c0_brcm_config(val)       __write_32bit_c0_register($22, 0, val)
1541
1542 #define read_c0_brcm_mode()             __read_32bit_c0_register($22, 1)
1543 #define write_c0_brcm_mode(val)         __write_32bit_c0_register($22, 1, val)
1544
1545 #define read_c0_brcm_action()           __read_32bit_c0_register($22, 2)
1546 #define write_c0_brcm_action(val)       __write_32bit_c0_register($22, 2, val)
1547
1548 #define read_c0_brcm_edsp()             __read_32bit_c0_register($22, 3)
1549 #define write_c0_brcm_edsp(val)         __write_32bit_c0_register($22, 3, val)
1550
1551 #define read_c0_brcm_bootvec()          __read_32bit_c0_register($22, 4)
1552 #define write_c0_brcm_bootvec(val)      __write_32bit_c0_register($22, 4, val)
1553
1554 #define read_c0_brcm_sleepcount()       __read_32bit_c0_register($22, 7)
1555 #define write_c0_brcm_sleepcount(val)   __write_32bit_c0_register($22, 7, val)
1556
1557 /*
1558  * Macros to access the floating point coprocessor control registers
1559  */
1560 #define _read_32bit_cp1_register(source, gas_hardfloat)                 \
1561 ({                                                                      \
1562         unsigned int __res;                                             \
1563                                                                         \
1564         __asm__ __volatile__(                                           \
1565         "       .set    push                                    \n"     \
1566         "       .set    reorder                                 \n"     \
1567         "       # gas fails to assemble cfc1 for some archs,    \n"     \
1568         "       # like Octeon.                                  \n"     \
1569         "       .set    mips1                                   \n"     \
1570         "       "STR(gas_hardfloat)"                            \n"     \
1571         "       cfc1    %0,"STR(source)"                        \n"     \
1572         "       .set    pop                                     \n"     \
1573         : "=r" (__res));                                                \
1574         __res;                                                          \
1575 })
1576
1577 #define _write_32bit_cp1_register(dest, val, gas_hardfloat)             \
1578 do {                                                                    \
1579         __asm__ __volatile__(                                           \
1580         "       .set    push                                    \n"     \
1581         "       .set    reorder                                 \n"     \
1582         "       "STR(gas_hardfloat)"                            \n"     \
1583         "       ctc1    %0,"STR(dest)"                          \n"     \
1584         "       .set    pop                                     \n"     \
1585         : : "r" (val));                                                 \
1586 } while (0)
1587
1588 #ifdef GAS_HAS_SET_HARDFLOAT
1589 #define read_32bit_cp1_register(source)                                 \
1590         _read_32bit_cp1_register(source, .set hardfloat)
1591 #define write_32bit_cp1_register(dest, val)                             \
1592         _write_32bit_cp1_register(dest, val, .set hardfloat)
1593 #else
1594 #define read_32bit_cp1_register(source)                                 \
1595         _read_32bit_cp1_register(source, )
1596 #define write_32bit_cp1_register(dest, val)                             \
1597         _write_32bit_cp1_register(dest, val, )
1598 #endif
1599
1600 #ifdef HAVE_AS_DSP
1601 #define rddsp(mask)                                                     \
1602 ({                                                                      \
1603         unsigned int __dspctl;                                          \
1604                                                                         \
1605         __asm__ __volatile__(                                           \
1606         "       .set push                                       \n"     \
1607         "       .set dsp                                        \n"     \
1608         "       rddsp   %0, %x1                                 \n"     \
1609         "       .set pop                                        \n"     \
1610         : "=r" (__dspctl)                                               \
1611         : "i" (mask));                                                  \
1612         __dspctl;                                                       \
1613 })
1614
1615 #define wrdsp(val, mask)                                                \
1616 do {                                                                    \
1617         __asm__ __volatile__(                                           \
1618         "       .set push                                       \n"     \
1619         "       .set dsp                                        \n"     \
1620         "       wrdsp   %0, %x1                                 \n"     \
1621         "       .set pop                                        \n"     \
1622         :                                                               \
1623         : "r" (val), "i" (mask));                                       \
1624 } while (0)
1625
1626 #define mflo0()                                                         \
1627 ({                                                                      \
1628         long mflo0;                                                     \
1629         __asm__(                                                        \
1630         "       .set push                                       \n"     \
1631         "       .set dsp                                        \n"     \
1632         "       mflo %0, $ac0                                   \n"     \
1633         "       .set pop                                        \n"     \
1634         : "=r" (mflo0));                                                \
1635         mflo0;                                                          \
1636 })
1637
1638 #define mflo1()                                                         \
1639 ({                                                                      \
1640         long mflo1;                                                     \
1641         __asm__(                                                        \
1642         "       .set push                                       \n"     \
1643         "       .set dsp                                        \n"     \
1644         "       mflo %0, $ac1                                   \n"     \
1645         "       .set pop                                        \n"     \
1646         : "=r" (mflo1));                                                \
1647         mflo1;                                                          \
1648 })
1649
1650 #define mflo2()                                                         \
1651 ({                                                                      \
1652         long mflo2;                                                     \
1653         __asm__(                                                        \
1654         "       .set push                                       \n"     \
1655         "       .set dsp                                        \n"     \
1656         "       mflo %0, $ac2                                   \n"     \
1657         "       .set pop                                        \n"     \
1658         : "=r" (mflo2));                                                \
1659         mflo2;                                                          \
1660 })
1661
1662 #define mflo3()                                                         \
1663 ({                                                                      \
1664         long mflo3;                                                     \
1665         __asm__(                                                        \
1666         "       .set push                                       \n"     \
1667         "       .set dsp                                        \n"     \
1668         "       mflo %0, $ac3                                   \n"     \
1669         "       .set pop                                        \n"     \
1670         : "=r" (mflo3));                                                \
1671         mflo3;                                                          \
1672 })
1673
1674 #define mfhi0()                                                         \
1675 ({                                                                      \
1676         long mfhi0;                                                     \
1677         __asm__(                                                        \
1678         "       .set push                                       \n"     \
1679         "       .set dsp                                        \n"     \
1680         "       mfhi %0, $ac0                                   \n"     \
1681         "       .set pop                                        \n"     \
1682         : "=r" (mfhi0));                                                \
1683         mfhi0;                                                          \
1684 })
1685
1686 #define mfhi1()                                                         \
1687 ({                                                                      \
1688         long mfhi1;                                                     \
1689         __asm__(                                                        \
1690         "       .set push                                       \n"     \
1691         "       .set dsp                                        \n"     \
1692         "       mfhi %0, $ac1                                   \n"     \
1693         "       .set pop                                        \n"     \
1694         : "=r" (mfhi1));                                                \
1695         mfhi1;                                                          \
1696 })
1697
1698 #define mfhi2()                                                         \
1699 ({                                                                      \
1700         long mfhi2;                                                     \
1701         __asm__(                                                        \
1702         "       .set push                                       \n"     \
1703         "       .set dsp                                        \n"     \
1704         "       mfhi %0, $ac2                                   \n"     \
1705         "       .set pop                                        \n"     \
1706         : "=r" (mfhi2));                                                \
1707         mfhi2;                                                          \
1708 })
1709
1710 #define mfhi3()                                                         \
1711 ({                                                                      \
1712         long mfhi3;                                                     \
1713         __asm__(                                                        \
1714         "       .set push                                       \n"     \
1715         "       .set dsp                                        \n"     \
1716         "       mfhi %0, $ac3                                   \n"     \
1717         "       .set pop                                        \n"     \
1718         : "=r" (mfhi3));                                                \
1719         mfhi3;                                                          \
1720 })
1721
1722
1723 #define mtlo0(x)                                                        \
1724 ({                                                                      \
1725         __asm__(                                                        \
1726         "       .set push                                       \n"     \
1727         "       .set dsp                                        \n"     \
1728         "       mtlo %0, $ac0                                   \n"     \
1729         "       .set pop                                        \n"     \
1730         :                                                               \
1731         : "r" (x));                                                     \
1732 })
1733
1734 #define mtlo1(x)                                                        \
1735 ({                                                                      \
1736         __asm__(                                                        \
1737         "       .set push                                       \n"     \
1738         "       .set dsp                                        \n"     \
1739         "       mtlo %0, $ac1                                   \n"     \
1740         "       .set pop                                        \n"     \
1741         :                                                               \
1742         : "r" (x));                                                     \
1743 })
1744
1745 #define mtlo2(x)                                                        \
1746 ({                                                                      \
1747         __asm__(                                                        \
1748         "       .set push                                       \n"     \
1749         "       .set dsp                                        \n"     \
1750         "       mtlo %0, $ac2                                   \n"     \
1751         "       .set pop                                        \n"     \
1752         :                                                               \
1753         : "r" (x));                                                     \
1754 })
1755
1756 #define mtlo3(x)                                                        \
1757 ({                                                                      \
1758         __asm__(                                                        \
1759         "       .set push                                       \n"     \
1760         "       .set dsp                                        \n"     \
1761         "       mtlo %0, $ac3                                   \n"     \
1762         "       .set pop                                        \n"     \
1763         :                                                               \
1764         : "r" (x));                                                     \
1765 })
1766
1767 #define mthi0(x)                                                        \
1768 ({                                                                      \
1769         __asm__(                                                        \
1770         "       .set push                                       \n"     \
1771         "       .set dsp                                        \n"     \
1772         "       mthi %0, $ac0                                   \n"     \
1773         "       .set pop                                        \n"     \
1774         :                                                               \
1775         : "r" (x));                                                     \
1776 })
1777
1778 #define mthi1(x)                                                        \
1779 ({                                                                      \
1780         __asm__(                                                        \
1781         "       .set push                                       \n"     \
1782         "       .set dsp                                        \n"     \
1783         "       mthi %0, $ac1                                   \n"     \
1784         "       .set pop                                        \n"     \
1785         :                                                               \
1786         : "r" (x));                                                     \
1787 })
1788
1789 #define mthi2(x)                                                        \
1790 ({                                                                      \
1791         __asm__(                                                        \
1792         "       .set push                                       \n"     \
1793         "       .set dsp                                        \n"     \
1794         "       mthi %0, $ac2                                   \n"     \
1795         "       .set pop                                        \n"     \
1796         :                                                               \
1797         : "r" (x));                                                     \
1798 })
1799
1800 #define mthi3(x)                                                        \
1801 ({                                                                      \
1802         __asm__(                                                        \
1803         "       .set push                                       \n"     \
1804         "       .set dsp                                        \n"     \
1805         "       mthi %0, $ac3                                   \n"     \
1806         "       .set pop                                        \n"     \
1807         :                                                               \
1808         : "r" (x));                                                     \
1809 })
1810
1811 #else
1812
1813 #ifdef CONFIG_CPU_MICROMIPS
1814 #define rddsp(mask)                                                     \
1815 ({                                                                      \
1816         unsigned int __res;                                             \
1817                                                                         \
1818         __asm__ __volatile__(                                           \
1819         "       .set    push                                    \n"     \
1820         "       .set    noat                                    \n"     \
1821         "       # rddsp $1, %x1                                 \n"     \
1822         "       .hword  ((0x0020067c | (%x1 << 14)) >> 16)      \n"     \
1823         "       .hword  ((0x0020067c | (%x1 << 14)) & 0xffff)   \n"     \
1824         "       move    %0, $1                                  \n"     \
1825         "       .set    pop                                     \n"     \
1826         : "=r" (__res)                                                  \
1827         : "i" (mask));                                                  \
1828         __res;                                                          \
1829 })
1830
1831 #define wrdsp(val, mask)                                                \
1832 do {                                                                    \
1833         __asm__ __volatile__(                                           \
1834         "       .set    push                                    \n"     \
1835         "       .set    noat                                    \n"     \
1836         "       move    $1, %0                                  \n"     \
1837         "       # wrdsp $1, %x1                                 \n"     \
1838         "       .hword  ((0x0020167c | (%x1 << 14)) >> 16)      \n"     \
1839         "       .hword  ((0x0020167c | (%x1 << 14)) & 0xffff)   \n"     \
1840         "       .set    pop                                     \n"     \
1841         :                                                               \
1842         : "r" (val), "i" (mask));                                       \
1843 } while (0)
1844
1845 #define _umips_dsp_mfxxx(ins)                                           \
1846 ({                                                                      \
1847         unsigned long __treg;                                           \
1848                                                                         \
1849         __asm__ __volatile__(                                           \
1850         "       .set    push                                    \n"     \
1851         "       .set    noat                                    \n"     \
1852         "       .hword  0x0001                                  \n"     \
1853         "       .hword  %x1                                     \n"     \
1854         "       move    %0, $1                                  \n"     \
1855         "       .set    pop                                     \n"     \
1856         : "=r" (__treg)                                                 \
1857         : "i" (ins));                                                   \
1858         __treg;                                                         \
1859 })
1860
1861 #define _umips_dsp_mtxxx(val, ins)                                      \
1862 do {                                                                    \
1863         __asm__ __volatile__(                                           \
1864         "       .set    push                                    \n"     \
1865         "       .set    noat                                    \n"     \
1866         "       move    $1, %0                                  \n"     \
1867         "       .hword  0x0001                                  \n"     \
1868         "       .hword  %x1                                     \n"     \
1869         "       .set    pop                                     \n"     \
1870         :                                                               \
1871         : "r" (val), "i" (ins));                                        \
1872 } while (0)
1873
1874 #define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c)
1875 #define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)
1876
1877 #define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
1878 #define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
1879
1880 #define mflo0() _umips_dsp_mflo(0)
1881 #define mflo1() _umips_dsp_mflo(1)
1882 #define mflo2() _umips_dsp_mflo(2)
1883 #define mflo3() _umips_dsp_mflo(3)
1884
1885 #define mfhi0() _umips_dsp_mfhi(0)
1886 #define mfhi1() _umips_dsp_mfhi(1)
1887 #define mfhi2() _umips_dsp_mfhi(2)
1888 #define mfhi3() _umips_dsp_mfhi(3)
1889
1890 #define mtlo0(x) _umips_dsp_mtlo(x, 0)
1891 #define mtlo1(x) _umips_dsp_mtlo(x, 1)
1892 #define mtlo2(x) _umips_dsp_mtlo(x, 2)
1893 #define mtlo3(x) _umips_dsp_mtlo(x, 3)
1894
1895 #define mthi0(x) _umips_dsp_mthi(x, 0)
1896 #define mthi1(x) _umips_dsp_mthi(x, 1)
1897 #define mthi2(x) _umips_dsp_mthi(x, 2)
1898 #define mthi3(x) _umips_dsp_mthi(x, 3)
1899
1900 #else  /* !CONFIG_CPU_MICROMIPS */
1901 #define rddsp(mask)                                                     \
1902 ({                                                                      \
1903         unsigned int __res;                                             \
1904                                                                         \
1905         __asm__ __volatile__(                                           \
1906         "       .set    push                            \n"             \
1907         "       .set    noat                            \n"             \
1908         "       # rddsp $1, %x1                         \n"             \
1909         "       .word   0x7c000cb8 | (%x1 << 16)        \n"             \
1910         "       move    %0, $1                          \n"             \
1911         "       .set    pop                             \n"             \
1912         : "=r" (__res)                                                  \
1913         : "i" (mask));                                                  \
1914         __res;                                                          \
1915 })
1916
1917 #define wrdsp(val, mask)                                                \
1918 do {                                                                    \
1919         __asm__ __volatile__(                                           \
1920         "       .set    push                                    \n"     \
1921         "       .set    noat                                    \n"     \
1922         "       move    $1, %0                                  \n"     \
1923         "       # wrdsp $1, %x1                                 \n"     \
1924         "       .word   0x7c2004f8 | (%x1 << 11)                \n"     \
1925         "       .set    pop                                     \n"     \
1926         :                                                               \
1927         : "r" (val), "i" (mask));                                       \
1928 } while (0)
1929
1930 #define _dsp_mfxxx(ins)                                                 \
1931 ({                                                                      \
1932         unsigned long __treg;                                           \
1933                                                                         \
1934         __asm__ __volatile__(                                           \
1935         "       .set    push                                    \n"     \
1936         "       .set    noat                                    \n"     \
1937         "       .word   (0x00000810 | %1)                       \n"     \
1938         "       move    %0, $1                                  \n"     \
1939         "       .set    pop                                     \n"     \
1940         : "=r" (__treg)                                                 \
1941         : "i" (ins));                                                   \
1942         __treg;                                                         \
1943 })
1944
1945 #define _dsp_mtxxx(val, ins)                                            \
1946 do {                                                                    \
1947         __asm__ __volatile__(                                           \
1948         "       .set    push                                    \n"     \
1949         "       .set    noat                                    \n"     \
1950         "       move    $1, %0                                  \n"     \
1951         "       .word   (0x00200011 | %1)                       \n"     \
1952         "       .set    pop                                     \n"     \
1953         :                                                               \
1954         : "r" (val), "i" (ins));                                        \
1955 } while (0)
1956
1957 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
1958 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
1959
1960 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
1961 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
1962
1963 #define mflo0() _dsp_mflo(0)
1964 #define mflo1() _dsp_mflo(1)
1965 #define mflo2() _dsp_mflo(2)
1966 #define mflo3() _dsp_mflo(3)
1967
1968 #define mfhi0() _dsp_mfhi(0)
1969 #define mfhi1() _dsp_mfhi(1)
1970 #define mfhi2() _dsp_mfhi(2)
1971 #define mfhi3() _dsp_mfhi(3)
1972
1973 #define mtlo0(x) _dsp_mtlo(x, 0)
1974 #define mtlo1(x) _dsp_mtlo(x, 1)
1975 #define mtlo2(x) _dsp_mtlo(x, 2)
1976 #define mtlo3(x) _dsp_mtlo(x, 3)
1977
1978 #define mthi0(x) _dsp_mthi(x, 0)
1979 #define mthi1(x) _dsp_mthi(x, 1)
1980 #define mthi2(x) _dsp_mthi(x, 2)
1981 #define mthi3(x) _dsp_mthi(x, 3)
1982
1983 #endif /* CONFIG_CPU_MICROMIPS */
1984 #endif
1985
1986 /*
1987  * TLB operations.
1988  *
1989  * It is responsibility of the caller to take care of any TLB hazards.
1990  */
1991 static inline void tlb_probe(void)
1992 {
1993         __asm__ __volatile__(
1994                 ".set noreorder\n\t"
1995                 "tlbp\n\t"
1996                 ".set reorder");
1997 }
1998
1999 static inline void tlb_read(void)
2000 {
2001 #if MIPS34K_MISSED_ITLB_WAR
2002         int res = 0;
2003
2004         __asm__ __volatile__(
2005         "       .set    push                                    \n"
2006         "       .set    noreorder                               \n"
2007         "       .set    noat                                    \n"
2008         "       .set    mips32r2                                \n"
2009         "       .word   0x41610001              # dvpe $1       \n"
2010         "       move    %0, $1                                  \n"
2011         "       ehb                                             \n"
2012         "       .set    pop                                     \n"
2013         : "=r" (res));
2014
2015         instruction_hazard();
2016 #endif
2017
2018         __asm__ __volatile__(
2019                 ".set noreorder\n\t"
2020                 "tlbr\n\t"
2021                 ".set reorder");
2022
2023 #if MIPS34K_MISSED_ITLB_WAR
2024         if ((res & _ULCAST_(1)))
2025                 __asm__ __volatile__(
2026                 "       .set    push                            \n"
2027                 "       .set    noreorder                       \n"
2028                 "       .set    noat                            \n"
2029                 "       .set    mips32r2                        \n"
2030                 "       .word   0x41600021      # evpe          \n"
2031                 "       ehb                                     \n"
2032                 "       .set    pop                             \n");
2033 #endif
2034 }
2035
2036 static inline void tlb_write_indexed(void)
2037 {
2038         __asm__ __volatile__(
2039                 ".set noreorder\n\t"
2040                 "tlbwi\n\t"
2041                 ".set reorder");
2042 }
2043
2044 static inline void tlb_write_random(void)
2045 {
2046         __asm__ __volatile__(
2047                 ".set noreorder\n\t"
2048                 "tlbwr\n\t"
2049                 ".set reorder");
2050 }
2051
2052 /*
2053  * Manipulate bits in a c0 register.
2054  */
2055 #define __BUILD_SET_C0(name)                                    \
2056 static inline unsigned int                                      \
2057 set_c0_##name(unsigned int set)                                 \
2058 {                                                               \
2059         unsigned int res, new;                                  \
2060                                                                 \
2061         res = read_c0_##name();                                 \
2062         new = res | set;                                        \
2063         write_c0_##name(new);                                   \
2064                                                                 \
2065         return res;                                             \
2066 }                                                               \
2067                                                                 \
2068 static inline unsigned int                                      \
2069 clear_c0_##name(unsigned int clear)                             \
2070 {                                                               \
2071         unsigned int res, new;                                  \
2072                                                                 \
2073         res = read_c0_##name();                                 \
2074         new = res & ~clear;                                     \
2075         write_c0_##name(new);                                   \
2076                                                                 \
2077         return res;                                             \
2078 }                                                               \
2079                                                                 \
2080 static inline unsigned int                                      \
2081 change_c0_##name(unsigned int change, unsigned int val)         \
2082 {                                                               \
2083         unsigned int res, new;                                  \
2084                                                                 \
2085         res = read_c0_##name();                                 \
2086         new = res & ~change;                                    \
2087         new |= (val & change);                                  \
2088         write_c0_##name(new);                                   \
2089                                                                 \
2090         return res;                                             \
2091 }
2092
2093 __BUILD_SET_C0(status)
2094 __BUILD_SET_C0(cause)
2095 __BUILD_SET_C0(config)
2096 __BUILD_SET_C0(config5)
2097 __BUILD_SET_C0(intcontrol)
2098 __BUILD_SET_C0(intctl)
2099 __BUILD_SET_C0(srsmap)
2100 __BUILD_SET_C0(pagegrain)
2101 __BUILD_SET_C0(brcm_config_0)
2102 __BUILD_SET_C0(brcm_bus_pll)
2103 __BUILD_SET_C0(brcm_reset)
2104 __BUILD_SET_C0(brcm_cmt_intr)
2105 __BUILD_SET_C0(brcm_cmt_ctrl)
2106 __BUILD_SET_C0(brcm_config)
2107 __BUILD_SET_C0(brcm_mode)
2108
2109 /*
2110  * Return low 10 bits of ebase.
2111  * Note that under KVM (MIPSVZ) this returns vcpu id.
2112  */
2113 static inline unsigned int get_ebase_cpunum(void)
2114 {
2115         return read_c0_ebase() & MIPS_EBASE_CPUNUM;
2116 }
2117
2118 #endif /* !__ASSEMBLY__ */
2119
2120 #endif /* _ASM_MIPSREGS_H */