arch/mips/include/asm/mipsregs.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
   7  * Copyright (C) 2000 Silicon Graphics, Inc.
   8  * Modified for further R[236]000 support by Paul M. Antoine, 1996.
   9  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  10  * Copyright (C) 2000, 07 MIPS Technologies, Inc.
  11  * Copyright (C) 2003, 2004  Maciej W. Rozycki
  12  */
  13 #ifndef _ASM_MIPSREGS_H
  14 #define _ASM_MIPSREGS_H
  15
  16 #include <linux/linkage.h>
  17 #include <linux/types.h>
  18 #include <asm/hazards.h>
  19 #include <asm/war.h>
  20
  21 /*
  22  * The following macros are especially useful for __asm__
  23  * inline assembler.
  24  */
  25 #ifndef __STR
  26 #define __STR(x) #x
  27 #endif
  28 #ifndef STR
  29 #define STR(x) __STR(x)
  30 #endif
  31
  32 /*
  33  *  Configure language
  34  */
  35 #ifdef __ASSEMBLY__
  36 #define _ULCAST_
  37 #else
  38 #define _ULCAST_ (unsigned long)
  39 #endif
  40
  41 /*
  42  * Coprocessor 0 register names
  43  */
  44 #define CP0_INDEX $0
  45 #define CP0_RANDOM $1
  46 #define CP0_ENTRYLO0 $2
  47 #define CP0_ENTRYLO1 $3
  48 #define CP0_CONF $3
  49 #define CP0_CONTEXT $4
  50 #define CP0_PAGEMASK $5
  51 #define CP0_WIRED $6
  52 #define CP0_INFO $7
  53 #define CP0_HWRENA $7, 0
  54 #define CP0_BADVADDR $8
  55 #define CP0_BADINSTR $8, 1
  56 #define CP0_COUNT $9
  57 #define CP0_ENTRYHI $10
  58 #define CP0_GUESTCTL1 $10, 4
  59 #define CP0_GUESTCTL2 $10, 5
  60 #define CP0_GUESTCTL3 $10, 6
  61 #define CP0_COMPARE $11
  62 #define CP0_GUESTCTL0EXT $11, 4
  63 #define CP0_STATUS $12
  64 #define CP0_GUESTCTL0 $12, 6
  65 #define CP0_GTOFFSET $12, 7
  66 #define CP0_CAUSE $13
  67 #define CP0_EPC $14
  68 #define CP0_PRID $15
  69 #define CP0_EBASE $15, 1
  70 #define CP0_CMGCRBASE $15, 3
  71 #define CP0_CONFIG $16
  72 #define CP0_CONFIG3 $16, 3
  73 #define CP0_CONFIG5 $16, 5
  74 #define CP0_LLADDR $17
  75 #define CP0_WATCHLO $18
  76 #define CP0_WATCHHI $19
  77 #define CP0_XCONTEXT $20
  78 #define CP0_FRAMEMASK $21
  79 #define CP0_DIAGNOSTIC $22
  80 #define CP0_DEBUG $23
  81 #define CP0_DEPC $24
  82 #define CP0_PERFORMANCE $25
  83 #define CP0_ECC $26
  84 #define CP0_CACHEERR $27
  85 #define CP0_TAGLO $28
  86 #define CP0_TAGHI $29
  87 #define CP0_ERROREPC $30
  88 #define CP0_DESAVE $31
  89
  90 /*
  91  * R4640/R4650 cp0 register names.  These registers are listed
  92  * here only for completeness; without MMU these CPUs are not useable
  93  * by Linux.  A future ELKS port might take make Linux run on them
  94  * though ...
  95  */
  96 #define CP0_IBASE $0
  97 #define CP0_IBOUND $1
  98 #define CP0_DBASE $2
  99 #define CP0_DBOUND $3
 100 #define CP0_CALG $17
 101 #define CP0_IWATCH $18
 102 #define CP0_DWATCH $19
 103
 104 /*
 105  * Coprocessor 0 Set 1 register names
 106  */
 107 #define CP0_S1_DERRADDR0  $26
 108 #define CP0_S1_DERRADDR1  $27
 109 #define CP0_S1_INTCONTROL $20
 110
 111 /*
 112  * Coprocessor 0 Set 2 register names
 113  */
 114 #define CP0_S2_SRSCTL     $12   /* MIPSR2 */
 115
 116 /*
 117  * Coprocessor 0 Set 3 register names
 118  */
 119 #define CP0_S3_SRSMAP     $12   /* MIPSR2 */
 120
 121 /*
 122  *  TX39 Series
 123  */
 124 #define CP0_TX39_CACHE  $7
 125
 126
 127 /* Generic EntryLo bit definitions */
 128 #define ENTRYLO_G               (_ULCAST_(1) << 0)
 129 #define ENTRYLO_V               (_ULCAST_(1) << 1)
 130 #define ENTRYLO_D               (_ULCAST_(1) << 2)
 131 #define ENTRYLO_C_SHIFT         3
 132 #define ENTRYLO_C               (_ULCAST_(7) << ENTRYLO_C_SHIFT)
 133
 134 /* R3000 EntryLo bit definitions */
 135 #define R3K_ENTRYLO_G           (_ULCAST_(1) << 8)
 136 #define R3K_ENTRYLO_V           (_ULCAST_(1) << 9)
 137 #define R3K_ENTRYLO_D           (_ULCAST_(1) << 10)
 138 #define R3K_ENTRYLO_N           (_ULCAST_(1) << 11)
 139
 140 /* MIPS32/64 EntryLo bit definitions */
 141 #define MIPS_ENTRYLO_PFN_SHIFT  6
 142 #define MIPS_ENTRYLO_XI         (_ULCAST_(1) << (BITS_PER_LONG - 2))
 143 #define MIPS_ENTRYLO_RI         (_ULCAST_(1) << (BITS_PER_LONG - 1))
 144
 145 /*
 146  * Values for PageMask register
 147  */
 148 #ifdef CONFIG_CPU_VR41XX
 149
 150 /* Why doesn't stupidity hurt ... */
 151
 152 #define PM_1K           0x00000000
 153 #define PM_4K           0x00001800
 154 #define PM_16K          0x00007800
 155 #define PM_64K          0x0001f800
 156 #define PM_256K         0x0007f800
 157
 158 #else
 159
 160 #define PM_4K           0x00000000
 161 #define PM_8K           0x00002000
 162 #define PM_16K          0x00006000
 163 #define PM_32K          0x0000e000
 164 #define PM_64K          0x0001e000
 165 #define PM_128K         0x0003e000
 166 #define PM_256K         0x0007e000
 167 #define PM_512K         0x000fe000
 168 #define PM_1M           0x001fe000
 169 #define PM_2M           0x003fe000
 170 #define PM_4M           0x007fe000
 171 #define PM_8M           0x00ffe000
 172 #define PM_16M          0x01ffe000
 173 #define PM_32M          0x03ffe000
 174 #define PM_64M          0x07ffe000
 175 #define PM_256M         0x1fffe000
 176 #define PM_1G           0x7fffe000
 177
 178 #endif
 179
 180 /*
 181  * Default page size for a given kernel configuration
 182  */
 183 #ifdef CONFIG_PAGE_SIZE_4KB
 184 #define PM_DEFAULT_MASK PM_4K
 185 #elif defined(CONFIG_PAGE_SIZE_8KB)
 186 #define PM_DEFAULT_MASK PM_8K
 187 #elif defined(CONFIG_PAGE_SIZE_16KB)
 188 #define PM_DEFAULT_MASK PM_16K
 189 #elif defined(CONFIG_PAGE_SIZE_32KB)
 190 #define PM_DEFAULT_MASK PM_32K
 191 #elif defined(CONFIG_PAGE_SIZE_64KB)
 192 #define PM_DEFAULT_MASK PM_64K
 193 #else
 194 #error Bad page size configuration!
 195 #endif
 196
 197 /*
 198  * Default huge tlb size for a given kernel configuration
 199  */
 200 #ifdef CONFIG_PAGE_SIZE_4KB
 201 #define PM_HUGE_MASK    PM_1M
 202 #elif defined(CONFIG_PAGE_SIZE_8KB)
 203 #define PM_HUGE_MASK    PM_4M
 204 #elif defined(CONFIG_PAGE_SIZE_16KB)
 205 #define PM_HUGE_MASK    PM_16M
 206 #elif defined(CONFIG_PAGE_SIZE_32KB)
 207 #define PM_HUGE_MASK    PM_64M
 208 #elif defined(CONFIG_PAGE_SIZE_64KB)
 209 #define PM_HUGE_MASK    PM_256M
 210 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
 211 #error Bad page size configuration for hugetlbfs!
 212 #endif
 213
 214 /*
 215  * Values used for computation of new tlb entries
 216  */
 217 #define PL_4K           12
 218 #define PL_16K          14
 219 #define PL_64K          16
 220 #define PL_256K         18
 221 #define PL_1M           20
 222 #define PL_4M           22
 223 #define PL_16M          24
 224 #define PL_64M          26
 225 #define PL_256M         28
 226
 227 /*
 228  * PageGrain bits
 229  */
 230 #define PG_RIE          (_ULCAST_(1) <<  31)
 231 #define PG_XIE          (_ULCAST_(1) <<  30)
 232 #define PG_ELPA         (_ULCAST_(1) <<  29)
 233 #define PG_ESP          (_ULCAST_(1) <<  28)
 234 #define PG_IEC          (_ULCAST_(1) <<  27)
 235
 236 /* MIPS32/64 EntryHI bit definitions */
 237 #define MIPS_ENTRYHI_EHINV      (_ULCAST_(1) << 10)
 238 #define MIPS_ENTRYHI_ASIDX      (_ULCAST_(0x3) << 8)
 239 #define MIPS_ENTRYHI_ASID       (_ULCAST_(0xff) << 0)
 240
 241 /*
 242  * R4x00 interrupt enable / cause bits
 243  */
 244 #define IE_SW0          (_ULCAST_(1) <<  8)
 245 #define IE_SW1          (_ULCAST_(1) <<  9)
 246 #define IE_IRQ0         (_ULCAST_(1) << 10)
 247 #define IE_IRQ1         (_ULCAST_(1) << 11)
 248 #define IE_IRQ2         (_ULCAST_(1) << 12)
 249 #define IE_IRQ3         (_ULCAST_(1) << 13)
 250 #define IE_IRQ4         (_ULCAST_(1) << 14)
 251 #define IE_IRQ5         (_ULCAST_(1) << 15)
 252
 253 /*
 254  * R4x00 interrupt cause bits
 255  */
 256 #define C_SW0           (_ULCAST_(1) <<  8)
 257 #define C_SW1           (_ULCAST_(1) <<  9)
 258 #define C_IRQ0          (_ULCAST_(1) << 10)
 259 #define C_IRQ1          (_ULCAST_(1) << 11)
 260 #define C_IRQ2          (_ULCAST_(1) << 12)
 261 #define C_IRQ3          (_ULCAST_(1) << 13)
 262 #define C_IRQ4          (_ULCAST_(1) << 14)
 263 #define C_IRQ5          (_ULCAST_(1) << 15)
 264
 265 /*
 266  * Bitfields in the R4xx0 cp0 status register
 267  */
 268 #define ST0_IE                  0x00000001
 269 #define ST0_EXL                 0x00000002
 270 #define ST0_ERL                 0x00000004
 271 #define ST0_KSU                 0x00000018
 272 #  define KSU_USER              0x00000010
 273 #  define KSU_SUPERVISOR        0x00000008
 274 #  define KSU_KERNEL            0x00000000
 275 #define ST0_UX                  0x00000020
 276 #define ST0_SX                  0x00000040
 277 #define ST0_KX                  0x00000080
 278 #define ST0_DE                  0x00010000
 279 #define ST0_CE                  0x00020000
 280
 281 /*
 282  * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
 283  * cacheops in userspace.  This bit exists only on RM7000 and RM9000
 284  * processors.
 285  */
 286 #define ST0_CO                  0x08000000
 287
 288 /*
 289  * Bitfields in the R[23]000 cp0 status register.
 290  */
 291 #define ST0_IEC                 0x00000001
 292 #define ST0_KUC                 0x00000002
 293 #define ST0_IEP                 0x00000004
 294 #define ST0_KUP                 0x00000008
 295 #define ST0_IEO                 0x00000010
 296 #define ST0_KUO                 0x00000020
 297 /* bits 6 & 7 are reserved on R[23]000 */
 298 #define ST0_ISC                 0x00010000
 299 #define ST0_SWC                 0x00020000
 300 #define ST0_CM                  0x00080000
 301
 302 /*
 303  * Bits specific to the R4640/R4650
 304  */
 305 #define ST0_UM                  (_ULCAST_(1) <<  4)
 306 #define ST0_IL                  (_ULCAST_(1) << 23)
 307 #define ST0_DL                  (_ULCAST_(1) << 24)
 308
 309 /*
 310  * Enable the MIPS MDMX and DSP ASEs
 311  */
 312 #define ST0_MX                  0x01000000
 313
 314 /*
 315  * Status register bits available in all MIPS CPUs.
 316  */
 317 #define ST0_IM                  0x0000ff00
 318 #define  STATUSB_IP0            8
 319 #define  STATUSF_IP0            (_ULCAST_(1) <<  8)
 320 #define  STATUSB_IP1            9
 321 #define  STATUSF_IP1            (_ULCAST_(1) <<  9)
 322 #define  STATUSB_IP2            10
 323 #define  STATUSF_IP2            (_ULCAST_(1) << 10)
 324 #define  STATUSB_IP3            11
 325 #define  STATUSF_IP3            (_ULCAST_(1) << 11)
 326 #define  STATUSB_IP4            12
 327 #define  STATUSF_IP4            (_ULCAST_(1) << 12)
 328 #define  STATUSB_IP5            13
 329 #define  STATUSF_IP5            (_ULCAST_(1) << 13)
 330 #define  STATUSB_IP6            14
 331 #define  STATUSF_IP6            (_ULCAST_(1) << 14)
 332 #define  STATUSB_IP7            15
 333 #define  STATUSF_IP7            (_ULCAST_(1) << 15)
 334 #define  STATUSB_IP8            0
 335 #define  STATUSF_IP8            (_ULCAST_(1) <<  0)
 336 #define  STATUSB_IP9            1
 337 #define  STATUSF_IP9            (_ULCAST_(1) <<  1)
 338 #define  STATUSB_IP10           2
 339 #define  STATUSF_IP10           (_ULCAST_(1) <<  2)
 340 #define  STATUSB_IP11           3
 341 #define  STATUSF_IP11           (_ULCAST_(1) <<  3)
 342 #define  STATUSB_IP12           4
 343 #define  STATUSF_IP12           (_ULCAST_(1) <<  4)
 344 #define  STATUSB_IP13           5
 345 #define  STATUSF_IP13           (_ULCAST_(1) <<  5)
 346 #define  STATUSB_IP14           6
 347 #define  STATUSF_IP14           (_ULCAST_(1) <<  6)
 348 #define  STATUSB_IP15           7
 349 #define  STATUSF_IP15           (_ULCAST_(1) <<  7)
 350 #define ST0_CH                  0x00040000
 351 #define ST0_NMI                 0x00080000
 352 #define ST0_SR                  0x00100000
 353 #define ST0_TS                  0x00200000
 354 #define ST0_BEV                 0x00400000
 355 #define ST0_RE                  0x02000000
 356 #define ST0_FR                  0x04000000
 357 #define ST0_CU                  0xf0000000
 358 #define ST0_CU0                 0x10000000
 359 #define ST0_CU1                 0x20000000
 360 #define ST0_CU2                 0x40000000
 361 #define ST0_CU3                 0x80000000
 362 #define ST0_XX                  0x80000000      /* MIPS IV naming */
 363
 364 /*
 365  * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
 366  */
 367 #define INTCTLB_IPFDC           23
 368 #define INTCTLF_IPFDC           (_ULCAST_(7) << INTCTLB_IPFDC)
 369 #define INTCTLB_IPPCI           26
 370 #define INTCTLF_IPPCI           (_ULCAST_(7) << INTCTLB_IPPCI)
 371 #define INTCTLB_IPTI            29
 372 #define INTCTLF_IPTI            (_ULCAST_(7) << INTCTLB_IPTI)
 373
 374 /*
 375  * Bitfields and bit numbers in the coprocessor 0 cause register.
 376  *
 377  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
 378  */
 379 #define CAUSEB_EXCCODE          2
 380 #define CAUSEF_EXCCODE          (_ULCAST_(31)  <<  2)
 381 #define CAUSEB_IP               8
 382 #define CAUSEF_IP               (_ULCAST_(255) <<  8)
 383 #define  CAUSEB_IP0             8
 384 #define  CAUSEF_IP0             (_ULCAST_(1)   <<  8)
 385 #define  CAUSEB_IP1             9
 386 #define  CAUSEF_IP1             (_ULCAST_(1)   <<  9)
 387 #define  CAUSEB_IP2             10
 388 #define  CAUSEF_IP2             (_ULCAST_(1)   << 10)
 389 #define  CAUSEB_IP3             11
 390 #define  CAUSEF_IP3             (_ULCAST_(1)   << 11)
 391 #define  CAUSEB_IP4             12
 392 #define  CAUSEF_IP4             (_ULCAST_(1)   << 12)
 393 #define  CAUSEB_IP5             13
 394 #define  CAUSEF_IP5             (_ULCAST_(1)   << 13)
 395 #define  CAUSEB_IP6             14
 396 #define  CAUSEF_IP6             (_ULCAST_(1)   << 14)
 397 #define  CAUSEB_IP7             15
 398 #define  CAUSEF_IP7             (_ULCAST_(1)   << 15)
 399 #define CAUSEB_FDCI             21
 400 #define CAUSEF_FDCI             (_ULCAST_(1)   << 21)
 401 #define CAUSEB_WP               22
 402 #define CAUSEF_WP               (_ULCAST_(1)   << 22)
 403 #define CAUSEB_IV               23
 404 #define CAUSEF_IV               (_ULCAST_(1)   << 23)
 405 #define CAUSEB_PCI              26
 406 #define CAUSEF_PCI              (_ULCAST_(1)   << 26)
 407 #define CAUSEB_DC               27
 408 #define CAUSEF_DC               (_ULCAST_(1)   << 27)
 409 #define CAUSEB_CE               28
 410 #define CAUSEF_CE               (_ULCAST_(3)   << 28)
 411 #define CAUSEB_TI               30
 412 #define CAUSEF_TI               (_ULCAST_(1)   << 30)
 413 #define CAUSEB_BD               31
 414 #define CAUSEF_BD               (_ULCAST_(1)   << 31)
 415
 416 /*
 417  * Cause.ExcCode trap codes.
 418  */
 419 #define EXCCODE_INT             0       /* Interrupt pending */
 420 #define EXCCODE_MOD             1       /* TLB modified fault */
 421 #define EXCCODE_TLBL            2       /* TLB miss on load or ifetch */
 422 #define EXCCODE_TLBS            3       /* TLB miss on a store */
 423 #define EXCCODE_ADEL            4       /* Address error on a load or ifetch */
 424 #define EXCCODE_ADES            5       /* Address error on a store */
 425 #define EXCCODE_IBE             6       /* Bus error on an ifetch */
 426 #define EXCCODE_DBE             7       /* Bus error on a load or store */
 427 #define EXCCODE_SYS             8       /* System call */
 428 #define EXCCODE_BP              9       /* Breakpoint */
 429 #define EXCCODE_RI              10      /* Reserved instruction exception */
 430 #define EXCCODE_CPU             11      /* Coprocessor unusable */
 431 #define EXCCODE_OV              12      /* Arithmetic overflow */
 432 #define EXCCODE_TR              13      /* Trap instruction */
 433 #define EXCCODE_MSAFPE          14      /* MSA floating point exception */
 434 #define EXCCODE_FPE             15      /* Floating point exception */
 435 #define EXCCODE_TLBRI           19      /* TLB Read-Inhibit exception */
 436 #define EXCCODE_TLBXI           20      /* TLB Execution-Inhibit exception */
 437 #define EXCCODE_MSADIS          21      /* MSA disabled exception */
 438 #define EXCCODE_MDMX            22      /* MDMX unusable exception */
 439 #define EXCCODE_WATCH           23      /* Watch address reference */
 440 #define EXCCODE_MCHECK          24      /* Machine check */
 441 #define EXCCODE_THREAD          25      /* Thread exceptions (MT) */
 442 #define EXCCODE_DSPDIS          26      /* DSP disabled exception */
 443 #define EXCCODE_GE              27      /* Virtualized guest exception (VZ) */
 444
 445 /* Implementation specific trap codes used by MIPS cores */
 446 #define MIPS_EXCCODE_TLBPAR     16      /* TLB parity error exception */
 447
 448 /*
 449  * Bits in the coprocessor 0 config register.
 450  */
 451 /* Generic bits.  */
 452 #define CONF_CM_CACHABLE_NO_WA          0
 453 #define CONF_CM_CACHABLE_WA             1
 454 #define CONF_CM_UNCACHED                2
 455 #define CONF_CM_CACHABLE_NONCOHERENT    3
 456 #define CONF_CM_CACHABLE_CE             4
 457 #define CONF_CM_CACHABLE_COW            5
 458 #define CONF_CM_CACHABLE_CUW            6
 459 #define CONF_CM_CACHABLE_ACCELERATED    7
 460 #define CONF_CM_CMASK                   7
 461 #define CONF_BE                 (_ULCAST_(1) << 15)
 462
 463 /* Bits common to various processors.  */
 464 #define CONF_CU                 (_ULCAST_(1) <<  3)
 465 #define CONF_DB                 (_ULCAST_(1) <<  4)
 466 #define CONF_IB                 (_ULCAST_(1) <<  5)
 467 #define CONF_DC                 (_ULCAST_(7) <<  6)
 468 #define CONF_IC                 (_ULCAST_(7) <<  9)
 469 #define CONF_EB                 (_ULCAST_(1) << 13)
 470 #define CONF_EM                 (_ULCAST_(1) << 14)
 471 #define CONF_SM                 (_ULCAST_(1) << 16)
 472 #define CONF_SC                 (_ULCAST_(1) << 17)
 473 #define CONF_EW                 (_ULCAST_(3) << 18)
 474 #define CONF_EP                 (_ULCAST_(15)<< 24)
 475 #define CONF_EC                 (_ULCAST_(7) << 28)
 476 #define CONF_CM                 (_ULCAST_(1) << 31)
 477
 478 /* Bits specific to the R4xx0.  */
 479 #define R4K_CONF_SW             (_ULCAST_(1) << 20)
 480 #define R4K_CONF_SS             (_ULCAST_(1) << 21)
 481 #define R4K_CONF_SB             (_ULCAST_(3) << 22)
 482
 483 /* Bits specific to the R5000.  */
 484 #define R5K_CONF_SE             (_ULCAST_(1) << 12)
 485 #define R5K_CONF_SS             (_ULCAST_(3) << 20)
 486
 487 /* Bits specific to the RM7000.  */
 488 #define RM7K_CONF_SE            (_ULCAST_(1) <<  3)
 489 #define RM7K_CONF_TE            (_ULCAST_(1) << 12)
 490 #define RM7K_CONF_CLK           (_ULCAST_(1) << 16)
 491 #define RM7K_CONF_TC            (_ULCAST_(1) << 17)
 492 #define RM7K_CONF_SI            (_ULCAST_(3) << 20)
 493 #define RM7K_CONF_SC            (_ULCAST_(1) << 31)
 494
 495 /* Bits specific to the R10000.  */
 496 #define R10K_CONF_DN            (_ULCAST_(3) <<  3)
 497 #define R10K_CONF_CT            (_ULCAST_(1) <<  5)
 498 #define R10K_CONF_PE            (_ULCAST_(1) <<  6)
 499 #define R10K_CONF_PM            (_ULCAST_(3) <<  7)
 500 #define R10K_CONF_EC            (_ULCAST_(15)<<  9)
 501 #define R10K_CONF_SB            (_ULCAST_(1) << 13)
 502 #define R10K_CONF_SK            (_ULCAST_(1) << 14)
 503 #define R10K_CONF_SS            (_ULCAST_(7) << 16)
 504 #define R10K_CONF_SC            (_ULCAST_(7) << 19)
 505 #define R10K_CONF_DC            (_ULCAST_(7) << 26)
 506 #define R10K_CONF_IC            (_ULCAST_(7) << 29)
 507
 508 /* Bits specific to the VR41xx.  */
 509 #define VR41_CONF_CS            (_ULCAST_(1) << 12)
 510 #define VR41_CONF_P4K           (_ULCAST_(1) << 13)
 511 #define VR41_CONF_BP            (_ULCAST_(1) << 16)
 512 #define VR41_CONF_M16           (_ULCAST_(1) << 20)
 513 #define VR41_CONF_AD            (_ULCAST_(1) << 23)
 514
 515 /* Bits specific to the R30xx.  */
 516 #define R30XX_CONF_FDM          (_ULCAST_(1) << 19)
 517 #define R30XX_CONF_REV          (_ULCAST_(1) << 22)
 518 #define R30XX_CONF_AC           (_ULCAST_(1) << 23)
 519 #define R30XX_CONF_RF           (_ULCAST_(1) << 24)
 520 #define R30XX_CONF_HALT         (_ULCAST_(1) << 25)
 521 #define R30XX_CONF_FPINT        (_ULCAST_(7) << 26)
 522 #define R30XX_CONF_DBR          (_ULCAST_(1) << 29)
 523 #define R30XX_CONF_SB           (_ULCAST_(1) << 30)
 524 #define R30XX_CONF_LOCK         (_ULCAST_(1) << 31)
 525
 526 /* Bits specific to the TX49.  */
 527 #define TX49_CONF_DC            (_ULCAST_(1) << 16)
 528 #define TX49_CONF_IC            (_ULCAST_(1) << 17)  /* conflict with CONF_SC */
 529 #define TX49_CONF_HALT          (_ULCAST_(1) << 18)
 530 #define TX49_CONF_CWFON         (_ULCAST_(1) << 27)
 531
 532 /* Bits specific to the MIPS32/64 PRA.  */
 533 #define MIPS_CONF_MT            (_ULCAST_(7) <<  7)
 534 #define MIPS_CONF_MT_TLB        (_ULCAST_(1) <<  7)
 535 #define MIPS_CONF_MT_FTLB       (_ULCAST_(4) <<  7)
 536 #define MIPS_CONF_AR            (_ULCAST_(7) << 10)
 537 #define MIPS_CONF_AT            (_ULCAST_(3) << 13)
 538 #define MIPS_CONF_M             (_ULCAST_(1) << 31)
 539
 540 /*
 541  * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
 542  */
 543 #define MIPS_CONF1_FP           (_ULCAST_(1) <<  0)
 544 #define MIPS_CONF1_EP           (_ULCAST_(1) <<  1)
 545 #define MIPS_CONF1_CA           (_ULCAST_(1) <<  2)
 546 #define MIPS_CONF1_WR           (_ULCAST_(1) <<  3)
 547 #define MIPS_CONF1_PC           (_ULCAST_(1) <<  4)
 548 #define MIPS_CONF1_MD           (_ULCAST_(1) <<  5)
 549 #define MIPS_CONF1_C2           (_ULCAST_(1) <<  6)
 550 #define MIPS_CONF1_DA_SHF       7
 551 #define MIPS_CONF1_DA_SZ        3
 552 #define MIPS_CONF1_DA           (_ULCAST_(7) <<  7)
 553 #define MIPS_CONF1_DL_SHF       10
 554 #define MIPS_CONF1_DL_SZ        3
 555 #define MIPS_CONF1_DL           (_ULCAST_(7) << 10)
 556 #define MIPS_CONF1_DS_SHF       13
 557 #define MIPS_CONF1_DS_SZ        3
 558 #define MIPS_CONF1_DS           (_ULCAST_(7) << 13)
 559 #define MIPS_CONF1_IA_SHF       16
 560 #define MIPS_CONF1_IA_SZ        3
 561 #define MIPS_CONF1_IA           (_ULCAST_(7) << 16)
 562 #define MIPS_CONF1_IL_SHF       19
 563 #define MIPS_CONF1_IL_SZ        3
 564 #define MIPS_CONF1_IL           (_ULCAST_(7) << 19)
 565 #define MIPS_CONF1_IS_SHF       22
 566 #define MIPS_CONF1_IS_SZ        3
 567 #define MIPS_CONF1_IS           (_ULCAST_(7) << 22)
 568 #define MIPS_CONF1_TLBS_SHIFT   (25)
 569 #define MIPS_CONF1_TLBS_SIZE    (6)
 570 #define MIPS_CONF1_TLBS         (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
 571
 572 #define MIPS_CONF2_SA           (_ULCAST_(15)<<  0)
 573 #define MIPS_CONF2_SL           (_ULCAST_(15)<<  4)
 574 #define MIPS_CONF2_SS           (_ULCAST_(15)<<  8)
 575 #define MIPS_CONF2_SU           (_ULCAST_(15)<< 12)
 576 #define MIPS_CONF2_TA           (_ULCAST_(15)<< 16)
 577 #define MIPS_CONF2_TL           (_ULCAST_(15)<< 20)
 578 #define MIPS_CONF2_TS           (_ULCAST_(15)<< 24)
 579 #define MIPS_CONF2_TU           (_ULCAST_(7) << 28)
 580
 581 #define MIPS_CONF3_TL           (_ULCAST_(1) <<  0)
 582 #define MIPS_CONF3_SM           (_ULCAST_(1) <<  1)
 583 #define MIPS_CONF3_MT           (_ULCAST_(1) <<  2)
 584 #define MIPS_CONF3_CDMM         (_ULCAST_(1) <<  3)
 585 #define MIPS_CONF3_SP           (_ULCAST_(1) <<  4)
 586 #define MIPS_CONF3_VINT         (_ULCAST_(1) <<  5)
 587 #define MIPS_CONF3_VEIC         (_ULCAST_(1) <<  6)
 588 #define MIPS_CONF3_LPA          (_ULCAST_(1) <<  7)
 589 #define MIPS_CONF3_ITL          (_ULCAST_(1) <<  8)
 590 #define MIPS_CONF3_CTXTC        (_ULCAST_(1) <<  9)
 591 #define MIPS_CONF3_DSP          (_ULCAST_(1) << 10)
 592 #define MIPS_CONF3_DSP2P        (_ULCAST_(1) << 11)
 593 #define MIPS_CONF3_RXI          (_ULCAST_(1) << 12)
 594 #define MIPS_CONF3_ULRI         (_ULCAST_(1) << 13)
 595 #define MIPS_CONF3_ISA          (_ULCAST_(3) << 14)
 596 #define MIPS_CONF3_ISA_OE       (_ULCAST_(1) << 16)
 597 #define MIPS_CONF3_MCU          (_ULCAST_(1) << 17)
 598 #define MIPS_CONF3_MMAR         (_ULCAST_(7) << 18)
 599 #define MIPS_CONF3_IPLW         (_ULCAST_(3) << 21)
 600 #define MIPS_CONF3_VZ           (_ULCAST_(1) << 23)
 601 #define MIPS_CONF3_PW           (_ULCAST_(1) << 24)
 602 #define MIPS_CONF3_SC           (_ULCAST_(1) << 25)
 603 #define MIPS_CONF3_BI           (_ULCAST_(1) << 26)
 604 #define MIPS_CONF3_BP           (_ULCAST_(1) << 27)
 605 #define MIPS_CONF3_MSA          (_ULCAST_(1) << 28)
 606 #define MIPS_CONF3_CMGCR        (_ULCAST_(1) << 29)
 607 #define MIPS_CONF3_BPG          (_ULCAST_(1) << 30)
 608
 609 #define MIPS_CONF4_MMUSIZEEXT_SHIFT     (0)
 610 #define MIPS_CONF4_MMUSIZEEXT   (_ULCAST_(255) << 0)
 611 #define MIPS_CONF4_FTLBSETS_SHIFT       (0)
 612 #define MIPS_CONF4_FTLBSETS     (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
 613 #define MIPS_CONF4_FTLBWAYS_SHIFT       (4)
 614 #define MIPS_CONF4_FTLBWAYS     (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
 615 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT   (8)
 616 /* bits 10:8 in FTLB-only configurations */
 617 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 618 /* bits 12:8 in VTLB-FTLB only configurations */
 619 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 620 #define MIPS_CONF4_MMUEXTDEF    (_ULCAST_(3) << 14)
 621 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
 622 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT        (_ULCAST_(2) << 14)
 623 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT        (_ULCAST_(3) << 14)
 624 #define MIPS_CONF4_KSCREXIST_SHIFT      (16)
 625 #define MIPS_CONF4_KSCREXIST    (_ULCAST_(255) << MIPS_CONF4_KSCREXIST_SHIFT)
 626 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT    (24)
 627 #define MIPS_CONF4_VTLBSIZEEXT  (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
 628 #define MIPS_CONF4_AE           (_ULCAST_(1) << 28)
 629 #define MIPS_CONF4_IE           (_ULCAST_(3) << 29)
 630 #define MIPS_CONF4_TLBINV       (_ULCAST_(2) << 29)
 631
 632 #define MIPS_CONF5_NF           (_ULCAST_(1) << 0)
 633 #define MIPS_CONF5_UFR          (_ULCAST_(1) << 2)
 634 #define MIPS_CONF5_MRP          (_ULCAST_(1) << 3)
 635 #define MIPS_CONF5_LLB          (_ULCAST_(1) << 4)
 636 #define MIPS_CONF5_MVH          (_ULCAST_(1) << 5)
 637 #define MIPS_CONF5_VP           (_ULCAST_(1) << 7)
 638 #define MIPS_CONF5_FRE          (_ULCAST_(1) << 8)
 639 #define MIPS_CONF5_UFE          (_ULCAST_(1) << 9)
 640 #define MIPS_CONF5_MSAEN        (_ULCAST_(1) << 27)
 641 #define MIPS_CONF5_EVA          (_ULCAST_(1) << 28)
 642 #define MIPS_CONF5_CV           (_ULCAST_(1) << 29)
 643 #define MIPS_CONF5_K            (_ULCAST_(1) << 30)
 644
 645 #define MIPS_CONF6_SYND         (_ULCAST_(1) << 13)
 646 /* proAptiv FTLB on/off bit */
 647 #define MIPS_CONF6_FTLBEN       (_ULCAST_(1) << 15)
 648 /* Loongson-3 FTLB on/off bit */
 649 #define MIPS_CONF6_FTLBDIS      (_ULCAST_(1) << 22)
 650 /* FTLB probability bits */
 651 #define MIPS_CONF6_FTLBP_SHIFT  (16)
 652
 653 #define MIPS_CONF7_WII          (_ULCAST_(1) << 31)
 654
 655 #define MIPS_CONF7_RPS          (_ULCAST_(1) << 2)
 656
 657 #define MIPS_CONF7_IAR          (_ULCAST_(1) << 10)
 658 #define MIPS_CONF7_AR           (_ULCAST_(1) << 16)
 659 /* FTLB probability bits for R6 */
 660 #define MIPS_CONF7_FTLBP_SHIFT  (18)
 661
 662 /* WatchLo* register definitions */
 663 #define MIPS_WATCHLO_IRW        (_ULCAST_(0x7) << 0)
 664
 665 /* WatchHi* register definitions */
 666 #define MIPS_WATCHHI_M          (_ULCAST_(1) << 31)
 667 #define MIPS_WATCHHI_G          (_ULCAST_(1) << 30)
 668 #define MIPS_WATCHHI_WM         (_ULCAST_(0x3) << 28)
 669 #define MIPS_WATCHHI_WM_R_RVA   (_ULCAST_(0) << 28)
 670 #define MIPS_WATCHHI_WM_R_GPA   (_ULCAST_(1) << 28)
 671 #define MIPS_WATCHHI_WM_G_GVA   (_ULCAST_(2) << 28)
 672 #define MIPS_WATCHHI_EAS        (_ULCAST_(0x3) << 24)
 673 #define MIPS_WATCHHI_ASID       (_ULCAST_(0xff) << 16)
 674 #define MIPS_WATCHHI_MASK       (_ULCAST_(0x1ff) << 3)
 675 #define MIPS_WATCHHI_I          (_ULCAST_(1) << 2)
 676 #define MIPS_WATCHHI_R          (_ULCAST_(1) << 1)
 677 #define MIPS_WATCHHI_W          (_ULCAST_(1) << 0)
 678 #define MIPS_WATCHHI_IRW        (_ULCAST_(0x7) << 0)
 679
 680 /* MAAR bit definitions */
 681 #define MIPS_MAAR_ADDR          ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
 682 #define MIPS_MAAR_ADDR_SHIFT    12
 683 #define MIPS_MAAR_S             (_ULCAST_(1) << 1)
 684 #define MIPS_MAAR_V             (_ULCAST_(1) << 0)
 685
 686 /* EBase bit definitions */
 687 #define MIPS_EBASE_CPUNUM_SHIFT 0
 688 #define MIPS_EBASE_CPUNUM       (_ULCAST_(0x3ff) << 0)
 689 #define MIPS_EBASE_WG_SHIFT     11
 690 #define MIPS_EBASE_WG           (_ULCAST_(1) << 11)
 691 #define MIPS_EBASE_BASE_SHIFT   12
 692 #define MIPS_EBASE_BASE         (~_ULCAST_((1 << MIPS_EBASE_BASE_SHIFT) - 1))
 693
 694 /* CMGCRBase bit definitions */
 695 #define MIPS_CMGCRB_BASE        11
 696 #define MIPS_CMGCRF_BASE        (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
 697
 698 /*
 699  * Bits in the MIPS32 Memory Segmentation registers.
 700  */
 701 #define MIPS_SEGCFG_PA_SHIFT    9
 702 #define MIPS_SEGCFG_PA          (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
 703 #define MIPS_SEGCFG_AM_SHIFT    4
 704 #define MIPS_SEGCFG_AM          (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
 705 #define MIPS_SEGCFG_EU_SHIFT    3
 706 #define MIPS_SEGCFG_EU          (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
 707 #define MIPS_SEGCFG_C_SHIFT     0
 708 #define MIPS_SEGCFG_C           (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
 709
 710 #define MIPS_SEGCFG_UUSK        _ULCAST_(7)
 711 #define MIPS_SEGCFG_USK         _ULCAST_(5)
 712 #define MIPS_SEGCFG_MUSUK       _ULCAST_(4)
 713 #define MIPS_SEGCFG_MUSK        _ULCAST_(3)
 714 #define MIPS_SEGCFG_MSK         _ULCAST_(2)
 715 #define MIPS_SEGCFG_MK          _ULCAST_(1)
 716 #define MIPS_SEGCFG_UK          _ULCAST_(0)
 717
 718 #define MIPS_PWFIELD_GDI_SHIFT  24
 719 #define MIPS_PWFIELD_GDI_MASK   0x3f000000
 720 #define MIPS_PWFIELD_UDI_SHIFT  18
 721 #define MIPS_PWFIELD_UDI_MASK   0x00fc0000
 722 #define MIPS_PWFIELD_MDI_SHIFT  12
 723 #define MIPS_PWFIELD_MDI_MASK   0x0003f000
 724 #define MIPS_PWFIELD_PTI_SHIFT  6
 725 #define MIPS_PWFIELD_PTI_MASK   0x00000fc0
 726 #define MIPS_PWFIELD_PTEI_SHIFT 0
 727 #define MIPS_PWFIELD_PTEI_MASK  0x0000003f
 728
 729 #define MIPS_PWSIZE_GDW_SHIFT   24
 730 #define MIPS_PWSIZE_GDW_MASK    0x3f000000
 731 #define MIPS_PWSIZE_UDW_SHIFT   18
 732 #define MIPS_PWSIZE_UDW_MASK    0x00fc0000
 733 #define MIPS_PWSIZE_MDW_SHIFT   12
 734 #define MIPS_PWSIZE_MDW_MASK    0x0003f000
 735 #define MIPS_PWSIZE_PTW_SHIFT   6
 736 #define MIPS_PWSIZE_PTW_MASK    0x00000fc0
 737 #define MIPS_PWSIZE_PTEW_SHIFT  0
 738 #define MIPS_PWSIZE_PTEW_MASK   0x0000003f
 739
 740 #define MIPS_PWCTL_PWEN_SHIFT   31
 741 #define MIPS_PWCTL_PWEN_MASK    0x80000000
 742 #define MIPS_PWCTL_DPH_SHIFT    7
 743 #define MIPS_PWCTL_DPH_MASK     0x00000080
 744 #define MIPS_PWCTL_HUGEPG_SHIFT 6
 745 #define MIPS_PWCTL_HUGEPG_MASK  0x00000060
 746 #define MIPS_PWCTL_PSN_SHIFT    0
 747 #define MIPS_PWCTL_PSN_MASK     0x0000003f
 748
 749 /* GuestCtl0 fields */
 750 #define MIPS_GCTL0_GM_SHIFT     31
 751 #define MIPS_GCTL0_GM           (_ULCAST_(1) << MIPS_GCTL0_GM_SHIFT)
 752 #define MIPS_GCTL0_RI_SHIFT     30
 753 #define MIPS_GCTL0_RI           (_ULCAST_(1) << MIPS_GCTL0_RI_SHIFT)
 754 #define MIPS_GCTL0_MC_SHIFT     29
 755 #define MIPS_GCTL0_MC           (_ULCAST_(1) << MIPS_GCTL0_MC_SHIFT)
 756 #define MIPS_GCTL0_CP0_SHIFT    28
 757 #define MIPS_GCTL0_CP0          (_ULCAST_(1) << MIPS_GCTL0_CP0_SHIFT)
 758 #define MIPS_GCTL0_AT_SHIFT     26
 759 #define MIPS_GCTL0_AT           (_ULCAST_(0x3) << MIPS_GCTL0_AT_SHIFT)
 760 #define MIPS_GCTL0_GT_SHIFT     25
 761 #define MIPS_GCTL0_GT           (_ULCAST_(1) << MIPS_GCTL0_GT_SHIFT)
 762 #define MIPS_GCTL0_CG_SHIFT     24
 763 #define MIPS_GCTL0_CG           (_ULCAST_(1) << MIPS_GCTL0_CG_SHIFT)
 764 #define MIPS_GCTL0_CF_SHIFT     23
 765 #define MIPS_GCTL0_CF           (_ULCAST_(1) << MIPS_GCTL0_CF_SHIFT)
 766 #define MIPS_GCTL0_G1_SHIFT     22
 767 #define MIPS_GCTL0_G1           (_ULCAST_(1) << MIPS_GCTL0_G1_SHIFT)
 768 #define MIPS_GCTL0_G0E_SHIFT    19
 769 #define MIPS_GCTL0_G0E          (_ULCAST_(1) << MIPS_GCTL0_G0E_SHIFT)
 770 #define MIPS_GCTL0_PT_SHIFT     18
 771 #define MIPS_GCTL0_PT           (_ULCAST_(1) << MIPS_GCTL0_PT_SHIFT)
 772 #define MIPS_GCTL0_RAD_SHIFT    9
 773 #define MIPS_GCTL0_RAD          (_ULCAST_(1) << MIPS_GCTL0_RAD_SHIFT)
 774 #define MIPS_GCTL0_DRG_SHIFT    8
 775 #define MIPS_GCTL0_DRG          (_ULCAST_(1) << MIPS_GCTL0_DRG_SHIFT)
 776 #define MIPS_GCTL0_G2_SHIFT     7
 777 #define MIPS_GCTL0_G2           (_ULCAST_(1) << MIPS_GCTL0_G2_SHIFT)
 778 #define MIPS_GCTL0_GEXC_SHIFT   2
 779 #define MIPS_GCTL0_GEXC         (_ULCAST_(0x1f) << MIPS_GCTL0_GEXC_SHIFT)
 780 #define MIPS_GCTL0_SFC2_SHIFT   1
 781 #define MIPS_GCTL0_SFC2         (_ULCAST_(1) << MIPS_GCTL0_SFC2_SHIFT)
 782 #define MIPS_GCTL0_SFC1_SHIFT   0
 783 #define MIPS_GCTL0_SFC1         (_ULCAST_(1) << MIPS_GCTL0_SFC1_SHIFT)
 784
 785 /* GuestCtl0.AT Guest address translation control */
 786 #define MIPS_GCTL0_AT_ROOT      1  /* Guest MMU under Root control */
 787 #define MIPS_GCTL0_AT_GUEST     3  /* Guest MMU under Guest control */
 788
 789 /* GuestCtl0.GExcCode Hypervisor exception cause codes */
 790 #define MIPS_GCTL0_GEXC_GPSI    0  /* Guest Privileged Sensitive Instruction */
 791 #define MIPS_GCTL0_GEXC_GSFC    1  /* Guest Software Field Change */
 792 #define MIPS_GCTL0_GEXC_HC      2  /* Hypercall */
 793 #define MIPS_GCTL0_GEXC_GRR     3  /* Guest Reserved Instruction Redirect */
 794 #define MIPS_GCTL0_GEXC_GVA     8  /* Guest Virtual Address available */
 795 #define MIPS_GCTL0_GEXC_GHFC    9  /* Guest Hardware Field Change */
 796 #define MIPS_GCTL0_GEXC_GPA     10 /* Guest Physical Address available */
 797
 798 /* GuestCtl0Ext fields */
 799 #define MIPS_GCTL0EXT_RPW_SHIFT 8
 800 #define MIPS_GCTL0EXT_RPW       (_ULCAST_(0x3) << MIPS_GCTL0EXT_RPW_SHIFT)
 801 #define MIPS_GCTL0EXT_NCC_SHIFT 6
 802 #define MIPS_GCTL0EXT_NCC       (_ULCAST_(0x3) << MIPS_GCTL0EXT_NCC_SHIFT)
 803 #define MIPS_GCTL0EXT_CGI_SHIFT 4
 804 #define MIPS_GCTL0EXT_CGI       (_ULCAST_(1) << MIPS_GCTL0EXT_CGI_SHIFT)
 805 #define MIPS_GCTL0EXT_FCD_SHIFT 3
 806 #define MIPS_GCTL0EXT_FCD       (_ULCAST_(1) << MIPS_GCTL0EXT_FCD_SHIFT)
 807 #define MIPS_GCTL0EXT_OG_SHIFT  2
 808 #define MIPS_GCTL0EXT_OG        (_ULCAST_(1) << MIPS_GCTL0EXT_OG_SHIFT)
 809 #define MIPS_GCTL0EXT_BG_SHIFT  1
 810 #define MIPS_GCTL0EXT_BG        (_ULCAST_(1) << MIPS_GCTL0EXT_BG_SHIFT)
 811 #define MIPS_GCTL0EXT_MG_SHIFT  0
 812 #define MIPS_GCTL0EXT_MG        (_ULCAST_(1) << MIPS_GCTL0EXT_MG_SHIFT)
 813
 814 /* GuestCtl0Ext.RPW Root page walk configuration */
 815 #define MIPS_GCTL0EXT_RPW_BOTH  0  /* Root PW for GPA->RPA and RVA->RPA */
 816 #define MIPS_GCTL0EXT_RPW_GPA   2  /* Root PW for GPA->RPA */
 817 #define MIPS_GCTL0EXT_RPW_RVA   3  /* Root PW for RVA->RPA */
 818
 819 /* GuestCtl0Ext.NCC Nested cache coherency attributes */
 820 #define MIPS_GCTL0EXT_NCC_IND   0  /* Guest CCA independent of Root CCA */
 821 #define MIPS_GCTL0EXT_NCC_MOD   1  /* Guest CCA modified by Root CCA */
 822
 823 /* GuestCtl1 fields */
 824 #define MIPS_GCTL1_ID_SHIFT     0
 825 #define MIPS_GCTL1_ID_WIDTH     8
 826 #define MIPS_GCTL1_ID           (_ULCAST_(0xff) << MIPS_GCTL1_ID_SHIFT)
 827 #define MIPS_GCTL1_RID_SHIFT    16
 828 #define MIPS_GCTL1_RID_WIDTH    8
 829 #define MIPS_GCTL1_RID          (_ULCAST_(0xff) << MIPS_GCTL1_RID_SHIFT)
 830 #define MIPS_GCTL1_EID_SHIFT    24
 831 #define MIPS_GCTL1_EID_WIDTH    8
 832 #define MIPS_GCTL1_EID          (_ULCAST_(0xff) << MIPS_GCTL1_EID_SHIFT)
 833
 834 /* GuestID reserved for root context */
 835 #define MIPS_GCTL1_ROOT_GUESTID 0
 836
 837 /* CDMMBase register bit definitions */
 838 #define MIPS_CDMMBASE_SIZE_SHIFT 0
 839 #define MIPS_CDMMBASE_SIZE      (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
 840 #define MIPS_CDMMBASE_CI        (_ULCAST_(1) << 9)
 841 #define MIPS_CDMMBASE_EN        (_ULCAST_(1) << 10)
 842 #define MIPS_CDMMBASE_ADDR_SHIFT 11
 843 #define MIPS_CDMMBASE_ADDR_START 15
 844
 845 /*
 846  * Bitfields in the TX39 family CP0 Configuration Register 3
 847  */
 848 #define TX39_CONF_ICS_SHIFT     19
 849 #define TX39_CONF_ICS_MASK      0x00380000
 850 #define TX39_CONF_ICS_1KB       0x00000000
 851 #define TX39_CONF_ICS_2KB       0x00080000
 852 #define TX39_CONF_ICS_4KB       0x00100000
 853 #define TX39_CONF_ICS_8KB       0x00180000
 854 #define TX39_CONF_ICS_16KB      0x00200000
 855
 856 #define TX39_CONF_DCS_SHIFT     16
 857 #define TX39_CONF_DCS_MASK      0x00070000
 858 #define TX39_CONF_DCS_1KB       0x00000000
 859 #define TX39_CONF_DCS_2KB       0x00010000
 860 #define TX39_CONF_DCS_4KB       0x00020000
 861 #define TX39_CONF_DCS_8KB       0x00030000
 862 #define TX39_CONF_DCS_16KB      0x00040000
 863
 864 #define TX39_CONF_CWFON         0x00004000
 865 #define TX39_CONF_WBON          0x00002000
 866 #define TX39_CONF_RF_SHIFT      10
 867 #define TX39_CONF_RF_MASK       0x00000c00
 868 #define TX39_CONF_DOZE          0x00000200
 869 #define TX39_CONF_HALT          0x00000100
 870 #define TX39_CONF_LOCK          0x00000080
 871 #define TX39_CONF_ICE           0x00000020
 872 #define TX39_CONF_DCE           0x00000010
 873 #define TX39_CONF_IRSIZE_SHIFT  2
 874 #define TX39_CONF_IRSIZE_MASK   0x0000000c
 875 #define TX39_CONF_DRSIZE_SHIFT  0
 876 #define TX39_CONF_DRSIZE_MASK   0x00000003
 877
 878 /*
 879  * Interesting Bits in the R10K CP0 Branch Diagnostic Register
 880  */
 881 /* Disable Branch Target Address Cache */
 882 #define R10K_DIAG_D_BTAC        (_ULCAST_(1) << 27)
 883 /* Enable Branch Prediction Global History */
 884 #define R10K_DIAG_E_GHIST       (_ULCAST_(1) << 26)
 885 /* Disable Branch Return Cache */
 886 #define R10K_DIAG_D_BRC         (_ULCAST_(1) << 22)
 887
 888 /* Flush ITLB */
 889 #define LOONGSON_DIAG_ITLB      (_ULCAST_(1) << 2)
 890 /* Flush DTLB */
 891 #define LOONGSON_DIAG_DTLB      (_ULCAST_(1) << 3)
 892 /* Flush VTLB */
 893 #define LOONGSON_DIAG_VTLB      (_ULCAST_(1) << 12)
 894 /* Flush FTLB */
 895 #define LOONGSON_DIAG_FTLB      (_ULCAST_(1) << 13)
 896
 897 /*
 898  * Coprocessor 1 (FPU) register names
 899  */
 900 #define CP1_REVISION    $0
 901 #define CP1_UFR         $1
 902 #define CP1_UNFR        $4
 903 #define CP1_FCCR        $25
 904 #define CP1_FEXR        $26
 905 #define CP1_FENR        $28
 906 #define CP1_STATUS      $31
 907
 908
 909 /*
 910  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
 911  */
 912 #define MIPS_FPIR_S             (_ULCAST_(1) << 16)
 913 #define MIPS_FPIR_D             (_ULCAST_(1) << 17)
 914 #define MIPS_FPIR_PS            (_ULCAST_(1) << 18)
 915 #define MIPS_FPIR_3D            (_ULCAST_(1) << 19)
 916 #define MIPS_FPIR_W             (_ULCAST_(1) << 20)
 917 #define MIPS_FPIR_L             (_ULCAST_(1) << 21)
 918 #define MIPS_FPIR_F64           (_ULCAST_(1) << 22)
 919 #define MIPS_FPIR_HAS2008       (_ULCAST_(1) << 23)
 920 #define MIPS_FPIR_UFRP          (_ULCAST_(1) << 28)
 921 #define MIPS_FPIR_FREP          (_ULCAST_(1) << 29)
 922
 923 /*
 924  * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
 925  */
 926 #define MIPS_FCCR_CONDX_S       0
 927 #define MIPS_FCCR_CONDX         (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
 928 #define MIPS_FCCR_COND0_S       0
 929 #define MIPS_FCCR_COND0         (_ULCAST_(1) << MIPS_FCCR_COND0_S)
 930 #define MIPS_FCCR_COND1_S       1
 931 #define MIPS_FCCR_COND1         (_ULCAST_(1) << MIPS_FCCR_COND1_S)
 932 #define MIPS_FCCR_COND2_S       2
 933 #define MIPS_FCCR_COND2         (_ULCAST_(1) << MIPS_FCCR_COND2_S)
 934 #define MIPS_FCCR_COND3_S       3
 935 #define MIPS_FCCR_COND3         (_ULCAST_(1) << MIPS_FCCR_COND3_S)
 936 #define MIPS_FCCR_COND4_S       4
 937 #define MIPS_FCCR_COND4         (_ULCAST_(1) << MIPS_FCCR_COND4_S)
 938 #define MIPS_FCCR_COND5_S       5
 939 #define MIPS_FCCR_COND5         (_ULCAST_(1) << MIPS_FCCR_COND5_S)
 940 #define MIPS_FCCR_COND6_S       6
 941 #define MIPS_FCCR_COND6         (_ULCAST_(1) << MIPS_FCCR_COND6_S)
 942 #define MIPS_FCCR_COND7_S       7
 943 #define MIPS_FCCR_COND7         (_ULCAST_(1) << MIPS_FCCR_COND7_S)
 944
 945 /*
 946  * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
 947  */
 948 #define MIPS_FENR_FS_S          2
 949 #define MIPS_FENR_FS            (_ULCAST_(1) << MIPS_FENR_FS_S)
 950
 951 /*
 952  * FPU Status Register Values
 953  */
 954 #define FPU_CSR_COND_S  23                                      /* $fcc0 */
 955 #define FPU_CSR_COND    (_ULCAST_(1) << FPU_CSR_COND_S)
 956
 957 #define FPU_CSR_FS_S    24              /* flush denormalised results to 0 */
 958 #define FPU_CSR_FS      (_ULCAST_(1) << FPU_CSR_FS_S)
 959
 960 #define FPU_CSR_CONDX_S 25                                      /* $fcc[7:1] */
 961 #define FPU_CSR_CONDX   (_ULCAST_(127) << FPU_CSR_CONDX_S)
 962 #define FPU_CSR_COND1_S 25                                      /* $fcc1 */
 963 #define FPU_CSR_COND1   (_ULCAST_(1) << FPU_CSR_COND1_S)
 964 #define FPU_CSR_COND2_S 26                                      /* $fcc2 */
 965 #define FPU_CSR_COND2   (_ULCAST_(1) << FPU_CSR_COND2_S)
 966 #define FPU_CSR_COND3_S 27                                      /* $fcc3 */
 967 #define FPU_CSR_COND3   (_ULCAST_(1) << FPU_CSR_COND3_S)
 968 #define FPU_CSR_COND4_S 28                                      /* $fcc4 */
 969 #define FPU_CSR_COND4   (_ULCAST_(1) << FPU_CSR_COND4_S)
 970 #define FPU_CSR_COND5_S 29                                      /* $fcc5 */
 971 #define FPU_CSR_COND5   (_ULCAST_(1) << FPU_CSR_COND5_S)
 972 #define FPU_CSR_COND6_S 30                                      /* $fcc6 */
 973 #define FPU_CSR_COND6   (_ULCAST_(1) << FPU_CSR_COND6_S)
 974 #define FPU_CSR_COND7_S 31                                      /* $fcc7 */
 975 #define FPU_CSR_COND7   (_ULCAST_(1) << FPU_CSR_COND7_S)
 976
 977 /*
 978  * Bits 22:20 of the FPU Status Register will be read as 0,
 979  * and should be written as zero.
 980  */
 981 #define FPU_CSR_RSVD    (_ULCAST_(7) << 20)
 982
 983 #define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
 984 #define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
 985
 986 /*
 987  * X the exception cause indicator
 988  * E the exception enable
 989  * S the sticky/flag bit
 990 */
 991 #define FPU_CSR_ALL_X   0x0003f000
 992 #define FPU_CSR_UNI_X   0x00020000
 993 #define FPU_CSR_INV_X   0x00010000
 994 #define FPU_CSR_DIV_X   0x00008000
 995 #define FPU_CSR_OVF_X   0x00004000
 996 #define FPU_CSR_UDF_X   0x00002000
 997 #define FPU_CSR_INE_X   0x00001000
 998
 999 #define FPU_CSR_ALL_E   0x00000f80
1000 #define FPU_CSR_INV_E   0x00000800
1001 #define FPU_CSR_DIV_E   0x00000400
1002 #define FPU_CSR_OVF_E   0x00000200
1003 #define FPU_CSR_UDF_E   0x00000100
1004 #define FPU_CSR_INE_E   0x00000080
1005
1006 #define FPU_CSR_ALL_S   0x0000007c
1007 #define FPU_CSR_INV_S   0x00000040
1008 #define FPU_CSR_DIV_S   0x00000020
1009 #define FPU_CSR_OVF_S   0x00000010
1010 #define FPU_CSR_UDF_S   0x00000008
1011 #define FPU_CSR_INE_S   0x00000004
1012
1013 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
1014 #define FPU_CSR_RM      0x00000003
1015 #define FPU_CSR_RN      0x0     /* nearest */
1016 #define FPU_CSR_RZ      0x1     /* towards zero */
1017 #define FPU_CSR_RU      0x2     /* towards +Infinity */
1018 #define FPU_CSR_RD      0x3     /* towards -Infinity */
1019
1020
1021 #ifndef __ASSEMBLY__
1022
1023 /*
1024  * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
1025  */
1026 #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
1027     defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
1028 #define get_isa16_mode(x)               ((x) & 0x1)
1029 #define msk_isa16_mode(x)               ((x) & ~0x1)
1030 #define set_isa16_mode(x)               do { (x) |= 0x1; } while(0)
1031 #else
1032 #define get_isa16_mode(x)               0
1033 #define msk_isa16_mode(x)               (x)
1034 #define set_isa16_mode(x)               do { } while(0)
1035 #endif
1036
1037 /*
1038  * microMIPS instructions can be 16-bit or 32-bit in length. This
1039  * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
1040  */
1041 static inline int mm_insn_16bit(u16 insn)
1042 {
1043         u16 opcode = (insn >> 10) & 0x7;
1044
1045         return (opcode >= 1 && opcode <= 3) ? 1 : 0;
1046 }
1047
1048 /*
1049  * TLB Invalidate Flush
1050  */
1051 static inline void tlbinvf(void)
1052 {
1053         __asm__ __volatile__(
1054                 ".set push\n\t"
1055                 ".set noreorder\n\t"
1056                 ".word 0x42000004\n\t" /* tlbinvf */
1057                 ".set pop");
1058 }
1059
1060
1061 /*
1062  * Functions to access the R10000 performance counters.  These are basically
1063  * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
1064  * performance counter number encoded into bits 1 ... 5 of the instruction.
1065  * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
1066  * disassembler these will look like an access to sel 0 or 1.
1067  */
1068 #define read_r10k_perf_cntr(counter)                            \
1069 ({                                                              \
1070         unsigned int __res;                                     \
1071         __asm__ __volatile__(                                   \
1072         "mfpc\t%0, %1"                                          \
1073         : "=r" (__res)                                          \
1074         : "i" (counter));                                       \
1075                                                                 \
1076         __res;                                                  \
1077 })
1078
1079 #define write_r10k_perf_cntr(counter,val)                       \
1080 do {                                                            \
1081         __asm__ __volatile__(                                   \
1082         "mtpc\t%0, %1"                                          \
1083         :                                                       \
1084         : "r" (val), "i" (counter));                            \
1085 } while (0)
1086
1087 #define read_r10k_perf_event(counter)                           \
1088 ({                                                              \
1089         unsigned int __res;                                     \
1090         __asm__ __volatile__(                                   \
1091         "mfps\t%0, %1"                                          \
1092         : "=r" (__res)                                          \
1093         : "i" (counter));                                       \
1094                                                                 \
1095         __res;                                                  \
1096 })
1097
1098 #define write_r10k_perf_cntl(counter,val)                       \
1099 do {                                                            \
1100         __asm__ __volatile__(                                   \
1101         "mtps\t%0, %1"                                          \
1102         :                                                       \
1103         : "r" (val), "i" (counter));                            \
1104 } while (0)
1105
1106
1107 /*
1108  * Macros to access the system control coprocessor
1109  */
1110
1111 #define __read_32bit_c0_register(source, sel)                           \
1112 ({ unsigned int __res;                                                  \
1113         if (sel == 0)                                                   \
1114                 __asm__ __volatile__(                                   \
1115                         "mfc0\t%0, " #source "\n\t"                     \
1116                         : "=r" (__res));                                \
1117         else                                                            \
1118                 __asm__ __volatile__(                                   \
1119                         ".set\tmips32\n\t"                              \
1120                         "mfc0\t%0, " #source ", " #sel "\n\t"           \
1121                         ".set\tmips0\n\t"                               \
1122                         : "=r" (__res));                                \
1123         __res;                                                          \
1124 })
1125
1126 #define __read_64bit_c0_register(source, sel)                           \
1127 ({ unsigned long long __res;                                            \
1128         if (sizeof(unsigned long) == 4)                                 \
1129                 __res = __read_64bit_c0_split(source, sel);             \
1130         else if (sel == 0)                                              \
1131                 __asm__ __volatile__(                                   \
1132                         ".set\tmips3\n\t"                               \
1133                         "dmfc0\t%0, " #source "\n\t"                    \
1134                         ".set\tmips0"                                   \
1135                         : "=r" (__res));                                \
1136         else                                                            \
1137                 __asm__ __volatile__(                                   \
1138                         ".set\tmips64\n\t"                              \
1139                         "dmfc0\t%0, " #source ", " #sel "\n\t"          \
1140                         ".set\tmips0"                                   \
1141                         : "=r" (__res));                                \
1142         __res;                                                          \
1143 })
1144
1145 #define __write_32bit_c0_register(register, sel, value)                 \
1146 do {                                                                    \
1147         if (sel == 0)                                                   \
1148                 __asm__ __volatile__(                                   \
1149                         "mtc0\t%z0, " #register "\n\t"                  \
1150                         : : "Jr" ((unsigned int)(value)));              \
1151         else                                                            \
1152                 __asm__ __volatile__(                                   \
1153                         ".set\tmips32\n\t"                              \
1154                         "mtc0\t%z0, " #register ", " #sel "\n\t"        \
1155                         ".set\tmips0"                                   \
1156                         : : "Jr" ((unsigned int)(value)));              \
1157 } while (0)
1158
1159 #define __write_64bit_c0_register(register, sel, value)                 \
1160 do {                                                                    \
1161         if (sizeof(unsigned long) == 4)                                 \
1162                 __write_64bit_c0_split(register, sel, value);           \
1163         else if (sel == 0)                                              \
1164                 __asm__ __volatile__(                                   \
1165                         ".set\tmips3\n\t"                               \
1166                         "dmtc0\t%z0, " #register "\n\t"                 \
1167                         ".set\tmips0"                                   \
1168                         : : "Jr" (value));                              \
1169         else                                                            \
1170                 __asm__ __volatile__(                                   \
1171                         ".set\tmips64\n\t"                              \
1172                         "dmtc0\t%z0, " #register ", " #sel "\n\t"       \
1173                         ".set\tmips0"                                   \
1174                         : : "Jr" (value));                              \
1175 } while (0)
1176
1177 #define __read_ulong_c0_register(reg, sel)                              \
1178         ((sizeof(unsigned long) == 4) ?                                 \
1179         (unsigned long) __read_32bit_c0_register(reg, sel) :            \
1180         (unsigned long) __read_64bit_c0_register(reg, sel))
1181
1182 #define __write_ulong_c0_register(reg, sel, val)                        \
1183 do {                                                                    \
1184         if (sizeof(unsigned long) == 4)                                 \
1185                 __write_32bit_c0_register(reg, sel, val);               \
1186         else                                                            \
1187                 __write_64bit_c0_register(reg, sel, val);               \
1188 } while (0)
1189
1190 /*
1191  * On RM7000/RM9000 these are uses to access cop0 set 1 registers
1192  */
1193 #define __read_32bit_c0_ctrl_register(source)                           \
1194 ({ unsigned int __res;                                                  \
1195         __asm__ __volatile__(                                           \
1196                 "cfc0\t%0, " #source "\n\t"                             \
1197                 : "=r" (__res));                                        \
1198         __res;                                                          \
1199 })
1200
1201 #define __write_32bit_c0_ctrl_register(register, value)                 \
1202 do {                                                                    \
1203         __asm__ __volatile__(                                           \
1204                 "ctc0\t%z0, " #register "\n\t"                          \
1205                 : : "Jr" ((unsigned int)(value)));                      \
1206 } while (0)
1207
1208 /*
1209  * These versions are only needed for systems with more than 38 bits of
1210  * physical address space running the 32-bit kernel.  That's none atm :-)
1211  */
1212 #define __read_64bit_c0_split(source, sel)                              \
1213 ({                                                                      \
1214         unsigned long long __val;                                       \
1215         unsigned long __flags;                                          \
1216                                                                         \
1217         local_irq_save(__flags);                                        \
1218         if (sel == 0)                                                   \
1219                 __asm__ __volatile__(                                   \
1220                         ".set\tmips64\n\t"                              \
1221                         "dmfc0\t%M0, " #source "\n\t"                   \
1222                         "dsll\t%L0, %M0, 32\n\t"                        \
1223                         "dsra\t%M0, %M0, 32\n\t"                        \
1224                         "dsra\t%L0, %L0, 32\n\t"                        \
1225                         ".set\tmips0"                                   \
1226                         : "=r" (__val));                                \
1227         else                                                            \
1228                 __asm__ __volatile__(                                   \
1229                         ".set\tmips64\n\t"                              \
1230                         "dmfc0\t%M0, " #source ", " #sel "\n\t"         \
1231                         "dsll\t%L0, %M0, 32\n\t"                        \
1232                         "dsra\t%M0, %M0, 32\n\t"                        \
1233                         "dsra\t%L0, %L0, 32\n\t"                        \
1234                         ".set\tmips0"                                   \
1235                         : "=r" (__val));                                \
1236         local_irq_restore(__flags);                                     \
1237                                                                         \
1238         __val;                                                          \
1239 })
1240
1241 #define __write_64bit_c0_split(source, sel, val)                        \
1242 do {                                                                    \
1243         unsigned long __flags;                                          \
1244                                                                         \
1245         local_irq_save(__flags);                                        \
1246         if (sel == 0)                                                   \
1247                 __asm__ __volatile__(                                   \
1248                         ".set\tmips64\n\t"                              \
1249                         "dsll\t%L0, %L0, 32\n\t"                        \
1250                         "dsrl\t%L0, %L0, 32\n\t"                        \
1251                         "dsll\t%M0, %M0, 32\n\t"                        \
1252                         "or\t%L0, %L0, %M0\n\t"                         \
1253                         "dmtc0\t%L0, " #source "\n\t"                   \
1254                         ".set\tmips0"                                   \
1255                         : : "r" (val));                                 \
1256         else                                                            \
1257                 __asm__ __volatile__(                                   \
1258                         ".set\tmips64\n\t"                              \
1259                         "dsll\t%L0, %L0, 32\n\t"                        \
1260                         "dsrl\t%L0, %L0, 32\n\t"                        \
1261                         "dsll\t%M0, %M0, 32\n\t"                        \
1262                         "or\t%L0, %L0, %M0\n\t"                         \
1263                         "dmtc0\t%L0, " #source ", " #sel "\n\t"         \
1264                         ".set\tmips0"                                   \
1265                         : : "r" (val));                                 \
1266         local_irq_restore(__flags);                                     \
1267 } while (0)
1268
1269 #define __readx_32bit_c0_register(source)                               \
1270 ({                                                                      \
1271         unsigned int __res;                                             \
1272                                                                         \
1273         __asm__ __volatile__(                                           \
1274         "       .set    push                                    \n"     \
1275         "       .set    noat                                    \n"     \
1276         "       .set    mips32r2                                \n"     \
1277         "       .insn                                           \n"     \
1278         "       # mfhc0 $1, %1                                  \n"     \
1279         "       .word   (0x40410000 | ((%1 & 0x1f) << 11))      \n"     \
1280         "       move    %0, $1                                  \n"     \
1281         "       .set    pop                                     \n"     \
1282         : "=r" (__res)                                                  \
1283         : "i" (source));                                                \
1284         __res;                                                          \
1285 })
1286
1287 #define __writex_32bit_c0_register(register, value)                     \
1288 do {                                                                    \
1289         __asm__ __volatile__(                                           \
1290         "       .set    push                                    \n"     \
1291         "       .set    noat                                    \n"     \
1292         "       .set    mips32r2                                \n"     \
1293         "       move    $1, %0                                  \n"     \
1294         "       # mthc0 $1, %1                                  \n"     \
1295         "       .insn                                           \n"     \
1296         "       .word   (0x40c10000 | ((%1 & 0x1f) << 11))      \n"     \
1297         "       .set    pop                                     \n"     \
1298         :                                                               \
1299         : "r" (value), "i" (register));                                 \
1300 } while (0)
1301
1302 #define read_c0_index()         __read_32bit_c0_register($0, 0)
1303 #define write_c0_index(val)     __write_32bit_c0_register($0, 0, val)
1304
1305 #define read_c0_random()        __read_32bit_c0_register($1, 0)
1306 #define write_c0_random(val)    __write_32bit_c0_register($1, 0, val)
1307
1308 #define read_c0_entrylo0()      __read_ulong_c0_register($2, 0)
1309 #define write_c0_entrylo0(val)  __write_ulong_c0_register($2, 0, val)
1310
1311 #define readx_c0_entrylo0()     __readx_32bit_c0_register(2)
1312 #define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val)
1313
1314 #define read_c0_entrylo1()      __read_ulong_c0_register($3, 0)
1315 #define write_c0_entrylo1(val)  __write_ulong_c0_register($3, 0, val)
1316
1317 #define readx_c0_entrylo1()     __readx_32bit_c0_register(3)
1318 #define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val)
1319
1320 #define read_c0_conf()          __read_32bit_c0_register($3, 0)
1321 #define write_c0_conf(val)      __write_32bit_c0_register($3, 0, val)
1322
1323 #define read_c0_context()       __read_ulong_c0_register($4, 0)
1324 #define write_c0_context(val)   __write_ulong_c0_register($4, 0, val)
1325
1326 #define read_c0_contextconfig()         __read_32bit_c0_register($4, 1)
1327 #define write_c0_contextconfig(val)     __write_32bit_c0_register($4, 1, val)
1328
1329 #define read_c0_userlocal()     __read_ulong_c0_register($4, 2)
1330 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1331
1332 #define read_c0_xcontextconfig()        __read_ulong_c0_register($4, 3)
1333 #define write_c0_xcontextconfig(val)    __write_ulong_c0_register($4, 3, val)
1334
1335 #define read_c0_pagemask()      __read_32bit_c0_register($5, 0)
1336 #define write_c0_pagemask(val)  __write_32bit_c0_register($5, 0, val)
1337
1338 #define read_c0_pagegrain()     __read_32bit_c0_register($5, 1)
1339 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1340
1341 #define read_c0_wired()         __read_32bit_c0_register($6, 0)
1342 #define write_c0_wired(val)     __write_32bit_c0_register($6, 0, val)
1343
1344 #define read_c0_info()          __read_32bit_c0_register($7, 0)
1345
1346 #define read_c0_cache()         __read_32bit_c0_register($7, 0) /* TX39xx */
1347 #define write_c0_cache(val)     __write_32bit_c0_register($7, 0, val)
1348
1349 #define read_c0_badvaddr()      __read_ulong_c0_register($8, 0)
1350 #define write_c0_badvaddr(val)  __write_ulong_c0_register($8, 0, val)
1351
1352 #define read_c0_badinstr()      __read_32bit_c0_register($8, 1)
1353 #define read_c0_badinstrp()     __read_32bit_c0_register($8, 2)
1354
1355 #define read_c0_count()         __read_32bit_c0_register($9, 0)
1356 #define write_c0_count(val)     __write_32bit_c0_register($9, 0, val)
1357
1358 #define read_c0_count2()        __read_32bit_c0_register($9, 6) /* pnx8550 */
1359 #define write_c0_count2(val)    __write_32bit_c0_register($9, 6, val)
1360
1361 #define read_c0_count3()        __read_32bit_c0_register($9, 7) /* pnx8550 */
1362 #define write_c0_count3(val)    __write_32bit_c0_register($9, 7, val)
1363
1364 #define read_c0_entryhi()       __read_ulong_c0_register($10, 0)
1365 #define write_c0_entryhi(val)   __write_ulong_c0_register($10, 0, val)
1366
1367 #define read_c0_guestctl1()     __read_32bit_c0_register($10, 4)
1368 #define write_c0_guestctl1(val) __write_32bit_c0_register($10, 4, val)
1369
1370 #define read_c0_guestctl2()     __read_32bit_c0_register($10, 5)
1371 #define write_c0_guestctl2(val) __write_32bit_c0_register($10, 5, val)
1372
1373 #define read_c0_guestctl3()     __read_32bit_c0_register($10, 6)
1374 #define write_c0_guestctl3(val) __write_32bit_c0_register($10, 6, val)
1375
1376 #define read_c0_compare()       __read_32bit_c0_register($11, 0)
1377 #define write_c0_compare(val)   __write_32bit_c0_register($11, 0, val)
1378
1379 #define read_c0_guestctl0ext()  __read_32bit_c0_register($11, 4)
1380 #define write_c0_guestctl0ext(val) __write_32bit_c0_register($11, 4, val)
1381
1382 #define read_c0_compare2()      __read_32bit_c0_register($11, 6) /* pnx8550 */
1383 #define write_c0_compare2(val)  __write_32bit_c0_register($11, 6, val)
1384
1385 #define read_c0_compare3()      __read_32bit_c0_register($11, 7) /* pnx8550 */
1386 #define write_c0_compare3(val)  __write_32bit_c0_register($11, 7, val)
1387
1388 #define read_c0_status()        __read_32bit_c0_register($12, 0)
1389
1390 #define write_c0_status(val)    __write_32bit_c0_register($12, 0, val)
1391
1392 #define read_c0_guestctl0()     __read_32bit_c0_register($12, 6)
1393 #define write_c0_guestctl0(val) __write_32bit_c0_register($12, 6, val)
1394
1395 #define read_c0_gtoffset()      __read_32bit_c0_register($12, 7)
1396 #define write_c0_gtoffset(val)  __write_32bit_c0_register($12, 7, val)
1397
1398 #define read_c0_cause()         __read_32bit_c0_register($13, 0)
1399 #define write_c0_cause(val)     __write_32bit_c0_register($13, 0, val)
1400
1401 #define read_c0_epc()           __read_ulong_c0_register($14, 0)
1402 #define write_c0_epc(val)       __write_ulong_c0_register($14, 0, val)
1403
1404 #define read_c0_prid()          __read_32bit_c0_register($15, 0)
1405
1406 #define read_c0_cmgcrbase()     __read_ulong_c0_register($15, 3)
1407
1408 #define read_c0_config()        __read_32bit_c0_register($16, 0)
1409 #define read_c0_config1()       __read_32bit_c0_register($16, 1)
1410 #define read_c0_config2()       __read_32bit_c0_register($16, 2)
1411 #define read_c0_config3()       __read_32bit_c0_register($16, 3)
1412 #define read_c0_config4()       __read_32bit_c0_register($16, 4)
1413 #define read_c0_config5()       __read_32bit_c0_register($16, 5)
1414 #define read_c0_config6()       __read_32bit_c0_register($16, 6)
1415 #define read_c0_config7()       __read_32bit_c0_register($16, 7)
1416 #define write_c0_config(val)    __write_32bit_c0_register($16, 0, val)
1417 #define write_c0_config1(val)   __write_32bit_c0_register($16, 1, val)
1418 #define write_c0_config2(val)   __write_32bit_c0_register($16, 2, val)
1419 #define write_c0_config3(val)   __write_32bit_c0_register($16, 3, val)
1420 #define write_c0_config4(val)   __write_32bit_c0_register($16, 4, val)
1421 #define write_c0_config5(val)   __write_32bit_c0_register($16, 5, val)
1422 #define write_c0_config6(val)   __write_32bit_c0_register($16, 6, val)
1423 #define write_c0_config7(val)   __write_32bit_c0_register($16, 7, val)
1424
1425 #define read_c0_lladdr()        __read_ulong_c0_register($17, 0)
1426 #define write_c0_lladdr(val)    __write_ulong_c0_register($17, 0, val)
1427 #define read_c0_maar()          __read_ulong_c0_register($17, 1)
1428 #define write_c0_maar(val)      __write_ulong_c0_register($17, 1, val)
1429 #define read_c0_maari()         __read_32bit_c0_register($17, 2)
1430 #define write_c0_maari(val)     __write_32bit_c0_register($17, 2, val)
1431
1432 /*
1433  * The WatchLo register.  There may be up to 8 of them.
1434  */
1435 #define read_c0_watchlo0()      __read_ulong_c0_register($18, 0)
1436 #define read_c0_watchlo1()      __read_ulong_c0_register($18, 1)
1437 #define read_c0_watchlo2()      __read_ulong_c0_register($18, 2)
1438 #define read_c0_watchlo3()      __read_ulong_c0_register($18, 3)
1439 #define read_c0_watchlo4()      __read_ulong_c0_register($18, 4)
1440 #define read_c0_watchlo5()      __read_ulong_c0_register($18, 5)
1441 #define read_c0_watchlo6()      __read_ulong_c0_register($18, 6)
1442 #define read_c0_watchlo7()      __read_ulong_c0_register($18, 7)
1443 #define write_c0_watchlo0(val)  __write_ulong_c0_register($18, 0, val)
1444 #define write_c0_watchlo1(val)  __write_ulong_c0_register($18, 1, val)
1445 #define write_c0_watchlo2(val)  __write_ulong_c0_register($18, 2, val)
1446 #define write_c0_watchlo3(val)  __write_ulong_c0_register($18, 3, val)
1447 #define write_c0_watchlo4(val)  __write_ulong_c0_register($18, 4, val)
1448 #define write_c0_watchlo5(val)  __write_ulong_c0_register($18, 5, val)
1449 #define write_c0_watchlo6(val)  __write_ulong_c0_register($18, 6, val)
1450 #define write_c0_watchlo7(val)  __write_ulong_c0_register($18, 7, val)
1451
1452 /*
1453  * The WatchHi register.  There may be up to 8 of them.
1454  */
1455 #define read_c0_watchhi0()      __read_32bit_c0_register($19, 0)
1456 #define read_c0_watchhi1()      __read_32bit_c0_register($19, 1)
1457 #define read_c0_watchhi2()      __read_32bit_c0_register($19, 2)
1458 #define read_c0_watchhi3()      __read_32bit_c0_register($19, 3)
1459 #define read_c0_watchhi4()      __read_32bit_c0_register($19, 4)
1460 #define read_c0_watchhi5()      __read_32bit_c0_register($19, 5)
1461 #define read_c0_watchhi6()      __read_32bit_c0_register($19, 6)
1462 #define read_c0_watchhi7()      __read_32bit_c0_register($19, 7)
1463
1464 #define write_c0_watchhi0(val)  __write_32bit_c0_register($19, 0, val)
1465 #define write_c0_watchhi1(val)  __write_32bit_c0_register($19, 1, val)
1466 #define write_c0_watchhi2(val)  __write_32bit_c0_register($19, 2, val)
1467 #define write_c0_watchhi3(val)  __write_32bit_c0_register($19, 3, val)
1468 #define write_c0_watchhi4(val)  __write_32bit_c0_register($19, 4, val)
1469 #define write_c0_watchhi5(val)  __write_32bit_c0_register($19, 5, val)
1470 #define write_c0_watchhi6(val)  __write_32bit_c0_register($19, 6, val)
1471 #define write_c0_watchhi7(val)  __write_32bit_c0_register($19, 7, val)
1472
1473 #define read_c0_xcontext()      __read_ulong_c0_register($20, 0)
1474 #define write_c0_xcontext(val)  __write_ulong_c0_register($20, 0, val)
1475
1476 #define read_c0_intcontrol()    __read_32bit_c0_ctrl_register($20)
1477 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1478
1479 #define read_c0_framemask()     __read_32bit_c0_register($21, 0)
1480 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1481
1482 #define read_c0_diag()          __read_32bit_c0_register($22, 0)
1483 #define write_c0_diag(val)      __write_32bit_c0_register($22, 0, val)
1484
1485 /* R10K CP0 Branch Diagnostic register is 64bits wide */
1486 #define read_c0_r10k_diag()     __read_64bit_c0_register($22, 0)
1487 #define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
1488
1489 #define read_c0_diag1()         __read_32bit_c0_register($22, 1)
1490 #define write_c0_diag1(val)     __write_32bit_c0_register($22, 1, val)
1491
1492 #define read_c0_diag2()         __read_32bit_c0_register($22, 2)
1493 #define write_c0_diag2(val)     __write_32bit_c0_register($22, 2, val)
1494
1495 #define read_c0_diag3()         __read_32bit_c0_register($22, 3)
1496 #define write_c0_diag3(val)     __write_32bit_c0_register($22, 3, val)
1497
1498 #define read_c0_diag4()         __read_32bit_c0_register($22, 4)
1499 #define write_c0_diag4(val)     __write_32bit_c0_register($22, 4, val)
1500
1501 #define read_c0_diag5()         __read_32bit_c0_register($22, 5)
1502 #define write_c0_diag5(val)     __write_32bit_c0_register($22, 5, val)
1503
1504 #define read_c0_debug()         __read_32bit_c0_register($23, 0)
1505 #define write_c0_debug(val)     __write_32bit_c0_register($23, 0, val)
1506
1507 #define read_c0_depc()          __read_ulong_c0_register($24, 0)
1508 #define write_c0_depc(val)      __write_ulong_c0_register($24, 0, val)
1509
1510 /*
1511  * MIPS32 / MIPS64 performance counters
1512  */
1513 #define read_c0_perfctrl0()     __read_32bit_c0_register($25, 0)
1514 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1515 #define read_c0_perfcntr0()     __read_32bit_c0_register($25, 1)
1516 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1517 #define read_c0_perfcntr0_64()  __read_64bit_c0_register($25, 1)
1518 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1519 #define read_c0_perfctrl1()     __read_32bit_c0_register($25, 2)
1520 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1521 #define read_c0_perfcntr1()     __read_32bit_c0_register($25, 3)
1522 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1523 #define read_c0_perfcntr1_64()  __read_64bit_c0_register($25, 3)
1524 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1525 #define read_c0_perfctrl2()     __read_32bit_c0_register($25, 4)
1526 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1527 #define read_c0_perfcntr2()     __read_32bit_c0_register($25, 5)
1528 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1529 #define read_c0_perfcntr2_64()  __read_64bit_c0_register($25, 5)
1530 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1531 #define read_c0_perfctrl3()     __read_32bit_c0_register($25, 6)
1532 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1533 #define read_c0_perfcntr3()     __read_32bit_c0_register($25, 7)
1534 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1535 #define read_c0_perfcntr3_64()  __read_64bit_c0_register($25, 7)
1536 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1537
1538 #define read_c0_ecc()           __read_32bit_c0_register($26, 0)
1539 #define write_c0_ecc(val)       __write_32bit_c0_register($26, 0, val)
1540
1541 #define read_c0_derraddr0()     __read_ulong_c0_register($26, 1)
1542 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1543
1544 #define read_c0_cacheerr()      __read_32bit_c0_register($27, 0)
1545
1546 #define read_c0_derraddr1()     __read_ulong_c0_register($27, 1)
1547 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1548
1549 #define read_c0_taglo()         __read_32bit_c0_register($28, 0)
1550 #define write_c0_taglo(val)     __write_32bit_c0_register($28, 0, val)
1551
1552 #define read_c0_dtaglo()        __read_32bit_c0_register($28, 2)
1553 #define write_c0_dtaglo(val)    __write_32bit_c0_register($28, 2, val)
1554
1555 #define read_c0_ddatalo()       __read_32bit_c0_register($28, 3)
1556 #define write_c0_ddatalo(val)   __write_32bit_c0_register($28, 3, val)
1557
1558 #define read_c0_staglo()        __read_32bit_c0_register($28, 4)
1559 #define write_c0_staglo(val)    __write_32bit_c0_register($28, 4, val)
1560
1561 #define read_c0_taghi()         __read_32bit_c0_register($29, 0)
1562 #define write_c0_taghi(val)     __write_32bit_c0_register($29, 0, val)
1563
1564 #define read_c0_errorepc()      __read_ulong_c0_register($30, 0)
1565 #define write_c0_errorepc(val)  __write_ulong_c0_register($30, 0, val)
1566
1567 /* MIPSR2 */
1568 #define read_c0_hwrena()        __read_32bit_c0_register($7, 0)
1569 #define write_c0_hwrena(val)    __write_32bit_c0_register($7, 0, val)
1570
1571 #define read_c0_intctl()        __read_32bit_c0_register($12, 1)
1572 #define write_c0_intctl(val)    __write_32bit_c0_register($12, 1, val)
1573
1574 #define read_c0_srsctl()        __read_32bit_c0_register($12, 2)
1575 #define write_c0_srsctl(val)    __write_32bit_c0_register($12, 2, val)
1576
1577 #define read_c0_srsmap()        __read_32bit_c0_register($12, 3)
1578 #define write_c0_srsmap(val)    __write_32bit_c0_register($12, 3, val)
1579
1580 #define read_c0_ebase()         __read_32bit_c0_register($15, 1)
1581 #define write_c0_ebase(val)     __write_32bit_c0_register($15, 1, val)
1582
1583 #define read_c0_ebase_64()      __read_64bit_c0_register($15, 1)
1584 #define write_c0_ebase_64(val)  __write_64bit_c0_register($15, 1, val)
1585
1586 #define read_c0_cdmmbase()      __read_ulong_c0_register($15, 2)
1587 #define write_c0_cdmmbase(val)  __write_ulong_c0_register($15, 2, val)
1588
1589 /* MIPSR3 */
1590 #define read_c0_segctl0()       __read_32bit_c0_register($5, 2)
1591 #define write_c0_segctl0(val)   __write_32bit_c0_register($5, 2, val)
1592
1593 #define read_c0_segctl1()       __read_32bit_c0_register($5, 3)
1594 #define write_c0_segctl1(val)   __write_32bit_c0_register($5, 3, val)
1595
1596 #define read_c0_segctl2()       __read_32bit_c0_register($5, 4)
1597 #define write_c0_segctl2(val)   __write_32bit_c0_register($5, 4, val)
1598
1599 /* Hardware Page Table Walker */
1600 #define read_c0_pwbase()        __read_ulong_c0_register($5, 5)
1601 #define write_c0_pwbase(val)    __write_ulong_c0_register($5, 5, val)
1602
1603 #define read_c0_pwfield()       __read_ulong_c0_register($5, 6)
1604 #define write_c0_pwfield(val)   __write_ulong_c0_register($5, 6, val)
1605
1606 #define read_c0_pwsize()        __read_ulong_c0_register($5, 7)
1607 #define write_c0_pwsize(val)    __write_ulong_c0_register($5, 7, val)
1608
1609 #define read_c0_pwctl()         __read_32bit_c0_register($6, 6)
1610 #define write_c0_pwctl(val)     __write_32bit_c0_register($6, 6, val)
1611
1612 #define read_c0_pgd()           __read_64bit_c0_register($9, 7)
1613 #define write_c0_pgd(val)       __write_64bit_c0_register($9, 7, val)
1614
1615 #define read_c0_kpgd()          __read_64bit_c0_register($31, 7)
1616 #define write_c0_kpgd(val)      __write_64bit_c0_register($31, 7, val)
1617
1618 /* Cavium OCTEON (cnMIPS) */
1619 #define read_c0_cvmcount()      __read_ulong_c0_register($9, 6)
1620 #define write_c0_cvmcount(val)  __write_ulong_c0_register($9, 6, val)
1621
1622 #define read_c0_cvmctl()        __read_64bit_c0_register($9, 7)
1623 #define write_c0_cvmctl(val)    __write_64bit_c0_register($9, 7, val)
1624
1625 #define read_c0_cvmmemctl()     __read_64bit_c0_register($11, 7)
1626 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1627 /*
1628  * The cacheerr registers are not standardized.  On OCTEON, they are
1629  * 64 bits wide.
1630  */
1631 #define read_octeon_c0_icacheerr()      __read_64bit_c0_register($27, 0)
1632 #define write_octeon_c0_icacheerr(val)  __write_64bit_c0_register($27, 0, val)
1633
1634 #define read_octeon_c0_dcacheerr()      __read_64bit_c0_register($27, 1)
1635 #define write_octeon_c0_dcacheerr(val)  __write_64bit_c0_register($27, 1, val)
1636
1637 /* BMIPS3300 */
1638 #define read_c0_brcm_config_0()         __read_32bit_c0_register($22, 0)
1639 #define write_c0_brcm_config_0(val)     __write_32bit_c0_register($22, 0, val)
1640
1641 #define read_c0_brcm_bus_pll()          __read_32bit_c0_register($22, 4)
1642 #define write_c0_brcm_bus_pll(val)      __write_32bit_c0_register($22, 4, val)
1643
1644 #define read_c0_brcm_reset()            __read_32bit_c0_register($22, 5)
1645 #define write_c0_brcm_reset(val)        __write_32bit_c0_register($22, 5, val)
1646
1647 /* BMIPS43xx */
1648 #define read_c0_brcm_cmt_intr()         __read_32bit_c0_register($22, 1)
1649 #define write_c0_brcm_cmt_intr(val)     __write_32bit_c0_register($22, 1, val)
1650
1651 #define read_c0_brcm_cmt_ctrl()         __read_32bit_c0_register($22, 2)
1652 #define write_c0_brcm_cmt_ctrl(val)     __write_32bit_c0_register($22, 2, val)
1653
1654 #define read_c0_brcm_cmt_local()        __read_32bit_c0_register($22, 3)
1655 #define write_c0_brcm_cmt_local(val)    __write_32bit_c0_register($22, 3, val)
1656
1657 #define read_c0_brcm_config_1()         __read_32bit_c0_register($22, 5)
1658 #define write_c0_brcm_config_1(val)     __write_32bit_c0_register($22, 5, val)
1659
1660 #define read_c0_brcm_cbr()              __read_32bit_c0_register($22, 6)
1661 #define write_c0_brcm_cbr(val)          __write_32bit_c0_register($22, 6, val)
1662
1663 /* BMIPS5000 */
1664 #define read_c0_brcm_config()           __read_32bit_c0_register($22, 0)
1665 #define write_c0_brcm_config(val)       __write_32bit_c0_register($22, 0, val)
1666
1667 #define read_c0_brcm_mode()             __read_32bit_c0_register($22, 1)
1668 #define write_c0_brcm_mode(val)         __write_32bit_c0_register($22, 1, val)
1669
1670 #define read_c0_brcm_action()           __read_32bit_c0_register($22, 2)
1671 #define write_c0_brcm_action(val)       __write_32bit_c0_register($22, 2, val)
1672
1673 #define read_c0_brcm_edsp()             __read_32bit_c0_register($22, 3)
1674 #define write_c0_brcm_edsp(val)         __write_32bit_c0_register($22, 3, val)
1675
1676 #define read_c0_brcm_bootvec()          __read_32bit_c0_register($22, 4)
1677 #define write_c0_brcm_bootvec(val)      __write_32bit_c0_register($22, 4, val)
1678
1679 #define read_c0_brcm_sleepcount()       __read_32bit_c0_register($22, 7)
1680 #define write_c0_brcm_sleepcount(val)   __write_32bit_c0_register($22, 7, val)
1681
1682 /*
1683  * Macros to access the floating point coprocessor control registers
1684  */
1685 #define _read_32bit_cp1_register(source, gas_hardfloat)                 \
1686 ({                                                                      \
1687         unsigned int __res;                                             \
1688                                                                         \
1689         __asm__ __volatile__(                                           \
1690         "       .set    push                                    \n"     \
1691         "       .set    reorder                                 \n"     \
1692         "       # gas fails to assemble cfc1 for some archs,    \n"     \
1693         "       # like Octeon.                                  \n"     \
1694         "       .set    mips1                                   \n"     \
1695         "       "STR(gas_hardfloat)"                            \n"     \
1696         "       cfc1    %0,"STR(source)"                        \n"     \
1697         "       .set    pop                                     \n"     \
1698         : "=r" (__res));                                                \
1699         __res;                                                          \
1700 })
1701
1702 #define _write_32bit_cp1_register(dest, val, gas_hardfloat)             \
1703 do {                                                                    \
1704         __asm__ __volatile__(                                           \
1705         "       .set    push                                    \n"     \
1706         "       .set    reorder                                 \n"     \
1707         "       "STR(gas_hardfloat)"                            \n"     \
1708         "       ctc1    %0,"STR(dest)"                          \n"     \
1709         "       .set    pop                                     \n"     \
1710         : : "r" (val));                                                 \
1711 } while (0)
1712
1713 #ifdef GAS_HAS_SET_HARDFLOAT
1714 #define read_32bit_cp1_register(source)                                 \
1715         _read_32bit_cp1_register(source, .set hardfloat)
1716 #define write_32bit_cp1_register(dest, val)                             \
1717         _write_32bit_cp1_register(dest, val, .set hardfloat)
1718 #else
1719 #define read_32bit_cp1_register(source)                                 \
1720         _read_32bit_cp1_register(source, )
1721 #define write_32bit_cp1_register(dest, val)                             \
1722         _write_32bit_cp1_register(dest, val, )
1723 #endif
1724
1725 #ifdef HAVE_AS_DSP
1726 #define rddsp(mask)                                                     \
1727 ({                                                                      \
1728         unsigned int __dspctl;                                          \
1729                                                                         \
1730         __asm__ __volatile__(                                           \
1731         "       .set push                                       \n"     \
1732         "       .set dsp                                        \n"     \
1733         "       rddsp   %0, %x1                                 \n"     \
1734         "       .set pop                                        \n"     \
1735         : "=r" (__dspctl)                                               \
1736         : "i" (mask));                                                  \
1737         __dspctl;                                                       \
1738 })
1739
1740 #define wrdsp(val, mask)                                                \
1741 do {                                                                    \
1742         __asm__ __volatile__(                                           \
1743         "       .set push                                       \n"     \
1744         "       .set dsp                                        \n"     \
1745         "       wrdsp   %0, %x1                                 \n"     \
1746         "       .set pop                                        \n"     \
1747         :                                                               \
1748         : "r" (val), "i" (mask));                                       \
1749 } while (0)
1750
1751 #define mflo0()                                                         \
1752 ({                                                                      \
1753         long mflo0;                                                     \
1754         __asm__(                                                        \
1755         "       .set push                                       \n"     \
1756         "       .set dsp                                        \n"     \
1757         "       mflo %0, $ac0                                   \n"     \
1758         "       .set pop                                        \n"     \
1759         : "=r" (mflo0));                                                \
1760         mflo0;                                                          \
1761 })
1762
1763 #define mflo1()                                                         \
1764 ({                                                                      \
1765         long mflo1;                                                     \
1766         __asm__(                                                        \
1767         "       .set push                                       \n"     \
1768         "       .set dsp                                        \n"     \
1769         "       mflo %0, $ac1                                   \n"     \
1770         "       .set pop                                        \n"     \
1771         : "=r" (mflo1));                                                \
1772         mflo1;                                                          \
1773 })
1774
1775 #define mflo2()                                                         \
1776 ({                                                                      \
1777         long mflo2;                                                     \
1778         __asm__(                                                        \
1779         "       .set push                                       \n"     \
1780         "       .set dsp                                        \n"     \
1781         "       mflo %0, $ac2                                   \n"     \
1782         "       .set pop                                        \n"     \
1783         : "=r" (mflo2));                                                \
1784         mflo2;                                                          \
1785 })
1786
1787 #define mflo3()                                                         \
1788 ({                                                                      \
1789         long mflo3;                                                     \
1790         __asm__(                                                        \
1791         "       .set push                                       \n"     \
1792         "       .set dsp                                        \n"     \
1793         "       mflo %0, $ac3                                   \n"     \
1794         "       .set pop                                        \n"     \
1795         : "=r" (mflo3));                                                \
1796         mflo3;                                                          \
1797 })
1798
1799 #define mfhi0()                                                         \
1800 ({                                                                      \
1801         long mfhi0;                                                     \
1802         __asm__(                                                        \
1803         "       .set push                                       \n"     \
1804         "       .set dsp                                        \n"     \
1805         "       mfhi %0, $ac0                                   \n"     \
1806         "       .set pop                                        \n"     \
1807         : "=r" (mfhi0));                                                \
1808         mfhi0;                                                          \
1809 })
1810
1811 #define mfhi1()                                                         \
1812 ({                                                                      \
1813         long mfhi1;                                                     \
1814         __asm__(                                                        \
1815         "       .set push                                       \n"     \
1816         "       .set dsp                                        \n"     \
1817         "       mfhi %0, $ac1                                   \n"     \
1818         "       .set pop                                        \n"     \
1819         : "=r" (mfhi1));                                                \
1820         mfhi1;                                                          \
1821 })
1822
1823 #define mfhi2()                                                         \
1824 ({                                                                      \
1825         long mfhi2;                                                     \
1826         __asm__(                                                        \
1827         "       .set push                                       \n"     \
1828         "       .set dsp                                        \n"     \
1829         "       mfhi %0, $ac2                                   \n"     \
1830         "       .set pop                                        \n"     \
1831         : "=r" (mfhi2));                                                \
1832         mfhi2;                                                          \
1833 })
1834
1835 #define mfhi3()                                                         \
1836 ({                                                                      \
1837         long mfhi3;                                                     \
1838         __asm__(                                                        \
1839         "       .set push                                       \n"     \
1840         "       .set dsp                                        \n"     \
1841         "       mfhi %0, $ac3                                   \n"     \
1842         "       .set pop                                        \n"     \
1843         : "=r" (mfhi3));                                                \
1844         mfhi3;                                                          \
1845 })
1846
1847
1848 #define mtlo0(x)                                                        \
1849 ({                                                                      \
1850         __asm__(                                                        \
1851         "       .set push                                       \n"     \
1852         "       .set dsp                                        \n"     \
1853         "       mtlo %0, $ac0                                   \n"     \
1854         "       .set pop                                        \n"     \
1855         :                                                               \
1856         : "r" (x));                                                     \
1857 })
1858
1859 #define mtlo1(x)                                                        \
1860 ({                                                                      \
1861         __asm__(                                                        \
1862         "       .set push                                       \n"     \
1863         "       .set dsp                                        \n"     \
1864         "       mtlo %0, $ac1                                   \n"     \
1865         "       .set pop                                        \n"     \
1866         :                                                               \
1867         : "r" (x));                                                     \
1868 })
1869
1870 #define mtlo2(x)                                                        \
1871 ({                                                                      \
1872         __asm__(                                                        \
1873         "       .set push                                       \n"     \
1874         "       .set dsp                                        \n"     \
1875         "       mtlo %0, $ac2                                   \n"     \
1876         "       .set pop                                        \n"     \
1877         :                                                               \
1878         : "r" (x));                                                     \
1879 })
1880
1881 #define mtlo3(x)                                                        \
1882 ({                                                                      \
1883         __asm__(                                                        \
1884         "       .set push                                       \n"     \
1885         "       .set dsp                                        \n"     \
1886         "       mtlo %0, $ac3                                   \n"     \
1887         "       .set pop                                        \n"     \
1888         :                                                               \
1889         : "r" (x));                                                     \
1890 })
1891
1892 #define mthi0(x)                                                        \
1893 ({                                                                      \
1894         __asm__(                                                        \
1895         "       .set push                                       \n"     \
1896         "       .set dsp                                        \n"     \
1897         "       mthi %0, $ac0                                   \n"     \
1898         "       .set pop                                        \n"     \
1899         :                                                               \
1900         : "r" (x));                                                     \
1901 })
1902
1903 #define mthi1(x)                                                        \
1904 ({                                                                      \
1905         __asm__(                                                        \
1906         "       .set push                                       \n"     \
1907         "       .set dsp                                        \n"     \
1908         "       mthi %0, $ac1                                   \n"     \
1909         "       .set pop                                        \n"     \
1910         :                                                               \
1911         : "r" (x));                                                     \
1912 })
1913
1914 #define mthi2(x)                                                        \
1915 ({                                                                      \
1916         __asm__(                                                        \
1917         "       .set push                                       \n"     \
1918         "       .set dsp                                        \n"     \
1919         "       mthi %0, $ac2                                   \n"     \
1920         "       .set pop                                        \n"     \
1921         :                                                               \
1922         : "r" (x));                                                     \
1923 })
1924
1925 #define mthi3(x)                                                        \
1926 ({                                                                      \
1927         __asm__(                                                        \
1928         "       .set push                                       \n"     \
1929         "       .set dsp                                        \n"     \
1930         "       mthi %0, $ac3                                   \n"     \
1931         "       .set pop                                        \n"     \
1932         :                                                               \
1933         : "r" (x));                                                     \
1934 })
1935
1936 #else
1937
1938 #ifdef CONFIG_CPU_MICROMIPS
1939 #define rddsp(mask)                                                     \
1940 ({                                                                      \
1941         unsigned int __res;                                             \
1942                                                                         \
1943         __asm__ __volatile__(                                           \
1944         "       .set    push                                    \n"     \
1945         "       .set    noat                                    \n"     \
1946         "       # rddsp $1, %x1                                 \n"     \
1947         "       .hword  ((0x0020067c | (%x1 << 14)) >> 16)      \n"     \
1948         "       .hword  ((0x0020067c | (%x1 << 14)) & 0xffff)   \n"     \
1949         "       move    %0, $1                                  \n"     \
1950         "       .set    pop                                     \n"     \
1951         : "=r" (__res)                                                  \
1952         : "i" (mask));                                                  \
1953         __res;                                                          \
1954 })
1955
1956 #define wrdsp(val, mask)                                                \
1957 do {                                                                    \
1958         __asm__ __volatile__(                                           \
1959         "       .set    push                                    \n"     \
1960         "       .set    noat                                    \n"     \
1961         "       move    $1, %0                                  \n"     \
1962         "       # wrdsp $1, %x1                                 \n"     \
1963         "       .hword  ((0x0020167c | (%x1 << 14)) >> 16)      \n"     \
1964         "       .hword  ((0x0020167c | (%x1 << 14)) & 0xffff)   \n"     \
1965         "       .set    pop                                     \n"     \
1966         :                                                               \
1967         : "r" (val), "i" (mask));                                       \
1968 } while (0)
1969
1970 #define _umips_dsp_mfxxx(ins)                                           \
1971 ({                                                                      \
1972         unsigned long __treg;                                           \
1973                                                                         \
1974         __asm__ __volatile__(                                           \
1975         "       .set    push                                    \n"     \
1976         "       .set    noat                                    \n"     \
1977         "       .hword  0x0001                                  \n"     \
1978         "       .hword  %x1                                     \n"     \
1979         "       move    %0, $1                                  \n"     \
1980         "       .set    pop                                     \n"     \
1981         : "=r" (__treg)                                                 \
1982         : "i" (ins));                                                   \
1983         __treg;                                                         \
1984 })
1985
1986 #define _umips_dsp_mtxxx(val, ins)                                      \
1987 do {                                                                    \
1988         __asm__ __volatile__(                                           \
1989         "       .set    push                                    \n"     \
1990         "       .set    noat                                    \n"     \
1991         "       move    $1, %0                                  \n"     \
1992         "       .hword  0x0001                                  \n"     \
1993         "       .hword  %x1                                     \n"     \
1994         "       .set    pop                                     \n"     \
1995         :                                                               \
1996         : "r" (val), "i" (ins));                                        \
1997 } while (0)
1998
1999 #define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c)
2000 #define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)
2001
2002 #define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
2003 #define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
2004
2005 #define mflo0() _umips_dsp_mflo(0)
2006 #define mflo1() _umips_dsp_mflo(1)
2007 #define mflo2() _umips_dsp_mflo(2)
2008 #define mflo3() _umips_dsp_mflo(3)
2009
2010 #define mfhi0() _umips_dsp_mfhi(0)
2011 #define mfhi1() _umips_dsp_mfhi(1)
2012 #define mfhi2() _umips_dsp_mfhi(2)
2013 #define mfhi3() _umips_dsp_mfhi(3)
2014
2015 #define mtlo0(x) _umips_dsp_mtlo(x, 0)
2016 #define mtlo1(x) _umips_dsp_mtlo(x, 1)
2017 #define mtlo2(x) _umips_dsp_mtlo(x, 2)
2018 #define mtlo3(x) _umips_dsp_mtlo(x, 3)
2019
2020 #define mthi0(x) _umips_dsp_mthi(x, 0)
2021 #define mthi1(x) _umips_dsp_mthi(x, 1)
2022 #define mthi2(x) _umips_dsp_mthi(x, 2)
2023 #define mthi3(x) _umips_dsp_mthi(x, 3)
2024
2025 #else  /* !CONFIG_CPU_MICROMIPS */
2026 #define rddsp(mask)                                                     \
2027 ({                                                                      \
2028         unsigned int __res;                                             \
2029                                                                         \
2030         __asm__ __volatile__(                                           \
2031         "       .set    push                            \n"             \
2032         "       .set    noat                            \n"             \
2033         "       # rddsp $1, %x1                         \n"             \
2034         "       .word   0x7c000cb8 | (%x1 << 16)        \n"             \
2035         "       move    %0, $1                          \n"             \
2036         "       .set    pop                             \n"             \
2037         : "=r" (__res)                                                  \
2038         : "i" (mask));                                                  \
2039         __res;                                                          \
2040 })
2041
2042 #define wrdsp(val, mask)                                                \
2043 do {                                                                    \
2044         __asm__ __volatile__(                                           \
2045         "       .set    push                                    \n"     \
2046         "       .set    noat                                    \n"     \
2047         "       move    $1, %0                                  \n"     \
2048         "       # wrdsp $1, %x1                                 \n"     \
2049         "       .word   0x7c2004f8 | (%x1 << 11)                \n"     \
2050         "       .set    pop                                     \n"     \
2051         :                                                               \
2052         : "r" (val), "i" (mask));                                       \
2053 } while (0)
2054
2055 #define _dsp_mfxxx(ins)                                                 \
2056 ({                                                                      \
2057         unsigned long __treg;                                           \
2058                                                                         \
2059         __asm__ __volatile__(                                           \
2060         "       .set    push                                    \n"     \
2061         "       .set    noat                                    \n"     \
2062         "       .word   (0x00000810 | %1)                       \n"     \
2063         "       move    %0, $1                                  \n"     \
2064         "       .set    pop                                     \n"     \
2065         : "=r" (__treg)                                                 \
2066         : "i" (ins));                                                   \
2067         __treg;                                                         \
2068 })
2069
2070 #define _dsp_mtxxx(val, ins)                                            \
2071 do {                                                                    \
2072         __asm__ __volatile__(                                           \
2073         "       .set    push                                    \n"     \
2074         "       .set    noat                                    \n"     \
2075         "       move    $1, %0                                  \n"     \
2076         "       .word   (0x00200011 | %1)                       \n"     \
2077         "       .set    pop                                     \n"     \
2078         :                                                               \
2079         : "r" (val), "i" (ins));                                        \
2080 } while (0)
2081
2082 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
2083 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
2084
2085 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
2086 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
2087
2088 #define mflo0() _dsp_mflo(0)
2089 #define mflo1() _dsp_mflo(1)
2090 #define mflo2() _dsp_mflo(2)
2091 #define mflo3() _dsp_mflo(3)
2092
2093 #define mfhi0() _dsp_mfhi(0)
2094 #define mfhi1() _dsp_mfhi(1)
2095 #define mfhi2() _dsp_mfhi(2)
2096 #define mfhi3() _dsp_mfhi(3)
2097
2098 #define mtlo0(x) _dsp_mtlo(x, 0)
2099 #define mtlo1(x) _dsp_mtlo(x, 1)
2100 #define mtlo2(x) _dsp_mtlo(x, 2)
2101 #define mtlo3(x) _dsp_mtlo(x, 3)
2102
2103 #define mthi0(x) _dsp_mthi(x, 0)
2104 #define mthi1(x) _dsp_mthi(x, 1)
2105 #define mthi2(x) _dsp_mthi(x, 2)
2106 #define mthi3(x) _dsp_mthi(x, 3)
2107
2108 #endif /* CONFIG_CPU_MICROMIPS */
2109 #endif
2110
2111 /*
2112  * TLB operations.
2113  *
2114  * It is responsibility of the caller to take care of any TLB hazards.
2115  */
2116 static inline void tlb_probe(void)
2117 {
2118         __asm__ __volatile__(
2119                 ".set noreorder\n\t"
2120                 "tlbp\n\t"
2121                 ".set reorder");
2122 }
2123
2124 static inline void tlb_read(void)
2125 {
2126 #if MIPS34K_MISSED_ITLB_WAR
2127         int res = 0;
2128
2129         __asm__ __volatile__(
2130         "       .set    push                                    \n"
2131         "       .set    noreorder                               \n"
2132         "       .set    noat                                    \n"
2133         "       .set    mips32r2                                \n"
2134         "       .word   0x41610001              # dvpe $1       \n"
2135         "       move    %0, $1                                  \n"
2136         "       ehb                                             \n"
2137         "       .set    pop                                     \n"
2138         : "=r" (res));
2139
2140         instruction_hazard();
2141 #endif
2142
2143         __asm__ __volatile__(
2144                 ".set noreorder\n\t"
2145                 "tlbr\n\t"
2146                 ".set reorder");
2147
2148 #if MIPS34K_MISSED_ITLB_WAR
2149         if ((res & _ULCAST_(1)))
2150                 __asm__ __volatile__(
2151                 "       .set    push                            \n"
2152                 "       .set    noreorder                       \n"
2153                 "       .set    noat                            \n"
2154                 "       .set    mips32r2                        \n"
2155                 "       .word   0x41600021      # evpe          \n"
2156                 "       ehb                                     \n"
2157                 "       .set    pop                             \n");
2158 #endif
2159 }
2160
2161 static inline void tlb_write_indexed(void)
2162 {
2163         __asm__ __volatile__(
2164                 ".set noreorder\n\t"
2165                 "tlbwi\n\t"
2166                 ".set reorder");
2167 }
2168
2169 static inline void tlb_write_random(void)
2170 {
2171         __asm__ __volatile__(
2172                 ".set noreorder\n\t"
2173                 "tlbwr\n\t"
2174                 ".set reorder");
2175 }
2176
2177 /*
2178  * Manipulate bits in a c0 register.
2179  */
2180 #define __BUILD_SET_C0(name)                                    \
2181 static inline unsigned int                                      \
2182 set_c0_##name(unsigned int set)                                 \
2183 {                                                               \
2184         unsigned int res, new;                                  \
2185                                                                 \
2186         res = read_c0_##name();                                 \
2187         new = res | set;                                        \
2188         write_c0_##name(new);                                   \
2189                                                                 \
2190         return res;                                             \
2191 }                                                               \
2192                                                                 \
2193 static inline unsigned int                                      \
2194 clear_c0_##name(unsigned int clear)                             \
2195 {                                                               \
2196         unsigned int res, new;                                  \
2197                                                                 \
2198         res = read_c0_##name();                                 \
2199         new = res & ~clear;                                     \
2200         write_c0_##name(new);                                   \
2201                                                                 \
2202         return res;                                             \
2203 }                                                               \
2204                                                                 \
2205 static inline unsigned int                                      \
2206 change_c0_##name(unsigned int change, unsigned int val)         \
2207 {                                                               \
2208         unsigned int res, new;                                  \
2209                                                                 \
2210         res = read_c0_##name();                                 \
2211         new = res & ~change;                                    \
2212         new |= (val & change);                                  \
2213         write_c0_##name(new);                                   \
2214                                                                 \
2215         return res;                                             \
2216 }
2217
2218 __BUILD_SET_C0(status)
2219 __BUILD_SET_C0(cause)
2220 __BUILD_SET_C0(config)
2221 __BUILD_SET_C0(config5)
2222 __BUILD_SET_C0(intcontrol)
2223 __BUILD_SET_C0(intctl)
2224 __BUILD_SET_C0(srsmap)
2225 __BUILD_SET_C0(pagegrain)
2226 __BUILD_SET_C0(guestctl0)
2227 __BUILD_SET_C0(guestctl0ext)
2228 __BUILD_SET_C0(guestctl1)
2229 __BUILD_SET_C0(guestctl2)
2230 __BUILD_SET_C0(guestctl3)
2231 __BUILD_SET_C0(brcm_config_0)
2232 __BUILD_SET_C0(brcm_bus_pll)
2233 __BUILD_SET_C0(brcm_reset)
2234 __BUILD_SET_C0(brcm_cmt_intr)
2235 __BUILD_SET_C0(brcm_cmt_ctrl)
2236 __BUILD_SET_C0(brcm_config)
2237 __BUILD_SET_C0(brcm_mode)
2238
2239 /*
2240  * Return low 10 bits of ebase.
2241  * Note that under KVM (MIPSVZ) this returns vcpu id.
2242  */
2243 static inline unsigned int get_ebase_cpunum(void)
2244 {
2245         return read_c0_ebase() & MIPS_EBASE_CPUNUM;
2246 }
2247
2248 #endif /* !__ASSEMBLY__ */
2249
2250 #endif /* _ASM_MIPSREGS_H */