arch/mips/kernel/smp-cps.c

   1 /*
   2  * Copyright (C) 2013 Imagination Technologies
   3  * Author: Paul Burton <paul.burton@imgtec.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation;  either version 2 of the  License, or (at your
   8  * option) any later version.
   9  */
  10
  11 #include <linux/delay.h>
  12 #include <linux/io.h>
  13 #include <linux/irqchip/mips-gic.h>
  14 #include <linux/sched.h>
  15 #include <linux/slab.h>
  16 #include <linux/smp.h>
  17 #include <linux/types.h>
  18
  19 #include <asm/bcache.h>
  20 #include <asm/mips-cm.h>
  21 #include <asm/mips-cpc.h>
  22 #include <asm/mips_mt.h>
  23 #include <asm/mipsregs.h>
  24 #include <asm/pm-cps.h>
  25 #include <asm/r4kcache.h>
  26 #include <asm/smp-cps.h>
  27 #include <asm/time.h>
  28 #include <asm/uasm.h>
  29
  30 static bool threads_disabled;
  31 static DECLARE_BITMAP(core_power, NR_CPUS);
  32
  33 struct core_boot_config *mips_cps_core_bootcfg;
  34
  35 static int __init setup_nothreads(char *s)
  36 {
  37         threads_disabled = true;
  38         return 0;
  39 }
  40 early_param("nothreads", setup_nothreads);
  41
  42 static unsigned core_vpe_count(unsigned core)
  43 {
  44         unsigned cfg;
  45
  46         if (threads_disabled)
  47                 return 1;
  48
  49         if ((!config_enabled(CONFIG_MIPS_MT_SMP) || !cpu_has_mipsmt)
  50                 && (!config_enabled(CONFIG_CPU_MIPSR6) || !cpu_has_vp))
  51                 return 1;
  52
  53         mips_cm_lock_other(core, 0);
  54         cfg = read_gcr_co_config() & CM_GCR_Cx_CONFIG_PVPE_MSK;
  55         mips_cm_unlock_other();
  56         return (cfg >> CM_GCR_Cx_CONFIG_PVPE_SHF) + 1;
  57 }
  58
  59 static void __init cps_smp_setup(void)
  60 {
  61         unsigned int ncores, nvpes, core_vpes;
  62         unsigned long core_entry;
  63         int c, v;
  64
  65         /* Detect & record VPE topology */
  66         ncores = mips_cm_numcores();
  67         pr_info("%s topology ", cpu_has_mips_r6 ? "VP" : "VPE");
  68         for (c = nvpes = 0; c < ncores; c++) {
  69                 core_vpes = core_vpe_count(c);
  70                 pr_cont("%c%u", c ? ',' : '{', core_vpes);
  71
  72                 /* Use the number of VPEs in core 0 for smp_num_siblings */
  73                 if (!c)
  74                         smp_num_siblings = core_vpes;
  75
  76                 for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) {
  77                         cpu_data[nvpes + v].core = c;
  78 #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_CPU_MIPSR6)
  79                         cpu_data[nvpes + v].vpe_id = v;
  80 #endif
  81                 }
  82
  83                 nvpes += core_vpes;
  84         }
  85         pr_cont("} total %u\n", nvpes);
  86
  87         /* Indicate present CPUs (CPU being synonymous with VPE) */
  88         for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) {
  89                 set_cpu_possible(v, true);
  90                 set_cpu_present(v, true);
  91                 __cpu_number_map[v] = v;
  92                 __cpu_logical_map[v] = v;
  93         }
  94
  95         /* Set a coherent default CCA (CWB) */
  96         change_c0_config(CONF_CM_CMASK, 0x5);
  97
  98         /* Core 0 is powered up (we're running on it) */
  99         bitmap_set(core_power, 0, 1);
 100
 101         /* Initialise core 0 */
 102         mips_cps_core_init();
 103
 104         /* Make core 0 coherent with everything */
 105         write_gcr_cl_coherence(0xff);
 106
 107         if (mips_cm_revision() >= CM_REV_CM3) {
 108                 core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry);
 109                 write_gcr_bev_base(core_entry);
 110         }
 111
 112 #ifdef CONFIG_MIPS_MT_FPAFF
 113         /* If we have an FPU, enroll ourselves in the FPU-full mask */
 114         if (cpu_has_fpu)
 115                 cpumask_set_cpu(0, &mt_fpu_cpumask);
 116 #endif /* CONFIG_MIPS_MT_FPAFF */
 117 }
 118
 119 static void __init cps_prepare_cpus(unsigned int max_cpus)
 120 {
 121         unsigned ncores, core_vpes, c, cca;
 122         bool cca_unsuitable;
 123         u32 *entry_code;
 124
 125         mips_mt_set_cpuoptions();
 126
 127         /* Detect whether the CCA is unsuited to multi-core SMP */
 128         cca = read_c0_config() & CONF_CM_CMASK;
 129         switch (cca) {
 130         case 0x4: /* CWBE */
 131         case 0x5: /* CWB */
 132                 /* The CCA is coherent, multi-core is fine */
 133                 cca_unsuitable = false;
 134                 break;
 135
 136         default:
 137                 /* CCA is not coherent, multi-core is not usable */
 138                 cca_unsuitable = true;
 139         }
 140
 141         /* Warn the user if the CCA prevents multi-core */
 142         ncores = mips_cm_numcores();
 143         if (cca_unsuitable && ncores > 1) {
 144                 pr_warn("Using only one core due to unsuitable CCA 0x%x\n",
 145                         cca);
 146
 147                 for_each_present_cpu(c) {
 148                         if (cpu_data[c].core)
 149                                 set_cpu_present(c, false);
 150                 }
 151         }
 152
 153         /*
 154          * Patch the start of mips_cps_core_entry to provide:
 155          *
 156          * s0 = kseg0 CCA
 157          */
 158         entry_code = (u32 *)&mips_cps_core_entry;
 159         uasm_i_addiu(&entry_code, 16, 0, cca);
 160         blast_dcache_range((unsigned long)&mips_cps_core_entry,
 161                            (unsigned long)entry_code);
 162         bc_wback_inv((unsigned long)&mips_cps_core_entry,
 163                      (void *)entry_code - (void *)&mips_cps_core_entry);
 164         __sync();
 165
 166         /* Allocate core boot configuration structs */
 167         mips_cps_core_bootcfg = kcalloc(ncores, sizeof(*mips_cps_core_bootcfg),
 168                                         GFP_KERNEL);
 169         if (!mips_cps_core_bootcfg) {
 170                 pr_err("Failed to allocate boot config for %u cores\n", ncores);
 171                 goto err_out;
 172         }
 173
 174         /* Allocate VPE boot configuration structs */
 175         for (c = 0; c < ncores; c++) {
 176                 core_vpes = core_vpe_count(c);
 177                 mips_cps_core_bootcfg[c].vpe_config = kcalloc(core_vpes,
 178                                 sizeof(*mips_cps_core_bootcfg[c].vpe_config),
 179                                 GFP_KERNEL);
 180                 if (!mips_cps_core_bootcfg[c].vpe_config) {
 181                         pr_err("Failed to allocate %u VPE boot configs\n",
 182                                core_vpes);
 183                         goto err_out;
 184                 }
 185         }
 186
 187         /* Mark this CPU as booted */
 188         atomic_set(&mips_cps_core_bootcfg[current_cpu_data.core].vpe_mask,
 189                    1 << cpu_vpe_id(&current_cpu_data));
 190
 191         return;
 192 err_out:
 193         /* Clean up allocations */
 194         if (mips_cps_core_bootcfg) {
 195                 for (c = 0; c < ncores; c++)
 196                         kfree(mips_cps_core_bootcfg[c].vpe_config);
 197                 kfree(mips_cps_core_bootcfg);
 198                 mips_cps_core_bootcfg = NULL;
 199         }
 200
 201         /* Effectively disable SMP by declaring CPUs not present */
 202         for_each_possible_cpu(c) {
 203                 if (c == 0)
 204                         continue;
 205                 set_cpu_present(c, false);
 206         }
 207 }
 208
 209 static void boot_core(unsigned core)
 210 {
 211         u32 access, stat, seq_state;
 212         unsigned timeout;
 213
 214         /* Select the appropriate core */
 215         mips_cm_lock_other(core, 0);
 216
 217         /* Set its reset vector */
 218         write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry));
 219
 220         /* Ensure its coherency is disabled */
 221         write_gcr_co_coherence(0);
 222
 223         /* Start it with the legacy memory map and exception base */
 224         write_gcr_co_reset_ext_base(CM_GCR_RESET_EXT_BASE_UEB);
 225
 226         /* Ensure the core can access the GCRs */
 227         access = read_gcr_access();
 228         access |= 1 << (CM_GCR_ACCESS_ACCESSEN_SHF + core);
 229         write_gcr_access(access);
 230
 231         if (mips_cpc_present()) {
 232                 /* Reset the core */
 233                 mips_cpc_lock_other(core);
 234
 235                 if (mips_cm_revision() >= CM_REV_CM3) {
 236                         /* Run VP0 following the reset */
 237                         write_cpc_co_vp_run(0x1);
 238
 239                         /*
 240                          * Ensure that the VP_RUN register is written before the
 241                          * core leaves reset.
 242                          */
 243                         wmb();
 244                 }
 245
 246                 write_cpc_co_cmd(CPC_Cx_CMD_RESET);
 247
 248                 timeout = 100;
 249                 while (true) {
 250                         stat = read_cpc_co_stat_conf();
 251                         seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE_MSK;
 252
 253                         /* U6 == coherent execution, ie. the core is up */
 254                         if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U6)
 255                                 break;
 256
 257                         /* Delay a little while before we start warning */
 258                         if (timeout) {
 259                                 timeout--;
 260                                 mdelay(10);
 261                                 continue;
 262                         }
 263
 264                         pr_warn("Waiting for core %u to start... STAT_CONF=0x%x\n",
 265                                 core, stat);
 266                         mdelay(1000);
 267                 }
 268
 269                 mips_cpc_unlock_other();
 270         } else {
 271                 /* Take the core out of reset */
 272                 write_gcr_co_reset_release(0);
 273         }
 274
 275         mips_cm_unlock_other();
 276
 277         /* The core is now powered up */
 278         bitmap_set(core_power, core, 1);
 279 }
 280
 281 static void remote_vpe_boot(void *dummy)
 282 {
 283         unsigned core = current_cpu_data.core;
 284         struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
 285
 286         mips_cps_boot_vpes(core_cfg, cpu_vpe_id(&current_cpu_data));
 287 }
 288
 289 static void cps_boot_secondary(int cpu, struct task_struct *idle)
 290 {
 291         unsigned core = cpu_data[cpu].core;
 292         unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
 293         struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
 294         struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id];
 295         unsigned long core_entry;
 296         unsigned int remote;
 297         int err;
 298
 299         vpe_cfg->pc = (unsigned long)&smp_bootstrap;
 300         vpe_cfg->sp = __KSTK_TOS(idle);
 301         vpe_cfg->gp = (unsigned long)task_thread_info(idle);
 302
 303         atomic_or(1 << cpu_vpe_id(&cpu_data[cpu]), &core_cfg->vpe_mask);
 304
 305         preempt_disable();
 306
 307         if (!test_bit(core, core_power)) {
 308                 /* Boot a VPE on a powered down core */
 309                 boot_core(core);
 310                 goto out;
 311         }
 312
 313         if (cpu_has_vp) {
 314                 mips_cm_lock_other(core, vpe_id);
 315                 core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry);
 316                 write_gcr_co_reset_base(core_entry);
 317                 mips_cm_unlock_other();
 318         }
 319
 320         if (core != current_cpu_data.core) {
 321                 /* Boot a VPE on another powered up core */
 322                 for (remote = 0; remote < NR_CPUS; remote++) {
 323                         if (cpu_data[remote].core != core)
 324                                 continue;
 325                         if (cpu_online(remote))
 326                                 break;
 327                 }
 328                 BUG_ON(remote >= NR_CPUS);
 329
 330                 err = smp_call_function_single(remote, remote_vpe_boot,
 331                                                NULL, 1);
 332                 if (err)
 333                         panic("Failed to call remote CPU\n");
 334                 goto out;
 335         }
 336
 337         BUG_ON(!cpu_has_mipsmt && !cpu_has_vp);
 338
 339         /* Boot a VPE on this core */
 340         mips_cps_boot_vpes(core_cfg, vpe_id);
 341 out:
 342         preempt_enable();
 343 }
 344
 345 static void cps_init_secondary(void)
 346 {
 347         /* Disable MT - we only want to run 1 TC per VPE */
 348         if (cpu_has_mipsmt)
 349                 dmt();
 350
 351         if (mips_cm_revision() >= CM_REV_CM3) {
 352                 unsigned ident = gic_read_local_vp_id();
 353
 354                 /*
 355                  * Ensure that our calculation of the VP ID matches up with
 356                  * what the GIC reports, otherwise we'll have configured
 357                  * interrupts incorrectly.
 358                  */
 359                 BUG_ON(ident != mips_cm_vp_id(smp_processor_id()));
 360         }
 361
 362         change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 |
 363                                  STATUSF_IP5 | STATUSF_IP6 | STATUSF_IP7);
 364 }
 365
 366 static void cps_smp_finish(void)
 367 {
 368         write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ));
 369
 370 #ifdef CONFIG_MIPS_MT_FPAFF
 371         /* If we have an FPU, enroll ourselves in the FPU-full mask */
 372         if (cpu_has_fpu)
 373                 cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask);
 374 #endif /* CONFIG_MIPS_MT_FPAFF */
 375
 376         local_irq_enable();
 377 }
 378
 379 #ifdef CONFIG_HOTPLUG_CPU
 380
 381 static int cps_cpu_disable(void)
 382 {
 383         unsigned cpu = smp_processor_id();
 384         struct core_boot_config *core_cfg;
 385
 386         if (!cpu)
 387                 return -EBUSY;
 388
 389         if (!cps_pm_support_state(CPS_PM_POWER_GATED))
 390                 return -EINVAL;
 391
 392         core_cfg = &mips_cps_core_bootcfg[current_cpu_data.core];
 393         atomic_sub(1 << cpu_vpe_id(&current_cpu_data), &core_cfg->vpe_mask);
 394         smp_mb__after_atomic();
 395         set_cpu_online(cpu, false);
 396         cpumask_clear_cpu(cpu, &cpu_callin_map);
 397
 398         return 0;
 399 }
 400
 401 static DECLARE_COMPLETION(cpu_death_chosen);
 402 static unsigned cpu_death_sibling;
 403 static enum {
 404         CPU_DEATH_HALT,
 405         CPU_DEATH_POWER,
 406 } cpu_death;
 407
 408 void play_dead(void)
 409 {
 410         unsigned cpu, core;
 411
 412         local_irq_disable();
 413         idle_task_exit();
 414         cpu = smp_processor_id();
 415         cpu_death = CPU_DEATH_POWER;
 416
 417         if (cpu_has_mipsmt) {
 418                 core = cpu_data[cpu].core;
 419
 420                 /* Look for another online VPE within the core */
 421                 for_each_online_cpu(cpu_death_sibling) {
 422                         if (cpu_data[cpu_death_sibling].core != core)
 423                                 continue;
 424
 425                         /*
 426                          * There is an online VPE within the core. Just halt
 427                          * this TC and leave the core alone.
 428                          */
 429                         cpu_death = CPU_DEATH_HALT;
 430                         break;
 431                 }
 432         }
 433
 434         /* This CPU has chosen its way out */
 435         complete(&cpu_death_chosen);
 436
 437         if (cpu_death == CPU_DEATH_HALT) {
 438                 /* Halt this TC */
 439                 write_c0_tchalt(TCHALT_H);
 440                 instruction_hazard();
 441         } else {
 442                 /* Power down the core */
 443                 cps_pm_enter_state(CPS_PM_POWER_GATED);
 444         }
 445
 446         /* This should never be reached */
 447         panic("Failed to offline CPU %u", cpu);
 448 }
 449
 450 static void wait_for_sibling_halt(void *ptr_cpu)
 451 {
 452         unsigned cpu = (unsigned long)ptr_cpu;
 453         unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
 454         unsigned halted;
 455         unsigned long flags;
 456
 457         do {
 458                 local_irq_save(flags);
 459                 settc(vpe_id);
 460                 halted = read_tc_c0_tchalt();
 461                 local_irq_restore(flags);
 462         } while (!(halted & TCHALT_H));
 463 }
 464
 465 static void cps_cpu_die(unsigned int cpu)
 466 {
 467         unsigned core = cpu_data[cpu].core;
 468         unsigned stat;
 469         int err;
 470
 471         /* Wait for the cpu to choose its way out */
 472         if (!wait_for_completion_timeout(&cpu_death_chosen,
 473                                          msecs_to_jiffies(5000))) {
 474                 pr_err("CPU%u: didn't offline\n", cpu);
 475                 return;
 476         }
 477
 478         /*
 479          * Now wait for the CPU to actually offline. Without doing this that
 480          * offlining may race with one or more of:
 481          *
 482          *   - Onlining the CPU again.
 483          *   - Powering down the core if another VPE within it is offlined.
 484          *   - A sibling VPE entering a non-coherent state.
 485          *
 486          * In the non-MT halt case (ie. infinite loop) the CPU is doing nothing
 487          * with which we could race, so do nothing.
 488          */
 489         if (cpu_death == CPU_DEATH_POWER) {
 490                 /*
 491                  * Wait for the core to enter a powered down or clock gated
 492                  * state, the latter happening when a JTAG probe is connected
 493                  * in which case the CPC will refuse to power down the core.
 494                  */
 495                 do {
 496                         mips_cpc_lock_other(core);
 497                         stat = read_cpc_co_stat_conf();
 498                         stat &= CPC_Cx_STAT_CONF_SEQSTATE_MSK;
 499                         mips_cpc_unlock_other();
 500                 } while (stat != CPC_Cx_STAT_CONF_SEQSTATE_D0 &&
 501                          stat != CPC_Cx_STAT_CONF_SEQSTATE_D2 &&
 502                          stat != CPC_Cx_STAT_CONF_SEQSTATE_U2);
 503
 504                 /* Indicate the core is powered off */
 505                 bitmap_clear(core_power, core, 1);
 506         } else if (cpu_has_mipsmt) {
 507                 /*
 508                  * Have a CPU with access to the offlined CPUs registers wait
 509                  * for its TC to halt.
 510                  */
 511                 err = smp_call_function_single(cpu_death_sibling,
 512                                                wait_for_sibling_halt,
 513                                                (void *)(unsigned long)cpu, 1);
 514                 if (err)
 515                         panic("Failed to call remote sibling CPU\n");
 516         }
 517 }
 518
 519 #endif /* CONFIG_HOTPLUG_CPU */
 520
 521 static struct plat_smp_ops cps_smp_ops = {
 522         .smp_setup              = cps_smp_setup,
 523         .prepare_cpus           = cps_prepare_cpus,
 524         .boot_secondary         = cps_boot_secondary,
 525         .init_secondary         = cps_init_secondary,
 526         .smp_finish             = cps_smp_finish,
 527         .send_ipi_single        = mips_smp_send_ipi_single,
 528         .send_ipi_mask          = mips_smp_send_ipi_mask,
 529 #ifdef CONFIG_HOTPLUG_CPU
 530         .cpu_disable            = cps_cpu_disable,
 531         .cpu_die                = cps_cpu_die,
 532 #endif
 533 };
 534
 535 bool mips_cps_smp_in_use(void)
 536 {
 537         extern struct plat_smp_ops *mp_ops;
 538         return mp_ops == &cps_smp_ops;
 539 }
 540
 541 int register_cps_smp_ops(void)
 542 {
 543         if (!mips_cm_present()) {
 544                 pr_warn("MIPS CPS SMP unable to proceed without a CM\n");
 545                 return -ENODEV;
 546         }
 547
 548         /* check we have a GIC - we need one for IPIs */
 549         if (!(read_gcr_gic_status() & CM_GCR_GIC_STATUS_EX_MSK)) {
 550                 pr_warn("MIPS CPS SMP unable to proceed without a GIC\n");
 551                 return -ENODEV;
 552         }
 553
 554         register_smp_ops(&cps_smp_ops);
 555         return 0;
 556 }