arch/mips/kernel/traps.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
   7  * Copyright (C) 1995, 1996 Paul M. Antoine
   8  * Copyright (C) 1998 Ulf Carlsson
   9  * Copyright (C) 1999 Silicon Graphics, Inc.
  10  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  11  * Copyright (C) 2002, 2003, 2004, 2005, 2007  Maciej W. Rozycki
  12  * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc.  All rights reserved.
  13  */
  14 #include <linux/bug.h>
  15 #include <linux/compiler.h>
  16 #include <linux/context_tracking.h>
  17 #include <linux/kexec.h>
  18 #include <linux/init.h>
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/mm.h>
  22 #include <linux/sched.h>
  23 #include <linux/smp.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/kallsyms.h>
  26 #include <linux/bootmem.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/ptrace.h>
  29 #include <linux/kgdb.h>
  30 #include <linux/kdebug.h>
  31 #include <linux/kprobes.h>
  32 #include <linux/notifier.h>
  33 #include <linux/kdb.h>
  34 #include <linux/irq.h>
  35 #include <linux/perf_event.h>
  36
  37 #include <asm/bootinfo.h>
  38 #include <asm/branch.h>
  39 #include <asm/break.h>
  40 #include <asm/cop2.h>
  41 #include <asm/cpu.h>
  42 #include <asm/cpu-type.h>
  43 #include <asm/dsp.h>
  44 #include <asm/fpu.h>
  45 #include <asm/fpu_emulator.h>
  46 #include <asm/idle.h>
  47 #include <asm/mipsregs.h>
  48 #include <asm/mipsmtregs.h>
  49 #include <asm/module.h>
  50 #include <asm/pgtable.h>
  51 #include <asm/ptrace.h>
  52 #include <asm/sections.h>
  53 #include <asm/tlbdebug.h>
  54 #include <asm/traps.h>
  55 #include <asm/uaccess.h>
  56 #include <asm/watch.h>
  57 #include <asm/mmu_context.h>
  58 #include <asm/types.h>
  59 #include <asm/stacktrace.h>
  60 #include <asm/uasm.h>
  61
  62 extern void check_wait(void);
  63 extern asmlinkage void rollback_handle_int(void);
  64 extern asmlinkage void handle_int(void);
  65 extern u32 handle_tlbl[];
  66 extern u32 handle_tlbs[];
  67 extern u32 handle_tlbm[];
  68 extern asmlinkage void handle_adel(void);
  69 extern asmlinkage void handle_ades(void);
  70 extern asmlinkage void handle_ibe(void);
  71 extern asmlinkage void handle_dbe(void);
  72 extern asmlinkage void handle_sys(void);
  73 extern asmlinkage void handle_bp(void);
  74 extern asmlinkage void handle_ri(void);
  75 extern asmlinkage void handle_ri_rdhwr_vivt(void);
  76 extern asmlinkage void handle_ri_rdhwr(void);
  77 extern asmlinkage void handle_cpu(void);
  78 extern asmlinkage void handle_ov(void);
  79 extern asmlinkage void handle_tr(void);
  80 extern asmlinkage void handle_fpe(void);
  81 extern asmlinkage void handle_ftlb(void);
  82 extern asmlinkage void handle_mdmx(void);
  83 extern asmlinkage void handle_watch(void);
  84 extern asmlinkage void handle_mt(void);
  85 extern asmlinkage void handle_dsp(void);
  86 extern asmlinkage void handle_mcheck(void);
  87 extern asmlinkage void handle_reserved(void);
  88
  89 void (*board_be_init)(void);
  90 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
  91 void (*board_nmi_handler_setup)(void);
  92 void (*board_ejtag_handler_setup)(void);
  93 void (*board_bind_eic_interrupt)(int irq, int regset);
  94 void (*board_ebase_setup)(void);
  95 void(*board_cache_error_setup)(void);
  96
  97 static void show_raw_backtrace(unsigned long reg29)
  98 {
  99         unsigned long *sp = (unsigned long *)(reg29 & ~3);
 100         unsigned long addr;
 101
 102         printk("Call Trace:");
 103 #ifdef CONFIG_KALLSYMS
 104         printk("\n");
 105 #endif
 106         while (!kstack_end(sp)) {
 107                 unsigned long __user *p =
 108                         (unsigned long __user *)(unsigned long)sp++;
 109                 if (__get_user(addr, p)) {
 110                         printk(" (Bad stack address)");
 111                         break;
 112                 }
 113                 if (__kernel_text_address(addr))
 114                         print_ip_sym(addr);
 115         }
 116         printk("\n");
 117 }
 118
 119 #ifdef CONFIG_KALLSYMS
 120 int raw_show_trace;
 121 static int __init set_raw_show_trace(char *str)
 122 {
 123         raw_show_trace = 1;
 124         return 1;
 125 }
 126 __setup("raw_show_trace", set_raw_show_trace);
 127 #endif
 128
 129 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
 130 {
 131         unsigned long sp = regs->regs[29];
 132         unsigned long ra = regs->regs[31];
 133         unsigned long pc = regs->cp0_epc;
 134
 135         if (!task)
 136                 task = current;
 137
 138         if (raw_show_trace || !__kernel_text_address(pc)) {
 139                 show_raw_backtrace(sp);
 140                 return;
 141         }
 142         printk("Call Trace:\n");
 143         do {
 144                 print_ip_sym(pc);
 145                 pc = unwind_stack(task, &sp, pc, &ra);
 146         } while (pc);
 147         printk("\n");
 148 }
 149
 150 /*
 151  * This routine abuses get_user()/put_user() to reference pointers
 152  * with at least a bit of error checking ...
 153  */
 154 static void show_stacktrace(struct task_struct *task,
 155         const struct pt_regs *regs)
 156 {
 157         const int field = 2 * sizeof(unsigned long);
 158         long stackdata;
 159         int i;
 160         unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
 161
 162         printk("Stack :");
 163         i = 0;
 164         while ((unsigned long) sp & (PAGE_SIZE - 1)) {
 165                 if (i && ((i % (64 / field)) == 0))
 166                         printk("\n       ");
 167                 if (i > 39) {
 168                         printk(" ...");
 169                         break;
 170                 }
 171
 172                 if (__get_user(stackdata, sp++)) {
 173                         printk(" (Bad stack address)");
 174                         break;
 175                 }
 176
 177                 printk(" %0*lx", field, stackdata);
 178                 i++;
 179         }
 180         printk("\n");
 181         show_backtrace(task, regs);
 182 }
 183
 184 void show_stack(struct task_struct *task, unsigned long *sp)
 185 {
 186         struct pt_regs regs;
 187         if (sp) {
 188                 regs.regs[29] = (unsigned long)sp;
 189                 regs.regs[31] = 0;
 190                 regs.cp0_epc = 0;
 191         } else {
 192                 if (task && task != current) {
 193                         regs.regs[29] = task->thread.reg29;
 194                         regs.regs[31] = 0;
 195                         regs.cp0_epc = task->thread.reg31;
 196 #ifdef CONFIG_KGDB_KDB
 197                 } else if (atomic_read(&kgdb_active) != -1 &&
 198                            kdb_current_regs) {
 199                         memcpy(&regs, kdb_current_regs, sizeof(regs));
 200 #endif /* CONFIG_KGDB_KDB */
 201                 } else {
 202                         prepare_frametrace(&regs);
 203                 }
 204         }
 205         show_stacktrace(task, &regs);
 206 }
 207
 208 static void show_code(unsigned int __user *pc)
 209 {
 210         long i;
 211         unsigned short __user *pc16 = NULL;
 212
 213         printk("\nCode:");
 214
 215         if ((unsigned long)pc & 1)
 216                 pc16 = (unsigned short __user *)((unsigned long)pc & ~1);
 217         for(i = -3 ; i < 6 ; i++) {
 218                 unsigned int insn;
 219                 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
 220                         printk(" (Bad address in epc)\n");
 221                         break;
 222                 }
 223                 printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
 224         }
 225 }
 226
 227 static void __show_regs(const struct pt_regs *regs)
 228 {
 229         const int field = 2 * sizeof(unsigned long);
 230         unsigned int cause = regs->cp0_cause;
 231         int i;
 232
 233         show_regs_print_info(KERN_DEFAULT);
 234
 235         /*
 236          * Saved main processor registers
 237          */
 238         for (i = 0; i < 32; ) {
 239                 if ((i % 4) == 0)
 240                         printk("$%2d   :", i);
 241                 if (i == 0)
 242                         printk(" %0*lx", field, 0UL);
 243                 else if (i == 26 || i == 27)
 244                         printk(" %*s", field, "");
 245                 else
 246                         printk(" %0*lx", field, regs->regs[i]);
 247
 248                 i++;
 249                 if ((i % 4) == 0)
 250                         printk("\n");
 251         }
 252
 253 #ifdef CONFIG_CPU_HAS_SMARTMIPS
 254         printk("Acx    : %0*lx\n", field, regs->acx);
 255 #endif
 256         printk("Hi    : %0*lx\n", field, regs->hi);
 257         printk("Lo    : %0*lx\n", field, regs->lo);
 258
 259         /*
 260          * Saved cp0 registers
 261          */
 262         printk("epc   : %0*lx %pS\n", field, regs->cp0_epc,
 263                (void *) regs->cp0_epc);
 264         printk("    %s\n", print_tainted());
 265         printk("ra    : %0*lx %pS\n", field, regs->regs[31],
 266                (void *) regs->regs[31]);
 267
 268         printk("Status: %08x    ", (uint32_t) regs->cp0_status);
 269
 270         if (cpu_has_3kex) {
 271                 if (regs->cp0_status & ST0_KUO)
 272                         printk("KUo ");
 273                 if (regs->cp0_status & ST0_IEO)
 274                         printk("IEo ");
 275                 if (regs->cp0_status & ST0_KUP)
 276                         printk("KUp ");
 277                 if (regs->cp0_status & ST0_IEP)
 278                         printk("IEp ");
 279                 if (regs->cp0_status & ST0_KUC)
 280                         printk("KUc ");
 281                 if (regs->cp0_status & ST0_IEC)
 282                         printk("IEc ");
 283         } else if (cpu_has_4kex) {
 284                 if (regs->cp0_status & ST0_KX)
 285                         printk("KX ");
 286                 if (regs->cp0_status & ST0_SX)
 287                         printk("SX ");
 288                 if (regs->cp0_status & ST0_UX)
 289                         printk("UX ");
 290                 switch (regs->cp0_status & ST0_KSU) {
 291                 case KSU_USER:
 292                         printk("USER ");
 293                         break;
 294                 case KSU_SUPERVISOR:
 295                         printk("SUPERVISOR ");
 296                         break;
 297                 case KSU_KERNEL:
 298                         printk("KERNEL ");
 299                         break;
 300                 default:
 301                         printk("BAD_MODE ");
 302                         break;
 303                 }
 304                 if (regs->cp0_status & ST0_ERL)
 305                         printk("ERL ");
 306                 if (regs->cp0_status & ST0_EXL)
 307                         printk("EXL ");
 308                 if (regs->cp0_status & ST0_IE)
 309                         printk("IE ");
 310         }
 311         printk("\n");
 312
 313         printk("Cause : %08x\n", cause);
 314
 315         cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
 316         if (1 <= cause && cause <= 5)
 317                 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
 318
 319         printk("PrId  : %08x (%s)\n", read_c0_prid(),
 320                cpu_name_string());
 321 }
 322
 323 /*
 324  * FIXME: really the generic show_regs should take a const pointer argument.
 325  */
 326 void show_regs(struct pt_regs *regs)
 327 {
 328         __show_regs((struct pt_regs *)regs);
 329 }
 330
 331 void show_registers(struct pt_regs *regs)
 332 {
 333         const int field = 2 * sizeof(unsigned long);
 334         mm_segment_t old_fs = get_fs();
 335
 336         __show_regs(regs);
 337         print_modules();
 338         printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
 339                current->comm, current->pid, current_thread_info(), current,
 340               field, current_thread_info()->tp_value);
 341         if (cpu_has_userlocal) {
 342                 unsigned long tls;
 343
 344                 tls = read_c0_userlocal();
 345                 if (tls != current_thread_info()->tp_value)
 346                         printk("*HwTLS: %0*lx\n", field, tls);
 347         }
 348
 349         if (!user_mode(regs))
 350                 /* Necessary for getting the correct stack content */
 351                 set_fs(KERNEL_DS);
 352         show_stacktrace(current, regs);
 353         show_code((unsigned int __user *) regs->cp0_epc);
 354         printk("\n");
 355         set_fs(old_fs);
 356 }
 357
 358 static int regs_to_trapnr(struct pt_regs *regs)
 359 {
 360         return (regs->cp0_cause >> 2) & 0x1f;
 361 }
 362
 363 static DEFINE_RAW_SPINLOCK(die_lock);
 364
 365 void __noreturn die(const char *str, struct pt_regs *regs)
 366 {
 367         static int die_counter;
 368         int sig = SIGSEGV;
 369 #ifdef CONFIG_MIPS_MT_SMTC
 370         unsigned long dvpret;
 371 #endif /* CONFIG_MIPS_MT_SMTC */
 372
 373         oops_enter();
 374
 375         if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs),
 376                        SIGSEGV) == NOTIFY_STOP)
 377                 sig = 0;
 378
 379         console_verbose();
 380         raw_spin_lock_irq(&die_lock);
 381 #ifdef CONFIG_MIPS_MT_SMTC
 382         dvpret = dvpe();
 383 #endif /* CONFIG_MIPS_MT_SMTC */
 384         bust_spinlocks(1);
 385 #ifdef CONFIG_MIPS_MT_SMTC
 386         mips_mt_regdump(dvpret);
 387 #endif /* CONFIG_MIPS_MT_SMTC */
 388
 389         printk("%s[#%d]:\n", str, ++die_counter);
 390         show_registers(regs);
 391         add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
 392         raw_spin_unlock_irq(&die_lock);
 393
 394         oops_exit();
 395
 396         if (in_interrupt())
 397                 panic("Fatal exception in interrupt");
 398
 399         if (panic_on_oops) {
 400                 printk(KERN_EMERG "Fatal exception: panic in 5 seconds");
 401                 ssleep(5);
 402                 panic("Fatal exception");
 403         }
 404
 405         if (regs && kexec_should_crash(current))
 406                 crash_kexec(regs);
 407
 408         do_exit(sig);
 409 }
 410
 411 extern struct exception_table_entry __start___dbe_table[];
 412 extern struct exception_table_entry __stop___dbe_table[];
 413
 414 __asm__(
 415 "       .section        __dbe_table, \"a\"\n"
 416 "       .previous                       \n");
 417
 418 /* Given an address, look for it in the exception tables. */
 419 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
 420 {
 421         const struct exception_table_entry *e;
 422
 423         e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
 424         if (!e)
 425                 e = search_module_dbetables(addr);
 426         return e;
 427 }
 428
 429 asmlinkage void do_be(struct pt_regs *regs)
 430 {
 431         const int field = 2 * sizeof(unsigned long);
 432         const struct exception_table_entry *fixup = NULL;
 433         int data = regs->cp0_cause & 4;
 434         int action = MIPS_BE_FATAL;
 435         enum ctx_state prev_state;
 436
 437         prev_state = exception_enter();
 438         /* XXX For now.  Fixme, this searches the wrong table ...  */
 439         if (data && !user_mode(regs))
 440                 fixup = search_dbe_tables(exception_epc(regs));
 441
 442         if (fixup)
 443                 action = MIPS_BE_FIXUP;
 444
 445         if (board_be_handler)
 446                 action = board_be_handler(regs, fixup != NULL);
 447
 448         switch (action) {
 449         case MIPS_BE_DISCARD:
 450                 goto out;
 451         case MIPS_BE_FIXUP:
 452                 if (fixup) {
 453                         regs->cp0_epc = fixup->nextinsn;
 454                         goto out;
 455                 }
 456                 break;
 457         default:
 458                 break;
 459         }
 460
 461         /*
 462          * Assume it would be too dangerous to continue ...
 463          */
 464         printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
 465                data ? "Data" : "Instruction",
 466                field, regs->cp0_epc, field, regs->regs[31]);
 467         if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs),
 468                        SIGBUS) == NOTIFY_STOP)
 469                 goto out;
 470
 471         die_if_kernel("Oops", regs);
 472         force_sig(SIGBUS, current);
 473
 474 out:
 475         exception_exit(prev_state);
 476 }
 477
 478 /*
 479  * ll/sc, rdhwr, sync emulation
 480  */
 481
 482 #define OPCODE 0xfc000000
 483 #define BASE   0x03e00000
 484 #define RT     0x001f0000
 485 #define OFFSET 0x0000ffff
 486 #define LL     0xc0000000
 487 #define SC     0xe0000000
 488 #define SPEC0  0x00000000
 489 #define SPEC3  0x7c000000
 490 #define RD     0x0000f800
 491 #define FUNC   0x0000003f
 492 #define SYNC   0x0000000f
 493 #define RDHWR  0x0000003b
 494
 495 /*  microMIPS definitions   */
 496 #define MM_POOL32A_FUNC 0xfc00ffff
 497 #define MM_RDHWR        0x00006b3c
 498 #define MM_RS           0x001f0000
 499 #define MM_RT           0x03e00000
 500
 501 /*
 502  * The ll_bit is cleared by r*_switch.S
 503  */
 504
 505 unsigned int ll_bit;
 506 struct task_struct *ll_task;
 507
 508 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
 509 {
 510         unsigned long value, __user *vaddr;
 511         long offset;
 512
 513         /*
 514          * analyse the ll instruction that just caused a ri exception
 515          * and put the referenced address to addr.
 516          */
 517
 518         /* sign extend offset */
 519         offset = opcode & OFFSET;
 520         offset <<= 16;
 521         offset >>= 16;
 522
 523         vaddr = (unsigned long __user *)
 524                 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
 525
 526         if ((unsigned long)vaddr & 3)
 527                 return SIGBUS;
 528         if (get_user(value, vaddr))
 529                 return SIGSEGV;
 530
 531         preempt_disable();
 532
 533         if (ll_task == NULL || ll_task == current) {
 534                 ll_bit = 1;
 535         } else {
 536                 ll_bit = 0;
 537         }
 538         ll_task = current;
 539
 540         preempt_enable();
 541
 542         regs->regs[(opcode & RT) >> 16] = value;
 543
 544         return 0;
 545 }
 546
 547 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
 548 {
 549         unsigned long __user *vaddr;
 550         unsigned long reg;
 551         long offset;
 552
 553         /*
 554          * analyse the sc instruction that just caused a ri exception
 555          * and put the referenced address to addr.
 556          */
 557
 558         /* sign extend offset */
 559         offset = opcode & OFFSET;
 560         offset <<= 16;
 561         offset >>= 16;
 562
 563         vaddr = (unsigned long __user *)
 564                 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
 565         reg = (opcode & RT) >> 16;
 566
 567         if ((unsigned long)vaddr & 3)
 568                 return SIGBUS;
 569
 570         preempt_disable();
 571
 572         if (ll_bit == 0 || ll_task != current) {
 573                 regs->regs[reg] = 0;
 574                 preempt_enable();
 575                 return 0;
 576         }
 577
 578         preempt_enable();
 579
 580         if (put_user(regs->regs[reg], vaddr))
 581                 return SIGSEGV;
 582
 583         regs->regs[reg] = 1;
 584
 585         return 0;
 586 }
 587
 588 /*
 589  * ll uses the opcode of lwc0 and sc uses the opcode of swc0.  That is both
 590  * opcodes are supposed to result in coprocessor unusable exceptions if
 591  * executed on ll/sc-less processors.  That's the theory.  In practice a
 592  * few processors such as NEC's VR4100 throw reserved instruction exceptions
 593  * instead, so we're doing the emulation thing in both exception handlers.
 594  */
 595 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
 596 {
 597         if ((opcode & OPCODE) == LL) {
 598                 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
 599                                 1, regs, 0);
 600                 return simulate_ll(regs, opcode);
 601         }
 602         if ((opcode & OPCODE) == SC) {
 603                 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
 604                                 1, regs, 0);
 605                 return simulate_sc(regs, opcode);
 606         }
 607
 608         return -1;                      /* Must be something else ... */
 609 }
 610
 611 /*
 612  * Simulate trapping 'rdhwr' instructions to provide user accessible
 613  * registers not implemented in hardware.
 614  */
 615 static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt)
 616 {
 617         struct thread_info *ti = task_thread_info(current);
 618
 619         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
 620                         1, regs, 0);
 621         switch (rd) {
 622         case 0:         /* CPU number */
 623                 regs->regs[rt] = smp_processor_id();
 624                 return 0;
 625         case 1:         /* SYNCI length */
 626                 regs->regs[rt] = min(current_cpu_data.dcache.linesz,
 627                                      current_cpu_data.icache.linesz);
 628                 return 0;
 629         case 2:         /* Read count register */
 630                 regs->regs[rt] = read_c0_count();
 631                 return 0;
 632         case 3:         /* Count register resolution */
 633                 switch (current_cpu_type()) {
 634                 case CPU_20KC:
 635                 case CPU_25KF:
 636                         regs->regs[rt] = 1;
 637                         break;
 638                 default:
 639                         regs->regs[rt] = 2;
 640                 }
 641                 return 0;
 642         case 29:
 643                 regs->regs[rt] = ti->tp_value;
 644                 return 0;
 645         default:
 646                 return -1;
 647         }
 648 }
 649
 650 static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode)
 651 {
 652         if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
 653                 int rd = (opcode & RD) >> 11;
 654                 int rt = (opcode & RT) >> 16;
 655
 656                 simulate_rdhwr(regs, rd, rt);
 657                 return 0;
 658         }
 659
 660         /* Not ours.  */
 661         return -1;
 662 }
 663
 664 static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned short opcode)
 665 {
 666         if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) {
 667                 int rd = (opcode & MM_RS) >> 16;
 668                 int rt = (opcode & MM_RT) >> 21;
 669                 simulate_rdhwr(regs, rd, rt);
 670                 return 0;
 671         }
 672
 673         /* Not ours.  */
 674         return -1;
 675 }
 676
 677 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
 678 {
 679         if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
 680                 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
 681                                 1, regs, 0);
 682                 return 0;
 683         }
 684
 685         return -1;                      /* Must be something else ... */
 686 }
 687
 688 asmlinkage void do_ov(struct pt_regs *regs)
 689 {
 690         enum ctx_state prev_state;
 691         siginfo_t info;
 692
 693         prev_state = exception_enter();
 694         die_if_kernel("Integer overflow", regs);
 695
 696         info.si_code = FPE_INTOVF;
 697         info.si_signo = SIGFPE;
 698         info.si_errno = 0;
 699         info.si_addr = (void __user *) regs->cp0_epc;
 700         force_sig_info(SIGFPE, &info, current);
 701         exception_exit(prev_state);
 702 }
 703
 704 int process_fpemu_return(int sig, void __user *fault_addr)
 705 {
 706         if (sig == SIGSEGV || sig == SIGBUS) {
 707                 struct siginfo si = {0};
 708                 si.si_addr = fault_addr;
 709                 si.si_signo = sig;
 710                 if (sig == SIGSEGV) {
 711                         if (find_vma(current->mm, (unsigned long)fault_addr))
 712                                 si.si_code = SEGV_ACCERR;
 713                         else
 714                                 si.si_code = SEGV_MAPERR;
 715                 } else {
 716                         si.si_code = BUS_ADRERR;
 717                 }
 718                 force_sig_info(sig, &si, current);
 719                 return 1;
 720         } else if (sig) {
 721                 force_sig(sig, current);
 722                 return 1;
 723         } else {
 724                 return 0;
 725         }
 726 }
 727
 728 /*
 729  * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
 730  */
 731 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
 732 {
 733         enum ctx_state prev_state;
 734         siginfo_t info = {0};
 735
 736         prev_state = exception_enter();
 737         if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs),
 738                        SIGFPE) == NOTIFY_STOP)
 739                 goto out;
 740         die_if_kernel("FP exception in kernel code", regs);
 741
 742         if (fcr31 & FPU_CSR_UNI_X) {
 743                 int sig;
 744                 void __user *fault_addr = NULL;
 745
 746                 /*
 747                  * Unimplemented operation exception.  If we've got the full
 748                  * software emulator on-board, let's use it...
 749                  *
 750                  * Force FPU to dump state into task/thread context.  We're
 751                  * moving a lot of data here for what is probably a single
 752                  * instruction, but the alternative is to pre-decode the FP
 753                  * register operands before invoking the emulator, which seems
 754                  * a bit extreme for what should be an infrequent event.
 755                  */
 756                 /* Ensure 'resume' not overwrite saved fp context again. */
 757                 lose_fpu(1);
 758
 759                 /* Run the emulator */
 760                 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
 761                                                &fault_addr);
 762
 763                 /*
 764                  * We can't allow the emulated instruction to leave any of
 765                  * the cause bit set in $fcr31.
 766                  */
 767                 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
 768
 769                 /* Restore the hardware register state */
 770                 own_fpu(1);     /* Using the FPU again.  */
 771
 772                 /* If something went wrong, signal */
 773                 process_fpemu_return(sig, fault_addr);
 774
 775                 goto out;
 776         } else if (fcr31 & FPU_CSR_INV_X)
 777                 info.si_code = FPE_FLTINV;
 778         else if (fcr31 & FPU_CSR_DIV_X)
 779                 info.si_code = FPE_FLTDIV;
 780         else if (fcr31 & FPU_CSR_OVF_X)
 781                 info.si_code = FPE_FLTOVF;
 782         else if (fcr31 & FPU_CSR_UDF_X)
 783                 info.si_code = FPE_FLTUND;
 784         else if (fcr31 & FPU_CSR_INE_X)
 785                 info.si_code = FPE_FLTRES;
 786         else
 787                 info.si_code = __SI_FAULT;
 788         info.si_signo = SIGFPE;
 789         info.si_errno = 0;
 790         info.si_addr = (void __user *) regs->cp0_epc;
 791         force_sig_info(SIGFPE, &info, current);
 792
 793 out:
 794         exception_exit(prev_state);
 795 }
 796
 797 static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
 798         const char *str)
 799 {
 800         siginfo_t info;
 801         char b[40];
 802
 803 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
 804         if (kgdb_ll_trap(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
 805                 return;
 806 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
 807
 808         if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs),
 809                        SIGTRAP) == NOTIFY_STOP)
 810                 return;
 811
 812         /*
 813          * A short test says that IRIX 5.3 sends SIGTRAP for all trap
 814          * insns, even for trap and break codes that indicate arithmetic
 815          * failures.  Weird ...
 816          * But should we continue the brokenness???  --macro
 817          */
 818         switch (code) {
 819         case BRK_OVERFLOW:
 820         case BRK_DIVZERO:
 821                 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
 822                 die_if_kernel(b, regs);
 823                 if (code == BRK_DIVZERO)
 824                         info.si_code = FPE_INTDIV;
 825                 else
 826                         info.si_code = FPE_INTOVF;
 827                 info.si_signo = SIGFPE;
 828                 info.si_errno = 0;
 829                 info.si_addr = (void __user *) regs->cp0_epc;
 830                 force_sig_info(SIGFPE, &info, current);
 831                 break;
 832         case BRK_BUG:
 833                 die_if_kernel("Kernel bug detected", regs);
 834                 force_sig(SIGTRAP, current);
 835                 break;
 836         case BRK_MEMU:
 837                 /*
 838                  * Address errors may be deliberately induced by the FPU
 839                  * emulator to retake control of the CPU after executing the
 840                  * instruction in the delay slot of an emulated branch.
 841                  *
 842                  * Terminate if exception was recognized as a delay slot return
 843                  * otherwise handle as normal.
 844                  */
 845                 if (do_dsemulret(regs))
 846                         return;
 847
 848                 die_if_kernel("Math emu break/trap", regs);
 849                 force_sig(SIGTRAP, current);
 850                 break;
 851         default:
 852                 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
 853                 die_if_kernel(b, regs);
 854                 force_sig(SIGTRAP, current);
 855         }
 856 }
 857
 858 asmlinkage void do_bp(struct pt_regs *regs)
 859 {
 860         unsigned int opcode, bcode;
 861         enum ctx_state prev_state;
 862         unsigned long epc;
 863         u16 instr[2];
 864
 865         prev_state = exception_enter();
 866         if (get_isa16_mode(regs->cp0_epc)) {
 867                 /* Calculate EPC. */
 868                 epc = exception_epc(regs);
 869                 if (cpu_has_mmips) {
 870                         if ((__get_user(instr[0], (u16 __user *)msk_isa16_mode(epc)) ||
 871                             (__get_user(instr[1], (u16 __user *)msk_isa16_mode(epc + 2)))))
 872                                 goto out_sigsegv;
 873                     opcode = (instr[0] << 16) | instr[1];
 874                 } else {
 875                     /* MIPS16e mode */
 876                     if (__get_user(instr[0], (u16 __user *)msk_isa16_mode(epc)))
 877                                 goto out_sigsegv;
 878                     bcode = (instr[0] >> 6) & 0x3f;
 879                     do_trap_or_bp(regs, bcode, "Break");
 880                     goto out;
 881                 }
 882         } else {
 883                 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
 884                         goto out_sigsegv;
 885         }
 886
 887         /*
 888          * There is the ancient bug in the MIPS assemblers that the break
 889          * code starts left to bit 16 instead to bit 6 in the opcode.
 890          * Gas is bug-compatible, but not always, grrr...
 891          * We handle both cases with a simple heuristics.  --macro
 892          */
 893         bcode = ((opcode >> 6) & ((1 << 20) - 1));
 894         if (bcode >= (1 << 10))
 895                 bcode >>= 10;
 896
 897         /*
 898          * notify the kprobe handlers, if instruction is likely to
 899          * pertain to them.
 900          */
 901         switch (bcode) {
 902         case BRK_KPROBE_BP:
 903                 if (notify_die(DIE_BREAK, "debug", regs, bcode,
 904                                regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
 905                         goto out;
 906                 else
 907                         break;
 908         case BRK_KPROBE_SSTEPBP:
 909                 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode,
 910                                regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
 911                         goto out;
 912                 else
 913                         break;
 914         default:
 915                 break;
 916         }
 917
 918         do_trap_or_bp(regs, bcode, "Break");
 919
 920 out:
 921         exception_exit(prev_state);
 922         return;
 923
 924 out_sigsegv:
 925         force_sig(SIGSEGV, current);
 926         goto out;
 927 }
 928
 929 asmlinkage void do_tr(struct pt_regs *regs)
 930 {
 931         u32 opcode, tcode = 0;
 932         enum ctx_state prev_state;
 933         u16 instr[2];
 934         unsigned long epc = msk_isa16_mode(exception_epc(regs));
 935
 936         prev_state = exception_enter();
 937         if (get_isa16_mode(regs->cp0_epc)) {
 938                 if (__get_user(instr[0], (u16 __user *)(epc + 0)) ||
 939                     __get_user(instr[1], (u16 __user *)(epc + 2)))
 940                         goto out_sigsegv;
 941                 opcode = (instr[0] << 16) | instr[1];
 942                 /* Immediate versions don't provide a code.  */
 943                 if (!(opcode & OPCODE))
 944                         tcode = (opcode >> 12) & ((1 << 4) - 1);
 945         } else {
 946                 if (__get_user(opcode, (u32 __user *)epc))
 947                         goto out_sigsegv;
 948                 /* Immediate versions don't provide a code.  */
 949                 if (!(opcode & OPCODE))
 950                         tcode = (opcode >> 6) & ((1 << 10) - 1);
 951         }
 952
 953         do_trap_or_bp(regs, tcode, "Trap");
 954
 955 out:
 956         exception_exit(prev_state);
 957         return;
 958
 959 out_sigsegv:
 960         force_sig(SIGSEGV, current);
 961         goto out;
 962 }
 963
 964 asmlinkage void do_ri(struct pt_regs *regs)
 965 {
 966         unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
 967         unsigned long old_epc = regs->cp0_epc;
 968         unsigned long old31 = regs->regs[31];
 969         enum ctx_state prev_state;
 970         unsigned int opcode = 0;
 971         int status = -1;
 972
 973         prev_state = exception_enter();
 974         if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs),
 975                        SIGILL) == NOTIFY_STOP)
 976                 goto out;
 977
 978         die_if_kernel("Reserved instruction in kernel code", regs);
 979
 980         if (unlikely(compute_return_epc(regs) < 0))
 981                 goto out;
 982
 983         if (get_isa16_mode(regs->cp0_epc)) {
 984                 unsigned short mmop[2] = { 0 };
 985
 986                 if (unlikely(get_user(mmop[0], epc) < 0))
 987                         status = SIGSEGV;
 988                 if (unlikely(get_user(mmop[1], epc) < 0))
 989                         status = SIGSEGV;
 990                 opcode = (mmop[0] << 16) | mmop[1];
 991
 992                 if (status < 0)
 993                         status = simulate_rdhwr_mm(regs, opcode);
 994         } else {
 995                 if (unlikely(get_user(opcode, epc) < 0))
 996                         status = SIGSEGV;
 997
 998                 if (!cpu_has_llsc && status < 0)
 999                         status = simulate_llsc(regs, opcode);
1000
1001                 if (status < 0)
1002                         status = simulate_rdhwr_normal(regs, opcode);
1003
1004                 if (status < 0)
1005                         status = simulate_sync(regs, opcode);
1006         }
1007
1008         if (status < 0)
1009                 status = SIGILL;
1010
1011         if (unlikely(status > 0)) {
1012                 regs->cp0_epc = old_epc;                /* Undo skip-over.  */
1013                 regs->regs[31] = old31;
1014                 force_sig(status, current);
1015         }
1016
1017 out:
1018         exception_exit(prev_state);
1019 }
1020
1021 /*
1022  * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
1023  * emulated more than some threshold number of instructions, force migration to
1024  * a "CPU" that has FP support.
1025  */
1026 static void mt_ase_fp_affinity(void)
1027 {
1028 #ifdef CONFIG_MIPS_MT_FPAFF
1029         if (mt_fpemul_threshold > 0 &&
1030              ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
1031                 /*
1032                  * If there's no FPU present, or if the application has already
1033                  * restricted the allowed set to exclude any CPUs with FPUs,
1034                  * we'll skip the procedure.
1035                  */
1036                 if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) {
1037                         cpumask_t tmask;
1038
1039                         current->thread.user_cpus_allowed
1040                                 = current->cpus_allowed;
1041                         cpus_and(tmask, current->cpus_allowed,
1042                                 mt_fpu_cpumask);
1043                         set_cpus_allowed_ptr(current, &tmask);
1044                         set_thread_flag(TIF_FPUBOUND);
1045                 }
1046         }
1047 #endif /* CONFIG_MIPS_MT_FPAFF */
1048 }
1049
1050 /*
1051  * No lock; only written during early bootup by CPU 0.
1052  */
1053 static RAW_NOTIFIER_HEAD(cu2_chain);
1054
1055 int __ref register_cu2_notifier(struct notifier_block *nb)
1056 {
1057         return raw_notifier_chain_register(&cu2_chain, nb);
1058 }
1059
1060 int cu2_notifier_call_chain(unsigned long val, void *v)
1061 {
1062         return raw_notifier_call_chain(&cu2_chain, val, v);
1063 }
1064
1065 static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
1066         void *data)
1067 {
1068         struct pt_regs *regs = data;
1069
1070         die_if_kernel("COP2: Unhandled kernel unaligned access or invalid "
1071                               "instruction", regs);
1072         force_sig(SIGILL, current);
1073
1074         return NOTIFY_OK;
1075 }
1076
1077 asmlinkage void do_cpu(struct pt_regs *regs)
1078 {
1079         enum ctx_state prev_state;
1080         unsigned int __user *epc;
1081         unsigned long old_epc, old31;
1082         unsigned int opcode;
1083         unsigned int cpid;
1084         int status, err;
1085         unsigned long __maybe_unused flags;
1086
1087         prev_state = exception_enter();
1088         cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
1089
1090         if (cpid != 2)
1091                 die_if_kernel("do_cpu invoked from kernel context!", regs);
1092
1093         switch (cpid) {
1094         case 0:
1095                 epc = (unsigned int __user *)exception_epc(regs);
1096                 old_epc = regs->cp0_epc;
1097                 old31 = regs->regs[31];
1098                 opcode = 0;
1099                 status = -1;
1100
1101                 if (unlikely(compute_return_epc(regs) < 0))
1102                         goto out;
1103
1104                 if (get_isa16_mode(regs->cp0_epc)) {
1105                         unsigned short mmop[2] = { 0 };
1106
1107                         if (unlikely(get_user(mmop[0], epc) < 0))
1108                                 status = SIGSEGV;
1109                         if (unlikely(get_user(mmop[1], epc) < 0))
1110                                 status = SIGSEGV;
1111                         opcode = (mmop[0] << 16) | mmop[1];
1112
1113                         if (status < 0)
1114                                 status = simulate_rdhwr_mm(regs, opcode);
1115                 } else {
1116                         if (unlikely(get_user(opcode, epc) < 0))
1117                                 status = SIGSEGV;
1118
1119                         if (!cpu_has_llsc && status < 0)
1120                                 status = simulate_llsc(regs, opcode);
1121
1122                         if (status < 0)
1123                                 status = simulate_rdhwr_normal(regs, opcode);
1124                 }
1125
1126                 if (status < 0)
1127                         status = SIGILL;
1128
1129                 if (unlikely(status > 0)) {
1130                         regs->cp0_epc = old_epc;        /* Undo skip-over.  */
1131                         regs->regs[31] = old31;
1132                         force_sig(status, current);
1133                 }
1134
1135                 goto out;
1136
1137         case 3:
1138                 /*
1139                  * Old (MIPS I and MIPS II) processors will set this code
1140                  * for COP1X opcode instructions that replaced the original
1141                  * COP3 space.  We don't limit COP1 space instructions in
1142                  * the emulator according to the CPU ISA, so we want to
1143                  * treat COP1X instructions consistently regardless of which
1144                  * code the CPU chose.  Therefore we redirect this trap to
1145                  * the FP emulator too.
1146                  *
1147                  * Then some newer FPU-less processors use this code
1148                  * erroneously too, so they are covered by this choice
1149                  * as well.
1150                  */
1151                 if (raw_cpu_has_fpu)
1152                         break;
1153                 /* Fall through.  */
1154
1155         case 1:
1156                 if (used_math())        /* Using the FPU again.  */
1157                         err = own_fpu(1);
1158                 else {                  /* First time FPU user.  */
1159                         err = init_fpu();
1160                         set_used_math();
1161                 }
1162
1163                 if (!raw_cpu_has_fpu || err) {
1164                         int sig;
1165                         void __user *fault_addr = NULL;
1166                         sig = fpu_emulator_cop1Handler(regs,
1167                                                        &current->thread.fpu,
1168                                                        0, &fault_addr);
1169                         if (!process_fpemu_return(sig, fault_addr) && !err)
1170                                 mt_ase_fp_affinity();
1171                 }
1172
1173                 goto out;
1174
1175         case 2:
1176                 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
1177                 goto out;
1178         }
1179
1180         force_sig(SIGILL, current);
1181
1182 out:
1183         exception_exit(prev_state);
1184 }
1185
1186 asmlinkage void do_mdmx(struct pt_regs *regs)
1187 {
1188         enum ctx_state prev_state;
1189
1190         prev_state = exception_enter();
1191         force_sig(SIGILL, current);
1192         exception_exit(prev_state);
1193 }
1194
1195 /*
1196  * Called with interrupts disabled.
1197  */
1198 asmlinkage void do_watch(struct pt_regs *regs)
1199 {
1200         enum ctx_state prev_state;
1201         u32 cause;
1202
1203         prev_state = exception_enter();
1204         /*
1205          * Clear WP (bit 22) bit of cause register so we don't loop
1206          * forever.
1207          */
1208         cause = read_c0_cause();
1209         cause &= ~(1 << 22);
1210         write_c0_cause(cause);
1211
1212         /*
1213          * If the current thread has the watch registers loaded, save
1214          * their values and send SIGTRAP.  Otherwise another thread
1215          * left the registers set, clear them and continue.
1216          */
1217         if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
1218                 mips_read_watch_registers();
1219                 local_irq_enable();
1220                 force_sig(SIGTRAP, current);
1221         } else {
1222                 mips_clear_watch_registers();
1223                 local_irq_enable();
1224         }
1225         exception_exit(prev_state);
1226 }
1227
1228 asmlinkage void do_mcheck(struct pt_regs *regs)
1229 {
1230         const int field = 2 * sizeof(unsigned long);
1231         int multi_match = regs->cp0_status & ST0_TS;
1232         enum ctx_state prev_state;
1233
1234         prev_state = exception_enter();
1235         show_regs(regs);
1236
1237         if (multi_match) {
1238                 printk("Index   : %0x\n", read_c0_index());
1239                 printk("Pagemask: %0x\n", read_c0_pagemask());
1240                 printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
1241                 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
1242                 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
1243                 printk("\n");
1244                 dump_tlb_all();
1245         }
1246
1247         show_code((unsigned int __user *) regs->cp0_epc);
1248
1249         /*
1250          * Some chips may have other causes of machine check (e.g. SB1
1251          * graduation timer)
1252          */
1253         panic("Caught Machine Check exception - %scaused by multiple "
1254               "matching entries in the TLB.",
1255               (multi_match) ? "" : "not ");
1256 }
1257
1258 asmlinkage void do_mt(struct pt_regs *regs)
1259 {
1260         int subcode;
1261
1262         subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
1263                         >> VPECONTROL_EXCPT_SHIFT;
1264         switch (subcode) {
1265         case 0:
1266                 printk(KERN_DEBUG "Thread Underflow\n");
1267                 break;
1268         case 1:
1269                 printk(KERN_DEBUG "Thread Overflow\n");
1270                 break;
1271         case 2:
1272                 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
1273                 break;
1274         case 3:
1275                 printk(KERN_DEBUG "Gating Storage Exception\n");
1276                 break;
1277         case 4:
1278                 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
1279                 break;
1280         case 5:
1281                 printk(KERN_DEBUG "Gating Storage Scheduler Exception\n");
1282                 break;
1283         default:
1284                 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
1285                         subcode);
1286                 break;
1287         }
1288         die_if_kernel("MIPS MT Thread exception in kernel", regs);
1289
1290         force_sig(SIGILL, current);
1291 }
1292
1293
1294 asmlinkage void do_dsp(struct pt_regs *regs)
1295 {
1296         if (cpu_has_dsp)
1297                 panic("Unexpected DSP exception");
1298
1299         force_sig(SIGILL, current);
1300 }
1301
1302 asmlinkage void do_reserved(struct pt_regs *regs)
1303 {
1304         /*
1305          * Game over - no way to handle this if it ever occurs.  Most probably
1306          * caused by a new unknown cpu type or after another deadly
1307          * hard/software error.
1308          */
1309         show_regs(regs);
1310         panic("Caught reserved exception %ld - should not happen.",
1311               (regs->cp0_cause & 0x7f) >> 2);
1312 }
1313
1314 static int __initdata l1parity = 1;
1315 static int __init nol1parity(char *s)
1316 {
1317         l1parity = 0;
1318         return 1;
1319 }
1320 __setup("nol1par", nol1parity);
1321 static int __initdata l2parity = 1;
1322 static int __init nol2parity(char *s)
1323 {
1324         l2parity = 0;
1325         return 1;
1326 }
1327 __setup("nol2par", nol2parity);
1328
1329 /*
1330  * Some MIPS CPUs can enable/disable for cache parity detection, but do
1331  * it different ways.
1332  */
1333 static inline void parity_protection_init(void)
1334 {
1335         switch (current_cpu_type()) {
1336         case CPU_24K:
1337         case CPU_34K:
1338         case CPU_74K:
1339         case CPU_1004K:
1340         case CPU_INTERAPTIV:
1341         case CPU_PROAPTIV:
1342                 {
1343 #define ERRCTL_PE       0x80000000
1344 #define ERRCTL_L2P      0x00800000
1345                         unsigned long errctl;
1346                         unsigned int l1parity_present, l2parity_present;
1347
1348                         errctl = read_c0_ecc();
1349                         errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1350
1351                         /* probe L1 parity support */
1352                         write_c0_ecc(errctl | ERRCTL_PE);
1353                         back_to_back_c0_hazard();
1354                         l1parity_present = (read_c0_ecc() & ERRCTL_PE);
1355
1356                         /* probe L2 parity support */
1357                         write_c0_ecc(errctl|ERRCTL_L2P);
1358                         back_to_back_c0_hazard();
1359                         l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
1360
1361                         if (l1parity_present && l2parity_present) {
1362                                 if (l1parity)
1363                                         errctl |= ERRCTL_PE;
1364                                 if (l1parity ^ l2parity)
1365                                         errctl |= ERRCTL_L2P;
1366                         } else if (l1parity_present) {
1367                                 if (l1parity)
1368                                         errctl |= ERRCTL_PE;
1369                         } else if (l2parity_present) {
1370                                 if (l2parity)
1371                                         errctl |= ERRCTL_L2P;
1372                         } else {
1373                                 /* No parity available */
1374                         }
1375
1376                         printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1377
1378                         write_c0_ecc(errctl);
1379                         back_to_back_c0_hazard();
1380                         errctl = read_c0_ecc();
1381                         printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1382
1383                         if (l1parity_present)
1384                                 printk(KERN_INFO "Cache parity protection %sabled\n",
1385                                        (errctl & ERRCTL_PE) ? "en" : "dis");
1386
1387                         if (l2parity_present) {
1388                                 if (l1parity_present && l1parity)
1389                                         errctl ^= ERRCTL_L2P;
1390                                 printk(KERN_INFO "L2 cache parity protection %sabled\n",
1391                                        (errctl & ERRCTL_L2P) ? "en" : "dis");
1392                         }
1393                 }
1394                 break;
1395
1396         case CPU_5KC:
1397         case CPU_5KE:
1398         case CPU_LOONGSON1:
1399                 write_c0_ecc(0x80000000);
1400                 back_to_back_c0_hazard();
1401                 /* Set the PE bit (bit 31) in the c0_errctl register. */
1402                 printk(KERN_INFO "Cache parity protection %sabled\n",
1403                        (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1404                 break;
1405         case CPU_20KC:
1406         case CPU_25KF:
1407                 /* Clear the DE bit (bit 16) in the c0_status register. */
1408                 printk(KERN_INFO "Enable cache parity protection for "
1409                        "MIPS 20KC/25KF CPUs.\n");
1410                 clear_c0_status(ST0_DE);
1411                 break;
1412         default:
1413                 break;
1414         }
1415 }
1416
1417 asmlinkage void cache_parity_error(void)
1418 {
1419         const int field = 2 * sizeof(unsigned long);
1420         unsigned int reg_val;
1421
1422         /* For the moment, report the problem and hang. */
1423         printk("Cache error exception:\n");
1424         printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1425         reg_val = read_c0_cacheerr();
1426         printk("c0_cacheerr == %08x\n", reg_val);
1427
1428         printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1429                reg_val & (1<<30) ? "secondary" : "primary",
1430                reg_val & (1<<31) ? "data" : "insn");
1431         if (cpu_has_mips_r2 &&
1432             ((current_cpu_data.processor_id && 0xff0000) == PRID_COMP_MIPS)) {
1433                 pr_err("Error bits: %s%s%s%s%s%s%s%s\n",
1434                         reg_val & (1<<29) ? "ED " : "",
1435                         reg_val & (1<<28) ? "ET " : "",
1436                         reg_val & (1<<27) ? "ES " : "",
1437                         reg_val & (1<<26) ? "EE " : "",
1438                         reg_val & (1<<25) ? "EB " : "",
1439                         reg_val & (1<<24) ? "EI " : "",
1440                         reg_val & (1<<23) ? "E1 " : "",
1441                         reg_val & (1<<22) ? "E0 " : "");
1442         } else {
1443                 pr_err("Error bits: %s%s%s%s%s%s%s\n",
1444                         reg_val & (1<<29) ? "ED " : "",
1445                         reg_val & (1<<28) ? "ET " : "",
1446                         reg_val & (1<<26) ? "EE " : "",
1447                         reg_val & (1<<25) ? "EB " : "",
1448                         reg_val & (1<<24) ? "EI " : "",
1449                         reg_val & (1<<23) ? "E1 " : "",
1450                         reg_val & (1<<22) ? "E0 " : "");
1451         }
1452         printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1453
1454 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1455         if (reg_val & (1<<22))
1456                 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1457
1458         if (reg_val & (1<<23))
1459                 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1460 #endif
1461
1462         panic("Can't handle the cache error!");
1463 }
1464
1465 asmlinkage void do_ftlb(void)
1466 {
1467         const int field = 2 * sizeof(unsigned long);
1468         unsigned int reg_val;
1469
1470         /* For the moment, report the problem and hang. */
1471         if (cpu_has_mips_r2 &&
1472             ((current_cpu_data.processor_id && 0xff0000) == PRID_COMP_MIPS)) {
1473                 pr_err("FTLB error exception, cp0_ecc=0x%08x:\n",
1474                        read_c0_ecc());
1475                 pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1476                 reg_val = read_c0_cacheerr();
1477                 pr_err("c0_cacheerr == %08x\n", reg_val);
1478
1479                 if ((reg_val & 0xc0000000) == 0xc0000000) {
1480                         pr_err("Decoded c0_cacheerr: FTLB parity error\n");
1481                 } else {
1482                         pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1483                                reg_val & (1<<30) ? "secondary" : "primary",
1484                                reg_val & (1<<31) ? "data" : "insn");
1485                 }
1486         } else {
1487                 pr_err("FTLB error exception\n");
1488         }
1489         /* Just print the cacheerr bits for now */
1490         cache_parity_error();
1491 }
1492
1493 /*
1494  * SDBBP EJTAG debug exception handler.
1495  * We skip the instruction and return to the next instruction.
1496  */
1497 void ejtag_exception_handler(struct pt_regs *regs)
1498 {
1499         const int field = 2 * sizeof(unsigned long);
1500         unsigned long depc, old_epc, old_ra;
1501         unsigned int debug;
1502
1503         printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1504         depc = read_c0_depc();
1505         debug = read_c0_debug();
1506         printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1507         if (debug & 0x80000000) {
1508                 /*
1509                  * In branch delay slot.
1510                  * We cheat a little bit here and use EPC to calculate the
1511                  * debug return address (DEPC). EPC is restored after the
1512                  * calculation.
1513                  */
1514                 old_epc = regs->cp0_epc;
1515                 old_ra = regs->regs[31];
1516                 regs->cp0_epc = depc;
1517                 compute_return_epc(regs);
1518                 depc = regs->cp0_epc;
1519                 regs->cp0_epc = old_epc;
1520                 regs->regs[31] = old_ra;
1521         } else
1522                 depc += 4;
1523         write_c0_depc(depc);
1524
1525 #if 0
1526         printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1527         write_c0_debug(debug | 0x100);
1528 #endif
1529 }
1530
1531 /*
1532  * NMI exception handler.
1533  * No lock; only written during early bootup by CPU 0.
1534  */
1535 static RAW_NOTIFIER_HEAD(nmi_chain);
1536
1537 int register_nmi_notifier(struct notifier_block *nb)
1538 {
1539         return raw_notifier_chain_register(&nmi_chain, nb);
1540 }
1541
1542 void __noreturn nmi_exception_handler(struct pt_regs *regs)
1543 {
1544         char str[100];
1545
1546         raw_notifier_call_chain(&nmi_chain, 0, regs);
1547         bust_spinlocks(1);
1548         snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n",
1549                  smp_processor_id(), regs->cp0_epc);
1550         regs->cp0_epc = read_c0_errorepc();
1551         die(str, regs);
1552 }
1553
1554 #define VECTORSPACING 0x100     /* for EI/VI mode */
1555
1556 unsigned long ebase;
1557 unsigned long exception_handlers[32];
1558 unsigned long vi_handlers[64];
1559
1560 void __init *set_except_vector(int n, void *addr)
1561 {
1562         unsigned long handler = (unsigned long) addr;
1563         unsigned long old_handler;
1564
1565 #ifdef CONFIG_CPU_MICROMIPS
1566         /*
1567          * Only the TLB handlers are cache aligned with an even
1568          * address. All other handlers are on an odd address and
1569          * require no modification. Otherwise, MIPS32 mode will
1570          * be entered when handling any TLB exceptions. That
1571          * would be bad...since we must stay in microMIPS mode.
1572          */
1573         if (!(handler & 0x1))
1574                 handler |= 1;
1575 #endif
1576         old_handler = xchg(&exception_handlers[n], handler);
1577
1578         if (n == 0 && cpu_has_divec) {
1579 #ifdef CONFIG_CPU_MICROMIPS
1580                 unsigned long jump_mask = ~((1 << 27) - 1);
1581 #else
1582                 unsigned long jump_mask = ~((1 << 28) - 1);
1583 #endif
1584                 u32 *buf = (u32 *)(ebase + 0x200);
1585                 unsigned int k0 = 26;
1586                 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
1587                         uasm_i_j(&buf, handler & ~jump_mask);
1588                         uasm_i_nop(&buf);
1589                 } else {
1590                         UASM_i_LA(&buf, k0, handler);
1591                         uasm_i_jr(&buf, k0);
1592                         uasm_i_nop(&buf);
1593                 }
1594                 local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
1595         }
1596         return (void *)old_handler;
1597 }
1598
1599 static void do_default_vi(void)
1600 {
1601         show_regs(get_irq_regs());
1602         panic("Caught unexpected vectored interrupt.");
1603 }
1604
1605 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1606 {
1607         unsigned long handler;
1608         unsigned long old_handler = vi_handlers[n];
1609         int srssets = current_cpu_data.srsets;
1610         u16 *h;
1611         unsigned char *b;
1612
1613         BUG_ON(!cpu_has_veic && !cpu_has_vint);
1614
1615         if (addr == NULL) {
1616                 handler = (unsigned long) do_default_vi;
1617                 srs = 0;
1618         } else
1619                 handler = (unsigned long) addr;
1620         vi_handlers[n] = handler;
1621
1622         b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1623
1624         if (srs >= srssets)
1625                 panic("Shadow register set %d not supported", srs);
1626
1627         if (cpu_has_veic) {
1628                 if (board_bind_eic_interrupt)
1629                         board_bind_eic_interrupt(n, srs);
1630         } else if (cpu_has_vint) {
1631                 /* SRSMap is only defined if shadow sets are implemented */
1632                 if (srssets > 1)
1633                         change_c0_srsmap(0xf << n*4, srs << n*4);
1634         }
1635
1636         if (srs == 0) {
1637                 /*
1638                  * If no shadow set is selected then use the default handler
1639                  * that does normal register saving and standard interrupt exit
1640                  */
1641                 extern char except_vec_vi, except_vec_vi_lui;
1642                 extern char except_vec_vi_ori, except_vec_vi_end;
1643                 extern char rollback_except_vec_vi;
1644                 char *vec_start = using_rollback_handler() ?
1645                         &rollback_except_vec_vi : &except_vec_vi;
1646 #ifdef CONFIG_MIPS_MT_SMTC
1647                 /*
1648                  * We need to provide the SMTC vectored interrupt handler
1649                  * not only with the address of the handler, but with the
1650                  * Status.IM bit to be masked before going there.
1651                  */
1652                 extern char except_vec_vi_mori;
1653 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
1654                 const int mori_offset = &except_vec_vi_mori - vec_start + 2;
1655 #else
1656                 const int mori_offset = &except_vec_vi_mori - vec_start;
1657 #endif
1658 #endif /* CONFIG_MIPS_MT_SMTC */
1659 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
1660                 const int lui_offset = &except_vec_vi_lui - vec_start + 2;
1661                 const int ori_offset = &except_vec_vi_ori - vec_start + 2;
1662 #else
1663                 const int lui_offset = &except_vec_vi_lui - vec_start;
1664                 const int ori_offset = &except_vec_vi_ori - vec_start;
1665 #endif
1666                 const int handler_len = &except_vec_vi_end - vec_start;
1667
1668                 if (handler_len > VECTORSPACING) {
1669                         /*
1670                          * Sigh... panicing won't help as the console
1671                          * is probably not configured :(
1672                          */
1673                         panic("VECTORSPACING too small");
1674                 }
1675
1676                 set_handler(((unsigned long)b - ebase), vec_start,
1677 #ifdef CONFIG_CPU_MICROMIPS
1678                                 (handler_len - 1));
1679 #else
1680                                 handler_len);
1681 #endif
1682 #ifdef CONFIG_MIPS_MT_SMTC
1683                 BUG_ON(n > 7);  /* Vector index %d exceeds SMTC maximum. */
1684
1685                 h = (u16 *)(b + mori_offset);
1686                 *h = (0x100 << n);
1687 #endif /* CONFIG_MIPS_MT_SMTC */
1688                 h = (u16 *)(b + lui_offset);
1689                 *h = (handler >> 16) & 0xffff;
1690                 h = (u16 *)(b + ori_offset);
1691                 *h = (handler & 0xffff);
1692                 local_flush_icache_range((unsigned long)b,
1693                                          (unsigned long)(b+handler_len));
1694         }
1695         else {
1696                 /*
1697                  * In other cases jump directly to the interrupt handler. It
1698                  * is the handler's responsibility to save registers if required
1699                  * (eg hi/lo) and return from the exception using "eret".
1700                  */
1701                 u32 insn;
1702
1703                 h = (u16 *)b;
1704                 /* j handler */
1705 #ifdef CONFIG_CPU_MICROMIPS
1706                 insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1);
1707 #else
1708                 insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2);
1709 #endif
1710                 h[0] = (insn >> 16) & 0xffff;
1711                 h[1] = insn & 0xffff;
1712                 h[2] = 0;
1713                 h[3] = 0;
1714                 local_flush_icache_range((unsigned long)b,
1715                                          (unsigned long)(b+8));
1716         }
1717
1718         return (void *)old_handler;
1719 }
1720
1721 void *set_vi_handler(int n, vi_handler_t addr)
1722 {
1723         return set_vi_srs_handler(n, addr, 0);
1724 }
1725
1726 extern void tlb_init(void);
1727
1728 /*
1729  * Timer interrupt
1730  */
1731 int cp0_compare_irq;
1732 EXPORT_SYMBOL_GPL(cp0_compare_irq);
1733 int cp0_compare_irq_shift;
1734
1735 /*
1736  * Performance counter IRQ or -1 if shared with timer
1737  */
1738 int cp0_perfcount_irq;
1739 EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
1740
1741 static int noulri;
1742
1743 static int __init ulri_disable(char *s)
1744 {
1745         pr_info("Disabling ulri\n");
1746         noulri = 1;
1747
1748         return 1;
1749 }
1750 __setup("noulri", ulri_disable);
1751
1752 void per_cpu_trap_init(bool is_boot_cpu)
1753 {
1754         unsigned int cpu = smp_processor_id();
1755         unsigned int status_set = ST0_CU0;
1756         unsigned int hwrena = cpu_hwrena_impl_bits;
1757 #ifdef CONFIG_MIPS_MT_SMTC
1758         int secondaryTC = 0;
1759         int bootTC = (cpu == 0);
1760
1761         /*
1762          * Only do per_cpu_trap_init() for first TC of Each VPE.
1763          * Note that this hack assumes that the SMTC init code
1764          * assigns TCs consecutively and in ascending order.
1765          */
1766
1767         if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
1768             ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id))
1769                 secondaryTC = 1;
1770 #endif /* CONFIG_MIPS_MT_SMTC */
1771
1772         /*
1773          * Disable coprocessors and select 32-bit or 64-bit addressing
1774          * and the 16/32 or 32/32 FPR register model.  Reset the BEV
1775          * flag that some firmware may have left set and the TS bit (for
1776          * IP27).  Set XX for ISA IV code to work.
1777          */
1778 #ifdef CONFIG_64BIT
1779         status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1780 #endif
1781         if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
1782                 status_set |= ST0_XX;
1783         if (cpu_has_dsp)
1784                 status_set |= ST0_MX;
1785
1786         change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1787                          status_set);
1788
1789         if (cpu_has_mips_r2)
1790                 hwrena |= 0x0000000f;
1791
1792         if (!noulri && cpu_has_userlocal)
1793                 hwrena |= (1 << 29);
1794
1795         if (hwrena)
1796                 write_c0_hwrena(hwrena);
1797
1798 #ifdef CONFIG_MIPS_MT_SMTC
1799         if (!secondaryTC) {
1800 #endif /* CONFIG_MIPS_MT_SMTC */
1801
1802         if (cpu_has_veic || cpu_has_vint) {
1803                 unsigned long sr = set_c0_status(ST0_BEV);
1804                 write_c0_ebase(ebase);
1805                 write_c0_status(sr);
1806                 /* Setting vector spacing enables EI/VI mode  */
1807                 change_c0_intctl(0x3e0, VECTORSPACING);
1808         }
1809         if (cpu_has_divec) {
1810                 if (cpu_has_mipsmt) {
1811                         unsigned int vpflags = dvpe();
1812                         set_c0_cause(CAUSEF_IV);
1813                         evpe(vpflags);
1814                 } else
1815                         set_c0_cause(CAUSEF_IV);
1816         }
1817
1818         /*
1819          * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
1820          *
1821          *  o read IntCtl.IPTI to determine the timer interrupt
1822          *  o read IntCtl.IPPCI to determine the performance counter interrupt
1823          */
1824         if (cpu_has_mips_r2) {
1825                 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
1826                 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
1827                 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
1828                 if (cp0_perfcount_irq == cp0_compare_irq)
1829                         cp0_perfcount_irq = -1;
1830         } else {
1831                 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
1832                 cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ;
1833                 cp0_perfcount_irq = -1;
1834         }
1835
1836 #ifdef CONFIG_MIPS_MT_SMTC
1837         }
1838 #endif /* CONFIG_MIPS_MT_SMTC */
1839
1840         if (!cpu_data[cpu].asid_cache)
1841                 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1842
1843         atomic_inc(&init_mm.mm_count);
1844         current->active_mm = &init_mm;
1845         BUG_ON(current->mm);
1846         enter_lazy_tlb(&init_mm, current);
1847
1848 #ifdef CONFIG_MIPS_MT_SMTC
1849         if (bootTC) {
1850 #endif /* CONFIG_MIPS_MT_SMTC */
1851                 /* Boot CPU's cache setup in setup_arch(). */
1852                 if (!is_boot_cpu)
1853                         cpu_cache_init();
1854                 tlb_init();
1855 #ifdef CONFIG_MIPS_MT_SMTC
1856         } else if (!secondaryTC) {
1857                 /*
1858                  * First TC in non-boot VPE must do subset of tlb_init()
1859                  * for MMU countrol registers.
1860                  */
1861                 write_c0_pagemask(PM_DEFAULT_MASK);
1862                 write_c0_wired(0);
1863         }
1864 #endif /* CONFIG_MIPS_MT_SMTC */
1865         TLBMISS_HANDLER_SETUP();
1866 }
1867
1868 /* Install CPU exception handler */
1869 void set_handler(unsigned long offset, void *addr, unsigned long size)
1870 {
1871 #ifdef CONFIG_CPU_MICROMIPS
1872         memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size);
1873 #else
1874         memcpy((void *)(ebase + offset), addr, size);
1875 #endif
1876         local_flush_icache_range(ebase + offset, ebase + offset + size);
1877 }
1878
1879 static char panic_null_cerr[] =
1880         "Trying to set NULL cache error exception handler";
1881
1882 /*
1883  * Install uncached CPU exception handler.
1884  * This is suitable only for the cache error exception which is the only
1885  * exception handler that is being run uncached.
1886  */
1887 void set_uncached_handler(unsigned long offset, void *addr,
1888         unsigned long size)
1889 {
1890         unsigned long uncached_ebase = CKSEG1ADDR(ebase);
1891
1892         if (!addr)
1893                 panic(panic_null_cerr);
1894
1895         memcpy((void *)(uncached_ebase + offset), addr, size);
1896 }
1897
1898 static int __initdata rdhwr_noopt;
1899 static int __init set_rdhwr_noopt(char *str)
1900 {
1901         rdhwr_noopt = 1;
1902         return 1;
1903 }
1904
1905 __setup("rdhwr_noopt", set_rdhwr_noopt);
1906
1907 void __init trap_init(void)
1908 {
1909         extern char except_vec3_generic;
1910         extern char except_vec4;
1911         extern char except_vec3_r4000;
1912         unsigned long i;
1913
1914         check_wait();
1915
1916 #if defined(CONFIG_KGDB)
1917         if (kgdb_early_setup)
1918                 return; /* Already done */
1919 #endif
1920
1921         if (cpu_has_veic || cpu_has_vint) {
1922                 unsigned long size = 0x200 + VECTORSPACING*64;
1923                 ebase = (unsigned long)
1924                         __alloc_bootmem(size, 1 << fls(size), 0);
1925         } else {
1926 #ifdef CONFIG_KVM_GUEST
1927 #define KVM_GUEST_KSEG0     0x40000000
1928         ebase = KVM_GUEST_KSEG0;
1929 #else
1930         ebase = CKSEG0;
1931 #endif
1932                 if (cpu_has_mips_r2)
1933                         ebase += (read_c0_ebase() & 0x3ffff000);
1934         }
1935
1936         if (cpu_has_mmips) {
1937                 unsigned int config3 = read_c0_config3();
1938
1939                 if (IS_ENABLED(CONFIG_CPU_MICROMIPS))
1940                         write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
1941                 else
1942                         write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);
1943         }
1944
1945         if (board_ebase_setup)
1946                 board_ebase_setup();
1947         per_cpu_trap_init(true);
1948
1949         /*
1950          * Copy the generic exception handlers to their final destination.
1951          * This will be overriden later as suitable for a particular
1952          * configuration.
1953          */
1954         set_handler(0x180, &except_vec3_generic, 0x80);
1955
1956         /*
1957          * Setup default vectors
1958          */
1959         for (i = 0; i <= 31; i++)
1960                 set_except_vector(i, handle_reserved);
1961
1962         /*
1963          * Copy the EJTAG debug exception vector handler code to it's final
1964          * destination.
1965          */
1966         if (cpu_has_ejtag && board_ejtag_handler_setup)
1967                 board_ejtag_handler_setup();
1968
1969         /*
1970          * Only some CPUs have the watch exceptions.
1971          */
1972         if (cpu_has_watch)
1973                 set_except_vector(23, handle_watch);
1974
1975         /*
1976          * Initialise interrupt handlers
1977          */
1978         if (cpu_has_veic || cpu_has_vint) {
1979                 int nvec = cpu_has_veic ? 64 : 8;
1980                 for (i = 0; i < nvec; i++)
1981                         set_vi_handler(i, NULL);
1982         }
1983         else if (cpu_has_divec)
1984                 set_handler(0x200, &except_vec4, 0x8);
1985
1986         /*
1987          * Some CPUs can enable/disable for cache parity detection, but does
1988          * it different ways.
1989          */
1990         parity_protection_init();
1991
1992         /*
1993          * The Data Bus Errors / Instruction Bus Errors are signaled
1994          * by external hardware.  Therefore these two exceptions
1995          * may have board specific handlers.
1996          */
1997         if (board_be_init)
1998                 board_be_init();
1999
2000         set_except_vector(0, using_rollback_handler() ? rollback_handle_int
2001                                                       : handle_int);
2002         set_except_vector(1, handle_tlbm);
2003         set_except_vector(2, handle_tlbl);
2004         set_except_vector(3, handle_tlbs);
2005
2006         set_except_vector(4, handle_adel);
2007         set_except_vector(5, handle_ades);
2008
2009         set_except_vector(6, handle_ibe);
2010         set_except_vector(7, handle_dbe);
2011
2012         set_except_vector(8, handle_sys);
2013         set_except_vector(9, handle_bp);
2014         set_except_vector(10, rdhwr_noopt ? handle_ri :
2015                           (cpu_has_vtag_icache ?
2016                            handle_ri_rdhwr_vivt : handle_ri_rdhwr));
2017         set_except_vector(11, handle_cpu);
2018         set_except_vector(12, handle_ov);
2019         set_except_vector(13, handle_tr);
2020
2021         if (current_cpu_type() == CPU_R6000 ||
2022             current_cpu_type() == CPU_R6000A) {
2023                 /*
2024                  * The R6000 is the only R-series CPU that features a machine
2025                  * check exception (similar to the R4000 cache error) and
2026                  * unaligned ldc1/sdc1 exception.  The handlers have not been
2027                  * written yet.  Well, anyway there is no R6000 machine on the
2028                  * current list of targets for Linux/MIPS.
2029                  * (Duh, crap, there is someone with a triple R6k machine)
2030                  */
2031                 //set_except_vector(14, handle_mc);
2032                 //set_except_vector(15, handle_ndc);
2033         }
2034
2035
2036         if (board_nmi_handler_setup)
2037                 board_nmi_handler_setup();
2038
2039         if (cpu_has_fpu && !cpu_has_nofpuex)
2040                 set_except_vector(15, handle_fpe);
2041
2042         set_except_vector(16, handle_ftlb);
2043         set_except_vector(22, handle_mdmx);
2044
2045         if (cpu_has_mcheck)
2046                 set_except_vector(24, handle_mcheck);
2047
2048         if (cpu_has_mipsmt)
2049                 set_except_vector(25, handle_mt);
2050
2051         set_except_vector(26, handle_dsp);
2052
2053         if (board_cache_error_setup)
2054                 board_cache_error_setup();
2055
2056         if (cpu_has_vce)
2057                 /* Special exception: R4[04]00 uses also the divec space. */
2058                 set_handler(0x180, &except_vec3_r4000, 0x100);
2059         else if (cpu_has_4kex)
2060                 set_handler(0x180, &except_vec3_generic, 0x80);
2061         else
2062                 set_handler(0x080, &except_vec3_generic, 0x80);
2063
2064         local_flush_icache_range(ebase, ebase + 0x400);
2065
2066         sort_extable(__start___dbe_table, __stop___dbe_table);
2067
2068         cu2_notifier(default_cu2_call, 0x80000000);     /* Run last  */
2069 }