2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Generation of main entry point for the guest, exception handling.
8 * Copyright (C) 2012 MIPS Technologies, Inc.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
11 * Copyright (C) 2016 Imagination Technologies Ltd.
14 #include <linux/kvm_host.h>
16 #include <asm/setup.h>
27 #if _MIPS_SIM == _MIPS_SIM_ABI32
32 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
34 #if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
39 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
50 /* Some CP0 registers */
51 #define C0_HWRENA 7, 0
52 #define C0_BADVADDR 8, 0
53 #define C0_ENTRYHI 10, 0
54 #define C0_STATUS 12, 0
55 #define C0_CAUSE 13, 0
57 #define C0_EBASE 15, 1
58 #define C0_CONFIG5 16, 5
59 #define C0_DDATA_LO 28, 3
60 #define C0_ERROREPC 30, 0
62 #define CALLFRAME_SIZ 32
64 static unsigned int scratch_vcpu[2] = { C0_DDATA_LO };
65 static unsigned int scratch_tmp[2] = { C0_ERROREPC };
76 UASM_L_LA(_return_to_host)
77 UASM_L_LA(_kernel_asid)
79 static void *kvm_mips_build_enter_guest(void *addr);
80 static void *kvm_mips_build_ret_from_exit(void *addr);
81 static void *kvm_mips_build_ret_to_guest(void *addr);
82 static void *kvm_mips_build_ret_to_host(void *addr);
85 * kvm_mips_entry_setup() - Perform global setup for entry code.
87 * Perform global setup for entry code, such as choosing a scratch register.
89 * Returns: 0 on success.
92 int kvm_mips_entry_setup(void)
95 * We prefer to use KScratchN registers if they are available over the
96 * defaults above, which may not work on all cores.
98 unsigned int kscratch_mask = cpu_data[0].kscratch_mask & 0xfc;
100 /* Pick a scratch register for storing VCPU */
102 scratch_vcpu[0] = 31;
103 scratch_vcpu[1] = ffs(kscratch_mask) - 1;
104 kscratch_mask &= ~BIT(scratch_vcpu[1]);
107 /* Pick a scratch register to use as a temp for saving state */
110 scratch_tmp[1] = ffs(kscratch_mask) - 1;
111 kscratch_mask &= ~BIT(scratch_tmp[1]);
117 static void kvm_mips_build_save_scratch(u32 **p, unsigned int tmp,
120 /* Save the VCPU scratch register value in cp0_epc of the stack frame */
121 uasm_i_mfc0(p, tmp, scratch_vcpu[0], scratch_vcpu[1]);
122 UASM_i_SW(p, tmp, offsetof(struct pt_regs, cp0_epc), frame);
124 /* Save the temp scratch register value in cp0_cause of stack frame */
125 if (scratch_tmp[0] == 31) {
126 uasm_i_mfc0(p, tmp, scratch_tmp[0], scratch_tmp[1]);
127 UASM_i_SW(p, tmp, offsetof(struct pt_regs, cp0_cause), frame);
131 static void kvm_mips_build_restore_scratch(u32 **p, unsigned int tmp,
135 * Restore host scratch register values saved by
136 * kvm_mips_build_save_scratch().
138 UASM_i_LW(p, tmp, offsetof(struct pt_regs, cp0_epc), frame);
139 uasm_i_mtc0(p, tmp, scratch_vcpu[0], scratch_vcpu[1]);
141 if (scratch_tmp[0] == 31) {
142 UASM_i_LW(p, tmp, offsetof(struct pt_regs, cp0_cause), frame);
143 uasm_i_mtc0(p, tmp, scratch_tmp[0], scratch_tmp[1]);
148 * kvm_mips_build_vcpu_run() - Assemble function to start running a guest VCPU.
149 * @addr: Address to start writing code.
151 * Assemble the start of the vcpu_run function to run a guest VCPU. The function
152 * conforms to the following prototype:
154 * int vcpu_run(struct kvm_run *run, struct kvm_vcpu *vcpu);
156 * The exit from the guest and return to the caller is handled by the code
157 * generated by kvm_mips_build_ret_to_host().
159 * Returns: Next address after end of written function.
161 void *kvm_mips_build_vcpu_run(void *addr)
171 /* k0/k1 not being used in host kernel context */
172 uasm_i_addiu(&p, K1, SP, -(int)sizeof(struct pt_regs));
173 for (i = 16; i < 32; ++i) {
176 UASM_i_SW(&p, i, offsetof(struct pt_regs, regs[i]), K1);
181 UASM_i_SW(&p, V0, offsetof(struct pt_regs, lo), K1);
183 UASM_i_SW(&p, V1, offsetof(struct pt_regs, hi), K1);
185 /* Save host status */
186 uasm_i_mfc0(&p, V0, C0_STATUS);
187 UASM_i_SW(&p, V0, offsetof(struct pt_regs, cp0_status), K1);
189 /* Save scratch registers, will be used to store pointer to vcpu etc */
190 kvm_mips_build_save_scratch(&p, V1, K1);
192 /* VCPU scratch register has pointer to vcpu */
193 uasm_i_mtc0(&p, A1, scratch_vcpu[0], scratch_vcpu[1]);
195 /* Offset into vcpu->arch */
196 uasm_i_addiu(&p, K1, A1, offsetof(struct kvm_vcpu, arch));
199 * Save the host stack to VCPU, used for exception processing
200 * when we exit from the Guest
202 UASM_i_SW(&p, SP, offsetof(struct kvm_vcpu_arch, host_stack), K1);
204 /* Save the kernel gp as well */
205 UASM_i_SW(&p, GP, offsetof(struct kvm_vcpu_arch, host_gp), K1);
208 * Setup status register for running the guest in UM, interrupts
211 UASM_i_LA(&p, K0, ST0_EXL | KSU_USER | ST0_BEV);
212 uasm_i_mtc0(&p, K0, C0_STATUS);
215 /* load up the new EBASE */
216 UASM_i_LW(&p, K0, offsetof(struct kvm_vcpu_arch, guest_ebase), K1);
217 uasm_i_mtc0(&p, K0, C0_EBASE);
220 * Now that the new EBASE has been loaded, unset BEV, set
221 * interrupt mask as it was but make sure that timer interrupts
224 uasm_i_addiu(&p, K0, ZERO, ST0_EXL | KSU_USER | ST0_IE);
225 uasm_i_andi(&p, V0, V0, ST0_IM);
226 uasm_i_or(&p, K0, K0, V0);
227 uasm_i_mtc0(&p, K0, C0_STATUS);
230 p = kvm_mips_build_enter_guest(p);
236 * kvm_mips_build_enter_guest() - Assemble code to resume guest execution.
237 * @addr: Address to start writing code.
239 * Assemble the code to resume guest execution. This code is common between the
240 * initial entry into the guest from the host, and returning from the exit
241 * handler back to the guest.
243 * Returns: Next address after end of written function.
245 static void *kvm_mips_build_enter_guest(void *addr)
249 struct uasm_label labels[2];
250 struct uasm_reloc relocs[2];
251 struct uasm_label *l = labels;
252 struct uasm_reloc *r = relocs;
254 memset(labels, 0, sizeof(labels));
255 memset(relocs, 0, sizeof(relocs));
258 UASM_i_LW(&p, T0, offsetof(struct kvm_vcpu_arch, pc), K1);
259 uasm_i_mtc0(&p, T0, C0_EPC);
261 /* Set the ASID for the Guest Kernel */
262 UASM_i_LW(&p, T0, offsetof(struct kvm_vcpu_arch, cop0), K1);
263 UASM_i_LW(&p, T0, offsetof(struct mips_coproc, reg[MIPS_CP0_STATUS][0]),
265 uasm_i_andi(&p, T0, T0, KSU_USER | ST0_ERL | ST0_EXL);
266 uasm_i_xori(&p, T0, T0, KSU_USER);
267 uasm_il_bnez(&p, &r, T0, label_kernel_asid);
268 uasm_i_addiu(&p, T1, K1,
269 offsetof(struct kvm_vcpu_arch, guest_kernel_asid));
271 uasm_i_addiu(&p, T1, K1,
272 offsetof(struct kvm_vcpu_arch, guest_user_asid));
273 uasm_l_kernel_asid(&l, p);
275 /* t1: contains the base of the ASID array, need to get the cpu id */
276 /* smp_processor_id */
277 UASM_i_LW(&p, T2, offsetof(struct thread_info, cpu), GP);
279 uasm_i_sll(&p, T2, T2, 2);
280 UASM_i_ADDU(&p, T3, T1, T2);
281 UASM_i_LW(&p, K0, 0, T3);
282 #ifdef CONFIG_MIPS_ASID_BITS_VARIABLE
283 /* x sizeof(struct cpuinfo_mips)/4 */
284 uasm_i_addiu(&p, T3, ZERO, sizeof(struct cpuinfo_mips)/4);
285 uasm_i_mul(&p, T2, T2, T3);
287 UASM_i_LA_mostly(&p, AT, (long)&cpu_data[0].asid_mask);
288 UASM_i_ADDU(&p, AT, AT, T2);
289 UASM_i_LW(&p, T2, uasm_rel_lo((long)&cpu_data[0].asid_mask), AT);
290 uasm_i_and(&p, K0, K0, T2);
292 uasm_i_andi(&p, K0, K0, MIPS_ENTRYHI_ASID);
294 uasm_i_mtc0(&p, K0, C0_ENTRYHI);
297 /* Disable RDHWR access */
298 uasm_i_mtc0(&p, ZERO, C0_HWRENA);
300 /* load the guest context from VCPU and return */
301 for (i = 1; i < 32; ++i) {
302 /* Guest k0/k1 loaded later */
303 if (i == K0 || i == K1)
305 UASM_i_LW(&p, i, offsetof(struct kvm_vcpu_arch, gprs[i]), K1);
309 UASM_i_LW(&p, K0, offsetof(struct kvm_vcpu_arch, hi), K1);
312 UASM_i_LW(&p, K0, offsetof(struct kvm_vcpu_arch, lo), K1);
315 /* Restore the guest's k0/k1 registers */
316 UASM_i_LW(&p, K0, offsetof(struct kvm_vcpu_arch, gprs[K0]), K1);
317 UASM_i_LW(&p, K1, offsetof(struct kvm_vcpu_arch, gprs[K1]), K1);
322 uasm_resolve_relocs(relocs, labels);
328 * kvm_mips_build_exception() - Assemble first level guest exception handler.
329 * @addr: Address to start writing code.
331 * Assemble exception vector code for guest execution. The generated vector will
332 * jump to the common exception handler generated by kvm_mips_build_exit().
334 * Returns: Next address after end of written function.
336 void *kvm_mips_build_exception(void *addr)
341 uasm_i_mtc0(&p, K0, scratch_tmp[0], scratch_tmp[1]);
345 uasm_i_mfc0(&p, K0, C0_EBASE);
346 /* Get rid of CPUNum */
347 uasm_i_srl(&p, K0, K0, 10);
348 uasm_i_sll(&p, K0, K0, 10);
349 /* Save k1 @ offset 0x3000 */
350 UASM_i_SW(&p, K1, 0x3000, K0);
352 /* Exception handler is installed @ offset 0x2000 */
353 uasm_i_addiu(&p, K0, K0, 0x2000);
354 /* Jump to the function */
362 * kvm_mips_build_exit() - Assemble common guest exit handler.
363 * @addr: Address to start writing code.
365 * Assemble the generic guest exit handling code. This is called by the
366 * exception vectors (generated by kvm_mips_build_exception()), and calls
367 * kvm_mips_handle_exit(), then either resumes the guest or returns to the host
368 * depending on the return value.
370 * Returns: Next address after end of written function.
372 void *kvm_mips_build_exit(void *addr)
376 struct uasm_label labels[3];
377 struct uasm_reloc relocs[3];
378 struct uasm_label *l = labels;
379 struct uasm_reloc *r = relocs;
381 memset(labels, 0, sizeof(labels));
382 memset(relocs, 0, sizeof(relocs));
385 * Generic Guest exception handler. We end up here when the guest
386 * does something that causes a trap to kernel mode.
389 /* Get the VCPU pointer from the scratch register */
390 uasm_i_mfc0(&p, K1, scratch_vcpu[0], scratch_vcpu[1]);
391 uasm_i_addiu(&p, K1, K1, offsetof(struct kvm_vcpu, arch));
393 /* Start saving Guest context to VCPU */
394 for (i = 0; i < 32; ++i) {
395 /* Guest k0/k1 saved later */
396 if (i == K0 || i == K1)
398 UASM_i_SW(&p, i, offsetof(struct kvm_vcpu_arch, gprs[i]), K1);
401 /* We need to save hi/lo and restore them on the way out */
403 UASM_i_SW(&p, T0, offsetof(struct kvm_vcpu_arch, hi), K1);
406 UASM_i_SW(&p, T0, offsetof(struct kvm_vcpu_arch, lo), K1);
408 /* Finally save guest k0/k1 to VCPU */
409 uasm_i_mfc0(&p, T0, scratch_tmp[0], scratch_tmp[1]);
410 UASM_i_SW(&p, T0, offsetof(struct kvm_vcpu_arch, gprs[K0]), K1);
412 /* Get GUEST k1 and save it in VCPU */
413 uasm_i_addiu(&p, T1, ZERO, ~0x2ff);
414 uasm_i_mfc0(&p, T0, C0_EBASE);
415 uasm_i_and(&p, T0, T0, T1);
416 UASM_i_LW(&p, T0, 0x3000, T0);
417 UASM_i_SW(&p, T0, offsetof(struct kvm_vcpu_arch, gprs[K1]), K1);
419 /* Now that context has been saved, we can use other registers */
422 uasm_i_mfc0(&p, A1, scratch_vcpu[0], scratch_vcpu[1]);
423 uasm_i_move(&p, S1, A1);
425 /* Restore run (vcpu->run) */
426 UASM_i_LW(&p, A0, offsetof(struct kvm_vcpu, run), A1);
427 /* Save pointer to run in s0, will be saved by the compiler */
428 uasm_i_move(&p, S0, A0);
431 * Save Host level EPC, BadVaddr and Cause to VCPU, useful to process
434 uasm_i_mfc0(&p, K0, C0_EPC);
435 UASM_i_SW(&p, K0, offsetof(struct kvm_vcpu_arch, pc), K1);
437 uasm_i_mfc0(&p, K0, C0_BADVADDR);
438 UASM_i_SW(&p, K0, offsetof(struct kvm_vcpu_arch, host_cp0_badvaddr),
441 uasm_i_mfc0(&p, K0, C0_CAUSE);
442 uasm_i_sw(&p, K0, offsetof(struct kvm_vcpu_arch, host_cp0_cause), K1);
444 /* Now restore the host state just enough to run the handlers */
446 /* Switch EBASE to the one used by Linux */
447 /* load up the host EBASE */
448 uasm_i_mfc0(&p, V0, C0_STATUS);
450 uasm_i_lui(&p, AT, ST0_BEV >> 16);
451 uasm_i_or(&p, K0, V0, AT);
453 uasm_i_mtc0(&p, K0, C0_STATUS);
456 UASM_i_LA_mostly(&p, K0, (long)&ebase);
457 UASM_i_LW(&p, K0, uasm_rel_lo((long)&ebase), K0);
458 uasm_i_mtc0(&p, K0, C0_EBASE);
460 if (raw_cpu_has_fpu) {
462 * If FPU is enabled, save FCR31 and clear it so that later
463 * ctc1's don't trigger FPE for pending exceptions.
465 uasm_i_lui(&p, AT, ST0_CU1 >> 16);
466 uasm_i_and(&p, V1, V0, AT);
467 uasm_il_beqz(&p, &r, V1, label_fpu_1);
469 uasm_i_cfc1(&p, T0, 31);
470 uasm_i_sw(&p, T0, offsetof(struct kvm_vcpu_arch, fpu.fcr31),
472 uasm_i_ctc1(&p, ZERO, 31);
478 * If MSA is enabled, save MSACSR and clear it so that later
479 * instructions don't trigger MSAFPE for pending exceptions.
481 uasm_i_mfc0(&p, T0, C0_CONFIG5);
482 uasm_i_ext(&p, T0, T0, 27, 1); /* MIPS_CONF5_MSAEN */
483 uasm_il_beqz(&p, &r, T0, label_msa_1);
485 uasm_i_cfcmsa(&p, T0, MSA_CSR);
486 uasm_i_sw(&p, T0, offsetof(struct kvm_vcpu_arch, fpu.msacsr),
488 uasm_i_ctcmsa(&p, MSA_CSR, ZERO);
492 /* Now that the new EBASE has been loaded, unset BEV and KSU_USER */
493 uasm_i_addiu(&p, AT, ZERO, ~(ST0_EXL | KSU_USER | ST0_IE));
494 uasm_i_and(&p, V0, V0, AT);
495 uasm_i_lui(&p, AT, ST0_CU0 >> 16);
496 uasm_i_or(&p, V0, V0, AT);
497 uasm_i_mtc0(&p, V0, C0_STATUS);
500 /* Load up host GP */
501 UASM_i_LW(&p, GP, offsetof(struct kvm_vcpu_arch, host_gp), K1);
503 /* Need a stack before we can jump to "C" */
504 UASM_i_LW(&p, SP, offsetof(struct kvm_vcpu_arch, host_stack), K1);
506 /* Saved host state */
507 uasm_i_addiu(&p, SP, SP, -(int)sizeof(struct pt_regs));
510 * XXXKYMA do we need to load the host ASID, maybe not because the
511 * kernel entries are marked GLOBAL, need to verify
514 /* Restore host scratch registers, as we'll have clobbered them */
515 kvm_mips_build_restore_scratch(&p, K0, SP);
517 /* Restore RDHWR access */
518 UASM_i_LA_mostly(&p, K0, (long)&hwrena);
519 uasm_i_lw(&p, K0, uasm_rel_lo((long)&hwrena), K0);
520 uasm_i_mtc0(&p, K0, C0_HWRENA);
522 /* Jump to handler */
524 * XXXKYMA: not sure if this is safe, how large is the stack??
525 * Now jump to the kvm_mips_handle_exit() to see if we can deal
526 * with this in the kernel
528 UASM_i_LA(&p, T9, (unsigned long)kvm_mips_handle_exit);
529 uasm_i_jalr(&p, RA, T9);
530 uasm_i_addiu(&p, SP, SP, -CALLFRAME_SIZ);
532 uasm_resolve_relocs(relocs, labels);
534 p = kvm_mips_build_ret_from_exit(p);
540 * kvm_mips_build_ret_from_exit() - Assemble guest exit return handler.
541 * @addr: Address to start writing code.
543 * Assemble the code to handle the return from kvm_mips_handle_exit(), either
544 * resuming the guest or returning to the host depending on the return value.
546 * Returns: Next address after end of written function.
548 static void *kvm_mips_build_ret_from_exit(void *addr)
551 struct uasm_label labels[2];
552 struct uasm_reloc relocs[2];
553 struct uasm_label *l = labels;
554 struct uasm_reloc *r = relocs;
556 memset(labels, 0, sizeof(labels));
557 memset(relocs, 0, sizeof(relocs));
559 /* Return from handler Make sure interrupts are disabled */
564 * XXXKYMA: k0/k1 could have been blown away if we processed
565 * an exception while we were handling the exception from the
569 uasm_i_move(&p, K1, S1);
570 uasm_i_addiu(&p, K1, K1, offsetof(struct kvm_vcpu, arch));
573 * Check return value, should tell us if we are returning to the
574 * host (handle I/O etc)or resuming the guest
576 uasm_i_andi(&p, T0, V0, RESUME_HOST);
577 uasm_il_bnez(&p, &r, T0, label_return_to_host);
580 p = kvm_mips_build_ret_to_guest(p);
582 uasm_l_return_to_host(&l, p);
583 p = kvm_mips_build_ret_to_host(p);
585 uasm_resolve_relocs(relocs, labels);
591 * kvm_mips_build_ret_to_guest() - Assemble code to return to the guest.
592 * @addr: Address to start writing code.
594 * Assemble the code to handle return from the guest exit handler
595 * (kvm_mips_handle_exit()) back to the guest.
597 * Returns: Next address after end of written function.
599 static void *kvm_mips_build_ret_to_guest(void *addr)
603 /* Put the saved pointer to vcpu (s1) back into the scratch register */
604 uasm_i_mtc0(&p, S1, scratch_vcpu[0], scratch_vcpu[1]);
606 /* Load up the Guest EBASE to minimize the window where BEV is set */
607 UASM_i_LW(&p, T0, offsetof(struct kvm_vcpu_arch, guest_ebase), K1);
609 /* Switch EBASE back to the one used by KVM */
610 uasm_i_mfc0(&p, V1, C0_STATUS);
611 uasm_i_lui(&p, AT, ST0_BEV >> 16);
612 uasm_i_or(&p, K0, V1, AT);
613 uasm_i_mtc0(&p, K0, C0_STATUS);
615 uasm_i_mtc0(&p, T0, C0_EBASE);
617 /* Setup status register for running guest in UM */
618 uasm_i_ori(&p, V1, V1, ST0_EXL | KSU_USER | ST0_IE);
619 UASM_i_LA(&p, AT, ~(ST0_CU0 | ST0_MX));
620 uasm_i_and(&p, V1, V1, AT);
621 uasm_i_mtc0(&p, V1, C0_STATUS);
624 p = kvm_mips_build_enter_guest(p);
630 * kvm_mips_build_ret_to_host() - Assemble code to return to the host.
631 * @addr: Address to start writing code.
633 * Assemble the code to handle return from the guest exit handler
634 * (kvm_mips_handle_exit()) back to the host, i.e. to the caller of the vcpu_run
635 * function generated by kvm_mips_build_vcpu_run().
637 * Returns: Next address after end of written function.
639 static void *kvm_mips_build_ret_to_host(void *addr)
644 /* EBASE is already pointing to Linux */
645 UASM_i_LW(&p, K1, offsetof(struct kvm_vcpu_arch, host_stack), K1);
646 uasm_i_addiu(&p, K1, K1, -(int)sizeof(struct pt_regs));
649 * r2/v0 is the return code, shift it down by 2 (arithmetic)
650 * to recover the err code
652 uasm_i_sra(&p, K0, V0, 2);
653 uasm_i_move(&p, V0, K0);
655 /* Load context saved on the host stack */
656 for (i = 16; i < 31; ++i) {
659 UASM_i_LW(&p, i, offsetof(struct pt_regs, regs[i]), K1);
662 UASM_i_LW(&p, K0, offsetof(struct pt_regs, hi), K1);
665 UASM_i_LW(&p, K0, offsetof(struct pt_regs, lo), K1);
668 /* Restore RDHWR access */
669 UASM_i_LA_mostly(&p, K0, (long)&hwrena);
670 uasm_i_lw(&p, K0, uasm_rel_lo((long)&hwrena), K0);
671 uasm_i_mtc0(&p, K0, C0_HWRENA);
673 /* Restore RA, which is the address we will return to */
674 UASM_i_LW(&p, RA, offsetof(struct pt_regs, regs[RA]), K1);