arch/mips/math-emu/cp1emu.c

   1 /*
   2  * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
   3  *
   4  * MIPS floating point support
   5  * Copyright (C) 1994-2000 Algorithmics Ltd.
   6  *
   7  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
   8  * Copyright (C) 2000  MIPS Technologies, Inc.
   9  *
  10  *  This program is free software; you can distribute it and/or modify it
  11  *  under the terms of the GNU General Public License (Version 2) as
  12  *  published by the Free Software Foundation.
  13  *
  14  *  This program is distributed in the hope it will be useful, but WITHOUT
  15  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  17  *  for more details.
  18  *
  19  *  You should have received a copy of the GNU General Public License along
  20  *  with this program; if not, write to the Free Software Foundation, Inc.,
  21  *  51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA.
  22  *
  23  * A complete emulator for MIPS coprocessor 1 instructions.  This is
  24  * required for #float(switch) or #float(trap), where it catches all
  25  * COP1 instructions via the "CoProcessor Unusable" exception.
  26  *
  27  * More surprisingly it is also required for #float(ieee), to help out
  28  * the hardware FPU at the boundaries of the IEEE-754 representation
  29  * (denormalised values, infinities, underflow, etc).  It is made
  30  * quite nasty because emulation of some non-COP1 instructions is
  31  * required, e.g. in branch delay slots.
  32  *
  33  * Note if you know that you won't have an FPU, then you'll get much
  34  * better performance by compiling with -msoft-float!
  35  */
  36 #include <linux/sched.h>
  37 #include <linux/debugfs.h>
  38 #include <linux/kconfig.h>
  39 #include <linux/percpu-defs.h>
  40 #include <linux/perf_event.h>
  41
  42 #include <asm/branch.h>
  43 #include <asm/inst.h>
  44 #include <asm/ptrace.h>
  45 #include <asm/signal.h>
  46 #include <asm/uaccess.h>
  47
  48 #include <asm/processor.h>
  49 #include <asm/fpu_emulator.h>
  50 #include <asm/fpu.h>
  51
  52 #include "ieee754.h"
  53
  54 /* Function which emulates a floating point instruction. */
  55
  56 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
  57         mips_instruction);
  58
  59 static int fpux_emu(struct pt_regs *,
  60         struct mips_fpu_struct *, mips_instruction, void *__user *);
  61
  62 /* Control registers */
  63
  64 #define FPCREG_RID      0       /* $0  = revision id */
  65 #define FPCREG_CSR      31      /* $31 = csr */
  66
  67 /* Determine rounding mode from the RM bits of the FCSR */
  68 #define modeindex(v) ((v) & FPU_CSR_RM)
  69
  70 /* convert condition code register number to csr bit */
  71 static const unsigned int fpucondbit[8] = {
  72         FPU_CSR_COND0,
  73         FPU_CSR_COND1,
  74         FPU_CSR_COND2,
  75         FPU_CSR_COND3,
  76         FPU_CSR_COND4,
  77         FPU_CSR_COND5,
  78         FPU_CSR_COND6,
  79         FPU_CSR_COND7
  80 };
  81
  82 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
  83 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
  84 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
  85 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
  86 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
  87
  88 /*
  89  * This functions translates a 32-bit microMIPS instruction
  90  * into a 32-bit MIPS32 instruction. Returns 0 on success
  91  * and SIGILL otherwise.
  92  */
  93 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
  94 {
  95         union mips_instruction insn = *insn_ptr;
  96         union mips_instruction mips32_insn = insn;
  97         int func, fmt, op;
  98
  99         switch (insn.mm_i_format.opcode) {
 100         case mm_ldc132_op:
 101                 mips32_insn.mm_i_format.opcode = ldc1_op;
 102                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 103                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 104                 break;
 105         case mm_lwc132_op:
 106                 mips32_insn.mm_i_format.opcode = lwc1_op;
 107                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 108                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 109                 break;
 110         case mm_sdc132_op:
 111                 mips32_insn.mm_i_format.opcode = sdc1_op;
 112                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 113                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 114                 break;
 115         case mm_swc132_op:
 116                 mips32_insn.mm_i_format.opcode = swc1_op;
 117                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 118                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 119                 break;
 120         case mm_pool32i_op:
 121                 /* NOTE: offset is << by 1 if in microMIPS mode. */
 122                 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
 123                     (insn.mm_i_format.rt == mm_bc1t_op)) {
 124                         mips32_insn.fb_format.opcode = cop1_op;
 125                         mips32_insn.fb_format.bc = bc_op;
 126                         mips32_insn.fb_format.flag =
 127                                 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
 128                 } else
 129                         return SIGILL;
 130                 break;
 131         case mm_pool32f_op:
 132                 switch (insn.mm_fp0_format.func) {
 133                 case mm_32f_01_op:
 134                 case mm_32f_11_op:
 135                 case mm_32f_02_op:
 136                 case mm_32f_12_op:
 137                 case mm_32f_41_op:
 138                 case mm_32f_51_op:
 139                 case mm_32f_42_op:
 140                 case mm_32f_52_op:
 141                         op = insn.mm_fp0_format.func;
 142                         if (op == mm_32f_01_op)
 143                                 func = madd_s_op;
 144                         else if (op == mm_32f_11_op)
 145                                 func = madd_d_op;
 146                         else if (op == mm_32f_02_op)
 147                                 func = nmadd_s_op;
 148                         else if (op == mm_32f_12_op)
 149                                 func = nmadd_d_op;
 150                         else if (op == mm_32f_41_op)
 151                                 func = msub_s_op;
 152                         else if (op == mm_32f_51_op)
 153                                 func = msub_d_op;
 154                         else if (op == mm_32f_42_op)
 155                                 func = nmsub_s_op;
 156                         else
 157                                 func = nmsub_d_op;
 158                         mips32_insn.fp6_format.opcode = cop1x_op;
 159                         mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
 160                         mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
 161                         mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
 162                         mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
 163                         mips32_insn.fp6_format.func = func;
 164                         break;
 165                 case mm_32f_10_op:
 166                         func = -1;      /* Invalid */
 167                         op = insn.mm_fp5_format.op & 0x7;
 168                         if (op == mm_ldxc1_op)
 169                                 func = ldxc1_op;
 170                         else if (op == mm_sdxc1_op)
 171                                 func = sdxc1_op;
 172                         else if (op == mm_lwxc1_op)
 173                                 func = lwxc1_op;
 174                         else if (op == mm_swxc1_op)
 175                                 func = swxc1_op;
 176
 177                         if (func != -1) {
 178                                 mips32_insn.r_format.opcode = cop1x_op;
 179                                 mips32_insn.r_format.rs =
 180                                         insn.mm_fp5_format.base;
 181                                 mips32_insn.r_format.rt =
 182                                         insn.mm_fp5_format.index;
 183                                 mips32_insn.r_format.rd = 0;
 184                                 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
 185                                 mips32_insn.r_format.func = func;
 186                         } else
 187                                 return SIGILL;
 188                         break;
 189                 case mm_32f_40_op:
 190                         op = -1;        /* Invalid */
 191                         if (insn.mm_fp2_format.op == mm_fmovt_op)
 192                                 op = 1;
 193                         else if (insn.mm_fp2_format.op == mm_fmovf_op)
 194                                 op = 0;
 195                         if (op != -1) {
 196                                 mips32_insn.fp0_format.opcode = cop1_op;
 197                                 mips32_insn.fp0_format.fmt =
 198                                         sdps_format[insn.mm_fp2_format.fmt];
 199                                 mips32_insn.fp0_format.ft =
 200                                         (insn.mm_fp2_format.cc<<2) + op;
 201                                 mips32_insn.fp0_format.fs =
 202                                         insn.mm_fp2_format.fs;
 203                                 mips32_insn.fp0_format.fd =
 204                                         insn.mm_fp2_format.fd;
 205                                 mips32_insn.fp0_format.func = fmovc_op;
 206                         } else
 207                                 return SIGILL;
 208                         break;
 209                 case mm_32f_60_op:
 210                         func = -1;      /* Invalid */
 211                         if (insn.mm_fp0_format.op == mm_fadd_op)
 212                                 func = fadd_op;
 213                         else if (insn.mm_fp0_format.op == mm_fsub_op)
 214                                 func = fsub_op;
 215                         else if (insn.mm_fp0_format.op == mm_fmul_op)
 216                                 func = fmul_op;
 217                         else if (insn.mm_fp0_format.op == mm_fdiv_op)
 218                                 func = fdiv_op;
 219                         if (func != -1) {
 220                                 mips32_insn.fp0_format.opcode = cop1_op;
 221                                 mips32_insn.fp0_format.fmt =
 222                                         sdps_format[insn.mm_fp0_format.fmt];
 223                                 mips32_insn.fp0_format.ft =
 224                                         insn.mm_fp0_format.ft;
 225                                 mips32_insn.fp0_format.fs =
 226                                         insn.mm_fp0_format.fs;
 227                                 mips32_insn.fp0_format.fd =
 228                                         insn.mm_fp0_format.fd;
 229                                 mips32_insn.fp0_format.func = func;
 230                         } else
 231                                 return SIGILL;
 232                         break;
 233                 case mm_32f_70_op:
 234                         func = -1;      /* Invalid */
 235                         if (insn.mm_fp0_format.op == mm_fmovn_op)
 236                                 func = fmovn_op;
 237                         else if (insn.mm_fp0_format.op == mm_fmovz_op)
 238                                 func = fmovz_op;
 239                         if (func != -1) {
 240                                 mips32_insn.fp0_format.opcode = cop1_op;
 241                                 mips32_insn.fp0_format.fmt =
 242                                         sdps_format[insn.mm_fp0_format.fmt];
 243                                 mips32_insn.fp0_format.ft =
 244                                         insn.mm_fp0_format.ft;
 245                                 mips32_insn.fp0_format.fs =
 246                                         insn.mm_fp0_format.fs;
 247                                 mips32_insn.fp0_format.fd =
 248                                         insn.mm_fp0_format.fd;
 249                                 mips32_insn.fp0_format.func = func;
 250                         } else
 251                                 return SIGILL;
 252                         break;
 253                 case mm_32f_73_op:    /* POOL32FXF */
 254                         switch (insn.mm_fp1_format.op) {
 255                         case mm_movf0_op:
 256                         case mm_movf1_op:
 257                         case mm_movt0_op:
 258                         case mm_movt1_op:
 259                                 if ((insn.mm_fp1_format.op & 0x7f) ==
 260                                     mm_movf0_op)
 261                                         op = 0;
 262                                 else
 263                                         op = 1;
 264                                 mips32_insn.r_format.opcode = spec_op;
 265                                 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
 266                                 mips32_insn.r_format.rt =
 267                                         (insn.mm_fp4_format.cc << 2) + op;
 268                                 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
 269                                 mips32_insn.r_format.re = 0;
 270                                 mips32_insn.r_format.func = movc_op;
 271                                 break;
 272                         case mm_fcvtd0_op:
 273                         case mm_fcvtd1_op:
 274                         case mm_fcvts0_op:
 275                         case mm_fcvts1_op:
 276                                 if ((insn.mm_fp1_format.op & 0x7f) ==
 277                                     mm_fcvtd0_op) {
 278                                         func = fcvtd_op;
 279                                         fmt = swl_format[insn.mm_fp3_format.fmt];
 280                                 } else {
 281                                         func = fcvts_op;
 282                                         fmt = dwl_format[insn.mm_fp3_format.fmt];
 283                                 }
 284                                 mips32_insn.fp0_format.opcode = cop1_op;
 285                                 mips32_insn.fp0_format.fmt = fmt;
 286                                 mips32_insn.fp0_format.ft = 0;
 287                                 mips32_insn.fp0_format.fs =
 288                                         insn.mm_fp3_format.fs;
 289                                 mips32_insn.fp0_format.fd =
 290                                         insn.mm_fp3_format.rt;
 291                                 mips32_insn.fp0_format.func = func;
 292                                 break;
 293                         case mm_fmov0_op:
 294                         case mm_fmov1_op:
 295                         case mm_fabs0_op:
 296                         case mm_fabs1_op:
 297                         case mm_fneg0_op:
 298                         case mm_fneg1_op:
 299                                 if ((insn.mm_fp1_format.op & 0x7f) ==
 300                                     mm_fmov0_op)
 301                                         func = fmov_op;
 302                                 else if ((insn.mm_fp1_format.op & 0x7f) ==
 303                                          mm_fabs0_op)
 304                                         func = fabs_op;
 305                                 else
 306                                         func = fneg_op;
 307                                 mips32_insn.fp0_format.opcode = cop1_op;
 308                                 mips32_insn.fp0_format.fmt =
 309                                         sdps_format[insn.mm_fp3_format.fmt];
 310                                 mips32_insn.fp0_format.ft = 0;
 311                                 mips32_insn.fp0_format.fs =
 312                                         insn.mm_fp3_format.fs;
 313                                 mips32_insn.fp0_format.fd =
 314                                         insn.mm_fp3_format.rt;
 315                                 mips32_insn.fp0_format.func = func;
 316                                 break;
 317                         case mm_ffloorl_op:
 318                         case mm_ffloorw_op:
 319                         case mm_fceill_op:
 320                         case mm_fceilw_op:
 321                         case mm_ftruncl_op:
 322                         case mm_ftruncw_op:
 323                         case mm_froundl_op:
 324                         case mm_froundw_op:
 325                         case mm_fcvtl_op:
 326                         case mm_fcvtw_op:
 327                                 if (insn.mm_fp1_format.op == mm_ffloorl_op)
 328                                         func = ffloorl_op;
 329                                 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
 330                                         func = ffloor_op;
 331                                 else if (insn.mm_fp1_format.op == mm_fceill_op)
 332                                         func = fceill_op;
 333                                 else if (insn.mm_fp1_format.op == mm_fceilw_op)
 334                                         func = fceil_op;
 335                                 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
 336                                         func = ftruncl_op;
 337                                 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
 338                                         func = ftrunc_op;
 339                                 else if (insn.mm_fp1_format.op == mm_froundl_op)
 340                                         func = froundl_op;
 341                                 else if (insn.mm_fp1_format.op == mm_froundw_op)
 342                                         func = fround_op;
 343                                 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
 344                                         func = fcvtl_op;
 345                                 else
 346                                         func = fcvtw_op;
 347                                 mips32_insn.fp0_format.opcode = cop1_op;
 348                                 mips32_insn.fp0_format.fmt =
 349                                         sd_format[insn.mm_fp1_format.fmt];
 350                                 mips32_insn.fp0_format.ft = 0;
 351                                 mips32_insn.fp0_format.fs =
 352                                         insn.mm_fp1_format.fs;
 353                                 mips32_insn.fp0_format.fd =
 354                                         insn.mm_fp1_format.rt;
 355                                 mips32_insn.fp0_format.func = func;
 356                                 break;
 357                         case mm_frsqrt_op:
 358                         case mm_fsqrt_op:
 359                         case mm_frecip_op:
 360                                 if (insn.mm_fp1_format.op == mm_frsqrt_op)
 361                                         func = frsqrt_op;
 362                                 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
 363                                         func = fsqrt_op;
 364                                 else
 365                                         func = frecip_op;
 366                                 mips32_insn.fp0_format.opcode = cop1_op;
 367                                 mips32_insn.fp0_format.fmt =
 368                                         sdps_format[insn.mm_fp1_format.fmt];
 369                                 mips32_insn.fp0_format.ft = 0;
 370                                 mips32_insn.fp0_format.fs =
 371                                         insn.mm_fp1_format.fs;
 372                                 mips32_insn.fp0_format.fd =
 373                                         insn.mm_fp1_format.rt;
 374                                 mips32_insn.fp0_format.func = func;
 375                                 break;
 376                         case mm_mfc1_op:
 377                         case mm_mtc1_op:
 378                         case mm_cfc1_op:
 379                         case mm_ctc1_op:
 380                         case mm_mfhc1_op:
 381                         case mm_mthc1_op:
 382                                 if (insn.mm_fp1_format.op == mm_mfc1_op)
 383                                         op = mfc_op;
 384                                 else if (insn.mm_fp1_format.op == mm_mtc1_op)
 385                                         op = mtc_op;
 386                                 else if (insn.mm_fp1_format.op == mm_cfc1_op)
 387                                         op = cfc_op;
 388                                 else if (insn.mm_fp1_format.op == mm_ctc1_op)
 389                                         op = ctc_op;
 390                                 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
 391                                         op = mfhc_op;
 392                                 else
 393                                         op = mthc_op;
 394                                 mips32_insn.fp1_format.opcode = cop1_op;
 395                                 mips32_insn.fp1_format.op = op;
 396                                 mips32_insn.fp1_format.rt =
 397                                         insn.mm_fp1_format.rt;
 398                                 mips32_insn.fp1_format.fs =
 399                                         insn.mm_fp1_format.fs;
 400                                 mips32_insn.fp1_format.fd = 0;
 401                                 mips32_insn.fp1_format.func = 0;
 402                                 break;
 403                         default:
 404                                 return SIGILL;
 405                         }
 406                         break;
 407                 case mm_32f_74_op:      /* c.cond.fmt */
 408                         mips32_insn.fp0_format.opcode = cop1_op;
 409                         mips32_insn.fp0_format.fmt =
 410                                 sdps_format[insn.mm_fp4_format.fmt];
 411                         mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
 412                         mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
 413                         mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
 414                         mips32_insn.fp0_format.func =
 415                                 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
 416                         break;
 417                 default:
 418                         return SIGILL;
 419                 }
 420                 break;
 421         default:
 422                 return SIGILL;
 423         }
 424
 425         *insn_ptr = mips32_insn;
 426         return 0;
 427 }
 428
 429 /*
 430  * Redundant with logic already in kernel/branch.c,
 431  * embedded in compute_return_epc.  At some point,
 432  * a single subroutine should be used across both
 433  * modules.
 434  */
 435 static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
 436                          unsigned long *contpc)
 437 {
 438         union mips_instruction insn = (union mips_instruction)dec_insn.insn;
 439         unsigned int fcr31;
 440         unsigned int bit = 0;
 441
 442         switch (insn.i_format.opcode) {
 443         case spec_op:
 444                 switch (insn.r_format.func) {
 445                 case jalr_op:
 446                         regs->regs[insn.r_format.rd] =
 447                                 regs->cp0_epc + dec_insn.pc_inc +
 448                                 dec_insn.next_pc_inc;
 449                         /* Fall through */
 450                 case jr_op:
 451                         /* For R6, JR already emulated in jalr_op */
 452                         if (NO_R6EMU && insn.r_format.opcode == jr_op)
 453                                 break;
 454                         *contpc = regs->regs[insn.r_format.rs];
 455                         return 1;
 456                 }
 457                 break;
 458         case bcond_op:
 459                 switch (insn.i_format.rt) {
 460                 case bltzal_op:
 461                 case bltzall_op:
 462                         if (NO_R6EMU && (insn.i_format.rs ||
 463                             insn.i_format.rt == bltzall_op))
 464                                 break;
 465
 466                         regs->regs[31] = regs->cp0_epc +
 467                                 dec_insn.pc_inc +
 468                                 dec_insn.next_pc_inc;
 469                         /* Fall through */
 470                 case bltzl_op:
 471                         if (NO_R6EMU)
 472                                 break;
 473                 case bltz_op:
 474                         if ((long)regs->regs[insn.i_format.rs] < 0)
 475                                 *contpc = regs->cp0_epc +
 476                                         dec_insn.pc_inc +
 477                                         (insn.i_format.simmediate << 2);
 478                         else
 479                                 *contpc = regs->cp0_epc +
 480                                         dec_insn.pc_inc +
 481                                         dec_insn.next_pc_inc;
 482                         return 1;
 483                 case bgezal_op:
 484                 case bgezall_op:
 485                         if (NO_R6EMU && (insn.i_format.rs ||
 486                             insn.i_format.rt == bgezall_op))
 487                                 break;
 488
 489                         regs->regs[31] = regs->cp0_epc +
 490                                 dec_insn.pc_inc +
 491                                 dec_insn.next_pc_inc;
 492                         /* Fall through */
 493                 case bgezl_op:
 494                         if (NO_R6EMU)
 495                                 break;
 496                 case bgez_op:
 497                         if ((long)regs->regs[insn.i_format.rs] >= 0)
 498                                 *contpc = regs->cp0_epc +
 499                                         dec_insn.pc_inc +
 500                                         (insn.i_format.simmediate << 2);
 501                         else
 502                                 *contpc = regs->cp0_epc +
 503                                         dec_insn.pc_inc +
 504                                         dec_insn.next_pc_inc;
 505                         return 1;
 506                 }
 507                 break;
 508         case jalx_op:
 509                 set_isa16_mode(bit);
 510         case jal_op:
 511                 regs->regs[31] = regs->cp0_epc +
 512                         dec_insn.pc_inc +
 513                         dec_insn.next_pc_inc;
 514                 /* Fall through */
 515         case j_op:
 516                 *contpc = regs->cp0_epc + dec_insn.pc_inc;
 517                 *contpc >>= 28;
 518                 *contpc <<= 28;
 519                 *contpc |= (insn.j_format.target << 2);
 520                 /* Set microMIPS mode bit: XOR for jalx. */
 521                 *contpc ^= bit;
 522                 return 1;
 523         case beql_op:
 524                 if (NO_R6EMU)
 525                         break;
 526         case beq_op:
 527                 if (regs->regs[insn.i_format.rs] ==
 528                     regs->regs[insn.i_format.rt])
 529                         *contpc = regs->cp0_epc +
 530                                 dec_insn.pc_inc +
 531                                 (insn.i_format.simmediate << 2);
 532                 else
 533                         *contpc = regs->cp0_epc +
 534                                 dec_insn.pc_inc +
 535                                 dec_insn.next_pc_inc;
 536                 return 1;
 537         case bnel_op:
 538                 if (NO_R6EMU)
 539                         break;
 540         case bne_op:
 541                 if (regs->regs[insn.i_format.rs] !=
 542                     regs->regs[insn.i_format.rt])
 543                         *contpc = regs->cp0_epc +
 544                                 dec_insn.pc_inc +
 545                                 (insn.i_format.simmediate << 2);
 546                 else
 547                         *contpc = regs->cp0_epc +
 548                                 dec_insn.pc_inc +
 549                                 dec_insn.next_pc_inc;
 550                 return 1;
 551         case blezl_op:
 552                 if (NO_R6EMU)
 553                         break;
 554         case blez_op:
 555                 if ((long)regs->regs[insn.i_format.rs] <= 0)
 556                         *contpc = regs->cp0_epc +
 557                                 dec_insn.pc_inc +
 558                                 (insn.i_format.simmediate << 2);
 559                 else
 560                         *contpc = regs->cp0_epc +
 561                                 dec_insn.pc_inc +
 562                                 dec_insn.next_pc_inc;
 563                 return 1;
 564         case bgtzl_op:
 565                 if (NO_R6EMU)
 566                         break;
 567         case bgtz_op:
 568                 if ((long)regs->regs[insn.i_format.rs] > 0)
 569                         *contpc = regs->cp0_epc +
 570                                 dec_insn.pc_inc +
 571                                 (insn.i_format.simmediate << 2);
 572                 else
 573                         *contpc = regs->cp0_epc +
 574                                 dec_insn.pc_inc +
 575                                 dec_insn.next_pc_inc;
 576                 return 1;
 577 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 578         case lwc2_op: /* This is bbit0 on Octeon */
 579                 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
 580                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 581                 else
 582                         *contpc = regs->cp0_epc + 8;
 583                 return 1;
 584         case ldc2_op: /* This is bbit032 on Octeon */
 585                 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
 586                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 587                 else
 588                         *contpc = regs->cp0_epc + 8;
 589                 return 1;
 590         case swc2_op: /* This is bbit1 on Octeon */
 591                 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
 592                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 593                 else
 594                         *contpc = regs->cp0_epc + 8;
 595                 return 1;
 596         case sdc2_op: /* This is bbit132 on Octeon */
 597                 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
 598                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 599                 else
 600                         *contpc = regs->cp0_epc + 8;
 601                 return 1;
 602 #endif
 603         case cop0_op:
 604         case cop1_op:
 605         case cop2_op:
 606         case cop1x_op:
 607                 if (insn.i_format.rs == bc_op) {
 608                         preempt_disable();
 609                         if (is_fpu_owner())
 610                                 fcr31 = read_32bit_cp1_register(CP1_STATUS);
 611                         else
 612                                 fcr31 = current->thread.fpu.fcr31;
 613                         preempt_enable();
 614
 615                         bit = (insn.i_format.rt >> 2);
 616                         bit += (bit != 0);
 617                         bit += 23;
 618                         switch (insn.i_format.rt & 3) {
 619                         case 0: /* bc1f */
 620                         case 2: /* bc1fl */
 621                                 if (~fcr31 & (1 << bit))
 622                                         *contpc = regs->cp0_epc +
 623                                                 dec_insn.pc_inc +
 624                                                 (insn.i_format.simmediate << 2);
 625                                 else
 626                                         *contpc = regs->cp0_epc +
 627                                                 dec_insn.pc_inc +
 628                                                 dec_insn.next_pc_inc;
 629                                 return 1;
 630                         case 1: /* bc1t */
 631                         case 3: /* bc1tl */
 632                                 if (fcr31 & (1 << bit))
 633                                         *contpc = regs->cp0_epc +
 634                                                 dec_insn.pc_inc +
 635                                                 (insn.i_format.simmediate << 2);
 636                                 else
 637                                         *contpc = regs->cp0_epc +
 638                                                 dec_insn.pc_inc +
 639                                                 dec_insn.next_pc_inc;
 640                                 return 1;
 641                         }
 642                 }
 643                 break;
 644         }
 645         return 0;
 646 }
 647
 648 /*
 649  * In the Linux kernel, we support selection of FPR format on the
 650  * basis of the Status.FR bit.  If an FPU is not present, the FR bit
 651  * is hardwired to zero, which would imply a 32-bit FPU even for
 652  * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
 653  * FPU emu is slow and bulky and optimizing this function offers fairly
 654  * sizeable benefits so we try to be clever and make this function return
 655  * a constant whenever possible, that is on 64-bit kernels without O32
 656  * compatibility enabled and on 32-bit without 64-bit FPU support.
 657  */
 658 static inline int cop1_64bit(struct pt_regs *xcp)
 659 {
 660         if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32))
 661                 return 1;
 662         else if (config_enabled(CONFIG_32BIT) &&
 663                  !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT))
 664                 return 0;
 665
 666         return !test_thread_flag(TIF_32BIT_FPREGS);
 667 }
 668
 669 static inline bool hybrid_fprs(void)
 670 {
 671         return test_thread_flag(TIF_HYBRID_FPREGS);
 672 }
 673
 674 #define SIFROMREG(si, x)                                                \
 675 do {                                                                    \
 676         if (cop1_64bit(xcp) && !hybrid_fprs())                          \
 677                 (si) = (int)get_fpr32(&ctx->fpr[x], 0);                 \
 678         else                                                            \
 679                 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1);    \
 680 } while (0)
 681
 682 #define SITOREG(si, x)                                                  \
 683 do {                                                                    \
 684         if (cop1_64bit(xcp) && !hybrid_fprs()) {                        \
 685                 unsigned i;                                             \
 686                 set_fpr32(&ctx->fpr[x], 0, si);                         \
 687                 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++)     \
 688                         set_fpr32(&ctx->fpr[x], i, 0);                  \
 689         } else {                                                        \
 690                 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si);            \
 691         }                                                               \
 692 } while (0)
 693
 694 #define SIFROMHREG(si, x)       ((si) = (int)get_fpr32(&ctx->fpr[x], 1))
 695
 696 #define SITOHREG(si, x)                                                 \
 697 do {                                                                    \
 698         unsigned i;                                                     \
 699         set_fpr32(&ctx->fpr[x], 1, si);                                 \
 700         for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++)             \
 701                 set_fpr32(&ctx->fpr[x], i, 0);                          \
 702 } while (0)
 703
 704 #define DIFROMREG(di, x)                                                \
 705         ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
 706
 707 #define DITOREG(di, x)                                                  \
 708 do {                                                                    \
 709         unsigned fpr, i;                                                \
 710         fpr = (x) & ~(cop1_64bit(xcp) == 0);                            \
 711         set_fpr64(&ctx->fpr[fpr], 0, di);                               \
 712         for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++)             \
 713                 set_fpr64(&ctx->fpr[fpr], i, 0);                        \
 714 } while (0)
 715
 716 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
 717 #define SPTOREG(sp, x)  SITOREG((sp).bits, x)
 718 #define DPFROMREG(dp, x)        DIFROMREG((dp).bits, x)
 719 #define DPTOREG(dp, x)  DITOREG((dp).bits, x)
 720
 721 /*
 722  * Emulate the single floating point instruction pointed at by EPC.
 723  * Two instructions if the instruction is in a branch delay slot.
 724  */
 725
 726 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 727                 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
 728 {
 729         unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
 730         unsigned int cond, cbit;
 731         mips_instruction ir;
 732         int likely, pc_inc;
 733         u32 __user *wva;
 734         u64 __user *dva;
 735         u32 value;
 736         u32 wval;
 737         u64 dval;
 738         int sig;
 739
 740         /*
 741          * These are giving gcc a gentle hint about what to expect in
 742          * dec_inst in order to do better optimization.
 743          */
 744         if (!cpu_has_mmips && dec_insn.micro_mips_mode)
 745                 unreachable();
 746
 747         /* XXX NEC Vr54xx bug workaround */
 748         if (delay_slot(xcp)) {
 749                 if (dec_insn.micro_mips_mode) {
 750                         if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
 751                                 clear_delay_slot(xcp);
 752                 } else {
 753                         if (!isBranchInstr(xcp, dec_insn, &contpc))
 754                                 clear_delay_slot(xcp);
 755                 }
 756         }
 757
 758         if (delay_slot(xcp)) {
 759                 /*
 760                  * The instruction to be emulated is in a branch delay slot
 761                  * which means that we have to  emulate the branch instruction
 762                  * BEFORE we do the cop1 instruction.
 763                  *
 764                  * This branch could be a COP1 branch, but in that case we
 765                  * would have had a trap for that instruction, and would not
 766                  * come through this route.
 767                  *
 768                  * Linux MIPS branch emulator operates on context, updating the
 769                  * cp0_epc.
 770                  */
 771                 ir = dec_insn.next_insn;  /* process delay slot instr */
 772                 pc_inc = dec_insn.next_pc_inc;
 773         } else {
 774                 ir = dec_insn.insn;       /* process current instr */
 775                 pc_inc = dec_insn.pc_inc;
 776         }
 777
 778         /*
 779          * Since microMIPS FPU instructios are a subset of MIPS32 FPU
 780          * instructions, we want to convert microMIPS FPU instructions
 781          * into MIPS32 instructions so that we could reuse all of the
 782          * FPU emulation code.
 783          *
 784          * NOTE: We cannot do this for branch instructions since they
 785          *       are not a subset. Example: Cannot emulate a 16-bit
 786          *       aligned target address with a MIPS32 instruction.
 787          */
 788         if (dec_insn.micro_mips_mode) {
 789                 /*
 790                  * If next instruction is a 16-bit instruction, then it
 791                  * it cannot be a FPU instruction. This could happen
 792                  * since we can be called for non-FPU instructions.
 793                  */
 794                 if ((pc_inc == 2) ||
 795                         (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
 796                          == SIGILL))
 797                         return SIGILL;
 798         }
 799
 800 emul:
 801         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
 802         MIPS_FPU_EMU_INC_STATS(emulated);
 803         switch (MIPSInst_OPCODE(ir)) {
 804         case ldc1_op:
 805                 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
 806                                      MIPSInst_SIMM(ir));
 807                 MIPS_FPU_EMU_INC_STATS(loads);
 808
 809                 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) {
 810                         MIPS_FPU_EMU_INC_STATS(errors);
 811                         *fault_addr = dva;
 812                         return SIGBUS;
 813                 }
 814                 if (__get_user(dval, dva)) {
 815                         MIPS_FPU_EMU_INC_STATS(errors);
 816                         *fault_addr = dva;
 817                         return SIGSEGV;
 818                 }
 819                 DITOREG(dval, MIPSInst_RT(ir));
 820                 break;
 821
 822         case sdc1_op:
 823                 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
 824                                       MIPSInst_SIMM(ir));
 825                 MIPS_FPU_EMU_INC_STATS(stores);
 826                 DIFROMREG(dval, MIPSInst_RT(ir));
 827                 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) {
 828                         MIPS_FPU_EMU_INC_STATS(errors);
 829                         *fault_addr = dva;
 830                         return SIGBUS;
 831                 }
 832                 if (__put_user(dval, dva)) {
 833                         MIPS_FPU_EMU_INC_STATS(errors);
 834                         *fault_addr = dva;
 835                         return SIGSEGV;
 836                 }
 837                 break;
 838
 839         case lwc1_op:
 840                 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
 841                                       MIPSInst_SIMM(ir));
 842                 MIPS_FPU_EMU_INC_STATS(loads);
 843                 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) {
 844                         MIPS_FPU_EMU_INC_STATS(errors);
 845                         *fault_addr = wva;
 846                         return SIGBUS;
 847                 }
 848                 if (__get_user(wval, wva)) {
 849                         MIPS_FPU_EMU_INC_STATS(errors);
 850                         *fault_addr = wva;
 851                         return SIGSEGV;
 852                 }
 853                 SITOREG(wval, MIPSInst_RT(ir));
 854                 break;
 855
 856         case swc1_op:
 857                 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
 858                                       MIPSInst_SIMM(ir));
 859                 MIPS_FPU_EMU_INC_STATS(stores);
 860                 SIFROMREG(wval, MIPSInst_RT(ir));
 861                 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) {
 862                         MIPS_FPU_EMU_INC_STATS(errors);
 863                         *fault_addr = wva;
 864                         return SIGBUS;
 865                 }
 866                 if (__put_user(wval, wva)) {
 867                         MIPS_FPU_EMU_INC_STATS(errors);
 868                         *fault_addr = wva;
 869                         return SIGSEGV;
 870                 }
 871                 break;
 872
 873         case cop1_op:
 874                 switch (MIPSInst_RS(ir)) {
 875                 case dmfc_op:
 876                         if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
 877                                 return SIGILL;
 878
 879                         /* copregister fs -> gpr[rt] */
 880                         if (MIPSInst_RT(ir) != 0) {
 881                                 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
 882                                         MIPSInst_RD(ir));
 883                         }
 884                         break;
 885
 886                 case dmtc_op:
 887                         if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
 888                                 return SIGILL;
 889
 890                         /* copregister fs <- rt */
 891                         DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
 892                         break;
 893
 894                 case mfhc_op:
 895                         if (!cpu_has_mips_r2)
 896                                 goto sigill;
 897
 898                         /* copregister rd -> gpr[rt] */
 899                         if (MIPSInst_RT(ir) != 0) {
 900                                 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
 901                                         MIPSInst_RD(ir));
 902                         }
 903                         break;
 904
 905                 case mthc_op:
 906                         if (!cpu_has_mips_r2)
 907                                 goto sigill;
 908
 909                         /* copregister rd <- gpr[rt] */
 910                         SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
 911                         break;
 912
 913                 case mfc_op:
 914                         /* copregister rd -> gpr[rt] */
 915                         if (MIPSInst_RT(ir) != 0) {
 916                                 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
 917                                         MIPSInst_RD(ir));
 918                         }
 919                         break;
 920
 921                 case mtc_op:
 922                         /* copregister rd <- rt */
 923                         SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
 924                         break;
 925
 926                 case cfc_op:
 927                         /* cop control register rd -> gpr[rt] */
 928                         if (MIPSInst_RD(ir) == FPCREG_CSR) {
 929                                 value = ctx->fcr31;
 930                                 value = (value & ~FPU_CSR_RM) | modeindex(value);
 931                                 pr_debug("%p gpr[%d]<-csr=%08x\n",
 932                                          (void *) (xcp->cp0_epc),
 933                                          MIPSInst_RT(ir), value);
 934                         }
 935                         else if (MIPSInst_RD(ir) == FPCREG_RID)
 936                                 value = 0;
 937                         else
 938                                 value = 0;
 939                         if (MIPSInst_RT(ir))
 940                                 xcp->regs[MIPSInst_RT(ir)] = value;
 941                         break;
 942
 943                 case ctc_op:
 944                         /* copregister rd <- rt */
 945                         if (MIPSInst_RT(ir) == 0)
 946                                 value = 0;
 947                         else
 948                                 value = xcp->regs[MIPSInst_RT(ir)];
 949
 950                         /* we only have one writable control reg
 951                          */
 952                         if (MIPSInst_RD(ir) == FPCREG_CSR) {
 953                                 pr_debug("%p gpr[%d]->csr=%08x\n",
 954                                          (void *) (xcp->cp0_epc),
 955                                          MIPSInst_RT(ir), value);
 956
 957                                 /*
 958                                  * Don't write reserved bits,
 959                                  * and convert to ieee library modes
 960                                  */
 961                                 ctx->fcr31 = (value & ~(FPU_CSR_RSVD | FPU_CSR_RM)) |
 962                                              modeindex(value);
 963                         }
 964                         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
 965                                 return SIGFPE;
 966                         }
 967                         break;
 968
 969                 case bc_op:
 970                         if (delay_slot(xcp))
 971                                 return SIGILL;
 972
 973                         if (cpu_has_mips_4_5_r)
 974                                 cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
 975                         else
 976                                 cbit = FPU_CSR_COND;
 977                         cond = ctx->fcr31 & cbit;
 978
 979                         likely = 0;
 980                         switch (MIPSInst_RT(ir) & 3) {
 981                         case bcfl_op:
 982                                 likely = 1;
 983                         case bcf_op:
 984                                 cond = !cond;
 985                                 break;
 986                         case bctl_op:
 987                                 likely = 1;
 988                         case bct_op:
 989                                 break;
 990                         default:
 991                                 /* thats an illegal instruction */
 992                                 return SIGILL;
 993                         }
 994
 995                         set_delay_slot(xcp);
 996                         if (cond) {
 997                                 /*
 998                                  * Branch taken: emulate dslot instruction
 999                                  */
1000                                 xcp->cp0_epc += dec_insn.pc_inc;
1001
1002                                 contpc = MIPSInst_SIMM(ir);
1003                                 ir = dec_insn.next_insn;
1004                                 if (dec_insn.micro_mips_mode) {
1005                                         contpc = (xcp->cp0_epc + (contpc << 1));
1006
1007                                         /* If 16-bit instruction, not FPU. */
1008                                         if ((dec_insn.next_pc_inc == 2) ||
1009                                                 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
1010
1011                                                 /*
1012                                                  * Since this instruction will
1013                                                  * be put on the stack with
1014                                                  * 32-bit words, get around
1015                                                  * this problem by putting a
1016                                                  * NOP16 as the second one.
1017                                                  */
1018                                                 if (dec_insn.next_pc_inc == 2)
1019                                                         ir = (ir & (~0xffff)) | MM_NOP16;
1020
1021                                                 /*
1022                                                  * Single step the non-CP1
1023                                                  * instruction in the dslot.
1024                                                  */
1025                                                 return mips_dsemul(xcp, ir, contpc);
1026                                         }
1027                                 } else
1028                                         contpc = (xcp->cp0_epc + (contpc << 2));
1029
1030                                 switch (MIPSInst_OPCODE(ir)) {
1031                                 case lwc1_op:
1032                                         goto emul;
1033
1034                                 case swc1_op:
1035                                         goto emul;
1036
1037                                 case ldc1_op:
1038                                 case sdc1_op:
1039                                         if (cpu_has_mips_2_3_4_5 ||
1040                                             cpu_has_mips64)
1041                                                 goto emul;
1042
1043                                         return SIGILL;
1044                                         goto emul;
1045
1046                                 case cop1_op:
1047                                         goto emul;
1048
1049                                 case cop1x_op:
1050                                         if (cpu_has_mips_4_5 || cpu_has_mips64 || cpu_has_mips32r2)
1051                                                 /* its one of ours */
1052                                                 goto emul;
1053
1054                                         return SIGILL;
1055
1056                                 case spec_op:
1057                                         if (!cpu_has_mips_4_5_r)
1058                                                 return SIGILL;
1059
1060                                         if (MIPSInst_FUNC(ir) == movc_op)
1061                                                 goto emul;
1062                                         break;
1063                                 }
1064
1065                                 /*
1066                                  * Single step the non-cp1
1067                                  * instruction in the dslot
1068                                  */
1069                                 return mips_dsemul(xcp, ir, contpc);
1070                         } else if (likely) {    /* branch not taken */
1071                                         /*
1072                                          * branch likely nullifies
1073                                          * dslot if not taken
1074                                          */
1075                                         xcp->cp0_epc += dec_insn.pc_inc;
1076                                         contpc += dec_insn.pc_inc;
1077                                         /*
1078                                          * else continue & execute
1079                                          * dslot as normal insn
1080                                          */
1081                                 }
1082                         break;
1083
1084                 default:
1085                         if (!(MIPSInst_RS(ir) & 0x10))
1086                                 return SIGILL;
1087
1088                         /* a real fpu computation instruction */
1089                         if ((sig = fpu_emu(xcp, ctx, ir)))
1090                                 return sig;
1091                 }
1092                 break;
1093
1094         case cop1x_op:
1095                 if (!cpu_has_mips_4_5 && !cpu_has_mips64 && !cpu_has_mips32r2)
1096                         return SIGILL;
1097
1098                 sig = fpux_emu(xcp, ctx, ir, fault_addr);
1099                 if (sig)
1100                         return sig;
1101                 break;
1102
1103         case spec_op:
1104                 if (!cpu_has_mips_4_5_r)
1105                         return SIGILL;
1106
1107                 if (MIPSInst_FUNC(ir) != movc_op)
1108                         return SIGILL;
1109                 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1110                 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1111                         xcp->regs[MIPSInst_RD(ir)] =
1112                                 xcp->regs[MIPSInst_RS(ir)];
1113                 break;
1114         default:
1115 sigill:
1116                 return SIGILL;
1117         }
1118
1119         /* we did it !! */
1120         xcp->cp0_epc = contpc;
1121         clear_delay_slot(xcp);
1122
1123         return 0;
1124 }
1125
1126 /*
1127  * Conversion table from MIPS compare ops 48-63
1128  * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1129  */
1130 static const unsigned char cmptab[8] = {
1131         0,                      /* cmp_0 (sig) cmp_sf */
1132         IEEE754_CUN,            /* cmp_un (sig) cmp_ngle */
1133         IEEE754_CEQ,            /* cmp_eq (sig) cmp_seq */
1134         IEEE754_CEQ | IEEE754_CUN,      /* cmp_ueq (sig) cmp_ngl  */
1135         IEEE754_CLT,            /* cmp_olt (sig) cmp_lt */
1136         IEEE754_CLT | IEEE754_CUN,      /* cmp_ult (sig) cmp_nge */
1137         IEEE754_CLT | IEEE754_CEQ,      /* cmp_ole (sig) cmp_le */
1138         IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN,        /* cmp_ule (sig) cmp_ngt */
1139 };
1140
1141
1142 /*
1143  * Additional MIPS4 instructions
1144  */
1145
1146 #define DEF3OP(name, p, f1, f2, f3)                                     \
1147 static union ieee754##p fpemu_##p##_##name(union ieee754##p r,          \
1148         union ieee754##p s, union ieee754##p t)                         \
1149 {                                                                       \
1150         struct _ieee754_csr ieee754_csr_save;                           \
1151         s = f1(s, t);                                                   \
1152         ieee754_csr_save = ieee754_csr;                                 \
1153         s = f2(s, r);                                                   \
1154         ieee754_csr_save.cx |= ieee754_csr.cx;                          \
1155         ieee754_csr_save.sx |= ieee754_csr.sx;                          \
1156         s = f3(s);                                                      \
1157         ieee754_csr.cx |= ieee754_csr_save.cx;                          \
1158         ieee754_csr.sx |= ieee754_csr_save.sx;                          \
1159         return s;                                                       \
1160 }
1161
1162 static union ieee754dp fpemu_dp_recip(union ieee754dp d)
1163 {
1164         return ieee754dp_div(ieee754dp_one(0), d);
1165 }
1166
1167 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
1168 {
1169         return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1170 }
1171
1172 static union ieee754sp fpemu_sp_recip(union ieee754sp s)
1173 {
1174         return ieee754sp_div(ieee754sp_one(0), s);
1175 }
1176
1177 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
1178 {
1179         return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1180 }
1181
1182 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1183 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1184 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1185 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
1186 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1187 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1188 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1189 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1190
1191 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1192         mips_instruction ir, void *__user *fault_addr)
1193 {
1194         unsigned rcsr = 0;      /* resulting csr */
1195
1196         MIPS_FPU_EMU_INC_STATS(cp1xops);
1197
1198         switch (MIPSInst_FMA_FFMT(ir)) {
1199         case s_fmt:{            /* 0 */
1200
1201                 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
1202                 union ieee754sp fd, fr, fs, ft;
1203                 u32 __user *va;
1204                 u32 val;
1205
1206                 switch (MIPSInst_FUNC(ir)) {
1207                 case lwxc1_op:
1208                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1209                                 xcp->regs[MIPSInst_FT(ir)]);
1210
1211                         MIPS_FPU_EMU_INC_STATS(loads);
1212                         if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1213                                 MIPS_FPU_EMU_INC_STATS(errors);
1214                                 *fault_addr = va;
1215                                 return SIGBUS;
1216                         }
1217                         if (__get_user(val, va)) {
1218                                 MIPS_FPU_EMU_INC_STATS(errors);
1219                                 *fault_addr = va;
1220                                 return SIGSEGV;
1221                         }
1222                         SITOREG(val, MIPSInst_FD(ir));
1223                         break;
1224
1225                 case swxc1_op:
1226                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1227                                 xcp->regs[MIPSInst_FT(ir)]);
1228
1229                         MIPS_FPU_EMU_INC_STATS(stores);
1230
1231                         SIFROMREG(val, MIPSInst_FS(ir));
1232                         if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1233                                 MIPS_FPU_EMU_INC_STATS(errors);
1234                                 *fault_addr = va;
1235                                 return SIGBUS;
1236                         }
1237                         if (put_user(val, va)) {
1238                                 MIPS_FPU_EMU_INC_STATS(errors);
1239                                 *fault_addr = va;
1240                                 return SIGSEGV;
1241                         }
1242                         break;
1243
1244                 case madd_s_op:
1245                         handler = fpemu_sp_madd;
1246                         goto scoptop;
1247                 case msub_s_op:
1248                         handler = fpemu_sp_msub;
1249                         goto scoptop;
1250                 case nmadd_s_op:
1251                         handler = fpemu_sp_nmadd;
1252                         goto scoptop;
1253                 case nmsub_s_op:
1254                         handler = fpemu_sp_nmsub;
1255                         goto scoptop;
1256
1257                       scoptop:
1258                         SPFROMREG(fr, MIPSInst_FR(ir));
1259                         SPFROMREG(fs, MIPSInst_FS(ir));
1260                         SPFROMREG(ft, MIPSInst_FT(ir));
1261                         fd = (*handler) (fr, fs, ft);
1262                         SPTOREG(fd, MIPSInst_FD(ir));
1263
1264                       copcsr:
1265                         if (ieee754_cxtest(IEEE754_INEXACT)) {
1266                                 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1267                                 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1268                         }
1269                         if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1270                                 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1271                                 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1272                         }
1273                         if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1274                                 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1275                                 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1276                         }
1277                         if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1278                                 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1279                                 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1280                         }
1281
1282                         ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1283                         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1284                                 /*printk ("SIGFPE: FPU csr = %08x\n",
1285                                    ctx->fcr31); */
1286                                 return SIGFPE;
1287                         }
1288
1289                         break;
1290
1291                 default:
1292                         return SIGILL;
1293                 }
1294                 break;
1295         }
1296
1297         case d_fmt:{            /* 1 */
1298                 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
1299                 union ieee754dp fd, fr, fs, ft;
1300                 u64 __user *va;
1301                 u64 val;
1302
1303                 switch (MIPSInst_FUNC(ir)) {
1304                 case ldxc1_op:
1305                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1306                                 xcp->regs[MIPSInst_FT(ir)]);
1307
1308                         MIPS_FPU_EMU_INC_STATS(loads);
1309                         if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
1310                                 MIPS_FPU_EMU_INC_STATS(errors);
1311                                 *fault_addr = va;
1312                                 return SIGBUS;
1313                         }
1314                         if (__get_user(val, va)) {
1315                                 MIPS_FPU_EMU_INC_STATS(errors);
1316                                 *fault_addr = va;
1317                                 return SIGSEGV;
1318                         }
1319                         DITOREG(val, MIPSInst_FD(ir));
1320                         break;
1321
1322                 case sdxc1_op:
1323                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1324                                 xcp->regs[MIPSInst_FT(ir)]);
1325
1326                         MIPS_FPU_EMU_INC_STATS(stores);
1327                         DIFROMREG(val, MIPSInst_FS(ir));
1328                         if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1329                                 MIPS_FPU_EMU_INC_STATS(errors);
1330                                 *fault_addr = va;
1331                                 return SIGBUS;
1332                         }
1333                         if (__put_user(val, va)) {
1334                                 MIPS_FPU_EMU_INC_STATS(errors);
1335                                 *fault_addr = va;
1336                                 return SIGSEGV;
1337                         }
1338                         break;
1339
1340                 case madd_d_op:
1341                         handler = fpemu_dp_madd;
1342                         goto dcoptop;
1343                 case msub_d_op:
1344                         handler = fpemu_dp_msub;
1345                         goto dcoptop;
1346                 case nmadd_d_op:
1347                         handler = fpemu_dp_nmadd;
1348                         goto dcoptop;
1349                 case nmsub_d_op:
1350                         handler = fpemu_dp_nmsub;
1351                         goto dcoptop;
1352
1353                       dcoptop:
1354                         DPFROMREG(fr, MIPSInst_FR(ir));
1355                         DPFROMREG(fs, MIPSInst_FS(ir));
1356                         DPFROMREG(ft, MIPSInst_FT(ir));
1357                         fd = (*handler) (fr, fs, ft);
1358                         DPTOREG(fd, MIPSInst_FD(ir));
1359                         goto copcsr;
1360
1361                 default:
1362                         return SIGILL;
1363                 }
1364                 break;
1365         }
1366
1367         case 0x3:
1368                 if (MIPSInst_FUNC(ir) != pfetch_op)
1369                         return SIGILL;
1370
1371                 /* ignore prefx operation */
1372                 break;
1373
1374         default:
1375                 return SIGILL;
1376         }
1377
1378         return 0;
1379 }
1380
1381
1382
1383 /*
1384  * Emulate a single COP1 arithmetic instruction.
1385  */
1386 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1387         mips_instruction ir)
1388 {
1389         int rfmt;               /* resulting format */
1390         unsigned rcsr = 0;      /* resulting csr */
1391         unsigned int oldrm;
1392         unsigned int cbit;
1393         unsigned cond;
1394         union {
1395                 union ieee754dp d;
1396                 union ieee754sp s;
1397                 int w;
1398                 s64 l;
1399         } rv;                   /* resulting value */
1400         u64 bits;
1401
1402         MIPS_FPU_EMU_INC_STATS(cp1ops);
1403         switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1404         case s_fmt: {           /* 0 */
1405                 union {
1406                         union ieee754sp(*b) (union ieee754sp, union ieee754sp);
1407                         union ieee754sp(*u) (union ieee754sp);
1408                 } handler;
1409                 union ieee754sp fs, ft;
1410
1411                 switch (MIPSInst_FUNC(ir)) {
1412                         /* binary ops */
1413                 case fadd_op:
1414                         handler.b = ieee754sp_add;
1415                         goto scopbop;
1416                 case fsub_op:
1417                         handler.b = ieee754sp_sub;
1418                         goto scopbop;
1419                 case fmul_op:
1420                         handler.b = ieee754sp_mul;
1421                         goto scopbop;
1422                 case fdiv_op:
1423                         handler.b = ieee754sp_div;
1424                         goto scopbop;
1425
1426                         /* unary  ops */
1427                 case fsqrt_op:
1428                         if (!cpu_has_mips_4_5_r)
1429                                 return SIGILL;
1430
1431                         handler.u = ieee754sp_sqrt;
1432                         goto scopuop;
1433
1434                 /*
1435                  * Note that on some MIPS IV implementations such as the
1436                  * R5000 and R8000 the FSQRT and FRECIP instructions do not
1437                  * achieve full IEEE-754 accuracy - however this emulator does.
1438                  */
1439                 case frsqrt_op:
1440                         if (!cpu_has_mips_4_5_r2)
1441                                 return SIGILL;
1442
1443                         handler.u = fpemu_sp_rsqrt;
1444                         goto scopuop;
1445
1446                 case frecip_op:
1447                         if (!cpu_has_mips_4_5_r2)
1448                                 return SIGILL;
1449
1450                         handler.u = fpemu_sp_recip;
1451                         goto scopuop;
1452
1453                 case fmovc_op:
1454                         if (!cpu_has_mips_4_5_r)
1455                                 return SIGILL;
1456
1457                         cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1458                         if (((ctx->fcr31 & cond) != 0) !=
1459                                 ((MIPSInst_FT(ir) & 1) != 0))
1460                                 return 0;
1461                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1462                         break;
1463
1464                 case fmovz_op:
1465                         if (!cpu_has_mips_4_5_r)
1466                                 return SIGILL;
1467
1468                         if (xcp->regs[MIPSInst_FT(ir)] != 0)
1469                                 return 0;
1470                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1471                         break;
1472
1473                 case fmovn_op:
1474                         if (!cpu_has_mips_4_5_r)
1475                                 return SIGILL;
1476
1477                         if (xcp->regs[MIPSInst_FT(ir)] == 0)
1478                                 return 0;
1479                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1480                         break;
1481
1482                 case fabs_op:
1483                         handler.u = ieee754sp_abs;
1484                         goto scopuop;
1485
1486                 case fneg_op:
1487                         handler.u = ieee754sp_neg;
1488                         goto scopuop;
1489
1490                 case fmov_op:
1491                         /* an easy one */
1492                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1493                         goto copcsr;
1494
1495                         /* binary op on handler */
1496 scopbop:
1497                         SPFROMREG(fs, MIPSInst_FS(ir));
1498                         SPFROMREG(ft, MIPSInst_FT(ir));
1499
1500                         rv.s = (*handler.b) (fs, ft);
1501                         goto copcsr;
1502 scopuop:
1503                         SPFROMREG(fs, MIPSInst_FS(ir));
1504                         rv.s = (*handler.u) (fs);
1505                         goto copcsr;
1506 copcsr:
1507                         if (ieee754_cxtest(IEEE754_INEXACT)) {
1508                                 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1509                                 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1510                         }
1511                         if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1512                                 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1513                                 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1514                         }
1515                         if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1516                                 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1517                                 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1518                         }
1519                         if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) {
1520                                 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv);
1521                                 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1522                         }
1523                         if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1524                                 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1525                                 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1526                         }
1527                         break;
1528
1529                         /* unary conv ops */
1530                 case fcvts_op:
1531                         return SIGILL;  /* not defined */
1532
1533                 case fcvtd_op:
1534                         SPFROMREG(fs, MIPSInst_FS(ir));
1535                         rv.d = ieee754dp_fsp(fs);
1536                         rfmt = d_fmt;
1537                         goto copcsr;
1538
1539                 case fcvtw_op:
1540                         SPFROMREG(fs, MIPSInst_FS(ir));
1541                         rv.w = ieee754sp_tint(fs);
1542                         rfmt = w_fmt;
1543                         goto copcsr;
1544
1545                 case fround_op:
1546                 case ftrunc_op:
1547                 case fceil_op:
1548                 case ffloor_op:
1549                         if (!cpu_has_mips_2_3_4_5 && !cpu_has_mips64)
1550                                 return SIGILL;
1551
1552                         oldrm = ieee754_csr.rm;
1553                         SPFROMREG(fs, MIPSInst_FS(ir));
1554                         ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1555                         rv.w = ieee754sp_tint(fs);
1556                         ieee754_csr.rm = oldrm;
1557                         rfmt = w_fmt;
1558                         goto copcsr;
1559
1560                 case fcvtl_op:
1561                         if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1562                                 return SIGILL;
1563
1564                         SPFROMREG(fs, MIPSInst_FS(ir));
1565                         rv.l = ieee754sp_tlong(fs);
1566                         rfmt = l_fmt;
1567                         goto copcsr;
1568
1569                 case froundl_op:
1570                 case ftruncl_op:
1571                 case fceill_op:
1572                 case ffloorl_op:
1573                         if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1574                                 return SIGILL;
1575
1576                         oldrm = ieee754_csr.rm;
1577                         SPFROMREG(fs, MIPSInst_FS(ir));
1578                         ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1579                         rv.l = ieee754sp_tlong(fs);
1580                         ieee754_csr.rm = oldrm;
1581                         rfmt = l_fmt;
1582                         goto copcsr;
1583
1584                 default:
1585                         if (MIPSInst_FUNC(ir) >= fcmp_op) {
1586                                 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1587                                 union ieee754sp fs, ft;
1588
1589                                 SPFROMREG(fs, MIPSInst_FS(ir));
1590                                 SPFROMREG(ft, MIPSInst_FT(ir));
1591                                 rv.w = ieee754sp_cmp(fs, ft,
1592                                         cmptab[cmpop & 0x7], cmpop & 0x8);
1593                                 rfmt = -1;
1594                                 if ((cmpop & 0x8) && ieee754_cxtest
1595                                         (IEEE754_INVALID_OPERATION))
1596                                         rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1597                                 else
1598                                         goto copcsr;
1599
1600                         } else
1601                                 return SIGILL;
1602                         break;
1603                 }
1604                 break;
1605         }
1606
1607         case d_fmt: {
1608                 union ieee754dp fs, ft;
1609                 union {
1610                         union ieee754dp(*b) (union ieee754dp, union ieee754dp);
1611                         union ieee754dp(*u) (union ieee754dp);
1612                 } handler;
1613
1614                 switch (MIPSInst_FUNC(ir)) {
1615                         /* binary ops */
1616                 case fadd_op:
1617                         handler.b = ieee754dp_add;
1618                         goto dcopbop;
1619                 case fsub_op:
1620                         handler.b = ieee754dp_sub;
1621                         goto dcopbop;
1622                 case fmul_op:
1623                         handler.b = ieee754dp_mul;
1624                         goto dcopbop;
1625                 case fdiv_op:
1626                         handler.b = ieee754dp_div;
1627                         goto dcopbop;
1628
1629                         /* unary  ops */
1630                 case fsqrt_op:
1631                         if (!cpu_has_mips_2_3_4_5_r)
1632                                 return SIGILL;
1633
1634                         handler.u = ieee754dp_sqrt;
1635                         goto dcopuop;
1636                 /*
1637                  * Note that on some MIPS IV implementations such as the
1638                  * R5000 and R8000 the FSQRT and FRECIP instructions do not
1639                  * achieve full IEEE-754 accuracy - however this emulator does.
1640                  */
1641                 case frsqrt_op:
1642                         if (!cpu_has_mips_4_5_r2)
1643                                 return SIGILL;
1644
1645                         handler.u = fpemu_dp_rsqrt;
1646                         goto dcopuop;
1647                 case frecip_op:
1648                         if (!cpu_has_mips_4_5_r2)
1649                                 return SIGILL;
1650
1651                         handler.u = fpemu_dp_recip;
1652                         goto dcopuop;
1653                 case fmovc_op:
1654                         if (!cpu_has_mips_4_5_r)
1655                                 return SIGILL;
1656
1657                         cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1658                         if (((ctx->fcr31 & cond) != 0) !=
1659                                 ((MIPSInst_FT(ir) & 1) != 0))
1660                                 return 0;
1661                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1662                         break;
1663                 case fmovz_op:
1664                         if (!cpu_has_mips_4_5_r)
1665                                 return SIGILL;
1666
1667                         if (xcp->regs[MIPSInst_FT(ir)] != 0)
1668                                 return 0;
1669                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1670                         break;
1671                 case fmovn_op:
1672                         if (!cpu_has_mips_4_5_r)
1673                                 return SIGILL;
1674
1675                         if (xcp->regs[MIPSInst_FT(ir)] == 0)
1676                                 return 0;
1677                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1678                         break;
1679                 case fabs_op:
1680                         handler.u = ieee754dp_abs;
1681                         goto dcopuop;
1682
1683                 case fneg_op:
1684                         handler.u = ieee754dp_neg;
1685                         goto dcopuop;
1686
1687                 case fmov_op:
1688                         /* an easy one */
1689                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1690                         goto copcsr;
1691
1692                         /* binary op on handler */
1693 dcopbop:
1694                         DPFROMREG(fs, MIPSInst_FS(ir));
1695                         DPFROMREG(ft, MIPSInst_FT(ir));
1696
1697                         rv.d = (*handler.b) (fs, ft);
1698                         goto copcsr;
1699 dcopuop:
1700                         DPFROMREG(fs, MIPSInst_FS(ir));
1701                         rv.d = (*handler.u) (fs);
1702                         goto copcsr;
1703
1704                 /*
1705                  * unary conv ops
1706                  */
1707                 case fcvts_op:
1708                         DPFROMREG(fs, MIPSInst_FS(ir));
1709                         rv.s = ieee754sp_fdp(fs);
1710                         rfmt = s_fmt;
1711                         goto copcsr;
1712
1713                 case fcvtd_op:
1714                         return SIGILL;  /* not defined */
1715
1716                 case fcvtw_op:
1717                         DPFROMREG(fs, MIPSInst_FS(ir));
1718                         rv.w = ieee754dp_tint(fs);      /* wrong */
1719                         rfmt = w_fmt;
1720                         goto copcsr;
1721
1722                 case fround_op:
1723                 case ftrunc_op:
1724                 case fceil_op:
1725                 case ffloor_op:
1726                         if (!cpu_has_mips_2_3_4_5_r)
1727                                 return SIGILL;
1728
1729                         oldrm = ieee754_csr.rm;
1730                         DPFROMREG(fs, MIPSInst_FS(ir));
1731                         ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1732                         rv.w = ieee754dp_tint(fs);
1733                         ieee754_csr.rm = oldrm;
1734                         rfmt = w_fmt;
1735                         goto copcsr;
1736
1737                 case fcvtl_op:
1738                         if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1739                                 return SIGILL;
1740
1741                         DPFROMREG(fs, MIPSInst_FS(ir));
1742                         rv.l = ieee754dp_tlong(fs);
1743                         rfmt = l_fmt;
1744                         goto copcsr;
1745
1746                 case froundl_op:
1747                 case ftruncl_op:
1748                 case fceill_op:
1749                 case ffloorl_op:
1750                         if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1751                                 return SIGILL;
1752
1753                         oldrm = ieee754_csr.rm;
1754                         DPFROMREG(fs, MIPSInst_FS(ir));
1755                         ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1756                         rv.l = ieee754dp_tlong(fs);
1757                         ieee754_csr.rm = oldrm;
1758                         rfmt = l_fmt;
1759                         goto copcsr;
1760
1761                 default:
1762                         if (MIPSInst_FUNC(ir) >= fcmp_op) {
1763                                 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1764                                 union ieee754dp fs, ft;
1765
1766                                 DPFROMREG(fs, MIPSInst_FS(ir));
1767                                 DPFROMREG(ft, MIPSInst_FT(ir));
1768                                 rv.w = ieee754dp_cmp(fs, ft,
1769                                         cmptab[cmpop & 0x7], cmpop & 0x8);
1770                                 rfmt = -1;
1771                                 if ((cmpop & 0x8)
1772                                         &&
1773                                         ieee754_cxtest
1774                                         (IEEE754_INVALID_OPERATION))
1775                                         rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1776                                 else
1777                                         goto copcsr;
1778
1779                         }
1780                         else {
1781                                 return SIGILL;
1782                         }
1783                         break;
1784                 }
1785                 break;
1786
1787         case w_fmt:
1788                 switch (MIPSInst_FUNC(ir)) {
1789                 case fcvts_op:
1790                         /* convert word to single precision real */
1791                         SPFROMREG(fs, MIPSInst_FS(ir));
1792                         rv.s = ieee754sp_fint(fs.bits);
1793                         rfmt = s_fmt;
1794                         goto copcsr;
1795                 case fcvtd_op:
1796                         /* convert word to double precision real */
1797                         SPFROMREG(fs, MIPSInst_FS(ir));
1798                         rv.d = ieee754dp_fint(fs.bits);
1799                         rfmt = d_fmt;
1800                         goto copcsr;
1801                 default:
1802                         return SIGILL;
1803                 }
1804                 break;
1805         }
1806
1807         case l_fmt:
1808
1809                 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1810                         return SIGILL;
1811
1812                 DIFROMREG(bits, MIPSInst_FS(ir));
1813
1814                 switch (MIPSInst_FUNC(ir)) {
1815                 case fcvts_op:
1816                         /* convert long to single precision real */
1817                         rv.s = ieee754sp_flong(bits);
1818                         rfmt = s_fmt;
1819                         goto copcsr;
1820                 case fcvtd_op:
1821                         /* convert long to double precision real */
1822                         rv.d = ieee754dp_flong(bits);
1823                         rfmt = d_fmt;
1824                         goto copcsr;
1825                 default:
1826                         return SIGILL;
1827                 }
1828                 break;
1829
1830         default:
1831                 return SIGILL;
1832         }
1833
1834         /*
1835          * Update the fpu CSR register for this operation.
1836          * If an exception is required, generate a tidy SIGFPE exception,
1837          * without updating the result register.
1838          * Note: cause exception bits do not accumulate, they are rewritten
1839          * for each op; only the flag/sticky bits accumulate.
1840          */
1841         ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1842         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1843                 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
1844                 return SIGFPE;
1845         }
1846
1847         /*
1848          * Now we can safely write the result back to the register file.
1849          */
1850         switch (rfmt) {
1851         case -1:
1852
1853                 if (cpu_has_mips_4_5_r)
1854                         cbit = fpucondbit[MIPSInst_FD(ir) >> 2];
1855                 else
1856                         cbit = FPU_CSR_COND;
1857                 if (rv.w)
1858                         ctx->fcr31 |= cbit;
1859                 else
1860                         ctx->fcr31 &= ~cbit;
1861                 break;
1862
1863         case d_fmt:
1864                 DPTOREG(rv.d, MIPSInst_FD(ir));
1865                 break;
1866         case s_fmt:
1867                 SPTOREG(rv.s, MIPSInst_FD(ir));
1868                 break;
1869         case w_fmt:
1870                 SITOREG(rv.w, MIPSInst_FD(ir));
1871                 break;
1872         case l_fmt:
1873                 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1874                         return SIGILL;
1875
1876                 DITOREG(rv.l, MIPSInst_FD(ir));
1877                 break;
1878         default:
1879                 return SIGILL;
1880         }
1881
1882         return 0;
1883 }
1884
1885 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1886         int has_fpu, void *__user *fault_addr)
1887 {
1888         unsigned long oldepc, prevepc;
1889         struct mm_decoded_insn dec_insn;
1890         u16 instr[4];
1891         u16 *instr_ptr;
1892         int sig = 0;
1893
1894         oldepc = xcp->cp0_epc;
1895         do {
1896                 prevepc = xcp->cp0_epc;
1897
1898                 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
1899                         /*
1900                          * Get next 2 microMIPS instructions and convert them
1901                          * into 32-bit instructions.
1902                          */
1903                         if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
1904                             (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
1905                             (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
1906                             (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
1907                                 MIPS_FPU_EMU_INC_STATS(errors);
1908                                 return SIGBUS;
1909                         }
1910                         instr_ptr = instr;
1911
1912                         /* Get first instruction. */
1913                         if (mm_insn_16bit(*instr_ptr)) {
1914                                 /* Duplicate the half-word. */
1915                                 dec_insn.insn = (*instr_ptr << 16) |
1916                                         (*instr_ptr);
1917                                 /* 16-bit instruction. */
1918                                 dec_insn.pc_inc = 2;
1919                                 instr_ptr += 1;
1920                         } else {
1921                                 dec_insn.insn = (*instr_ptr << 16) |
1922                                         *(instr_ptr+1);
1923                                 /* 32-bit instruction. */
1924                                 dec_insn.pc_inc = 4;
1925                                 instr_ptr += 2;
1926                         }
1927                         /* Get second instruction. */
1928                         if (mm_insn_16bit(*instr_ptr)) {
1929                                 /* Duplicate the half-word. */
1930                                 dec_insn.next_insn = (*instr_ptr << 16) |
1931                                         (*instr_ptr);
1932                                 /* 16-bit instruction. */
1933                                 dec_insn.next_pc_inc = 2;
1934                         } else {
1935                                 dec_insn.next_insn = (*instr_ptr << 16) |
1936                                         *(instr_ptr+1);
1937                                 /* 32-bit instruction. */
1938                                 dec_insn.next_pc_inc = 4;
1939                         }
1940                         dec_insn.micro_mips_mode = 1;
1941                 } else {
1942                         if ((get_user(dec_insn.insn,
1943                             (mips_instruction __user *) xcp->cp0_epc)) ||
1944                             (get_user(dec_insn.next_insn,
1945                             (mips_instruction __user *)(xcp->cp0_epc+4)))) {
1946                                 MIPS_FPU_EMU_INC_STATS(errors);
1947                                 return SIGBUS;
1948                         }
1949                         dec_insn.pc_inc = 4;
1950                         dec_insn.next_pc_inc = 4;
1951                         dec_insn.micro_mips_mode = 0;
1952                 }
1953
1954                 if ((dec_insn.insn == 0) ||
1955                    ((dec_insn.pc_inc == 2) &&
1956                    ((dec_insn.insn & 0xffff) == MM_NOP16)))
1957                         xcp->cp0_epc += dec_insn.pc_inc;        /* Skip NOPs */
1958                 else {
1959                         /*
1960                          * The 'ieee754_csr' is an alias of
1961                          * ctx->fcr31.  No need to copy ctx->fcr31 to
1962                          * ieee754_csr.  But ieee754_csr.rm is ieee
1963                          * library modes. (not mips rounding mode)
1964                          */
1965                         sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
1966                 }
1967
1968                 if (has_fpu)
1969                         break;
1970                 if (sig)
1971                         break;
1972
1973                 cond_resched();
1974         } while (xcp->cp0_epc > prevepc);
1975
1976         /* SIGILL indicates a non-fpu instruction */
1977         if (sig == SIGILL && xcp->cp0_epc != oldepc)
1978                 /* but if EPC has advanced, then ignore it */
1979                 sig = 0;
1980
1981         return sig;
1982 }