arch/mips/math-emu/cp1emu.c

   1 /*
   2  * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
   3  *
   4  * MIPS floating point support
   5  * Copyright (C) 1994-2000 Algorithmics Ltd.
   6  *
   7  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
   8  * Copyright (C) 2000  MIPS Technologies, Inc.
   9  *
  10  *  This program is free software; you can distribute it and/or modify it
  11  *  under the terms of the GNU General Public License (Version 2) as
  12  *  published by the Free Software Foundation.
  13  *
  14  *  This program is distributed in the hope it will be useful, but WITHOUT
  15  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  17  *  for more details.
  18  *
  19  *  You should have received a copy of the GNU General Public License along
  20  *  with this program; if not, write to the Free Software Foundation, Inc.,
  21  *  51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA.
  22  *
  23  * A complete emulator for MIPS coprocessor 1 instructions.  This is
  24  * required for #float(switch) or #float(trap), where it catches all
  25  * COP1 instructions via the "CoProcessor Unusable" exception.
  26  *
  27  * More surprisingly it is also required for #float(ieee), to help out
  28  * the hardware FPU at the boundaries of the IEEE-754 representation
  29  * (denormalised values, infinities, underflow, etc).  It is made
  30  * quite nasty because emulation of some non-COP1 instructions is
  31  * required, e.g. in branch delay slots.
  32  *
  33  * Note if you know that you won't have an FPU, then you'll get much
  34  * better performance by compiling with -msoft-float!
  35  */
  36 #include <linux/sched.h>
  37 #include <linux/debugfs.h>
  38 #include <linux/kconfig.h>
  39 #include <linux/percpu-defs.h>
  40 #include <linux/perf_event.h>
  41
  42 #include <asm/branch.h>
  43 #include <asm/inst.h>
  44 #include <asm/ptrace.h>
  45 #include <asm/signal.h>
  46 #include <asm/uaccess.h>
  47
  48 #include <asm/processor.h>
  49 #include <asm/fpu_emulator.h>
  50 #include <asm/fpu.h>
  51
  52 #include "ieee754.h"
  53
  54 /* Function which emulates a floating point instruction. */
  55
  56 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
  57         mips_instruction);
  58
  59 static int fpux_emu(struct pt_regs *,
  60         struct mips_fpu_struct *, mips_instruction, void *__user *);
  61
  62 /* Control registers */
  63
  64 #define FPCREG_RID      0       /* $0  = revision id */
  65 #define FPCREG_CSR      31      /* $31 = csr */
  66
  67 /* Determine rounding mode from the RM bits of the FCSR */
  68 #define modeindex(v) ((v) & FPU_CSR_RM)
  69
  70 /* convert condition code register number to csr bit */
  71 static const unsigned int fpucondbit[8] = {
  72         FPU_CSR_COND0,
  73         FPU_CSR_COND1,
  74         FPU_CSR_COND2,
  75         FPU_CSR_COND3,
  76         FPU_CSR_COND4,
  77         FPU_CSR_COND5,
  78         FPU_CSR_COND6,
  79         FPU_CSR_COND7
  80 };
  81
  82 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
  83 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
  84 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
  85 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
  86 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
  87
  88 /*
  89  * This functions translates a 32-bit microMIPS instruction
  90  * into a 32-bit MIPS32 instruction. Returns 0 on success
  91  * and SIGILL otherwise.
  92  */
  93 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
  94 {
  95         union mips_instruction insn = *insn_ptr;
  96         union mips_instruction mips32_insn = insn;
  97         int func, fmt, op;
  98
  99         switch (insn.mm_i_format.opcode) {
 100         case mm_ldc132_op:
 101                 mips32_insn.mm_i_format.opcode = ldc1_op;
 102                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 103                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 104                 break;
 105         case mm_lwc132_op:
 106                 mips32_insn.mm_i_format.opcode = lwc1_op;
 107                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 108                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 109                 break;
 110         case mm_sdc132_op:
 111                 mips32_insn.mm_i_format.opcode = sdc1_op;
 112                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 113                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 114                 break;
 115         case mm_swc132_op:
 116                 mips32_insn.mm_i_format.opcode = swc1_op;
 117                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 118                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 119                 break;
 120         case mm_pool32i_op:
 121                 /* NOTE: offset is << by 1 if in microMIPS mode. */
 122                 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
 123                     (insn.mm_i_format.rt == mm_bc1t_op)) {
 124                         mips32_insn.fb_format.opcode = cop1_op;
 125                         mips32_insn.fb_format.bc = bc_op;
 126                         mips32_insn.fb_format.flag =
 127                                 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
 128                 } else
 129                         return SIGILL;
 130                 break;
 131         case mm_pool32f_op:
 132                 switch (insn.mm_fp0_format.func) {
 133                 case mm_32f_01_op:
 134                 case mm_32f_11_op:
 135                 case mm_32f_02_op:
 136                 case mm_32f_12_op:
 137                 case mm_32f_41_op:
 138                 case mm_32f_51_op:
 139                 case mm_32f_42_op:
 140                 case mm_32f_52_op:
 141                         op = insn.mm_fp0_format.func;
 142                         if (op == mm_32f_01_op)
 143                                 func = madd_s_op;
 144                         else if (op == mm_32f_11_op)
 145                                 func = madd_d_op;
 146                         else if (op == mm_32f_02_op)
 147                                 func = nmadd_s_op;
 148                         else if (op == mm_32f_12_op)
 149                                 func = nmadd_d_op;
 150                         else if (op == mm_32f_41_op)
 151                                 func = msub_s_op;
 152                         else if (op == mm_32f_51_op)
 153                                 func = msub_d_op;
 154                         else if (op == mm_32f_42_op)
 155                                 func = nmsub_s_op;
 156                         else
 157                                 func = nmsub_d_op;
 158                         mips32_insn.fp6_format.opcode = cop1x_op;
 159                         mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
 160                         mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
 161                         mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
 162                         mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
 163                         mips32_insn.fp6_format.func = func;
 164                         break;
 165                 case mm_32f_10_op:
 166                         func = -1;      /* Invalid */
 167                         op = insn.mm_fp5_format.op & 0x7;
 168                         if (op == mm_ldxc1_op)
 169                                 func = ldxc1_op;
 170                         else if (op == mm_sdxc1_op)
 171                                 func = sdxc1_op;
 172                         else if (op == mm_lwxc1_op)
 173                                 func = lwxc1_op;
 174                         else if (op == mm_swxc1_op)
 175                                 func = swxc1_op;
 176
 177                         if (func != -1) {
 178                                 mips32_insn.r_format.opcode = cop1x_op;
 179                                 mips32_insn.r_format.rs =
 180                                         insn.mm_fp5_format.base;
 181                                 mips32_insn.r_format.rt =
 182                                         insn.mm_fp5_format.index;
 183                                 mips32_insn.r_format.rd = 0;
 184                                 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
 185                                 mips32_insn.r_format.func = func;
 186                         } else
 187                                 return SIGILL;
 188                         break;
 189                 case mm_32f_40_op:
 190                         op = -1;        /* Invalid */
 191                         if (insn.mm_fp2_format.op == mm_fmovt_op)
 192                                 op = 1;
 193                         else if (insn.mm_fp2_format.op == mm_fmovf_op)
 194                                 op = 0;
 195                         if (op != -1) {
 196                                 mips32_insn.fp0_format.opcode = cop1_op;
 197                                 mips32_insn.fp0_format.fmt =
 198                                         sdps_format[insn.mm_fp2_format.fmt];
 199                                 mips32_insn.fp0_format.ft =
 200                                         (insn.mm_fp2_format.cc<<2) + op;
 201                                 mips32_insn.fp0_format.fs =
 202                                         insn.mm_fp2_format.fs;
 203                                 mips32_insn.fp0_format.fd =
 204                                         insn.mm_fp2_format.fd;
 205                                 mips32_insn.fp0_format.func = fmovc_op;
 206                         } else
 207                                 return SIGILL;
 208                         break;
 209                 case mm_32f_60_op:
 210                         func = -1;      /* Invalid */
 211                         if (insn.mm_fp0_format.op == mm_fadd_op)
 212                                 func = fadd_op;
 213                         else if (insn.mm_fp0_format.op == mm_fsub_op)
 214                                 func = fsub_op;
 215                         else if (insn.mm_fp0_format.op == mm_fmul_op)
 216                                 func = fmul_op;
 217                         else if (insn.mm_fp0_format.op == mm_fdiv_op)
 218                                 func = fdiv_op;
 219                         if (func != -1) {
 220                                 mips32_insn.fp0_format.opcode = cop1_op;
 221                                 mips32_insn.fp0_format.fmt =
 222                                         sdps_format[insn.mm_fp0_format.fmt];
 223                                 mips32_insn.fp0_format.ft =
 224                                         insn.mm_fp0_format.ft;
 225                                 mips32_insn.fp0_format.fs =
 226                                         insn.mm_fp0_format.fs;
 227                                 mips32_insn.fp0_format.fd =
 228                                         insn.mm_fp0_format.fd;
 229                                 mips32_insn.fp0_format.func = func;
 230                         } else
 231                                 return SIGILL;
 232                         break;
 233                 case mm_32f_70_op:
 234                         func = -1;      /* Invalid */
 235                         if (insn.mm_fp0_format.op == mm_fmovn_op)
 236                                 func = fmovn_op;
 237                         else if (insn.mm_fp0_format.op == mm_fmovz_op)
 238                                 func = fmovz_op;
 239                         if (func != -1) {
 240                                 mips32_insn.fp0_format.opcode = cop1_op;
 241                                 mips32_insn.fp0_format.fmt =
 242                                         sdps_format[insn.mm_fp0_format.fmt];
 243                                 mips32_insn.fp0_format.ft =
 244                                         insn.mm_fp0_format.ft;
 245                                 mips32_insn.fp0_format.fs =
 246                                         insn.mm_fp0_format.fs;
 247                                 mips32_insn.fp0_format.fd =
 248                                         insn.mm_fp0_format.fd;
 249                                 mips32_insn.fp0_format.func = func;
 250                         } else
 251                                 return SIGILL;
 252                         break;
 253                 case mm_32f_73_op:    /* POOL32FXF */
 254                         switch (insn.mm_fp1_format.op) {
 255                         case mm_movf0_op:
 256                         case mm_movf1_op:
 257                         case mm_movt0_op:
 258                         case mm_movt1_op:
 259                                 if ((insn.mm_fp1_format.op & 0x7f) ==
 260                                     mm_movf0_op)
 261                                         op = 0;
 262                                 else
 263                                         op = 1;
 264                                 mips32_insn.r_format.opcode = spec_op;
 265                                 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
 266                                 mips32_insn.r_format.rt =
 267                                         (insn.mm_fp4_format.cc << 2) + op;
 268                                 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
 269                                 mips32_insn.r_format.re = 0;
 270                                 mips32_insn.r_format.func = movc_op;
 271                                 break;
 272                         case mm_fcvtd0_op:
 273                         case mm_fcvtd1_op:
 274                         case mm_fcvts0_op:
 275                         case mm_fcvts1_op:
 276                                 if ((insn.mm_fp1_format.op & 0x7f) ==
 277                                     mm_fcvtd0_op) {
 278                                         func = fcvtd_op;
 279                                         fmt = swl_format[insn.mm_fp3_format.fmt];
 280                                 } else {
 281                                         func = fcvts_op;
 282                                         fmt = dwl_format[insn.mm_fp3_format.fmt];
 283                                 }
 284                                 mips32_insn.fp0_format.opcode = cop1_op;
 285                                 mips32_insn.fp0_format.fmt = fmt;
 286                                 mips32_insn.fp0_format.ft = 0;
 287                                 mips32_insn.fp0_format.fs =
 288                                         insn.mm_fp3_format.fs;
 289                                 mips32_insn.fp0_format.fd =
 290                                         insn.mm_fp3_format.rt;
 291                                 mips32_insn.fp0_format.func = func;
 292                                 break;
 293                         case mm_fmov0_op:
 294                         case mm_fmov1_op:
 295                         case mm_fabs0_op:
 296                         case mm_fabs1_op:
 297                         case mm_fneg0_op:
 298                         case mm_fneg1_op:
 299                                 if ((insn.mm_fp1_format.op & 0x7f) ==
 300                                     mm_fmov0_op)
 301                                         func = fmov_op;
 302                                 else if ((insn.mm_fp1_format.op & 0x7f) ==
 303                                          mm_fabs0_op)
 304                                         func = fabs_op;
 305                                 else
 306                                         func = fneg_op;
 307                                 mips32_insn.fp0_format.opcode = cop1_op;
 308                                 mips32_insn.fp0_format.fmt =
 309                                         sdps_format[insn.mm_fp3_format.fmt];
 310                                 mips32_insn.fp0_format.ft = 0;
 311                                 mips32_insn.fp0_format.fs =
 312                                         insn.mm_fp3_format.fs;
 313                                 mips32_insn.fp0_format.fd =
 314                                         insn.mm_fp3_format.rt;
 315                                 mips32_insn.fp0_format.func = func;
 316                                 break;
 317                         case mm_ffloorl_op:
 318                         case mm_ffloorw_op:
 319                         case mm_fceill_op:
 320                         case mm_fceilw_op:
 321                         case mm_ftruncl_op:
 322                         case mm_ftruncw_op:
 323                         case mm_froundl_op:
 324                         case mm_froundw_op:
 325                         case mm_fcvtl_op:
 326                         case mm_fcvtw_op:
 327                                 if (insn.mm_fp1_format.op == mm_ffloorl_op)
 328                                         func = ffloorl_op;
 329                                 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
 330                                         func = ffloor_op;
 331                                 else if (insn.mm_fp1_format.op == mm_fceill_op)
 332                                         func = fceill_op;
 333                                 else if (insn.mm_fp1_format.op == mm_fceilw_op)
 334                                         func = fceil_op;
 335                                 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
 336                                         func = ftruncl_op;
 337                                 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
 338                                         func = ftrunc_op;
 339                                 else if (insn.mm_fp1_format.op == mm_froundl_op)
 340                                         func = froundl_op;
 341                                 else if (insn.mm_fp1_format.op == mm_froundw_op)
 342                                         func = fround_op;
 343                                 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
 344                                         func = fcvtl_op;
 345                                 else
 346                                         func = fcvtw_op;
 347                                 mips32_insn.fp0_format.opcode = cop1_op;
 348                                 mips32_insn.fp0_format.fmt =
 349                                         sd_format[insn.mm_fp1_format.fmt];
 350                                 mips32_insn.fp0_format.ft = 0;
 351                                 mips32_insn.fp0_format.fs =
 352                                         insn.mm_fp1_format.fs;
 353                                 mips32_insn.fp0_format.fd =
 354                                         insn.mm_fp1_format.rt;
 355                                 mips32_insn.fp0_format.func = func;
 356                                 break;
 357                         case mm_frsqrt_op:
 358                         case mm_fsqrt_op:
 359                         case mm_frecip_op:
 360                                 if (insn.mm_fp1_format.op == mm_frsqrt_op)
 361                                         func = frsqrt_op;
 362                                 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
 363                                         func = fsqrt_op;
 364                                 else
 365                                         func = frecip_op;
 366                                 mips32_insn.fp0_format.opcode = cop1_op;
 367                                 mips32_insn.fp0_format.fmt =
 368                                         sdps_format[insn.mm_fp1_format.fmt];
 369                                 mips32_insn.fp0_format.ft = 0;
 370                                 mips32_insn.fp0_format.fs =
 371                                         insn.mm_fp1_format.fs;
 372                                 mips32_insn.fp0_format.fd =
 373                                         insn.mm_fp1_format.rt;
 374                                 mips32_insn.fp0_format.func = func;
 375                                 break;
 376                         case mm_mfc1_op:
 377                         case mm_mtc1_op:
 378                         case mm_cfc1_op:
 379                         case mm_ctc1_op:
 380                         case mm_mfhc1_op:
 381                         case mm_mthc1_op:
 382                                 if (insn.mm_fp1_format.op == mm_mfc1_op)
 383                                         op = mfc_op;
 384                                 else if (insn.mm_fp1_format.op == mm_mtc1_op)
 385                                         op = mtc_op;
 386                                 else if (insn.mm_fp1_format.op == mm_cfc1_op)
 387                                         op = cfc_op;
 388                                 else if (insn.mm_fp1_format.op == mm_ctc1_op)
 389                                         op = ctc_op;
 390                                 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
 391                                         op = mfhc_op;
 392                                 else
 393                                         op = mthc_op;
 394                                 mips32_insn.fp1_format.opcode = cop1_op;
 395                                 mips32_insn.fp1_format.op = op;
 396                                 mips32_insn.fp1_format.rt =
 397                                         insn.mm_fp1_format.rt;
 398                                 mips32_insn.fp1_format.fs =
 399                                         insn.mm_fp1_format.fs;
 400                                 mips32_insn.fp1_format.fd = 0;
 401                                 mips32_insn.fp1_format.func = 0;
 402                                 break;
 403                         default:
 404                                 return SIGILL;
 405                         }
 406                         break;
 407                 case mm_32f_74_op:      /* c.cond.fmt */
 408                         mips32_insn.fp0_format.opcode = cop1_op;
 409                         mips32_insn.fp0_format.fmt =
 410                                 sdps_format[insn.mm_fp4_format.fmt];
 411                         mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
 412                         mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
 413                         mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
 414                         mips32_insn.fp0_format.func =
 415                                 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
 416                         break;
 417                 default:
 418                         return SIGILL;
 419                 }
 420                 break;
 421         default:
 422                 return SIGILL;
 423         }
 424
 425         *insn_ptr = mips32_insn;
 426         return 0;
 427 }
 428
 429 /*
 430  * Redundant with logic already in kernel/branch.c,
 431  * embedded in compute_return_epc.  At some point,
 432  * a single subroutine should be used across both
 433  * modules.
 434  */
 435 static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
 436                          unsigned long *contpc)
 437 {
 438         union mips_instruction insn = (union mips_instruction)dec_insn.insn;
 439         unsigned int fcr31;
 440         unsigned int bit = 0;
 441
 442         switch (insn.i_format.opcode) {
 443         case spec_op:
 444                 switch (insn.r_format.func) {
 445                 case jalr_op:
 446                         regs->regs[insn.r_format.rd] =
 447                                 regs->cp0_epc + dec_insn.pc_inc +
 448                                 dec_insn.next_pc_inc;
 449                         /* Fall through */
 450                 case jr_op:
 451                         /* For R6, JR already emulated in jalr_op */
 452                         if (NO_R6EMU && insn.r_format.opcode == jr_op)
 453                                 break;
 454                         *contpc = regs->regs[insn.r_format.rs];
 455                         return 1;
 456                 }
 457                 break;
 458         case bcond_op:
 459                 switch (insn.i_format.rt) {
 460                 case bltzal_op:
 461                 case bltzall_op:
 462                         regs->regs[31] = regs->cp0_epc +
 463                                 dec_insn.pc_inc +
 464                                 dec_insn.next_pc_inc;
 465                         /* Fall through */
 466                 case bltz_op:
 467                 case bltzl_op:
 468                         if ((long)regs->regs[insn.i_format.rs] < 0)
 469                                 *contpc = regs->cp0_epc +
 470                                         dec_insn.pc_inc +
 471                                         (insn.i_format.simmediate << 2);
 472                         else
 473                                 *contpc = regs->cp0_epc +
 474                                         dec_insn.pc_inc +
 475                                         dec_insn.next_pc_inc;
 476                         return 1;
 477                 case bgezal_op:
 478                 case bgezall_op:
 479                         regs->regs[31] = regs->cp0_epc +
 480                                 dec_insn.pc_inc +
 481                                 dec_insn.next_pc_inc;
 482                         /* Fall through */
 483                 case bgez_op:
 484                 case bgezl_op:
 485                         if ((long)regs->regs[insn.i_format.rs] >= 0)
 486                                 *contpc = regs->cp0_epc +
 487                                         dec_insn.pc_inc +
 488                                         (insn.i_format.simmediate << 2);
 489                         else
 490                                 *contpc = regs->cp0_epc +
 491                                         dec_insn.pc_inc +
 492                                         dec_insn.next_pc_inc;
 493                         return 1;
 494                 }
 495                 break;
 496         case jalx_op:
 497                 set_isa16_mode(bit);
 498         case jal_op:
 499                 regs->regs[31] = regs->cp0_epc +
 500                         dec_insn.pc_inc +
 501                         dec_insn.next_pc_inc;
 502                 /* Fall through */
 503         case j_op:
 504                 *contpc = regs->cp0_epc + dec_insn.pc_inc;
 505                 *contpc >>= 28;
 506                 *contpc <<= 28;
 507                 *contpc |= (insn.j_format.target << 2);
 508                 /* Set microMIPS mode bit: XOR for jalx. */
 509                 *contpc ^= bit;
 510                 return 1;
 511         case beq_op:
 512         case beql_op:
 513                 if (regs->regs[insn.i_format.rs] ==
 514                     regs->regs[insn.i_format.rt])
 515                         *contpc = regs->cp0_epc +
 516                                 dec_insn.pc_inc +
 517                                 (insn.i_format.simmediate << 2);
 518                 else
 519                         *contpc = regs->cp0_epc +
 520                                 dec_insn.pc_inc +
 521                                 dec_insn.next_pc_inc;
 522                 return 1;
 523         case bne_op:
 524         case bnel_op:
 525                 if (regs->regs[insn.i_format.rs] !=
 526                     regs->regs[insn.i_format.rt])
 527                         *contpc = regs->cp0_epc +
 528                                 dec_insn.pc_inc +
 529                                 (insn.i_format.simmediate << 2);
 530                 else
 531                         *contpc = regs->cp0_epc +
 532                                 dec_insn.pc_inc +
 533                                 dec_insn.next_pc_inc;
 534                 return 1;
 535         case blez_op:
 536         case blezl_op:
 537                 if ((long)regs->regs[insn.i_format.rs] <= 0)
 538                         *contpc = regs->cp0_epc +
 539                                 dec_insn.pc_inc +
 540                                 (insn.i_format.simmediate << 2);
 541                 else
 542                         *contpc = regs->cp0_epc +
 543                                 dec_insn.pc_inc +
 544                                 dec_insn.next_pc_inc;
 545                 return 1;
 546         case bgtz_op:
 547         case bgtzl_op:
 548                 if ((long)regs->regs[insn.i_format.rs] > 0)
 549                         *contpc = regs->cp0_epc +
 550                                 dec_insn.pc_inc +
 551                                 (insn.i_format.simmediate << 2);
 552                 else
 553                         *contpc = regs->cp0_epc +
 554                                 dec_insn.pc_inc +
 555                                 dec_insn.next_pc_inc;
 556                 return 1;
 557 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 558         case lwc2_op: /* This is bbit0 on Octeon */
 559                 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
 560                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 561                 else
 562                         *contpc = regs->cp0_epc + 8;
 563                 return 1;
 564         case ldc2_op: /* This is bbit032 on Octeon */
 565                 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
 566                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 567                 else
 568                         *contpc = regs->cp0_epc + 8;
 569                 return 1;
 570         case swc2_op: /* This is bbit1 on Octeon */
 571                 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
 572                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 573                 else
 574                         *contpc = regs->cp0_epc + 8;
 575                 return 1;
 576         case sdc2_op: /* This is bbit132 on Octeon */
 577                 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
 578                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 579                 else
 580                         *contpc = regs->cp0_epc + 8;
 581                 return 1;
 582 #endif
 583         case cop0_op:
 584         case cop1_op:
 585         case cop2_op:
 586         case cop1x_op:
 587                 if (insn.i_format.rs == bc_op) {
 588                         preempt_disable();
 589                         if (is_fpu_owner())
 590                                 fcr31 = read_32bit_cp1_register(CP1_STATUS);
 591                         else
 592                                 fcr31 = current->thread.fpu.fcr31;
 593                         preempt_enable();
 594
 595                         bit = (insn.i_format.rt >> 2);
 596                         bit += (bit != 0);
 597                         bit += 23;
 598                         switch (insn.i_format.rt & 3) {
 599                         case 0: /* bc1f */
 600                         case 2: /* bc1fl */
 601                                 if (~fcr31 & (1 << bit))
 602                                         *contpc = regs->cp0_epc +
 603                                                 dec_insn.pc_inc +
 604                                                 (insn.i_format.simmediate << 2);
 605                                 else
 606                                         *contpc = regs->cp0_epc +
 607                                                 dec_insn.pc_inc +
 608                                                 dec_insn.next_pc_inc;
 609                                 return 1;
 610                         case 1: /* bc1t */
 611                         case 3: /* bc1tl */
 612                                 if (fcr31 & (1 << bit))
 613                                         *contpc = regs->cp0_epc +
 614                                                 dec_insn.pc_inc +
 615                                                 (insn.i_format.simmediate << 2);
 616                                 else
 617                                         *contpc = regs->cp0_epc +
 618                                                 dec_insn.pc_inc +
 619                                                 dec_insn.next_pc_inc;
 620                                 return 1;
 621                         }
 622                 }
 623                 break;
 624         }
 625         return 0;
 626 }
 627
 628 /*
 629  * In the Linux kernel, we support selection of FPR format on the
 630  * basis of the Status.FR bit.  If an FPU is not present, the FR bit
 631  * is hardwired to zero, which would imply a 32-bit FPU even for
 632  * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
 633  * FPU emu is slow and bulky and optimizing this function offers fairly
 634  * sizeable benefits so we try to be clever and make this function return
 635  * a constant whenever possible, that is on 64-bit kernels without O32
 636  * compatibility enabled and on 32-bit without 64-bit FPU support.
 637  */
 638 static inline int cop1_64bit(struct pt_regs *xcp)
 639 {
 640         if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32))
 641                 return 1;
 642         else if (config_enabled(CONFIG_32BIT) &&
 643                  !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT))
 644                 return 0;
 645
 646         return !test_thread_flag(TIF_32BIT_FPREGS);
 647 }
 648
 649 static inline bool hybrid_fprs(void)
 650 {
 651         return test_thread_flag(TIF_HYBRID_FPREGS);
 652 }
 653
 654 #define SIFROMREG(si, x)                                                \
 655 do {                                                                    \
 656         if (cop1_64bit(xcp) && !hybrid_fprs())                          \
 657                 (si) = (int)get_fpr32(&ctx->fpr[x], 0);                 \
 658         else                                                            \
 659                 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1);    \
 660 } while (0)
 661
 662 #define SITOREG(si, x)                                                  \
 663 do {                                                                    \
 664         if (cop1_64bit(xcp) && !hybrid_fprs()) {                        \
 665                 unsigned i;                                             \
 666                 set_fpr32(&ctx->fpr[x], 0, si);                         \
 667                 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++)     \
 668                         set_fpr32(&ctx->fpr[x], i, 0);                  \
 669         } else {                                                        \
 670                 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si);            \
 671         }                                                               \
 672 } while (0)
 673
 674 #define SIFROMHREG(si, x)       ((si) = (int)get_fpr32(&ctx->fpr[x], 1))
 675
 676 #define SITOHREG(si, x)                                                 \
 677 do {                                                                    \
 678         unsigned i;                                                     \
 679         set_fpr32(&ctx->fpr[x], 1, si);                                 \
 680         for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++)             \
 681                 set_fpr32(&ctx->fpr[x], i, 0);                          \
 682 } while (0)
 683
 684 #define DIFROMREG(di, x)                                                \
 685         ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
 686
 687 #define DITOREG(di, x)                                                  \
 688 do {                                                                    \
 689         unsigned fpr, i;                                                \
 690         fpr = (x) & ~(cop1_64bit(xcp) == 0);                            \
 691         set_fpr64(&ctx->fpr[fpr], 0, di);                               \
 692         for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++)             \
 693                 set_fpr64(&ctx->fpr[fpr], i, 0);                        \
 694 } while (0)
 695
 696 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
 697 #define SPTOREG(sp, x)  SITOREG((sp).bits, x)
 698 #define DPFROMREG(dp, x)        DIFROMREG((dp).bits, x)
 699 #define DPTOREG(dp, x)  DITOREG((dp).bits, x)
 700
 701 /*
 702  * Emulate the single floating point instruction pointed at by EPC.
 703  * Two instructions if the instruction is in a branch delay slot.
 704  */
 705
 706 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 707                 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
 708 {
 709         unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
 710         unsigned int cond, cbit;
 711         mips_instruction ir;
 712         int likely, pc_inc;
 713         u32 __user *wva;
 714         u64 __user *dva;
 715         u32 value;
 716         u32 wval;
 717         u64 dval;
 718         int sig;
 719
 720         /*
 721          * These are giving gcc a gentle hint about what to expect in
 722          * dec_inst in order to do better optimization.
 723          */
 724         if (!cpu_has_mmips && dec_insn.micro_mips_mode)
 725                 unreachable();
 726
 727         /* XXX NEC Vr54xx bug workaround */
 728         if (delay_slot(xcp)) {
 729                 if (dec_insn.micro_mips_mode) {
 730                         if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
 731                                 clear_delay_slot(xcp);
 732                 } else {
 733                         if (!isBranchInstr(xcp, dec_insn, &contpc))
 734                                 clear_delay_slot(xcp);
 735                 }
 736         }
 737
 738         if (delay_slot(xcp)) {
 739                 /*
 740                  * The instruction to be emulated is in a branch delay slot
 741                  * which means that we have to  emulate the branch instruction
 742                  * BEFORE we do the cop1 instruction.
 743                  *
 744                  * This branch could be a COP1 branch, but in that case we
 745                  * would have had a trap for that instruction, and would not
 746                  * come through this route.
 747                  *
 748                  * Linux MIPS branch emulator operates on context, updating the
 749                  * cp0_epc.
 750                  */
 751                 ir = dec_insn.next_insn;  /* process delay slot instr */
 752                 pc_inc = dec_insn.next_pc_inc;
 753         } else {
 754                 ir = dec_insn.insn;       /* process current instr */
 755                 pc_inc = dec_insn.pc_inc;
 756         }
 757
 758         /*
 759          * Since microMIPS FPU instructios are a subset of MIPS32 FPU
 760          * instructions, we want to convert microMIPS FPU instructions
 761          * into MIPS32 instructions so that we could reuse all of the
 762          * FPU emulation code.
 763          *
 764          * NOTE: We cannot do this for branch instructions since they
 765          *       are not a subset. Example: Cannot emulate a 16-bit
 766          *       aligned target address with a MIPS32 instruction.
 767          */
 768         if (dec_insn.micro_mips_mode) {
 769                 /*
 770                  * If next instruction is a 16-bit instruction, then it
 771                  * it cannot be a FPU instruction. This could happen
 772                  * since we can be called for non-FPU instructions.
 773                  */
 774                 if ((pc_inc == 2) ||
 775                         (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
 776                          == SIGILL))
 777                         return SIGILL;
 778         }
 779
 780 emul:
 781         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
 782         MIPS_FPU_EMU_INC_STATS(emulated);
 783         switch (MIPSInst_OPCODE(ir)) {
 784         case ldc1_op:
 785                 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
 786                                      MIPSInst_SIMM(ir));
 787                 MIPS_FPU_EMU_INC_STATS(loads);
 788
 789                 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) {
 790                         MIPS_FPU_EMU_INC_STATS(errors);
 791                         *fault_addr = dva;
 792                         return SIGBUS;
 793                 }
 794                 if (__get_user(dval, dva)) {
 795                         MIPS_FPU_EMU_INC_STATS(errors);
 796                         *fault_addr = dva;
 797                         return SIGSEGV;
 798                 }
 799                 DITOREG(dval, MIPSInst_RT(ir));
 800                 break;
 801
 802         case sdc1_op:
 803                 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
 804                                       MIPSInst_SIMM(ir));
 805                 MIPS_FPU_EMU_INC_STATS(stores);
 806                 DIFROMREG(dval, MIPSInst_RT(ir));
 807                 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) {
 808                         MIPS_FPU_EMU_INC_STATS(errors);
 809                         *fault_addr = dva;
 810                         return SIGBUS;
 811                 }
 812                 if (__put_user(dval, dva)) {
 813                         MIPS_FPU_EMU_INC_STATS(errors);
 814                         *fault_addr = dva;
 815                         return SIGSEGV;
 816                 }
 817                 break;
 818
 819         case lwc1_op:
 820                 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
 821                                       MIPSInst_SIMM(ir));
 822                 MIPS_FPU_EMU_INC_STATS(loads);
 823                 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) {
 824                         MIPS_FPU_EMU_INC_STATS(errors);
 825                         *fault_addr = wva;
 826                         return SIGBUS;
 827                 }
 828                 if (__get_user(wval, wva)) {
 829                         MIPS_FPU_EMU_INC_STATS(errors);
 830                         *fault_addr = wva;
 831                         return SIGSEGV;
 832                 }
 833                 SITOREG(wval, MIPSInst_RT(ir));
 834                 break;
 835
 836         case swc1_op:
 837                 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
 838                                       MIPSInst_SIMM(ir));
 839                 MIPS_FPU_EMU_INC_STATS(stores);
 840                 SIFROMREG(wval, MIPSInst_RT(ir));
 841                 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) {
 842                         MIPS_FPU_EMU_INC_STATS(errors);
 843                         *fault_addr = wva;
 844                         return SIGBUS;
 845                 }
 846                 if (__put_user(wval, wva)) {
 847                         MIPS_FPU_EMU_INC_STATS(errors);
 848                         *fault_addr = wva;
 849                         return SIGSEGV;
 850                 }
 851                 break;
 852
 853         case cop1_op:
 854                 switch (MIPSInst_RS(ir)) {
 855                 case dmfc_op:
 856                         if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
 857                                 return SIGILL;
 858
 859                         /* copregister fs -> gpr[rt] */
 860                         if (MIPSInst_RT(ir) != 0) {
 861                                 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
 862                                         MIPSInst_RD(ir));
 863                         }
 864                         break;
 865
 866                 case dmtc_op:
 867                         if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
 868                                 return SIGILL;
 869
 870                         /* copregister fs <- rt */
 871                         DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
 872                         break;
 873
 874                 case mfhc_op:
 875                         if (!cpu_has_mips_r2)
 876                                 goto sigill;
 877
 878                         /* copregister rd -> gpr[rt] */
 879                         if (MIPSInst_RT(ir) != 0) {
 880                                 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
 881                                         MIPSInst_RD(ir));
 882                         }
 883                         break;
 884
 885                 case mthc_op:
 886                         if (!cpu_has_mips_r2)
 887                                 goto sigill;
 888
 889                         /* copregister rd <- gpr[rt] */
 890                         SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
 891                         break;
 892
 893                 case mfc_op:
 894                         /* copregister rd -> gpr[rt] */
 895                         if (MIPSInst_RT(ir) != 0) {
 896                                 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
 897                                         MIPSInst_RD(ir));
 898                         }
 899                         break;
 900
 901                 case mtc_op:
 902                         /* copregister rd <- rt */
 903                         SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
 904                         break;
 905
 906                 case cfc_op:
 907                         /* cop control register rd -> gpr[rt] */
 908                         if (MIPSInst_RD(ir) == FPCREG_CSR) {
 909                                 value = ctx->fcr31;
 910                                 value = (value & ~FPU_CSR_RM) | modeindex(value);
 911                                 pr_debug("%p gpr[%d]<-csr=%08x\n",
 912                                          (void *) (xcp->cp0_epc),
 913                                          MIPSInst_RT(ir), value);
 914                         }
 915                         else if (MIPSInst_RD(ir) == FPCREG_RID)
 916                                 value = 0;
 917                         else
 918                                 value = 0;
 919                         if (MIPSInst_RT(ir))
 920                                 xcp->regs[MIPSInst_RT(ir)] = value;
 921                         break;
 922
 923                 case ctc_op:
 924                         /* copregister rd <- rt */
 925                         if (MIPSInst_RT(ir) == 0)
 926                                 value = 0;
 927                         else
 928                                 value = xcp->regs[MIPSInst_RT(ir)];
 929
 930                         /* we only have one writable control reg
 931                          */
 932                         if (MIPSInst_RD(ir) == FPCREG_CSR) {
 933                                 pr_debug("%p gpr[%d]->csr=%08x\n",
 934                                          (void *) (xcp->cp0_epc),
 935                                          MIPSInst_RT(ir), value);
 936
 937                                 /*
 938                                  * Don't write reserved bits,
 939                                  * and convert to ieee library modes
 940                                  */
 941                                 ctx->fcr31 = (value & ~(FPU_CSR_RSVD | FPU_CSR_RM)) |
 942                                              modeindex(value);
 943                         }
 944                         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
 945                                 return SIGFPE;
 946                         }
 947                         break;
 948
 949                 case bc_op:
 950                         if (delay_slot(xcp))
 951                                 return SIGILL;
 952
 953                         if (cpu_has_mips_4_5_r)
 954                                 cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
 955                         else
 956                                 cbit = FPU_CSR_COND;
 957                         cond = ctx->fcr31 & cbit;
 958
 959                         likely = 0;
 960                         switch (MIPSInst_RT(ir) & 3) {
 961                         case bcfl_op:
 962                                 likely = 1;
 963                         case bcf_op:
 964                                 cond = !cond;
 965                                 break;
 966                         case bctl_op:
 967                                 likely = 1;
 968                         case bct_op:
 969                                 break;
 970                         default:
 971                                 /* thats an illegal instruction */
 972                                 return SIGILL;
 973                         }
 974
 975                         set_delay_slot(xcp);
 976                         if (cond) {
 977                                 /*
 978                                  * Branch taken: emulate dslot instruction
 979                                  */
 980                                 xcp->cp0_epc += dec_insn.pc_inc;
 981
 982                                 contpc = MIPSInst_SIMM(ir);
 983                                 ir = dec_insn.next_insn;
 984                                 if (dec_insn.micro_mips_mode) {
 985                                         contpc = (xcp->cp0_epc + (contpc << 1));
 986
 987                                         /* If 16-bit instruction, not FPU. */
 988                                         if ((dec_insn.next_pc_inc == 2) ||
 989                                                 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
 990
 991                                                 /*
 992                                                  * Since this instruction will
 993                                                  * be put on the stack with
 994                                                  * 32-bit words, get around
 995                                                  * this problem by putting a
 996                                                  * NOP16 as the second one.
 997                                                  */
 998                                                 if (dec_insn.next_pc_inc == 2)
 999                                                         ir = (ir & (~0xffff)) | MM_NOP16;
1000
1001                                                 /*
1002                                                  * Single step the non-CP1
1003                                                  * instruction in the dslot.
1004                                                  */
1005                                                 return mips_dsemul(xcp, ir, contpc);
1006                                         }
1007                                 } else
1008                                         contpc = (xcp->cp0_epc + (contpc << 2));
1009
1010                                 switch (MIPSInst_OPCODE(ir)) {
1011                                 case lwc1_op:
1012                                         goto emul;
1013
1014                                 case swc1_op:
1015                                         goto emul;
1016
1017                                 case ldc1_op:
1018                                 case sdc1_op:
1019                                         if (cpu_has_mips_2_3_4_5 ||
1020                                             cpu_has_mips64)
1021                                                 goto emul;
1022
1023                                         return SIGILL;
1024                                         goto emul;
1025
1026                                 case cop1_op:
1027                                         goto emul;
1028
1029                                 case cop1x_op:
1030                                         if (cpu_has_mips_4_5 || cpu_has_mips64 || cpu_has_mips32r2)
1031                                                 /* its one of ours */
1032                                                 goto emul;
1033
1034                                         return SIGILL;
1035
1036                                 case spec_op:
1037                                         if (!cpu_has_mips_4_5_r)
1038                                                 return SIGILL;
1039
1040                                         if (MIPSInst_FUNC(ir) == movc_op)
1041                                                 goto emul;
1042                                         break;
1043                                 }
1044
1045                                 /*
1046                                  * Single step the non-cp1
1047                                  * instruction in the dslot
1048                                  */
1049                                 return mips_dsemul(xcp, ir, contpc);
1050                         } else if (likely) {    /* branch not taken */
1051                                         /*
1052                                          * branch likely nullifies
1053                                          * dslot if not taken
1054                                          */
1055                                         xcp->cp0_epc += dec_insn.pc_inc;
1056                                         contpc += dec_insn.pc_inc;
1057                                         /*
1058                                          * else continue & execute
1059                                          * dslot as normal insn
1060                                          */
1061                                 }
1062                         break;
1063
1064                 default:
1065                         if (!(MIPSInst_RS(ir) & 0x10))
1066                                 return SIGILL;
1067
1068                         /* a real fpu computation instruction */
1069                         if ((sig = fpu_emu(xcp, ctx, ir)))
1070                                 return sig;
1071                 }
1072                 break;
1073
1074         case cop1x_op:
1075                 if (!cpu_has_mips_4_5 && !cpu_has_mips64 && !cpu_has_mips32r2)
1076                         return SIGILL;
1077
1078                 sig = fpux_emu(xcp, ctx, ir, fault_addr);
1079                 if (sig)
1080                         return sig;
1081                 break;
1082
1083         case spec_op:
1084                 if (!cpu_has_mips_4_5_r)
1085                         return SIGILL;
1086
1087                 if (MIPSInst_FUNC(ir) != movc_op)
1088                         return SIGILL;
1089                 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1090                 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1091                         xcp->regs[MIPSInst_RD(ir)] =
1092                                 xcp->regs[MIPSInst_RS(ir)];
1093                 break;
1094         default:
1095 sigill:
1096                 return SIGILL;
1097         }
1098
1099         /* we did it !! */
1100         xcp->cp0_epc = contpc;
1101         clear_delay_slot(xcp);
1102
1103         return 0;
1104 }
1105
1106 /*
1107  * Conversion table from MIPS compare ops 48-63
1108  * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1109  */
1110 static const unsigned char cmptab[8] = {
1111         0,                      /* cmp_0 (sig) cmp_sf */
1112         IEEE754_CUN,            /* cmp_un (sig) cmp_ngle */
1113         IEEE754_CEQ,            /* cmp_eq (sig) cmp_seq */
1114         IEEE754_CEQ | IEEE754_CUN,      /* cmp_ueq (sig) cmp_ngl  */
1115         IEEE754_CLT,            /* cmp_olt (sig) cmp_lt */
1116         IEEE754_CLT | IEEE754_CUN,      /* cmp_ult (sig) cmp_nge */
1117         IEEE754_CLT | IEEE754_CEQ,      /* cmp_ole (sig) cmp_le */
1118         IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN,        /* cmp_ule (sig) cmp_ngt */
1119 };
1120
1121
1122 /*
1123  * Additional MIPS4 instructions
1124  */
1125
1126 #define DEF3OP(name, p, f1, f2, f3)                                     \
1127 static union ieee754##p fpemu_##p##_##name(union ieee754##p r,          \
1128         union ieee754##p s, union ieee754##p t)                         \
1129 {                                                                       \
1130         struct _ieee754_csr ieee754_csr_save;                           \
1131         s = f1(s, t);                                                   \
1132         ieee754_csr_save = ieee754_csr;                                 \
1133         s = f2(s, r);                                                   \
1134         ieee754_csr_save.cx |= ieee754_csr.cx;                          \
1135         ieee754_csr_save.sx |= ieee754_csr.sx;                          \
1136         s = f3(s);                                                      \
1137         ieee754_csr.cx |= ieee754_csr_save.cx;                          \
1138         ieee754_csr.sx |= ieee754_csr_save.sx;                          \
1139         return s;                                                       \
1140 }
1141
1142 static union ieee754dp fpemu_dp_recip(union ieee754dp d)
1143 {
1144         return ieee754dp_div(ieee754dp_one(0), d);
1145 }
1146
1147 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
1148 {
1149         return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1150 }
1151
1152 static union ieee754sp fpemu_sp_recip(union ieee754sp s)
1153 {
1154         return ieee754sp_div(ieee754sp_one(0), s);
1155 }
1156
1157 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
1158 {
1159         return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1160 }
1161
1162 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1163 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1164 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1165 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
1166 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1167 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1168 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1169 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1170
1171 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1172         mips_instruction ir, void *__user *fault_addr)
1173 {
1174         unsigned rcsr = 0;      /* resulting csr */
1175
1176         MIPS_FPU_EMU_INC_STATS(cp1xops);
1177
1178         switch (MIPSInst_FMA_FFMT(ir)) {
1179         case s_fmt:{            /* 0 */
1180
1181                 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
1182                 union ieee754sp fd, fr, fs, ft;
1183                 u32 __user *va;
1184                 u32 val;
1185
1186                 switch (MIPSInst_FUNC(ir)) {
1187                 case lwxc1_op:
1188                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1189                                 xcp->regs[MIPSInst_FT(ir)]);
1190
1191                         MIPS_FPU_EMU_INC_STATS(loads);
1192                         if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1193                                 MIPS_FPU_EMU_INC_STATS(errors);
1194                                 *fault_addr = va;
1195                                 return SIGBUS;
1196                         }
1197                         if (__get_user(val, va)) {
1198                                 MIPS_FPU_EMU_INC_STATS(errors);
1199                                 *fault_addr = va;
1200                                 return SIGSEGV;
1201                         }
1202                         SITOREG(val, MIPSInst_FD(ir));
1203                         break;
1204
1205                 case swxc1_op:
1206                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1207                                 xcp->regs[MIPSInst_FT(ir)]);
1208
1209                         MIPS_FPU_EMU_INC_STATS(stores);
1210
1211                         SIFROMREG(val, MIPSInst_FS(ir));
1212                         if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1213                                 MIPS_FPU_EMU_INC_STATS(errors);
1214                                 *fault_addr = va;
1215                                 return SIGBUS;
1216                         }
1217                         if (put_user(val, va)) {
1218                                 MIPS_FPU_EMU_INC_STATS(errors);
1219                                 *fault_addr = va;
1220                                 return SIGSEGV;
1221                         }
1222                         break;
1223
1224                 case madd_s_op:
1225                         handler = fpemu_sp_madd;
1226                         goto scoptop;
1227                 case msub_s_op:
1228                         handler = fpemu_sp_msub;
1229                         goto scoptop;
1230                 case nmadd_s_op:
1231                         handler = fpemu_sp_nmadd;
1232                         goto scoptop;
1233                 case nmsub_s_op:
1234                         handler = fpemu_sp_nmsub;
1235                         goto scoptop;
1236
1237                       scoptop:
1238                         SPFROMREG(fr, MIPSInst_FR(ir));
1239                         SPFROMREG(fs, MIPSInst_FS(ir));
1240                         SPFROMREG(ft, MIPSInst_FT(ir));
1241                         fd = (*handler) (fr, fs, ft);
1242                         SPTOREG(fd, MIPSInst_FD(ir));
1243
1244                       copcsr:
1245                         if (ieee754_cxtest(IEEE754_INEXACT)) {
1246                                 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1247                                 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1248                         }
1249                         if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1250                                 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1251                                 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1252                         }
1253                         if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1254                                 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1255                                 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1256                         }
1257                         if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1258                                 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1259                                 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1260                         }
1261
1262                         ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1263                         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1264                                 /*printk ("SIGFPE: FPU csr = %08x\n",
1265                                    ctx->fcr31); */
1266                                 return SIGFPE;
1267                         }
1268
1269                         break;
1270
1271                 default:
1272                         return SIGILL;
1273                 }
1274                 break;
1275         }
1276
1277         case d_fmt:{            /* 1 */
1278                 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
1279                 union ieee754dp fd, fr, fs, ft;
1280                 u64 __user *va;
1281                 u64 val;
1282
1283                 switch (MIPSInst_FUNC(ir)) {
1284                 case ldxc1_op:
1285                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1286                                 xcp->regs[MIPSInst_FT(ir)]);
1287
1288                         MIPS_FPU_EMU_INC_STATS(loads);
1289                         if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
1290                                 MIPS_FPU_EMU_INC_STATS(errors);
1291                                 *fault_addr = va;
1292                                 return SIGBUS;
1293                         }
1294                         if (__get_user(val, va)) {
1295                                 MIPS_FPU_EMU_INC_STATS(errors);
1296                                 *fault_addr = va;
1297                                 return SIGSEGV;
1298                         }
1299                         DITOREG(val, MIPSInst_FD(ir));
1300                         break;
1301
1302                 case sdxc1_op:
1303                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1304                                 xcp->regs[MIPSInst_FT(ir)]);
1305
1306                         MIPS_FPU_EMU_INC_STATS(stores);
1307                         DIFROMREG(val, MIPSInst_FS(ir));
1308                         if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1309                                 MIPS_FPU_EMU_INC_STATS(errors);
1310                                 *fault_addr = va;
1311                                 return SIGBUS;
1312                         }
1313                         if (__put_user(val, va)) {
1314                                 MIPS_FPU_EMU_INC_STATS(errors);
1315                                 *fault_addr = va;
1316                                 return SIGSEGV;
1317                         }
1318                         break;
1319
1320                 case madd_d_op:
1321                         handler = fpemu_dp_madd;
1322                         goto dcoptop;
1323                 case msub_d_op:
1324                         handler = fpemu_dp_msub;
1325                         goto dcoptop;
1326                 case nmadd_d_op:
1327                         handler = fpemu_dp_nmadd;
1328                         goto dcoptop;
1329                 case nmsub_d_op:
1330                         handler = fpemu_dp_nmsub;
1331                         goto dcoptop;
1332
1333                       dcoptop:
1334                         DPFROMREG(fr, MIPSInst_FR(ir));
1335                         DPFROMREG(fs, MIPSInst_FS(ir));
1336                         DPFROMREG(ft, MIPSInst_FT(ir));
1337                         fd = (*handler) (fr, fs, ft);
1338                         DPTOREG(fd, MIPSInst_FD(ir));
1339                         goto copcsr;
1340
1341                 default:
1342                         return SIGILL;
1343                 }
1344                 break;
1345         }
1346
1347         case 0x3:
1348                 if (MIPSInst_FUNC(ir) != pfetch_op)
1349                         return SIGILL;
1350
1351                 /* ignore prefx operation */
1352                 break;
1353
1354         default:
1355                 return SIGILL;
1356         }
1357
1358         return 0;
1359 }
1360
1361
1362
1363 /*
1364  * Emulate a single COP1 arithmetic instruction.
1365  */
1366 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1367         mips_instruction ir)
1368 {
1369         int rfmt;               /* resulting format */
1370         unsigned rcsr = 0;      /* resulting csr */
1371         unsigned int oldrm;
1372         unsigned int cbit;
1373         unsigned cond;
1374         union {
1375                 union ieee754dp d;
1376                 union ieee754sp s;
1377                 int w;
1378                 s64 l;
1379         } rv;                   /* resulting value */
1380         u64 bits;
1381
1382         MIPS_FPU_EMU_INC_STATS(cp1ops);
1383         switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1384         case s_fmt: {           /* 0 */
1385                 union {
1386                         union ieee754sp(*b) (union ieee754sp, union ieee754sp);
1387                         union ieee754sp(*u) (union ieee754sp);
1388                 } handler;
1389                 union ieee754sp fs, ft;
1390
1391                 switch (MIPSInst_FUNC(ir)) {
1392                         /* binary ops */
1393                 case fadd_op:
1394                         handler.b = ieee754sp_add;
1395                         goto scopbop;
1396                 case fsub_op:
1397                         handler.b = ieee754sp_sub;
1398                         goto scopbop;
1399                 case fmul_op:
1400                         handler.b = ieee754sp_mul;
1401                         goto scopbop;
1402                 case fdiv_op:
1403                         handler.b = ieee754sp_div;
1404                         goto scopbop;
1405
1406                         /* unary  ops */
1407                 case fsqrt_op:
1408                         if (!cpu_has_mips_4_5_r)
1409                                 return SIGILL;
1410
1411                         handler.u = ieee754sp_sqrt;
1412                         goto scopuop;
1413
1414                 /*
1415                  * Note that on some MIPS IV implementations such as the
1416                  * R5000 and R8000 the FSQRT and FRECIP instructions do not
1417                  * achieve full IEEE-754 accuracy - however this emulator does.
1418                  */
1419                 case frsqrt_op:
1420                         if (!cpu_has_mips_4_5_r2)
1421                                 return SIGILL;
1422
1423                         handler.u = fpemu_sp_rsqrt;
1424                         goto scopuop;
1425
1426                 case frecip_op:
1427                         if (!cpu_has_mips_4_5_r2)
1428                                 return SIGILL;
1429
1430                         handler.u = fpemu_sp_recip;
1431                         goto scopuop;
1432
1433                 case fmovc_op:
1434                         if (!cpu_has_mips_4_5_r)
1435                                 return SIGILL;
1436
1437                         cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1438                         if (((ctx->fcr31 & cond) != 0) !=
1439                                 ((MIPSInst_FT(ir) & 1) != 0))
1440                                 return 0;
1441                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1442                         break;
1443
1444                 case fmovz_op:
1445                         if (!cpu_has_mips_4_5_r)
1446                                 return SIGILL;
1447
1448                         if (xcp->regs[MIPSInst_FT(ir)] != 0)
1449                                 return 0;
1450                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1451                         break;
1452
1453                 case fmovn_op:
1454                         if (!cpu_has_mips_4_5_r)
1455                                 return SIGILL;
1456
1457                         if (xcp->regs[MIPSInst_FT(ir)] == 0)
1458                                 return 0;
1459                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1460                         break;
1461
1462                 case fabs_op:
1463                         handler.u = ieee754sp_abs;
1464                         goto scopuop;
1465
1466                 case fneg_op:
1467                         handler.u = ieee754sp_neg;
1468                         goto scopuop;
1469
1470                 case fmov_op:
1471                         /* an easy one */
1472                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1473                         goto copcsr;
1474
1475                         /* binary op on handler */
1476 scopbop:
1477                         SPFROMREG(fs, MIPSInst_FS(ir));
1478                         SPFROMREG(ft, MIPSInst_FT(ir));
1479
1480                         rv.s = (*handler.b) (fs, ft);
1481                         goto copcsr;
1482 scopuop:
1483                         SPFROMREG(fs, MIPSInst_FS(ir));
1484                         rv.s = (*handler.u) (fs);
1485                         goto copcsr;
1486 copcsr:
1487                         if (ieee754_cxtest(IEEE754_INEXACT)) {
1488                                 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1489                                 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1490                         }
1491                         if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1492                                 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1493                                 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1494                         }
1495                         if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1496                                 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1497                                 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1498                         }
1499                         if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) {
1500                                 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv);
1501                                 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1502                         }
1503                         if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1504                                 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1505                                 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1506                         }
1507                         break;
1508
1509                         /* unary conv ops */
1510                 case fcvts_op:
1511                         return SIGILL;  /* not defined */
1512
1513                 case fcvtd_op:
1514                         SPFROMREG(fs, MIPSInst_FS(ir));
1515                         rv.d = ieee754dp_fsp(fs);
1516                         rfmt = d_fmt;
1517                         goto copcsr;
1518
1519                 case fcvtw_op:
1520                         SPFROMREG(fs, MIPSInst_FS(ir));
1521                         rv.w = ieee754sp_tint(fs);
1522                         rfmt = w_fmt;
1523                         goto copcsr;
1524
1525                 case fround_op:
1526                 case ftrunc_op:
1527                 case fceil_op:
1528                 case ffloor_op:
1529                         if (!cpu_has_mips_2_3_4_5 && !cpu_has_mips64)
1530                                 return SIGILL;
1531
1532                         oldrm = ieee754_csr.rm;
1533                         SPFROMREG(fs, MIPSInst_FS(ir));
1534                         ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1535                         rv.w = ieee754sp_tint(fs);
1536                         ieee754_csr.rm = oldrm;
1537                         rfmt = w_fmt;
1538                         goto copcsr;
1539
1540                 case fcvtl_op:
1541                         if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1542                                 return SIGILL;
1543
1544                         SPFROMREG(fs, MIPSInst_FS(ir));
1545                         rv.l = ieee754sp_tlong(fs);
1546                         rfmt = l_fmt;
1547                         goto copcsr;
1548
1549                 case froundl_op:
1550                 case ftruncl_op:
1551                 case fceill_op:
1552                 case ffloorl_op:
1553                         if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1554                                 return SIGILL;
1555
1556                         oldrm = ieee754_csr.rm;
1557                         SPFROMREG(fs, MIPSInst_FS(ir));
1558                         ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1559                         rv.l = ieee754sp_tlong(fs);
1560                         ieee754_csr.rm = oldrm;
1561                         rfmt = l_fmt;
1562                         goto copcsr;
1563
1564                 default:
1565                         if (MIPSInst_FUNC(ir) >= fcmp_op) {
1566                                 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1567                                 union ieee754sp fs, ft;
1568
1569                                 SPFROMREG(fs, MIPSInst_FS(ir));
1570                                 SPFROMREG(ft, MIPSInst_FT(ir));
1571                                 rv.w = ieee754sp_cmp(fs, ft,
1572                                         cmptab[cmpop & 0x7], cmpop & 0x8);
1573                                 rfmt = -1;
1574                                 if ((cmpop & 0x8) && ieee754_cxtest
1575                                         (IEEE754_INVALID_OPERATION))
1576                                         rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1577                                 else
1578                                         goto copcsr;
1579
1580                         } else
1581                                 return SIGILL;
1582                         break;
1583                 }
1584                 break;
1585         }
1586
1587         case d_fmt: {
1588                 union ieee754dp fs, ft;
1589                 union {
1590                         union ieee754dp(*b) (union ieee754dp, union ieee754dp);
1591                         union ieee754dp(*u) (union ieee754dp);
1592                 } handler;
1593
1594                 switch (MIPSInst_FUNC(ir)) {
1595                         /* binary ops */
1596                 case fadd_op:
1597                         handler.b = ieee754dp_add;
1598                         goto dcopbop;
1599                 case fsub_op:
1600                         handler.b = ieee754dp_sub;
1601                         goto dcopbop;
1602                 case fmul_op:
1603                         handler.b = ieee754dp_mul;
1604                         goto dcopbop;
1605                 case fdiv_op:
1606                         handler.b = ieee754dp_div;
1607                         goto dcopbop;
1608
1609                         /* unary  ops */
1610                 case fsqrt_op:
1611                         if (!cpu_has_mips_2_3_4_5_r)
1612                                 return SIGILL;
1613
1614                         handler.u = ieee754dp_sqrt;
1615                         goto dcopuop;
1616                 /*
1617                  * Note that on some MIPS IV implementations such as the
1618                  * R5000 and R8000 the FSQRT and FRECIP instructions do not
1619                  * achieve full IEEE-754 accuracy - however this emulator does.
1620                  */
1621                 case frsqrt_op:
1622                         if (!cpu_has_mips_4_5_r2)
1623                                 return SIGILL;
1624
1625                         handler.u = fpemu_dp_rsqrt;
1626                         goto dcopuop;
1627                 case frecip_op:
1628                         if (!cpu_has_mips_4_5_r2)
1629                                 return SIGILL;
1630
1631                         handler.u = fpemu_dp_recip;
1632                         goto dcopuop;
1633                 case fmovc_op:
1634                         if (!cpu_has_mips_4_5_r)
1635                                 return SIGILL;
1636
1637                         cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1638                         if (((ctx->fcr31 & cond) != 0) !=
1639                                 ((MIPSInst_FT(ir) & 1) != 0))
1640                                 return 0;
1641                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1642                         break;
1643                 case fmovz_op:
1644                         if (!cpu_has_mips_4_5_r)
1645                                 return SIGILL;
1646
1647                         if (xcp->regs[MIPSInst_FT(ir)] != 0)
1648                                 return 0;
1649                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1650                         break;
1651                 case fmovn_op:
1652                         if (!cpu_has_mips_4_5_r)
1653                                 return SIGILL;
1654
1655                         if (xcp->regs[MIPSInst_FT(ir)] == 0)
1656                                 return 0;
1657                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1658                         break;
1659                 case fabs_op:
1660                         handler.u = ieee754dp_abs;
1661                         goto dcopuop;
1662
1663                 case fneg_op:
1664                         handler.u = ieee754dp_neg;
1665                         goto dcopuop;
1666
1667                 case fmov_op:
1668                         /* an easy one */
1669                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1670                         goto copcsr;
1671
1672                         /* binary op on handler */
1673 dcopbop:
1674                         DPFROMREG(fs, MIPSInst_FS(ir));
1675                         DPFROMREG(ft, MIPSInst_FT(ir));
1676
1677                         rv.d = (*handler.b) (fs, ft);
1678                         goto copcsr;
1679 dcopuop:
1680                         DPFROMREG(fs, MIPSInst_FS(ir));
1681                         rv.d = (*handler.u) (fs);
1682                         goto copcsr;
1683
1684                 /*
1685                  * unary conv ops
1686                  */
1687                 case fcvts_op:
1688                         DPFROMREG(fs, MIPSInst_FS(ir));
1689                         rv.s = ieee754sp_fdp(fs);
1690                         rfmt = s_fmt;
1691                         goto copcsr;
1692
1693                 case fcvtd_op:
1694                         return SIGILL;  /* not defined */
1695
1696                 case fcvtw_op:
1697                         DPFROMREG(fs, MIPSInst_FS(ir));
1698                         rv.w = ieee754dp_tint(fs);      /* wrong */
1699                         rfmt = w_fmt;
1700                         goto copcsr;
1701
1702                 case fround_op:
1703                 case ftrunc_op:
1704                 case fceil_op:
1705                 case ffloor_op:
1706                         if (!cpu_has_mips_2_3_4_5_r)
1707                                 return SIGILL;
1708
1709                         oldrm = ieee754_csr.rm;
1710                         DPFROMREG(fs, MIPSInst_FS(ir));
1711                         ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1712                         rv.w = ieee754dp_tint(fs);
1713                         ieee754_csr.rm = oldrm;
1714                         rfmt = w_fmt;
1715                         goto copcsr;
1716
1717                 case fcvtl_op:
1718                         if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1719                                 return SIGILL;
1720
1721                         DPFROMREG(fs, MIPSInst_FS(ir));
1722                         rv.l = ieee754dp_tlong(fs);
1723                         rfmt = l_fmt;
1724                         goto copcsr;
1725
1726                 case froundl_op:
1727                 case ftruncl_op:
1728                 case fceill_op:
1729                 case ffloorl_op:
1730                         if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1731                                 return SIGILL;
1732
1733                         oldrm = ieee754_csr.rm;
1734                         DPFROMREG(fs, MIPSInst_FS(ir));
1735                         ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1736                         rv.l = ieee754dp_tlong(fs);
1737                         ieee754_csr.rm = oldrm;
1738                         rfmt = l_fmt;
1739                         goto copcsr;
1740
1741                 default:
1742                         if (MIPSInst_FUNC(ir) >= fcmp_op) {
1743                                 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1744                                 union ieee754dp fs, ft;
1745
1746                                 DPFROMREG(fs, MIPSInst_FS(ir));
1747                                 DPFROMREG(ft, MIPSInst_FT(ir));
1748                                 rv.w = ieee754dp_cmp(fs, ft,
1749                                         cmptab[cmpop & 0x7], cmpop & 0x8);
1750                                 rfmt = -1;
1751                                 if ((cmpop & 0x8)
1752                                         &&
1753                                         ieee754_cxtest
1754                                         (IEEE754_INVALID_OPERATION))
1755                                         rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1756                                 else
1757                                         goto copcsr;
1758
1759                         }
1760                         else {
1761                                 return SIGILL;
1762                         }
1763                         break;
1764                 }
1765                 break;
1766
1767         case w_fmt:
1768                 switch (MIPSInst_FUNC(ir)) {
1769                 case fcvts_op:
1770                         /* convert word to single precision real */
1771                         SPFROMREG(fs, MIPSInst_FS(ir));
1772                         rv.s = ieee754sp_fint(fs.bits);
1773                         rfmt = s_fmt;
1774                         goto copcsr;
1775                 case fcvtd_op:
1776                         /* convert word to double precision real */
1777                         SPFROMREG(fs, MIPSInst_FS(ir));
1778                         rv.d = ieee754dp_fint(fs.bits);
1779                         rfmt = d_fmt;
1780                         goto copcsr;
1781                 default:
1782                         return SIGILL;
1783                 }
1784                 break;
1785         }
1786
1787         case l_fmt:
1788
1789                 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1790                         return SIGILL;
1791
1792                 DIFROMREG(bits, MIPSInst_FS(ir));
1793
1794                 switch (MIPSInst_FUNC(ir)) {
1795                 case fcvts_op:
1796                         /* convert long to single precision real */
1797                         rv.s = ieee754sp_flong(bits);
1798                         rfmt = s_fmt;
1799                         goto copcsr;
1800                 case fcvtd_op:
1801                         /* convert long to double precision real */
1802                         rv.d = ieee754dp_flong(bits);
1803                         rfmt = d_fmt;
1804                         goto copcsr;
1805                 default:
1806                         return SIGILL;
1807                 }
1808                 break;
1809
1810         default:
1811                 return SIGILL;
1812         }
1813
1814         /*
1815          * Update the fpu CSR register for this operation.
1816          * If an exception is required, generate a tidy SIGFPE exception,
1817          * without updating the result register.
1818          * Note: cause exception bits do not accumulate, they are rewritten
1819          * for each op; only the flag/sticky bits accumulate.
1820          */
1821         ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1822         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1823                 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
1824                 return SIGFPE;
1825         }
1826
1827         /*
1828          * Now we can safely write the result back to the register file.
1829          */
1830         switch (rfmt) {
1831         case -1:
1832
1833                 if (cpu_has_mips_4_5_r)
1834                         cbit = fpucondbit[MIPSInst_FD(ir) >> 2];
1835                 else
1836                         cbit = FPU_CSR_COND;
1837                 if (rv.w)
1838                         ctx->fcr31 |= cbit;
1839                 else
1840                         ctx->fcr31 &= ~cbit;
1841                 break;
1842
1843         case d_fmt:
1844                 DPTOREG(rv.d, MIPSInst_FD(ir));
1845                 break;
1846         case s_fmt:
1847                 SPTOREG(rv.s, MIPSInst_FD(ir));
1848                 break;
1849         case w_fmt:
1850                 SITOREG(rv.w, MIPSInst_FD(ir));
1851                 break;
1852         case l_fmt:
1853                 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1854                         return SIGILL;
1855
1856                 DITOREG(rv.l, MIPSInst_FD(ir));
1857                 break;
1858         default:
1859                 return SIGILL;
1860         }
1861
1862         return 0;
1863 }
1864
1865 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1866         int has_fpu, void *__user *fault_addr)
1867 {
1868         unsigned long oldepc, prevepc;
1869         struct mm_decoded_insn dec_insn;
1870         u16 instr[4];
1871         u16 *instr_ptr;
1872         int sig = 0;
1873
1874         oldepc = xcp->cp0_epc;
1875         do {
1876                 prevepc = xcp->cp0_epc;
1877
1878                 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
1879                         /*
1880                          * Get next 2 microMIPS instructions and convert them
1881                          * into 32-bit instructions.
1882                          */
1883                         if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
1884                             (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
1885                             (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
1886                             (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
1887                                 MIPS_FPU_EMU_INC_STATS(errors);
1888                                 return SIGBUS;
1889                         }
1890                         instr_ptr = instr;
1891
1892                         /* Get first instruction. */
1893                         if (mm_insn_16bit(*instr_ptr)) {
1894                                 /* Duplicate the half-word. */
1895                                 dec_insn.insn = (*instr_ptr << 16) |
1896                                         (*instr_ptr);
1897                                 /* 16-bit instruction. */
1898                                 dec_insn.pc_inc = 2;
1899                                 instr_ptr += 1;
1900                         } else {
1901                                 dec_insn.insn = (*instr_ptr << 16) |
1902                                         *(instr_ptr+1);
1903                                 /* 32-bit instruction. */
1904                                 dec_insn.pc_inc = 4;
1905                                 instr_ptr += 2;
1906                         }
1907                         /* Get second instruction. */
1908                         if (mm_insn_16bit(*instr_ptr)) {
1909                                 /* Duplicate the half-word. */
1910                                 dec_insn.next_insn = (*instr_ptr << 16) |
1911                                         (*instr_ptr);
1912                                 /* 16-bit instruction. */
1913                                 dec_insn.next_pc_inc = 2;
1914                         } else {
1915                                 dec_insn.next_insn = (*instr_ptr << 16) |
1916                                         *(instr_ptr+1);
1917                                 /* 32-bit instruction. */
1918                                 dec_insn.next_pc_inc = 4;
1919                         }
1920                         dec_insn.micro_mips_mode = 1;
1921                 } else {
1922                         if ((get_user(dec_insn.insn,
1923                             (mips_instruction __user *) xcp->cp0_epc)) ||
1924                             (get_user(dec_insn.next_insn,
1925                             (mips_instruction __user *)(xcp->cp0_epc+4)))) {
1926                                 MIPS_FPU_EMU_INC_STATS(errors);
1927                                 return SIGBUS;
1928                         }
1929                         dec_insn.pc_inc = 4;
1930                         dec_insn.next_pc_inc = 4;
1931                         dec_insn.micro_mips_mode = 0;
1932                 }
1933
1934                 if ((dec_insn.insn == 0) ||
1935                    ((dec_insn.pc_inc == 2) &&
1936                    ((dec_insn.insn & 0xffff) == MM_NOP16)))
1937                         xcp->cp0_epc += dec_insn.pc_inc;        /* Skip NOPs */
1938                 else {
1939                         /*
1940                          * The 'ieee754_csr' is an alias of
1941                          * ctx->fcr31.  No need to copy ctx->fcr31 to
1942                          * ieee754_csr.  But ieee754_csr.rm is ieee
1943                          * library modes. (not mips rounding mode)
1944                          */
1945                         sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
1946                 }
1947
1948                 if (has_fpu)
1949                         break;
1950                 if (sig)
1951                         break;
1952
1953                 cond_resched();
1954         } while (xcp->cp0_epc > prevepc);
1955
1956         /* SIGILL indicates a non-fpu instruction */
1957         if (sig == SIGILL && xcp->cp0_epc != oldepc)
1958                 /* but if EPC has advanced, then ignore it */
1959                 sig = 0;
1960
1961         return sig;
1962 }