2 * Just-In-Time compiler for BPF filters on MIPS
4 * Copyright (c) 2014 Imagination Technologies Ltd.
5 * Author: Markos Chandras <markos.chandras@imgtec.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; version 2 of the License.
12 #include <linux/bitops.h>
13 #include <linux/compiler.h>
14 #include <linux/errno.h>
15 #include <linux/filter.h>
16 #include <linux/if_vlan.h>
17 #include <linux/kconfig.h>
18 #include <linux/moduleloader.h>
19 #include <linux/netdevice.h>
20 #include <linux/string.h>
21 #include <linux/slab.h>
22 #include <linux/types.h>
23 #include <asm/bitops.h>
24 #include <asm/cacheflush.h>
25 #include <asm/cpu-features.h>
32 * s0 1st scratch register
33 * s1 2nd scratch register
40 * On entry (*bpf_func)(*skb, *filter)
41 * a0 = MIPS_R_A0 = skb;
42 * a1 = MIPS_R_A1 = filter;
54 * saved reg 0 <-- r_sp
59 * <--------------------- len ------------------------>
60 * <--skb-len(r_skb_hl)-->< ----- skb->data_len ------>
61 * ----------------------------------------------------
63 * ----------------------------------------------------
66 #define RSIZE (sizeof(unsigned long))
67 #define ptr typeof(unsigned long)
69 /* ABI specific return values */
70 #ifdef CONFIG_32BIT /* O32 */
71 #ifdef CONFIG_CPU_LITTLE_ENDIAN
72 #define r_err MIPS_R_V1
73 #define r_val MIPS_R_V0
74 #else /* CONFIG_CPU_LITTLE_ENDIAN */
75 #define r_err MIPS_R_V0
76 #define r_val MIPS_R_V1
79 #define r_err MIPS_R_V0
80 #define r_val MIPS_R_V0
83 #define r_ret MIPS_R_V0
86 * Use 2 scratch registers to avoid pipeline interlocks.
87 * There is no overhead during epilogue and prologue since
88 * any of the $s0-$s6 registers will only be preserved if
89 * they are going to actually be used.
91 #define r_s0 MIPS_R_S0 /* scratch reg 1 */
92 #define r_s1 MIPS_R_S1 /* scratch reg 2 */
93 #define r_off MIPS_R_S2
96 #define r_skb MIPS_R_S5
98 #define r_tmp_imm MIPS_R_T6 /* No need to preserve this */
99 #define r_tmp MIPS_R_T7 /* No need to preserve this */
100 #define r_zero MIPS_R_ZERO
101 #define r_sp MIPS_R_SP
102 #define r_ra MIPS_R_RA
104 #define SCRATCH_OFF(k) (4 * (k))
107 #define SEEN_CALL (1 << BPF_MEMWORDS)
108 #define SEEN_SREG_SFT (BPF_MEMWORDS + 1)
109 #define SEEN_SREG_BASE (1 << SEEN_SREG_SFT)
110 #define SEEN_SREG(x) (SEEN_SREG_BASE << (x))
111 #define SEEN_S0 SEEN_SREG(0)
112 #define SEEN_S1 SEEN_SREG(1)
113 #define SEEN_OFF SEEN_SREG(2)
114 #define SEEN_A SEEN_SREG(3)
115 #define SEEN_X SEEN_SREG(4)
116 #define SEEN_SKB SEEN_SREG(5)
117 #define SEEN_MEM SEEN_SREG(6)
119 /* Arguments used by JIT */
120 #define ARGS_USED_BY_JIT 2 /* only applicable to 64-bit */
122 #define SBIT(x) (1 << (x)) /* Signed version of BIT() */
125 * struct jit_ctx - JIT context
126 * @skf: The sk_filter
127 * @prologue_bytes: Number of bytes for prologue
128 * @idx: Instruction index
130 * @offsets: Instruction offsets
131 * @target: Memory location for the compiled filter
134 const struct sk_filter *skf;
135 unsigned int prologue_bytes;
143 static inline int optimize_div(u32 *k)
145 /* power of 2 divides can be implemented with right shift */
146 if (!(*k & (*k-1))) {
154 /* Simply emit the instruction if the JIT memory space has been allocated */
155 #define emit_instr(ctx, func, ...) \
157 if ((ctx)->target != NULL) { \
158 u32 *p = &(ctx)->target[ctx->idx]; \
159 uasm_i_##func(&p, ##__VA_ARGS__); \
164 /* Determine if immediate is within the 16-bit signed range */
165 static inline bool is_range16(s32 imm)
167 return !(imm >= SBIT(15) || imm < -SBIT(15));
170 static inline void emit_addu(unsigned int dst, unsigned int src1,
171 unsigned int src2, struct jit_ctx *ctx)
173 emit_instr(ctx, addu, dst, src1, src2);
176 static inline void emit_nop(struct jit_ctx *ctx)
178 emit_instr(ctx, nop);
181 /* Load a u32 immediate to a register */
182 static inline void emit_load_imm(unsigned int dst, u32 imm, struct jit_ctx *ctx)
184 if (ctx->target != NULL) {
185 /* addiu can only handle s16 */
186 if (!is_range16(imm)) {
187 u32 *p = &ctx->target[ctx->idx];
188 uasm_i_lui(&p, r_tmp_imm, (s32)imm >> 16);
189 p = &ctx->target[ctx->idx + 1];
190 uasm_i_ori(&p, dst, r_tmp_imm, imm & 0xffff);
192 u32 *p = &ctx->target[ctx->idx];
193 uasm_i_addiu(&p, dst, r_zero, imm);
198 if (!is_range16(imm))
202 static inline void emit_or(unsigned int dst, unsigned int src1,
203 unsigned int src2, struct jit_ctx *ctx)
205 emit_instr(ctx, or, dst, src1, src2);
208 static inline void emit_ori(unsigned int dst, unsigned src, u32 imm,
211 if (imm >= BIT(16)) {
212 emit_load_imm(r_tmp, imm, ctx);
213 emit_or(dst, src, r_tmp, ctx);
215 emit_instr(ctx, ori, dst, src, imm);
220 static inline void emit_daddu(unsigned int dst, unsigned int src1,
221 unsigned int src2, struct jit_ctx *ctx)
223 emit_instr(ctx, daddu, dst, src1, src2);
226 static inline void emit_daddiu(unsigned int dst, unsigned int src,
227 int imm, struct jit_ctx *ctx)
230 * Only used for stack, so the imm is relatively small
231 * and it fits in 15-bits
233 emit_instr(ctx, daddiu, dst, src, imm);
236 static inline void emit_addiu(unsigned int dst, unsigned int src,
237 u32 imm, struct jit_ctx *ctx)
239 if (!is_range16(imm)) {
240 emit_load_imm(r_tmp, imm, ctx);
241 emit_addu(dst, r_tmp, src, ctx);
243 emit_instr(ctx, addiu, dst, src, imm);
247 static inline void emit_and(unsigned int dst, unsigned int src1,
248 unsigned int src2, struct jit_ctx *ctx)
250 emit_instr(ctx, and, dst, src1, src2);
253 static inline void emit_andi(unsigned int dst, unsigned int src,
254 u32 imm, struct jit_ctx *ctx)
256 /* If imm does not fit in u16 then load it to register */
257 if (imm >= BIT(16)) {
258 emit_load_imm(r_tmp, imm, ctx);
259 emit_and(dst, src, r_tmp, ctx);
261 emit_instr(ctx, andi, dst, src, imm);
265 static inline void emit_xor(unsigned int dst, unsigned int src1,
266 unsigned int src2, struct jit_ctx *ctx)
268 emit_instr(ctx, xor, dst, src1, src2);
271 static inline void emit_xori(ptr dst, ptr src, u32 imm, struct jit_ctx *ctx)
273 /* If imm does not fit in u16 then load it to register */
274 if (imm >= BIT(16)) {
275 emit_load_imm(r_tmp, imm, ctx);
276 emit_xor(dst, src, r_tmp, ctx);
278 emit_instr(ctx, xori, dst, src, imm);
282 static inline void emit_stack_offset(int offset, struct jit_ctx *ctx)
284 if (config_enabled(CONFIG_64BIT))
285 emit_instr(ctx, daddiu, r_sp, r_sp, offset);
287 emit_instr(ctx, addiu, r_sp, r_sp, offset);
291 static inline void emit_subu(unsigned int dst, unsigned int src1,
292 unsigned int src2, struct jit_ctx *ctx)
294 emit_instr(ctx, subu, dst, src1, src2);
297 static inline void emit_neg(unsigned int reg, struct jit_ctx *ctx)
299 emit_subu(reg, r_zero, reg, ctx);
302 static inline void emit_sllv(unsigned int dst, unsigned int src,
303 unsigned int sa, struct jit_ctx *ctx)
305 emit_instr(ctx, sllv, dst, src, sa);
308 static inline void emit_sll(unsigned int dst, unsigned int src,
309 unsigned int sa, struct jit_ctx *ctx)
311 /* sa is 5-bits long */
312 BUG_ON(sa >= BIT(5));
313 emit_instr(ctx, sll, dst, src, sa);
316 static inline void emit_srlv(unsigned int dst, unsigned int src,
317 unsigned int sa, struct jit_ctx *ctx)
319 emit_instr(ctx, srlv, dst, src, sa);
322 static inline void emit_srl(unsigned int dst, unsigned int src,
323 unsigned int sa, struct jit_ctx *ctx)
325 /* sa is 5-bits long */
326 BUG_ON(sa >= BIT(5));
327 emit_instr(ctx, srl, dst, src, sa);
330 static inline void emit_slt(unsigned int dst, unsigned int src1,
331 unsigned int src2, struct jit_ctx *ctx)
333 emit_instr(ctx, slt, dst, src1, src2);
336 static inline void emit_sltu(unsigned int dst, unsigned int src1,
337 unsigned int src2, struct jit_ctx *ctx)
339 emit_instr(ctx, sltu, dst, src1, src2);
342 static inline void emit_sltiu(unsigned dst, unsigned int src,
343 unsigned int imm, struct jit_ctx *ctx)
345 /* 16 bit immediate */
346 if (!is_range16((s32)imm)) {
347 emit_load_imm(r_tmp, imm, ctx);
348 emit_sltu(dst, src, r_tmp, ctx);
350 emit_instr(ctx, sltiu, dst, src, imm);
355 /* Store register on the stack */
356 static inline void emit_store_stack_reg(ptr reg, ptr base,
360 if (config_enabled(CONFIG_64BIT))
361 emit_instr(ctx, sd, reg, offset, base);
363 emit_instr(ctx, sw, reg, offset, base);
366 static inline void emit_store(ptr reg, ptr base, unsigned int offset,
369 emit_instr(ctx, sw, reg, offset, base);
372 static inline void emit_load_stack_reg(ptr reg, ptr base,
376 if (config_enabled(CONFIG_64BIT))
377 emit_instr(ctx, ld, reg, offset, base);
379 emit_instr(ctx, lw, reg, offset, base);
382 static inline void emit_load(unsigned int reg, unsigned int base,
383 unsigned int offset, struct jit_ctx *ctx)
385 emit_instr(ctx, lw, reg, offset, base);
388 static inline void emit_load_byte(unsigned int reg, unsigned int base,
389 unsigned int offset, struct jit_ctx *ctx)
391 emit_instr(ctx, lb, reg, offset, base);
394 static inline void emit_half_load(unsigned int reg, unsigned int base,
395 unsigned int offset, struct jit_ctx *ctx)
397 emit_instr(ctx, lh, reg, offset, base);
400 static inline void emit_mul(unsigned int dst, unsigned int src1,
401 unsigned int src2, struct jit_ctx *ctx)
403 emit_instr(ctx, mul, dst, src1, src2);
406 static inline void emit_div(unsigned int dst, unsigned int src,
409 if (ctx->target != NULL) {
410 u32 *p = &ctx->target[ctx->idx];
411 uasm_i_divu(&p, dst, src);
412 p = &ctx->target[ctx->idx + 1];
413 uasm_i_mflo(&p, dst);
415 ctx->idx += 2; /* 2 insts */
418 static inline void emit_mod(unsigned int dst, unsigned int src,
421 if (ctx->target != NULL) {
422 u32 *p = &ctx->target[ctx->idx];
423 uasm_i_divu(&p, dst, src);
424 p = &ctx->target[ctx->idx + 1];
425 uasm_i_mflo(&p, dst);
427 ctx->idx += 2; /* 2 insts */
430 static inline void emit_dsll(unsigned int dst, unsigned int src,
431 unsigned int sa, struct jit_ctx *ctx)
433 emit_instr(ctx, dsll, dst, src, sa);
436 static inline void emit_dsrl32(unsigned int dst, unsigned int src,
437 unsigned int sa, struct jit_ctx *ctx)
439 emit_instr(ctx, dsrl32, dst, src, sa);
442 static inline void emit_wsbh(unsigned int dst, unsigned int src,
445 emit_instr(ctx, wsbh, dst, src);
448 /* load a function pointer to register */
449 static inline void emit_load_func(unsigned int reg, ptr imm,
452 if (config_enabled(CONFIG_64BIT)) {
453 /* At this point imm is always 64-bit */
454 emit_load_imm(r_tmp, (u64)imm >> 32, ctx);
455 emit_dsll(r_tmp_imm, r_tmp, 16, ctx); /* left shift by 16 */
456 emit_ori(r_tmp, r_tmp_imm, (imm >> 16) & 0xffff, ctx);
457 emit_dsll(r_tmp_imm, r_tmp, 16, ctx); /* left shift by 16 */
458 emit_ori(reg, r_tmp_imm, imm & 0xffff, ctx);
460 emit_load_imm(reg, imm, ctx);
464 /* Move to real MIPS register */
465 static inline void emit_reg_move(ptr dst, ptr src, struct jit_ctx *ctx)
467 if (config_enabled(CONFIG_64BIT))
468 emit_daddu(dst, src, r_zero, ctx);
470 emit_addu(dst, src, r_zero, ctx);
473 /* Move to JIT (32-bit) register */
474 static inline void emit_jit_reg_move(ptr dst, ptr src, struct jit_ctx *ctx)
476 emit_addu(dst, src, r_zero, ctx);
479 /* Compute the immediate value for PC-relative branches. */
480 static inline u32 b_imm(unsigned int tgt, struct jit_ctx *ctx)
482 if (ctx->target == NULL)
486 * We want a pc-relative branch. We only do forward branches
487 * so tgt is always after pc. tgt is the instruction offset
488 * we want to jump to.
491 * I: target_offset <- sign_extend(offset)
492 * I+1: PC += target_offset (delay slot)
494 * ctx->idx currently points to the branch instruction
495 * but the offset is added to the delay slot so we need
498 return ctx->offsets[tgt] -
499 (ctx->idx * 4 - ctx->prologue_bytes) - 4;
502 static inline void emit_bcond(int cond, unsigned int reg1, unsigned int reg2,
503 unsigned int imm, struct jit_ctx *ctx)
505 if (ctx->target != NULL) {
506 u32 *p = &ctx->target[ctx->idx];
510 uasm_i_beq(&p, reg1, reg2, imm);
513 uasm_i_bne(&p, reg1, reg2, imm);
519 pr_warn("%s: Unhandled branch conditional: %d\n",
526 static inline void emit_b(unsigned int imm, struct jit_ctx *ctx)
528 emit_bcond(MIPS_COND_ALL, r_zero, r_zero, imm, ctx);
531 static inline void emit_jalr(unsigned int link, unsigned int reg,
534 emit_instr(ctx, jalr, link, reg);
537 static inline void emit_jr(unsigned int reg, struct jit_ctx *ctx)
539 emit_instr(ctx, jr, reg);
542 static inline u16 align_sp(unsigned int num)
544 /* Double word alignment for 32-bit, quadword for 64-bit */
545 unsigned int align = config_enabled(CONFIG_64BIT) ? 16 : 8;
546 num = (num + (align - 1)) & -align;
550 static bool is_load_to_a(u16 inst)
553 case BPF_LD | BPF_W | BPF_LEN:
554 case BPF_LD | BPF_W | BPF_ABS:
555 case BPF_LD | BPF_H | BPF_ABS:
556 case BPF_LD | BPF_B | BPF_ABS:
563 static void save_bpf_jit_regs(struct jit_ctx *ctx, unsigned offset)
565 int i = 0, real_off = 0;
566 u32 sflags, tmp_flags;
568 /* Adjust the stack pointer */
569 emit_stack_offset(-align_sp(offset), ctx);
571 if (ctx->flags & SEEN_CALL) {
572 /* Argument save area */
573 if (config_enabled(CONFIG_64BIT))
574 /* Bottom of current frame */
575 real_off = align_sp(offset) - RSIZE;
577 /* Top of previous frame */
578 real_off = align_sp(offset) + RSIZE;
579 emit_store_stack_reg(MIPS_R_A0, r_sp, real_off, ctx);
580 emit_store_stack_reg(MIPS_R_A1, r_sp, real_off + RSIZE, ctx);
585 tmp_flags = sflags = ctx->flags >> SEEN_SREG_SFT;
586 /* sflags is essentially a bitmap */
588 if ((sflags >> i) & 0x1) {
589 emit_store_stack_reg(MIPS_R_S0 + i, r_sp, real_off,
597 /* save return address */
598 if (ctx->flags & SEEN_CALL) {
599 emit_store_stack_reg(r_ra, r_sp, real_off, ctx);
603 /* Setup r_M leaving the alignment gap if necessary */
604 if (ctx->flags & SEEN_MEM) {
605 if (real_off % (RSIZE * 2))
607 emit_addiu(r_M, r_sp, real_off, ctx);
611 static void restore_bpf_jit_regs(struct jit_ctx *ctx,
615 u32 sflags, tmp_flags;
617 if (ctx->flags & SEEN_CALL) {
618 if (config_enabled(CONFIG_64BIT))
619 /* Bottom of current frame */
620 real_off = align_sp(offset) - RSIZE;
622 /* Top of previous frame */
623 real_off = align_sp(offset) + RSIZE;
624 emit_load_stack_reg(MIPS_R_A0, r_sp, real_off, ctx);
625 emit_load_stack_reg(MIPS_R_A1, r_sp, real_off + RSIZE, ctx);
630 tmp_flags = sflags = ctx->flags >> SEEN_SREG_SFT;
631 /* sflags is a bitmap */
634 if ((sflags >> i) & 0x1) {
635 emit_load_stack_reg(MIPS_R_S0 + i, r_sp, real_off,
643 /* restore return address */
644 if (ctx->flags & SEEN_CALL)
645 emit_load_stack_reg(r_ra, r_sp, real_off, ctx);
647 /* Restore the sp and discard the scrach memory */
648 emit_stack_offset(align_sp(offset), ctx);
651 static unsigned int get_stack_depth(struct jit_ctx *ctx)
656 /* How may s* regs do we need to preserved? */
657 sp_off += hweight32(ctx->flags >> SEEN_SREG_SFT) * RSIZE;
659 if (ctx->flags & SEEN_MEM)
660 sp_off += 4 * BPF_MEMWORDS; /* BPF_MEMWORDS are 32-bit */
662 if (ctx->flags & SEEN_CALL)
664 * The JIT code make calls to external functions using 2
665 * arguments. Therefore, for o32 we don't need to allocate
666 * space because we don't care if the argumetns are lost
667 * across calls. We do need however to preserve incoming
668 * arguments but the space is already allocated for us by
669 * the caller. On the other hand, for n64, we need to allocate
670 * this space ourselves. We need to preserve $ra as well.
672 sp_off += config_enabled(CONFIG_64BIT) ?
673 (ARGS_USED_BY_JIT + 1) * RSIZE : RSIZE;
676 * Subtract the bytes for the last registers since we only care about
677 * the location on the stack pointer.
679 return sp_off - RSIZE;
682 static void build_prologue(struct jit_ctx *ctx)
684 u16 first_inst = ctx->skf->insns[0].code;
687 /* Calculate the total offset for the stack pointer */
688 sp_off = get_stack_depth(ctx);
689 save_bpf_jit_regs(ctx, sp_off);
691 if (ctx->flags & SEEN_SKB)
692 emit_reg_move(r_skb, MIPS_R_A0, ctx);
694 if (ctx->flags & SEEN_X)
695 emit_jit_reg_move(r_X, r_zero, ctx);
697 /* Do not leak kernel data to userspace */
698 if ((first_inst != (BPF_RET | BPF_K)) && !(is_load_to_a(first_inst)))
699 emit_jit_reg_move(r_A, r_zero, ctx);
702 static void build_epilogue(struct jit_ctx *ctx)
706 /* Calculate the total offset for the stack pointer */
708 sp_off = get_stack_depth(ctx);
709 restore_bpf_jit_regs(ctx, sp_off);
716 static u64 jit_get_skb_b(struct sk_buff *skb, unsigned offset)
721 err = skb_copy_bits(skb, offset, &ret, 1);
723 return (u64)err << 32 | ret;
726 static u64 jit_get_skb_h(struct sk_buff *skb, unsigned offset)
731 err = skb_copy_bits(skb, offset, &ret, 2);
733 return (u64)err << 32 | ntohs(ret);
736 static u64 jit_get_skb_w(struct sk_buff *skb, unsigned offset)
741 err = skb_copy_bits(skb, offset, &ret, 4);
743 return (u64)err << 32 | ntohl(ret);
746 #define PKT_TYPE_MAX 7
747 static int pkt_type_offset(void)
749 struct sk_buff skb_probe = {
752 char *ct = (char *)&skb_probe;
755 for (off = 0; off < sizeof(struct sk_buff); off++) {
756 if (ct[off] == PKT_TYPE_MAX)
759 pr_err_once("Please fix pkt_type_offset(), as pkt_type couldn't be found\n");
763 static int build_body(struct jit_ctx *ctx)
765 void *load_func[] = {jit_get_skb_b, jit_get_skb_h, jit_get_skb_w};
766 const struct sk_filter *prog = ctx->skf;
767 const struct sock_filter *inst;
768 unsigned int i, off, load_order, condt;
769 u32 k, b_off __maybe_unused;
771 for (i = 0; i < prog->len; i++) {
774 inst = &(prog->insns[i]);
775 pr_debug("%s: code->0x%02x, jt->0x%x, jf->0x%x, k->0x%x\n",
776 __func__, inst->code, inst->jt, inst->jf, inst->k);
778 code = bpf_anc_helper(inst);
780 if (ctx->target == NULL)
781 ctx->offsets[i] = ctx->idx * 4;
784 case BPF_LD | BPF_IMM:
785 /* A <- k ==> li r_A, k */
786 ctx->flags |= SEEN_A;
787 emit_load_imm(r_A, k, ctx);
789 case BPF_LD | BPF_W | BPF_LEN:
790 BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, len) != 4);
791 /* A <- len ==> lw r_A, offset(skb) */
792 ctx->flags |= SEEN_SKB | SEEN_A;
793 off = offsetof(struct sk_buff, len);
794 emit_load(r_A, r_skb, off, ctx);
796 case BPF_LD | BPF_MEM:
797 /* A <- M[k] ==> lw r_A, offset(M) */
798 ctx->flags |= SEEN_MEM | SEEN_A;
799 emit_load(r_A, r_M, SCRATCH_OFF(k), ctx);
801 case BPF_LD | BPF_W | BPF_ABS:
805 case BPF_LD | BPF_H | BPF_ABS:
809 case BPF_LD | BPF_B | BPF_ABS:
813 /* the interpreter will deal with the negative K */
817 emit_load_imm(r_off, k, ctx);
820 * We may got here from the indirect loads so
821 * return if offset is negative.
823 emit_slt(r_s0, r_off, r_zero, ctx);
824 emit_bcond(MIPS_COND_NE, r_s0, r_zero,
825 b_imm(prog->len, ctx), ctx);
826 emit_reg_move(r_ret, r_zero, ctx);
828 ctx->flags |= SEEN_CALL | SEEN_OFF | SEEN_S0 |
831 emit_load_func(r_s0, (ptr)load_func[load_order],
833 emit_reg_move(MIPS_R_A0, r_skb, ctx);
834 emit_jalr(MIPS_R_RA, r_s0, ctx);
835 /* Load second argument to delay slot */
836 emit_reg_move(MIPS_R_A1, r_off, ctx);
837 /* Check the error value */
838 if (config_enabled(CONFIG_64BIT)) {
839 /* Get error code from the top 32-bits */
840 emit_dsrl32(r_s0, r_val, 0, ctx);
841 /* Branch to 3 instructions ahead */
842 emit_bcond(MIPS_COND_NE, r_s0, r_zero, 3 << 2,
845 /* Branch to 3 instructions ahead */
846 emit_bcond(MIPS_COND_NE, r_err, r_zero, 3 << 2,
851 emit_b(b_imm(i + 1, ctx), ctx);
852 emit_jit_reg_move(r_A, r_val, ctx);
853 /* Return with error */
854 emit_b(b_imm(prog->len, ctx), ctx);
855 emit_reg_move(r_ret, r_zero, ctx);
857 case BPF_LD | BPF_W | BPF_IND:
858 /* A <- P[X + k:4] */
861 case BPF_LD | BPF_H | BPF_IND:
862 /* A <- P[X + k:2] */
865 case BPF_LD | BPF_B | BPF_IND:
866 /* A <- P[X + k:1] */
869 ctx->flags |= SEEN_OFF | SEEN_X;
870 emit_addiu(r_off, r_X, k, ctx);
872 case BPF_LDX | BPF_IMM:
874 ctx->flags |= SEEN_X;
875 emit_load_imm(r_X, k, ctx);
877 case BPF_LDX | BPF_MEM:
879 ctx->flags |= SEEN_X | SEEN_MEM;
880 emit_load(r_X, r_M, SCRATCH_OFF(k), ctx);
882 case BPF_LDX | BPF_W | BPF_LEN:
884 ctx->flags |= SEEN_X | SEEN_SKB;
885 off = offsetof(struct sk_buff, len);
886 emit_load(r_X, r_skb, off, ctx);
888 case BPF_LDX | BPF_B | BPF_MSH:
889 /* the interpreter will deal with the negative K */
893 /* X <- 4 * (P[k:1] & 0xf) */
894 ctx->flags |= SEEN_X | SEEN_CALL | SEEN_S0 | SEEN_SKB;
895 /* Load offset to a1 */
896 emit_load_func(r_s0, (ptr)jit_get_skb_b, ctx);
898 * This may emit two instructions so it may not fit
899 * in the delay slot. So use a0 in the delay slot.
901 emit_load_imm(MIPS_R_A1, k, ctx);
902 emit_jalr(MIPS_R_RA, r_s0, ctx);
903 emit_reg_move(MIPS_R_A0, r_skb, ctx); /* delay slot */
904 /* Check the error value */
905 if (config_enabled(CONFIG_64BIT)) {
906 /* Top 32-bits of $v0 on 64-bit */
907 emit_dsrl32(r_s0, r_val, 0, ctx);
908 emit_bcond(MIPS_COND_NE, r_s0, r_zero,
911 emit_bcond(MIPS_COND_NE, r_err, r_zero,
914 /* No need for delay slot */
916 /* X <- P[1:K] & 0xf */
917 emit_andi(r_X, r_val, 0xf, ctx);
919 emit_b(b_imm(i + 1, ctx), ctx);
920 emit_sll(r_X, r_X, 2, ctx); /* delay slot */
921 /* Return with error */
922 emit_b(b_imm(prog->len, ctx), ctx);
923 emit_load_imm(r_ret, 0, ctx); /* delay slot */
927 ctx->flags |= SEEN_MEM | SEEN_A;
928 emit_store(r_A, r_M, SCRATCH_OFF(k), ctx);
932 ctx->flags |= SEEN_MEM | SEEN_X;
933 emit_store(r_X, r_M, SCRATCH_OFF(k), ctx);
935 case BPF_ALU | BPF_ADD | BPF_K:
937 ctx->flags |= SEEN_A;
938 emit_addiu(r_A, r_A, k, ctx);
940 case BPF_ALU | BPF_ADD | BPF_X:
942 ctx->flags |= SEEN_A | SEEN_X;
943 emit_addu(r_A, r_A, r_X, ctx);
945 case BPF_ALU | BPF_SUB | BPF_K:
947 ctx->flags |= SEEN_A;
948 emit_addiu(r_A, r_A, -k, ctx);
950 case BPF_ALU | BPF_SUB | BPF_X:
952 ctx->flags |= SEEN_A | SEEN_X;
953 emit_subu(r_A, r_A, r_X, ctx);
955 case BPF_ALU | BPF_MUL | BPF_K:
957 /* Load K to scratch register before MUL */
958 ctx->flags |= SEEN_A | SEEN_S0;
959 emit_load_imm(r_s0, k, ctx);
960 emit_mul(r_A, r_A, r_s0, ctx);
962 case BPF_ALU | BPF_MUL | BPF_X:
964 ctx->flags |= SEEN_A | SEEN_X;
965 emit_mul(r_A, r_A, r_X, ctx);
967 case BPF_ALU | BPF_DIV | BPF_K:
971 if (optimize_div(&k)) {
972 ctx->flags |= SEEN_A;
973 emit_srl(r_A, r_A, k, ctx);
976 ctx->flags |= SEEN_A | SEEN_S0;
977 emit_load_imm(r_s0, k, ctx);
978 emit_div(r_A, r_s0, ctx);
980 case BPF_ALU | BPF_MOD | BPF_K:
982 if (k == 1 || optimize_div(&k)) {
983 ctx->flags |= SEEN_A;
984 emit_jit_reg_move(r_A, r_zero, ctx);
986 ctx->flags |= SEEN_A | SEEN_S0;
987 emit_load_imm(r_s0, k, ctx);
988 emit_mod(r_A, r_s0, ctx);
991 case BPF_ALU | BPF_DIV | BPF_X:
993 ctx->flags |= SEEN_X | SEEN_A;
994 /* Check if r_X is zero */
995 emit_bcond(MIPS_COND_EQ, r_X, r_zero,
996 b_imm(prog->len, ctx), ctx);
997 emit_load_imm(r_val, 0, ctx); /* delay slot */
998 emit_div(r_A, r_X, ctx);
1000 case BPF_ALU | BPF_MOD | BPF_X:
1002 ctx->flags |= SEEN_X | SEEN_A;
1003 /* Check if r_X is zero */
1004 emit_bcond(MIPS_COND_EQ, r_X, r_zero,
1005 b_imm(prog->len, ctx), ctx);
1006 emit_load_imm(r_val, 0, ctx); /* delay slot */
1007 emit_mod(r_A, r_X, ctx);
1009 case BPF_ALU | BPF_OR | BPF_K:
1011 ctx->flags |= SEEN_A;
1012 emit_ori(r_A, r_A, k, ctx);
1014 case BPF_ALU | BPF_OR | BPF_X:
1016 ctx->flags |= SEEN_A;
1017 emit_ori(r_A, r_A, r_X, ctx);
1019 case BPF_ALU | BPF_XOR | BPF_K:
1021 ctx->flags |= SEEN_A;
1022 emit_xori(r_A, r_A, k, ctx);
1024 case BPF_ANC | SKF_AD_ALU_XOR_X:
1025 case BPF_ALU | BPF_XOR | BPF_X:
1027 ctx->flags |= SEEN_A;
1028 emit_xor(r_A, r_A, r_X, ctx);
1030 case BPF_ALU | BPF_AND | BPF_K:
1032 ctx->flags |= SEEN_A;
1033 emit_andi(r_A, r_A, k, ctx);
1035 case BPF_ALU | BPF_AND | BPF_X:
1037 ctx->flags |= SEEN_A | SEEN_X;
1038 emit_and(r_A, r_A, r_X, ctx);
1040 case BPF_ALU | BPF_LSH | BPF_K:
1042 ctx->flags |= SEEN_A;
1043 emit_sll(r_A, r_A, k, ctx);
1045 case BPF_ALU | BPF_LSH | BPF_X:
1047 ctx->flags |= SEEN_A | SEEN_X;
1048 emit_sllv(r_A, r_A, r_X, ctx);
1050 case BPF_ALU | BPF_RSH | BPF_K:
1052 ctx->flags |= SEEN_A;
1053 emit_srl(r_A, r_A, k, ctx);
1055 case BPF_ALU | BPF_RSH | BPF_X:
1056 ctx->flags |= SEEN_A | SEEN_X;
1057 emit_srlv(r_A, r_A, r_X, ctx);
1059 case BPF_ALU | BPF_NEG:
1061 ctx->flags |= SEEN_A;
1064 case BPF_JMP | BPF_JA:
1066 emit_b(b_imm(i + k + 1, ctx), ctx);
1069 case BPF_JMP | BPF_JEQ | BPF_K:
1070 /* pc += ( A == K ) ? pc->jt : pc->jf */
1071 condt = MIPS_COND_EQ | MIPS_COND_K;
1073 case BPF_JMP | BPF_JEQ | BPF_X:
1074 ctx->flags |= SEEN_X;
1075 /* pc += ( A == X ) ? pc->jt : pc->jf */
1076 condt = MIPS_COND_EQ | MIPS_COND_X;
1078 case BPF_JMP | BPF_JGE | BPF_K:
1079 /* pc += ( A >= K ) ? pc->jt : pc->jf */
1080 condt = MIPS_COND_GE | MIPS_COND_K;
1082 case BPF_JMP | BPF_JGE | BPF_X:
1083 ctx->flags |= SEEN_X;
1084 /* pc += ( A >= X ) ? pc->jt : pc->jf */
1085 condt = MIPS_COND_GE | MIPS_COND_X;
1087 case BPF_JMP | BPF_JGT | BPF_K:
1088 /* pc += ( A > K ) ? pc->jt : pc->jf */
1089 condt = MIPS_COND_GT | MIPS_COND_K;
1091 case BPF_JMP | BPF_JGT | BPF_X:
1092 ctx->flags |= SEEN_X;
1093 /* pc += ( A > X ) ? pc->jt : pc->jf */
1094 condt = MIPS_COND_GT | MIPS_COND_X;
1096 /* Greater or Equal */
1097 if ((condt & MIPS_COND_GE) ||
1098 (condt & MIPS_COND_GT)) {
1099 if (condt & MIPS_COND_K) { /* K */
1100 ctx->flags |= SEEN_S0 | SEEN_A;
1101 emit_sltiu(r_s0, r_A, k, ctx);
1103 ctx->flags |= SEEN_S0 | SEEN_A |
1105 emit_sltu(r_s0, r_A, r_X, ctx);
1107 /* A < (K|X) ? r_scrach = 1 */
1108 b_off = b_imm(i + inst->jf + 1, ctx);
1109 emit_bcond(MIPS_COND_NE, r_s0, r_zero, b_off,
1112 /* A > (K|X) ? scratch = 0 */
1113 if (condt & MIPS_COND_GT) {
1114 /* Checking for equality */
1115 ctx->flags |= SEEN_S0 | SEEN_A | SEEN_X;
1116 if (condt & MIPS_COND_K)
1117 emit_load_imm(r_s0, k, ctx);
1119 emit_jit_reg_move(r_s0, r_X,
1121 b_off = b_imm(i + inst->jf + 1, ctx);
1122 emit_bcond(MIPS_COND_EQ, r_A, r_s0,
1125 /* Finally, A > K|X */
1126 b_off = b_imm(i + inst->jt + 1, ctx);
1130 /* A >= (K|X) so jump */
1131 b_off = b_imm(i + inst->jt + 1, ctx);
1137 if (condt & MIPS_COND_K) { /* K */
1138 ctx->flags |= SEEN_S0 | SEEN_A;
1139 emit_load_imm(r_s0, k, ctx);
1141 b_off = b_imm(i + inst->jt + 1, ctx);
1142 emit_bcond(MIPS_COND_EQ, r_A, r_s0,
1146 b_off = b_imm(i + inst->jf + 1,
1148 emit_bcond(MIPS_COND_NE, r_A, r_s0,
1153 ctx->flags |= SEEN_A | SEEN_X;
1154 b_off = b_imm(i + inst->jt + 1,
1156 emit_bcond(MIPS_COND_EQ, r_A, r_X,
1160 b_off = b_imm(i + inst->jf + 1, ctx);
1161 emit_bcond(MIPS_COND_NE, r_A, r_X,
1167 case BPF_JMP | BPF_JSET | BPF_K:
1168 ctx->flags |= SEEN_S0 | SEEN_S1 | SEEN_A;
1169 /* pc += (A & K) ? pc -> jt : pc -> jf */
1170 emit_load_imm(r_s1, k, ctx);
1171 emit_and(r_s0, r_A, r_s1, ctx);
1173 b_off = b_imm(i + inst->jt + 1, ctx);
1174 emit_bcond(MIPS_COND_NE, r_s0, r_zero, b_off, ctx);
1177 b_off = b_imm(i + inst->jf + 1, ctx);
1181 case BPF_JMP | BPF_JSET | BPF_X:
1182 ctx->flags |= SEEN_S0 | SEEN_X | SEEN_A;
1183 /* pc += (A & X) ? pc -> jt : pc -> jf */
1184 emit_and(r_s0, r_A, r_X, ctx);
1186 b_off = b_imm(i + inst->jt + 1, ctx);
1187 emit_bcond(MIPS_COND_NE, r_s0, r_zero, b_off, ctx);
1190 b_off = b_imm(i + inst->jf + 1, ctx);
1194 case BPF_RET | BPF_A:
1195 ctx->flags |= SEEN_A;
1196 if (i != prog->len - 1)
1198 * If this is not the last instruction
1199 * then jump to the epilogue
1201 emit_b(b_imm(prog->len, ctx), ctx);
1202 emit_reg_move(r_ret, r_A, ctx); /* delay slot */
1204 case BPF_RET | BPF_K:
1206 * It can emit two instructions so it does not fit on
1209 emit_load_imm(r_ret, k, ctx);
1210 if (i != prog->len - 1) {
1212 * If this is not the last instruction
1213 * then jump to the epilogue
1215 emit_b(b_imm(prog->len, ctx), ctx);
1219 case BPF_MISC | BPF_TAX:
1221 ctx->flags |= SEEN_X | SEEN_A;
1222 emit_jit_reg_move(r_X, r_A, ctx);
1224 case BPF_MISC | BPF_TXA:
1226 ctx->flags |= SEEN_A | SEEN_X;
1227 emit_jit_reg_move(r_A, r_X, ctx);
1230 case BPF_ANC | SKF_AD_PROTOCOL:
1231 /* A = ntohs(skb->protocol */
1232 ctx->flags |= SEEN_SKB | SEEN_OFF | SEEN_A;
1233 BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff,
1235 off = offsetof(struct sk_buff, protocol);
1236 emit_half_load(r_A, r_skb, off, ctx);
1237 #ifdef CONFIG_CPU_LITTLE_ENDIAN
1238 /* This needs little endian fixup */
1239 if (cpu_has_mips_r2) {
1240 /* R2 and later have the wsbh instruction */
1241 emit_wsbh(r_A, r_A, ctx);
1243 /* Get first byte */
1244 emit_andi(r_tmp_imm, r_A, 0xff, ctx);
1246 emit_sll(r_tmp, r_tmp_imm, 8, ctx);
1247 /* Get second byte */
1248 emit_srl(r_tmp_imm, r_A, 8, ctx);
1249 emit_andi(r_tmp_imm, r_tmp_imm, 0xff, ctx);
1250 /* Put everyting together in r_A */
1251 emit_or(r_A, r_tmp, r_tmp_imm, ctx);
1255 case BPF_ANC | SKF_AD_CPU:
1256 ctx->flags |= SEEN_A | SEEN_OFF;
1257 /* A = current_thread_info()->cpu */
1258 BUILD_BUG_ON(FIELD_SIZEOF(struct thread_info,
1260 off = offsetof(struct thread_info, cpu);
1261 /* $28/gp points to the thread_info struct */
1262 emit_load(r_A, 28, off, ctx);
1264 case BPF_ANC | SKF_AD_IFINDEX:
1265 /* A = skb->dev->ifindex */
1266 ctx->flags |= SEEN_SKB | SEEN_A | SEEN_S0;
1267 off = offsetof(struct sk_buff, dev);
1268 emit_load(r_s0, r_skb, off, ctx);
1269 /* error (0) in the delay slot */
1270 emit_bcond(MIPS_COND_EQ, r_s0, r_zero,
1271 b_imm(prog->len, ctx), ctx);
1272 emit_reg_move(r_ret, r_zero, ctx);
1273 BUILD_BUG_ON(FIELD_SIZEOF(struct net_device,
1275 off = offsetof(struct net_device, ifindex);
1276 emit_load(r_A, r_s0, off, ctx);
1278 case BPF_ANC | SKF_AD_MARK:
1279 ctx->flags |= SEEN_SKB | SEEN_A;
1280 BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, mark) != 4);
1281 off = offsetof(struct sk_buff, mark);
1282 emit_load(r_A, r_skb, off, ctx);
1284 case BPF_ANC | SKF_AD_RXHASH:
1285 ctx->flags |= SEEN_SKB | SEEN_A;
1286 BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, hash) != 4);
1287 off = offsetof(struct sk_buff, hash);
1288 emit_load(r_A, r_skb, off, ctx);
1290 case BPF_ANC | SKF_AD_VLAN_TAG:
1291 case BPF_ANC | SKF_AD_VLAN_TAG_PRESENT:
1292 ctx->flags |= SEEN_SKB | SEEN_S0 | SEEN_A;
1293 BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff,
1295 off = offsetof(struct sk_buff, vlan_tci);
1296 emit_half_load(r_s0, r_skb, off, ctx);
1297 if (code == (BPF_ANC | SKF_AD_VLAN_TAG)) {
1298 emit_andi(r_A, r_s0, (u16)~VLAN_TAG_PRESENT, ctx);
1300 emit_andi(r_A, r_s0, VLAN_TAG_PRESENT, ctx);
1301 /* return 1 if present */
1302 emit_sltu(r_A, r_zero, r_A, ctx);
1305 case BPF_ANC | SKF_AD_PKTTYPE:
1306 ctx->flags |= SEEN_SKB;
1308 off = pkt_type_offset();
1312 emit_load_byte(r_tmp, r_skb, off, ctx);
1313 /* Keep only the last 3 bits */
1314 emit_andi(r_A, r_tmp, PKT_TYPE_MAX, ctx);
1316 case BPF_ANC | SKF_AD_QUEUE:
1317 ctx->flags |= SEEN_SKB | SEEN_A;
1318 BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff,
1319 queue_mapping) != 2);
1320 BUILD_BUG_ON(offsetof(struct sk_buff,
1321 queue_mapping) > 0xff);
1322 off = offsetof(struct sk_buff, queue_mapping);
1323 emit_half_load(r_A, r_skb, off, ctx);
1326 pr_debug("%s: Unhandled opcode: 0x%02x\n", __FILE__,
1332 /* compute offsets only during the first pass */
1333 if (ctx->target == NULL)
1334 ctx->offsets[i] = ctx->idx * 4;
1339 int bpf_jit_enable __read_mostly;
1341 void bpf_jit_compile(struct sk_filter *fp)
1344 unsigned int alloc_size, tmp_idx;
1346 if (!bpf_jit_enable)
1349 memset(&ctx, 0, sizeof(ctx));
1351 ctx.offsets = kcalloc(fp->len, sizeof(*ctx.offsets), GFP_KERNEL);
1352 if (ctx.offsets == NULL)
1357 if (build_body(&ctx))
1361 build_prologue(&ctx);
1362 ctx.prologue_bytes = (ctx.idx - tmp_idx) * 4;
1363 /* just to complete the ctx.idx count */
1364 build_epilogue(&ctx);
1366 alloc_size = 4 * ctx.idx;
1367 ctx.target = module_alloc(alloc_size);
1368 if (ctx.target == NULL)
1372 memset(ctx.target, 0, alloc_size);
1376 /* Generate the actual JIT code */
1377 build_prologue(&ctx);
1379 build_epilogue(&ctx);
1381 /* Update the icache */
1382 flush_icache_range((ptr)ctx.target, (ptr)(ctx.target + ctx.idx));
1384 if (bpf_jit_enable > 1)
1386 bpf_jit_dump(fp->len, alloc_size, 2, ctx.target);
1388 fp->bpf_func = (void *)ctx.target;
1395 void bpf_jit_free(struct sk_filter *fp)
1398 module_free(NULL, fp->bpf_func);