3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Adapted for Power Macintosh by Paul Mackerras.
7 * Low-level exception handlers and MMU support
8 * rewritten by Paul Mackerras.
9 * Copyright (C) 1996 Paul Mackerras.
10 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * This file contains the system call entry code, context switch
13 * code, and exception/interrupt return code for PowerPC.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
21 #include <linux/errno.h>
22 #include <linux/err.h>
23 #include <asm/unistd.h>
24 #include <asm/processor.h>
27 #include <asm/thread_info.h>
28 #include <asm/ppc_asm.h>
29 #include <asm/asm-offsets.h>
30 #include <asm/cputable.h>
31 #include <asm/firmware.h>
33 #include <asm/ptrace.h>
34 #include <asm/irqflags.h>
35 #include <asm/ftrace.h>
36 #include <asm/hw_irq.h>
37 #include <asm/context_tracking.h>
45 .tc sys_call_table[TC],sys_call_table
47 /* This value is used to mark exception frames on the stack. */
49 .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
54 .globl system_call_common
56 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
58 extrdi. r10, r12, 1, (63-MSR_TS_T_LG) /* transaction active? */
60 END_FTR_SECTION_IFSET(CPU_FTR_TM)
64 addi r1,r1,-INT_FRAME_SIZE
72 beq 2f /* if from kernel mode */
73 ACCOUNT_CPU_USER_ENTRY(r10, r11)
92 * This clears CR0.SO (bit 28), which is the error indication on
93 * return from this system call.
95 rldimi r2,r11,28,(63-28)
102 addi r9,r1,STACK_FRAME_OVERHEAD
103 ld r11,exception_marker@toc(r2)
104 std r11,-16(r9) /* "regshere" marker */
105 #if defined(CONFIG_VIRT_CPU_ACCOUNTING_NATIVE) && defined(CONFIG_PPC_SPLPAR)
108 /* if from user, see if there are any DTL entries to process */
109 ld r10,PACALPPACAPTR(r13) /* get ptr to VPA */
110 ld r11,PACA_DTL_RIDX(r13) /* get log read index */
111 addi r10,r10,LPPACA_DTLIDX
112 LDX_BE r10,0,r10 /* get log write index */
115 bl accumulate_stolen_time
119 addi r9,r1,STACK_FRAME_OVERHEAD
121 END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
122 #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE && CONFIG_PPC_SPLPAR */
125 * A syscall should always be called with interrupts enabled
126 * so we just unconditionally hard-enable here. When some kind
127 * of irq tracing is used, we additionally check that condition
130 #if defined(CONFIG_TRACE_IRQFLAGS) && defined(CONFIG_BUG)
131 lbz r10,PACASOFTIRQEN(r13)
134 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
137 #ifdef CONFIG_PPC_BOOK3E
143 #endif /* CONFIG_PPC_BOOK3E */
145 /* We do need to set SOFTE in the stack frame or the return
146 * from interrupt will be painful
151 CURRENT_THREAD_INFO(r11, r1)
153 andi. r11,r10,_TIF_SYSCALL_DOTRACE
154 bne syscall_dotrace /* does not return */
155 cmpldi 0,r0,NR_syscalls
158 system_call: /* label this so stack traces look sane */
160 * Need to vector to 32 Bit or default sys_call_table here,
161 * based on caller's run-mode / personality.
163 ld r11,SYS_CALL_TABLE@toc(2)
164 andi. r10,r10,_TIF_32BIT
166 addi r11,r11,8 /* use 32-bit syscall entries */
175 ldx r12,r11,r0 /* Fetch system call handler [ptr] */
177 bctrl /* Call handler */
181 CURRENT_THREAD_INFO(r12, r1)
184 #ifdef CONFIG_PPC_BOOK3S
185 /* No MSR:RI on BookE */
190 * Disable interrupts so current_thread_info()->flags can't change,
191 * and so that we don't get interrupted after loading SRR0/1.
193 #ifdef CONFIG_PPC_BOOK3E
198 * For performance reasons we clear RI the same time that we
199 * clear EE. We only need to clear RI just before we restore r13
200 * below, but batching it with EE saves us one expensive mtmsrd call.
201 * We have to be careful to restore RI if we branch anywhere from
202 * here (eg syscall_exit_work).
207 #endif /* CONFIG_PPC_BOOK3E */
211 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
212 bne- syscall_exit_work
216 .Lsyscall_error_cont:
219 stdcx. r0,0,r1 /* to clear the reservation */
220 END_FTR_SECTION_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
225 ACCOUNT_CPU_USER_EXIT(r11, r12)
229 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
231 ld r13,GPR13(r1) /* only restore r13 if returning to usermode */
239 b . /* prevent speculative execution */
242 oris r5,r5,0x1000 /* Set SO bit in CR */
245 b .Lsyscall_error_cont
247 /* Traced system call support */
250 addi r3,r1,STACK_FRAME_OVERHEAD
251 bl do_syscall_trace_enter
254 * We use the return value of do_syscall_trace_enter() as the syscall
255 * number. If the syscall was rejected for any reason do_syscall_trace_enter()
256 * returns an invalid syscall number and the test below against
257 * NR_syscalls will fail.
261 /* Restore argument registers just clobbered and/or possibly changed. */
269 /* Repopulate r9 and r10 for the system_call path */
270 addi r9,r1,STACK_FRAME_OVERHEAD
271 CURRENT_THREAD_INFO(r10, r1)
274 cmpldi r0,NR_syscalls
277 /* Return code is already in r3 thanks to do_syscall_trace_enter() */
286 #ifdef CONFIG_PPC_BOOK3S
287 mtmsrd r10,1 /* Restore RI */
289 /* If TIF_RESTOREALL is set, don't scribble on either r3 or ccr.
290 If TIF_NOERROR is set, just save r3 as it is. */
292 andi. r0,r9,_TIF_RESTOREALL
296 0: cmpld r3,r11 /* r11 is -MAX_ERRNO */
298 andi. r0,r9,_TIF_NOERROR
302 oris r5,r5,0x1000 /* Set SO bit in CR */
305 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
308 /* Clear per-syscall TIF flags if any are set. */
310 li r11,_TIF_PERSYSCALL_MASK
311 addi r12,r12,TI_FLAGS
316 subi r12,r12,TI_FLAGS
318 4: /* Anything else left to do? */
319 SET_DEFAULT_THREAD_PPR(r3, r10) /* Set thread.ppr = 3 */
320 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP)
321 beq ret_from_except_lite
323 /* Re-enable interrupts */
324 #ifdef CONFIG_PPC_BOOK3E
330 #endif /* CONFIG_PPC_BOOK3E */
333 addi r3,r1,STACK_FRAME_OVERHEAD
334 bl do_syscall_trace_leave
337 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
339 /* Firstly we need to enable TM in the kernel */
342 rldimi r10, r13, MSR_TM_LG, 63-MSR_TM_LG
345 /* tabort, this dooms the transaction, nothing else */
346 li r13, (TM_CAUSE_SYSCALL|TM_CAUSE_PERSISTENT)
350 * Return directly to userspace. We have corrupted user register state,
351 * but userspace will never see that register state. Execution will
352 * resume after the tbegin of the aborted transaction with the
353 * checkpointed register state.
362 b . /* prevent speculative execution */
365 /* Save non-volatile GPRs, if not already saved. */
377 * The sigsuspend and rt_sigsuspend system calls can call do_signal
378 * and thus put the process into the stopped state where we might
379 * want to examine its user state with ptrace. Therefore we need
380 * to save all the nonvolatile registers (r14 - r31) before calling
381 * the C code. Similarly, fork, vfork and clone need the full
382 * register state on the stack so that it can be copied to the child.
400 _GLOBAL(ppc32_swapcontext)
402 bl compat_sys_swapcontext
405 _GLOBAL(ppc64_swapcontext)
410 _GLOBAL(ppc_switch_endian)
415 _GLOBAL(ret_from_fork)
421 _GLOBAL(ret_from_kernel_thread)
426 #if defined(_CALL_ELF) && _CALL_ELF == 2
434 * This routine switches between two different tasks. The process
435 * state of one is saved on its kernel stack. Then the state
436 * of the other is restored from its kernel stack. The memory
437 * management hardware is updated to the second process's state.
438 * Finally, we can return to the second process, via ret_from_except.
439 * On entry, r3 points to the THREAD for the current task, r4
440 * points to the THREAD for the new task.
442 * Note: there are two ways to get to the "going out" portion
443 * of this code; either by coming in via the entry (_switch)
444 * or via "fork" which must set up an environment equivalent
445 * to the "_switch" path. If you change this you'll have to change
446 * the fork code also.
448 * The code which creates the new task context is in 'copy_thread'
449 * in arch/powerpc/kernel/process.c
455 stdu r1,-SWITCH_FRAME_SIZE(r1)
456 /* r3-r13 are caller saved -- Cort */
459 std r0,_NIP(r1) /* Return to switch caller */
462 std r1,KSP(r3) /* Set old stack pointer */
465 /* We need a sync somewhere here to make sure that if the
466 * previous task gets rescheduled on another CPU, it sees all
467 * stores it has performed on this one.
470 #endif /* CONFIG_SMP */
473 * If we optimise away the clear of the reservation in system
474 * calls because we know the CPU tracks the address of the
475 * reservation, then we need to clear it here to cover the
476 * case that the kernel context switch path has no larx
481 END_FTR_SECTION_IFSET(CPU_FTR_STCX_CHECKS_ADDRESS)
483 #ifdef CONFIG_PPC_BOOK3S
484 /* Cancel all explict user streams as they will have no use after context
485 * switch and will stop the HW from creating streams itself
487 DCBT_STOP_ALL_STREAM_IDS(r6)
490 addi r6,r4,-THREAD /* Convert THREAD to 'current' */
491 std r6,PACACURRENT(r13) /* Set new 'current' */
493 ld r8,KSP(r4) /* new stack pointer */
494 #ifdef CONFIG_PPC_BOOK3S
496 clrrdi r6,r8,28 /* get its ESID */
497 clrrdi r9,r1,28 /* get current sp ESID */
499 clrrdi r6,r8,40 /* get its 1T ESID */
500 clrrdi r9,r1,40 /* get current sp 1T ESID */
501 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_1T_SEGMENT)
502 clrldi. r0,r6,2 /* is new ESID c00000000? */
503 cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */
505 beq 2f /* if yes, don't slbie it */
507 /* Bolt in the new stack SLB entry */
508 ld r7,KSP_VSID(r4) /* Get new stack's VSID */
509 oris r0,r6,(SLB_ESID_V)@h
510 ori r0,r0,(SLB_NUM_BOLTED-1)@l
512 li r9,MMU_SEGSIZE_1T /* insert B field */
513 oris r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h
514 rldimi r7,r9,SLB_VSID_SSIZE_SHIFT,0
515 END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
517 /* Update the last bolted SLB. No write barriers are needed
518 * here, provided we only update the current CPU's SLB shadow
521 ld r9,PACA_SLBSHADOWPTR(r13)
523 std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */
524 li r12,SLBSHADOW_STACKVSID
525 STDX_BE r7,r12,r9 /* Save VSID */
526 li r12,SLBSHADOW_STACKESID
527 STDX_BE r0,r12,r9 /* Save ESID */
529 /* No need to check for MMU_FTR_NO_SLBIE_B here, since when
530 * we have 1TB segments, the only CPUs known to have the errata
531 * only support less than 1TB of system memory and we'll never
532 * actually hit this code path.
536 slbie r6 /* Workaround POWER5 < DD2.1 issue */
540 #endif /* !CONFIG_PPC_BOOK3S */
542 CURRENT_THREAD_INFO(r7, r8) /* base of new stack */
543 /* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE
544 because we don't need to leave the 288-byte ABI gap at the
545 top of the kernel stack. */
546 addi r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE
548 mr r1,r8 /* start using new stack pointer */
549 std r7,PACAKSAVE(r13)
554 /* r3-r13 are destroyed -- Cort */
558 /* convert old thread to its task_struct for return value */
560 ld r7,_NIP(r1) /* Return to _switch caller in new task */
562 addi r1,r1,SWITCH_FRAME_SIZE
566 _GLOBAL(ret_from_except)
569 bne ret_from_except_lite
572 _GLOBAL(ret_from_except_lite)
574 * Disable interrupts so that current_thread_info()->flags
575 * can't change between when we test it and when we return
576 * from the interrupt.
578 #ifdef CONFIG_PPC_BOOK3E
581 ld r10,PACAKMSR(r13) /* Get kernel MSR without EE */
582 mtmsrd r10,1 /* Update machine state */
583 #endif /* CONFIG_PPC_BOOK3E */
585 CURRENT_THREAD_INFO(r9, r1)
587 #ifdef CONFIG_PPC_BOOK3E
588 ld r10,PACACURRENT(r13)
589 #endif /* CONFIG_PPC_BOOK3E */
593 #ifdef CONFIG_PPC_BOOK3E
594 lwz r3,(THREAD+THREAD_DBCR0)(r10)
595 #endif /* CONFIG_PPC_BOOK3E */
597 /* Check current_thread_info()->flags */
598 andi. r0,r4,_TIF_USER_WORK_MASK
599 #ifdef CONFIG_PPC_BOOK3E
602 * Check to see if the dbcr0 register is set up to debug.
603 * Use the internal debug mode bit to do this.
605 andis. r0,r3,DBCR0_IDM@h
608 rlwinm r0,r0,0,~MSR_DE /* Clear MSR.DE */
617 1: andi. r0,r4,_TIF_NEED_RESCHED
619 bl restore_interrupts
621 b ret_from_except_lite
623 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
624 andi. r0,r4,_TIF_USER_WORK_MASK & ~_TIF_RESTORE_TM
625 bne 3f /* only restore TM if nothing else to do */
626 addi r3,r1,STACK_FRAME_OVERHEAD
633 * Use a non volatile GPR to save and restore our thread_info flags
634 * across the call to restore_interrupts.
637 bl restore_interrupts
639 addi r3,r1,STACK_FRAME_OVERHEAD
644 /* check current_thread_info, _TIF_EMULATE_STACK_STORE */
645 andis. r8,r4,_TIF_EMULATE_STACK_STORE@h
648 addi r8,r1,INT_FRAME_SIZE /* Get the kprobed function entry */
651 subi r3,r3,INT_FRAME_SIZE /* dst: Allocate a trampoline exception frame */
652 mr r4,r1 /* src: current exception frame */
653 mr r1,r3 /* Reroute the trampoline frame to r1 */
655 /* Copy from the original to the trampoline. */
656 li r5,INT_FRAME_SIZE/8 /* size: INT_FRAME_SIZE */
657 li r6,0 /* start offset: 0 */
664 /* Do real store operation to complete stwu */
668 /* Clear _TIF_EMULATE_STACK_STORE flag */
669 lis r11,_TIF_EMULATE_STACK_STORE@h
677 #ifdef CONFIG_PREEMPT
678 /* Check if we need to preempt */
679 andi. r0,r4,_TIF_NEED_RESCHED
681 /* Check that preempt_count() == 0 and interrupts are enabled */
682 lwz r8,TI_PREEMPT(r9)
686 crandc eq,cr1*4+eq,eq
690 * Here we are preempting the current task. We want to make
691 * sure we are soft-disabled first and reconcile irq state.
693 RECONCILE_IRQ_STATE(r3,r4)
694 1: bl preempt_schedule_irq
696 /* Re-test flags and eventually loop */
697 CURRENT_THREAD_INFO(r9, r1)
699 andi. r0,r4,_TIF_NEED_RESCHED
703 * arch_local_irq_restore() from preempt_schedule_irq above may
704 * enable hard interrupt but we really should disable interrupts
705 * when we return from the interrupt, and so that we don't get
706 * interrupted after loading SRR0/1.
708 #ifdef CONFIG_PPC_BOOK3E
711 ld r10,PACAKMSR(r13) /* Get kernel MSR without EE */
712 mtmsrd r10,1 /* Update machine state */
713 #endif /* CONFIG_PPC_BOOK3E */
714 #endif /* CONFIG_PREEMPT */
716 .globl fast_exc_return_irq
720 * This is the main kernel exit path. First we check if we
721 * are about to re-enable interrupts
724 lbz r6,PACASOFTIRQEN(r13)
728 /* We are enabling, were we already enabled ? Yes, just return */
733 * We are about to soft-enable interrupts (we are hard disabled
734 * at this point). We check if there's anything that needs to
737 lbz r0,PACAIRQHAPPENED(r13)
739 bne- restore_check_irq_replay
742 * Get here when nothing happened while soft-disabled, just
743 * soft-enable and move-on. We will hard-enable as a side
749 stb r0,PACASOFTIRQEN(r13);
752 * Final return path. BookE is handled in a different file
755 #ifdef CONFIG_PPC_BOOK3E
756 b exception_return_book3e
759 * Clear the reservation. If we know the CPU tracks the address of
760 * the reservation then we can potentially save some cycles and use
761 * a larx. On POWER6 and POWER7 this is significantly faster.
764 stdcx. r0,0,r1 /* to clear the reservation */
767 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
770 * Some code path such as load_up_fpu or altivec return directly
771 * here. They run entirely hard disabled and do not alter the
772 * interrupt state. They also don't use lwarx/stwcx. and thus
773 * are known not to leave dangling reservations.
775 .globl fast_exception_return
776 fast_exception_return:
790 /* Load PPR from thread struct before we clear MSR:RI */
792 ld r2,PACACURRENT(r13)
793 ld r2,TASKTHREADPPR(r2)
794 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
797 * Clear RI before restoring r13. If we are returning to
798 * userspace and we take an exception after restoring r13,
799 * we end up corrupting the userspace r13 value.
801 ld r4,PACAKMSR(r13) /* Get kernel MSR without EE */
802 andc r4,r4,r0 /* r0 contains MSR_RI here */
805 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
807 std r3, PACATMSCRATCH(r13) /* Stash returned-to MSR */
810 * r13 is our per cpu area, only restore it if we are returning to
811 * userspace the value stored in the stack frame may belong to
817 mtspr SPRN_PPR,r2 /* Restore PPR */
818 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
819 ACCOUNT_CPU_USER_EXIT(r2, r4)
836 b . /* prevent speculative execution */
838 #endif /* CONFIG_PPC_BOOK3E */
841 * We are returning to a context with interrupts soft disabled.
843 * However, we may also about to hard enable, so we need to
844 * make sure that in this case, we also clear PACA_IRQ_HARD_DIS
845 * or that bit can get out of sync and bad things will happen
849 lbz r7,PACAIRQHAPPENED(r13)
852 rlwinm r7,r7,0,~PACA_IRQ_HARD_DIS
853 stb r7,PACAIRQHAPPENED(r13)
855 stb r0,PACASOFTIRQEN(r13);
860 * Something did happen, check if a re-emit is needed
861 * (this also clears paca->irq_happened)
863 restore_check_irq_replay:
864 /* XXX: We could implement a fast path here where we check
865 * for irq_happened being just 0x01, in which case we can
866 * clear it and return. That means that we would potentially
867 * miss a decrementer having wrapped all the way around.
869 * Still, this might be useful for things like hash_page
871 bl __check_irq_replay
873 beq restore_no_replay
876 * We need to re-emit an interrupt. We do so by re-using our
877 * existing exception frame. We first change the trap value,
878 * but we need to ensure we preserve the low nibble of it
886 * Then find the right handler and call it. Interrupts are
887 * still soft-disabled and we keep them that way.
891 addi r3,r1,STACK_FRAME_OVERHEAD;
894 1: cmpwi cr0,r3,0xe60
896 addi r3,r1,STACK_FRAME_OVERHEAD;
897 bl handle_hmi_exception
899 1: cmpwi cr0,r3,0x900
901 addi r3,r1,STACK_FRAME_OVERHEAD;
904 #ifdef CONFIG_PPC_DOORBELL
906 #ifdef CONFIG_PPC_BOOK3E
913 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
914 #endif /* CONFIG_PPC_BOOK3E */
916 addi r3,r1,STACK_FRAME_OVERHEAD;
917 bl doorbell_exception
919 #endif /* CONFIG_PPC_DOORBELL */
920 1: b ret_from_except /* What else to do here ? */
923 addi r3,r1,STACK_FRAME_OVERHEAD
924 bl unrecoverable_exception
927 #ifdef CONFIG_PPC_RTAS
929 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
930 * called with the MMU off.
932 * In addition, we need to be in 32b mode, at least for now.
934 * Note: r3 is an input parameter to rtas, so don't trash it...
939 stdu r1,-RTAS_FRAME_SIZE(r1) /* Save SP and create stack space. */
941 /* Because RTAS is running in 32b mode, it clobbers the high order half
942 * of all registers that it saves. We therefore save those registers
943 * RTAS might touch to the stack. (r0, r3-r13 are caller saved)
945 SAVE_GPR(2, r1) /* Save the TOC */
946 SAVE_GPR(13, r1) /* Save paca */
947 SAVE_8GPRS(14, r1) /* Save the non-volatiles */
948 SAVE_10GPRS(22, r1) /* ditto */
961 /* Temporary workaround to clear CR until RTAS can be modified to
968 /* There is no way it is acceptable to get here with interrupts enabled,
969 * check it with the asm equivalent of WARN_ON
971 lbz r0,PACASOFTIRQEN(r13)
973 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
976 /* Hard-disable interrupts */
982 /* Unfortunately, the stack pointer and the MSR are also clobbered,
983 * so they are saved in the PACA which allows us to restore
984 * our original state after RTAS returns.
987 std r6,PACASAVEDMSR(r13)
989 /* Setup our real return addr */
990 LOAD_REG_ADDR(r4,rtas_return_loc)
991 clrldi r4,r4,2 /* convert to realmode address */
995 ori r0,r0,MSR_EE|MSR_SE|MSR_BE|MSR_RI
999 rldicr r9,r9,MSR_SF_LG,(63-MSR_SF_LG)
1000 ori r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP|MSR_RI|MSR_LE
1002 sync /* disable interrupts so SRR0/1 */
1003 mtmsrd r0 /* don't get trashed */
1005 LOAD_REG_ADDR(r4, rtas)
1006 ld r5,RTASENTRY(r4) /* get the rtas->entry value */
1007 ld r4,RTASBASE(r4) /* get the rtas->base value */
1012 b . /* prevent speculative execution */
1017 /* relocation is off at this point */
1019 clrldi r4,r4,2 /* convert to realmode address */
1023 ld r3,(1f-0b)(r3) /* get &rtas_restore_regs */
1031 ld r1,PACAR1(r4) /* Restore our SP */
1032 ld r4,PACASAVEDMSR(r4) /* Restore our MSR */
1037 b . /* prevent speculative execution */
1040 1: .llong rtas_restore_regs
1043 /* relocation is on at this point */
1044 REST_GPR(2, r1) /* Restore the TOC */
1045 REST_GPR(13, r1) /* Restore paca */
1046 REST_8GPRS(14, r1) /* Restore the non-volatiles */
1047 REST_10GPRS(22, r1) /* ditto */
1062 addi r1,r1,RTAS_FRAME_SIZE /* Unstack our frame */
1063 ld r0,16(r1) /* get return address */
1066 blr /* return to caller */
1068 #endif /* CONFIG_PPC_RTAS */
1073 stdu r1,-PROM_FRAME_SIZE(r1) /* Save SP and create stack space */
1075 /* Because PROM is running in 32b mode, it clobbers the high order half
1076 * of all registers that it saves. We therefore save those registers
1077 * PROM might touch to the stack. (r0, r3-r13 are caller saved)
1088 /* Put PROM address in SRR0 */
1091 /* Setup our trampoline return addr in LR */
1094 addi r4,r4,(1f - 0b)
1097 /* Prepare a 32-bit mode big endian MSR
1099 #ifdef CONFIG_PPC_BOOK3E
1100 rlwinm r11,r11,0,1,31
1103 #else /* CONFIG_PPC_BOOK3E */
1104 LOAD_REG_IMMEDIATE(r12, MSR_SF | MSR_ISF | MSR_LE)
1108 #endif /* CONFIG_PPC_BOOK3E */
1110 1: /* Return from OF */
1113 /* Just make sure that r1 top 32 bits didn't get
1118 /* Restore the MSR (back to 64 bits) */
1123 /* Restore other registers */
1131 addi r1,r1,PROM_FRAME_SIZE
1136 #ifdef CONFIG_FUNCTION_TRACER
1137 #ifdef CONFIG_DYNAMIC_FTRACE
1142 _GLOBAL_TOC(ftrace_caller)
1143 /* Taken from output of objdump from lib64/glibc */
1149 subi r3, r3, MCOUNT_INSN_SIZE
1154 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1155 .globl ftrace_graph_call
1158 _GLOBAL(ftrace_graph_stub)
1163 _GLOBAL(ftrace_stub)
1166 _GLOBAL_TOC(_mcount)
1167 /* Taken from output of objdump from lib64/glibc */
1174 subi r3, r3, MCOUNT_INSN_SIZE
1175 LOAD_REG_ADDR(r5,ftrace_trace_function)
1183 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1184 b ftrace_graph_caller
1189 _GLOBAL(ftrace_stub)
1192 #endif /* CONFIG_DYNAMIC_FTRACE */
1194 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1195 _GLOBAL(ftrace_graph_caller)
1196 /* load r4 with local address */
1198 subi r4, r4, MCOUNT_INSN_SIZE
1200 /* Grab the LR out of the caller stack frame */
1204 bl prepare_ftrace_return
1208 * prepare_ftrace_return gives us the address we divert to.
1209 * Change the LR in the callers stack frame to this.
1219 _GLOBAL(return_to_handler)
1220 /* need to save return values */
1230 * We might be called from a module.
1231 * Switch to our TOC to run inside the core kernel.
1235 bl ftrace_return_to_handler
1238 /* return value has real return address */
1247 /* Jump back to real return address */
1249 #endif /* CONFIG_FUNCTION_GRAPH_TRACER */
1250 #endif /* CONFIG_FUNCTION_TRACER */