2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/delay.h>
24 #include <linux/export.h>
25 #include <linux/of_address.h>
26 #include <linux/of_pci.h>
28 #include <linux/list.h>
29 #include <linux/syscalls.h>
30 #include <linux/irq.h>
31 #include <linux/vmalloc.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
35 #include <asm/processor.h>
38 #include <asm/pci-bridge.h>
39 #include <asm/byteorder.h>
40 #include <asm/machdep.h>
41 #include <asm/ppc-pci.h>
44 static DEFINE_SPINLOCK(hose_spinlock);
47 /* XXX kill that some day ... */
48 static int global_phb_number; /* Global phb counter */
50 /* ISA Memory physical address */
51 resource_size_t isa_mem_base;
54 static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
56 void set_pci_dma_ops(struct dma_map_ops *dma_ops)
58 pci_dma_ops = dma_ops;
61 struct dma_map_ops *get_pci_dma_ops(void)
65 EXPORT_SYMBOL(get_pci_dma_ops);
67 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
69 struct pci_controller *phb;
71 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
74 spin_lock(&hose_spinlock);
75 phb->global_number = global_phb_number++;
76 list_add_tail(&phb->list_node, &hose_list);
77 spin_unlock(&hose_spinlock);
79 phb->is_dynamic = slab_is_available();
82 int nid = of_node_to_nid(dev);
84 if (nid < 0 || !node_online(nid))
87 PHB_SET_NODE(phb, nid);
92 EXPORT_SYMBOL_GPL(pcibios_alloc_controller);
94 void pcibios_free_controller(struct pci_controller *phb)
96 spin_lock(&hose_spinlock);
97 list_del(&phb->list_node);
98 spin_unlock(&hose_spinlock);
103 EXPORT_SYMBOL_GPL(pcibios_free_controller);
106 * The function is used to return the minimal alignment
107 * for memory or I/O windows of the associated P2P bridge.
108 * By default, 4KiB alignment for I/O windows and 1MiB for
111 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
114 struct pci_controller *phb = pci_bus_to_host(bus);
116 if (phb->controller_ops.window_alignment)
117 return phb->controller_ops.window_alignment(bus, type);
120 * PCI core will figure out the default
121 * alignment: 4KiB for I/O and 1MiB for
127 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type)
129 struct pci_controller *hose = pci_bus_to_host(bus);
131 if (hose->controller_ops.setup_bridge)
132 hose->controller_ops.setup_bridge(bus, type);
135 void pcibios_reset_secondary_bus(struct pci_dev *dev)
137 struct pci_controller *phb = pci_bus_to_host(dev->bus);
139 if (phb->controller_ops.reset_secondary_bus) {
140 phb->controller_ops.reset_secondary_bus(dev);
144 pci_reset_secondary_bus(dev);
147 #ifdef CONFIG_PCI_IOV
148 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *pdev, int resno)
150 if (ppc_md.pcibios_iov_resource_alignment)
151 return ppc_md.pcibios_iov_resource_alignment(pdev, resno);
153 return pci_iov_resource_size(pdev, resno);
155 #endif /* CONFIG_PCI_IOV */
157 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
160 return hose->pci_io_size;
162 return resource_size(&hose->io_resource);
166 int pcibios_vaddr_is_ioport(void __iomem *address)
169 struct pci_controller *hose;
170 resource_size_t size;
172 spin_lock(&hose_spinlock);
173 list_for_each_entry(hose, &hose_list, list_node) {
174 size = pcibios_io_size(hose);
175 if (address >= hose->io_base_virt &&
176 address < (hose->io_base_virt + size)) {
181 spin_unlock(&hose_spinlock);
185 unsigned long pci_address_to_pio(phys_addr_t address)
187 struct pci_controller *hose;
188 resource_size_t size;
189 unsigned long ret = ~0;
191 spin_lock(&hose_spinlock);
192 list_for_each_entry(hose, &hose_list, list_node) {
193 size = pcibios_io_size(hose);
194 if (address >= hose->io_base_phys &&
195 address < (hose->io_base_phys + size)) {
197 (unsigned long)hose->io_base_virt - _IO_BASE;
198 ret = base + (address - hose->io_base_phys);
202 spin_unlock(&hose_spinlock);
206 EXPORT_SYMBOL_GPL(pci_address_to_pio);
209 * Return the domain number for this bus.
211 int pci_domain_nr(struct pci_bus *bus)
213 struct pci_controller *hose = pci_bus_to_host(bus);
215 return hose->global_number;
217 EXPORT_SYMBOL(pci_domain_nr);
219 /* This routine is meant to be used early during boot, when the
220 * PCI bus numbers have not yet been assigned, and you need to
221 * issue PCI config cycles to an OF device.
222 * It could also be used to "fix" RTAS config cycles if you want
223 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
226 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
229 struct pci_controller *hose, *tmp;
230 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
231 if (hose->dn == node)
239 * Reads the interrupt pin to determine if interrupt is use by card.
240 * If the interrupt is used, then gets the interrupt line from the
241 * openfirmware and sets it in the pci_dev and pci_config line.
243 static int pci_read_irq_line(struct pci_dev *pci_dev)
245 struct of_phandle_args oirq;
248 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
251 memset(&oirq, 0xff, sizeof(oirq));
253 /* Try to get a mapping from the device-tree */
254 if (of_irq_parse_pci(pci_dev, &oirq)) {
257 /* If that fails, lets fallback to what is in the config
258 * space and map that through the default controller. We
259 * also set the type to level low since that's what PCI
260 * interrupts are. If your platform does differently, then
261 * either provide a proper interrupt tree or don't use this
264 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
268 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
269 line == 0xff || line == 0) {
272 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
275 virq = irq_create_mapping(NULL, line);
277 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
279 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
280 oirq.args_count, oirq.args[0], oirq.args[1],
281 of_node_full_name(oirq.np));
283 virq = irq_create_of_mapping(&oirq);
286 pr_debug(" Failed to map !\n");
290 pr_debug(" Mapped to linux irq %d\n", virq);
298 * Platform support for /proc/bus/pci/X/Y mmap()s,
299 * modelled on the sparc64 implementation by Dave Miller.
304 * Adjust vm_pgoff of VMA such that it is the physical page offset
305 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
307 * Basically, the user finds the base address for his device which he wishes
308 * to mmap. They read the 32-bit value from the config space base register,
309 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
310 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
312 * Returns negative error code on failure, zero on success.
314 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
315 resource_size_t *offset,
316 enum pci_mmap_state mmap_state)
318 struct pci_controller *hose = pci_bus_to_host(dev->bus);
319 unsigned long io_offset = 0;
323 return NULL; /* should never happen */
325 /* If memory, add on the PCI bridge address offset */
326 if (mmap_state == pci_mmap_mem) {
327 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
328 *offset += hose->pci_mem_offset;
330 res_bit = IORESOURCE_MEM;
332 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
333 *offset += io_offset;
334 res_bit = IORESOURCE_IO;
338 * Check that the offset requested corresponds to one of the
339 * resources of the device.
341 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
342 struct resource *rp = &dev->resource[i];
343 int flags = rp->flags;
345 /* treat ROM as memory (should be already) */
346 if (i == PCI_ROM_RESOURCE)
347 flags |= IORESOURCE_MEM;
349 /* Active and same type? */
350 if ((flags & res_bit) == 0)
353 /* In the range of this resource? */
354 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
357 /* found it! construct the final physical address */
358 if (mmap_state == pci_mmap_io)
359 *offset += hose->io_base_phys - io_offset;
367 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
370 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
372 enum pci_mmap_state mmap_state,
376 /* Write combine is always 0 on non-memory space mappings. On
377 * memory space, if the user didn't pass 1, we check for a
378 * "prefetchable" resource. This is a bit hackish, but we use
379 * this to workaround the inability of /sysfs to provide a write
382 if (mmap_state != pci_mmap_mem)
384 else if (write_combine == 0) {
385 if (rp->flags & IORESOURCE_PREFETCH)
389 /* XXX would be nice to have a way to ask for write-through */
391 return pgprot_noncached_wc(protection);
393 return pgprot_noncached(protection);
397 * This one is used by /dev/mem and fbdev who have no clue about the
398 * PCI device, it tries to find the PCI device first and calls the
401 pgprot_t pci_phys_mem_access_prot(struct file *file,
406 struct pci_dev *pdev = NULL;
407 struct resource *found = NULL;
408 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
411 if (page_is_ram(pfn))
414 prot = pgprot_noncached(prot);
415 for_each_pci_dev(pdev) {
416 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
417 struct resource *rp = &pdev->resource[i];
418 int flags = rp->flags;
420 /* Active and same type? */
421 if ((flags & IORESOURCE_MEM) == 0)
423 /* In the range of this resource? */
424 if (offset < (rp->start & PAGE_MASK) ||
434 if (found->flags & IORESOURCE_PREFETCH)
435 prot = pgprot_noncached_wc(prot);
439 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
440 (unsigned long long)offset, pgprot_val(prot));
447 * Perform the actual remap of the pages for a PCI device mapping, as
448 * appropriate for this architecture. The region in the process to map
449 * is described by vm_start and vm_end members of VMA, the base physical
450 * address is found in vm_pgoff.
451 * The pci device structure is provided so that architectures may make mapping
452 * decisions on a per-device or per-bus basis.
454 * Returns a negative error code on failure, zero on success.
456 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
457 enum pci_mmap_state mmap_state, int write_combine)
459 resource_size_t offset =
460 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
464 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
468 vma->vm_pgoff = offset >> PAGE_SHIFT;
469 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
471 mmap_state, write_combine);
473 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
474 vma->vm_end - vma->vm_start, vma->vm_page_prot);
479 /* This provides legacy IO read access on a bus */
480 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
482 unsigned long offset;
483 struct pci_controller *hose = pci_bus_to_host(bus);
484 struct resource *rp = &hose->io_resource;
487 /* Check if port can be supported by that bus. We only check
488 * the ranges of the PHB though, not the bus itself as the rules
489 * for forwarding legacy cycles down bridges are not our problem
490 * here. So if the host bridge supports it, we do it.
492 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
495 if (!(rp->flags & IORESOURCE_IO))
497 if (offset < rp->start || (offset + size) > rp->end)
499 addr = hose->io_base_virt + port;
503 *((u8 *)val) = in_8(addr);
508 *((u16 *)val) = in_le16(addr);
513 *((u32 *)val) = in_le32(addr);
519 /* This provides legacy IO write access on a bus */
520 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
522 unsigned long offset;
523 struct pci_controller *hose = pci_bus_to_host(bus);
524 struct resource *rp = &hose->io_resource;
527 /* Check if port can be supported by that bus. We only check
528 * the ranges of the PHB though, not the bus itself as the rules
529 * for forwarding legacy cycles down bridges are not our problem
530 * here. So if the host bridge supports it, we do it.
532 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
535 if (!(rp->flags & IORESOURCE_IO))
537 if (offset < rp->start || (offset + size) > rp->end)
539 addr = hose->io_base_virt + port;
541 /* WARNING: The generic code is idiotic. It gets passed a pointer
542 * to what can be a 1, 2 or 4 byte quantity and always reads that
543 * as a u32, which means that we have to correct the location of
544 * the data read within those 32 bits for size 1 and 2
548 out_8(addr, val >> 24);
553 out_le16(addr, val >> 16);
564 /* This provides legacy IO or memory mmap access on a bus */
565 int pci_mmap_legacy_page_range(struct pci_bus *bus,
566 struct vm_area_struct *vma,
567 enum pci_mmap_state mmap_state)
569 struct pci_controller *hose = pci_bus_to_host(bus);
570 resource_size_t offset =
571 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
572 resource_size_t size = vma->vm_end - vma->vm_start;
575 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
576 pci_domain_nr(bus), bus->number,
577 mmap_state == pci_mmap_mem ? "MEM" : "IO",
578 (unsigned long long)offset,
579 (unsigned long long)(offset + size - 1));
581 if (mmap_state == pci_mmap_mem) {
584 * Because X is lame and can fail starting if it gets an error trying
585 * to mmap legacy_mem (instead of just moving on without legacy memory
586 * access) we fake it here by giving it anonymous memory, effectively
587 * behaving just like /dev/zero
589 if ((offset + size) > hose->isa_mem_size) {
591 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
592 current->comm, current->pid, pci_domain_nr(bus), bus->number);
593 if (vma->vm_flags & VM_SHARED)
594 return shmem_zero_setup(vma);
597 offset += hose->isa_mem_phys;
599 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
600 unsigned long roffset = offset + io_offset;
601 rp = &hose->io_resource;
602 if (!(rp->flags & IORESOURCE_IO))
604 if (roffset < rp->start || (roffset + size) > rp->end)
606 offset += hose->io_base_phys;
608 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
610 vma->vm_pgoff = offset >> PAGE_SHIFT;
611 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
612 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
613 vma->vm_end - vma->vm_start,
617 void pci_resource_to_user(const struct pci_dev *dev, int bar,
618 const struct resource *rsrc,
619 resource_size_t *start, resource_size_t *end)
621 struct pci_controller *hose = pci_bus_to_host(dev->bus);
622 resource_size_t offset = 0;
627 if (rsrc->flags & IORESOURCE_IO)
628 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
630 /* We pass a fully fixed up address to userland for MMIO instead of
631 * a BAR value because X is lame and expects to be able to use that
632 * to pass to /dev/mem !
634 * That means that we'll have potentially 64 bits values where some
635 * userland apps only expect 32 (like X itself since it thinks only
636 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
639 * Hopefully, the sysfs insterface is immune to that gunk. Once X
640 * has been fixed (and the fix spread enough), we can re-enable the
641 * 2 lines below and pass down a BAR value to userland. In that case
642 * we'll also have to re-enable the matching code in
643 * __pci_mmap_make_offset().
648 else if (rsrc->flags & IORESOURCE_MEM)
649 offset = hose->pci_mem_offset;
652 *start = rsrc->start - offset;
653 *end = rsrc->end - offset;
657 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
658 * @hose: newly allocated pci_controller to be setup
659 * @dev: device node of the host bridge
660 * @primary: set if primary bus (32 bits only, soon to be deprecated)
662 * This function will parse the "ranges" property of a PCI host bridge device
663 * node and setup the resource mapping of a pci controller based on its
666 * Life would be boring if it wasn't for a few issues that we have to deal
669 * - We can only cope with one IO space range and up to 3 Memory space
670 * ranges. However, some machines (thanks Apple !) tend to split their
671 * space into lots of small contiguous ranges. So we have to coalesce.
673 * - Some busses have IO space not starting at 0, which causes trouble with
674 * the way we do our IO resource renumbering. The code somewhat deals with
675 * it for 64 bits but I would expect problems on 32 bits.
677 * - Some 32 bits platforms such as 4xx can have physical space larger than
678 * 32 bits so we need to use 64 bits values for the parsing
680 void pci_process_bridge_OF_ranges(struct pci_controller *hose,
681 struct device_node *dev, int primary)
684 struct resource *res;
685 struct of_pci_range range;
686 struct of_pci_range_parser parser;
688 printk(KERN_INFO "PCI host bridge %s %s ranges:\n",
689 dev->full_name, primary ? "(primary)" : "");
691 /* Check for ranges property */
692 if (of_pci_range_parser_init(&parser, dev))
696 for_each_of_pci_range(&parser, &range) {
697 /* If we failed translation or got a zero-sized region
698 * (some FW try to feed us with non sensical zero sized regions
699 * such as power3 which look like some kind of attempt at exposing
700 * the VGA memory hole)
702 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
705 /* Act based on address space type */
707 switch (range.flags & IORESOURCE_TYPE_BITS) {
710 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
711 range.cpu_addr, range.cpu_addr + range.size - 1,
714 /* We support only one IO range */
715 if (hose->pci_io_size) {
717 " \\--> Skipped (too many) !\n");
721 /* On 32 bits, limit I/O space to 16MB */
722 if (range.size > 0x01000000)
723 range.size = 0x01000000;
725 /* 32 bits needs to map IOs here */
726 hose->io_base_virt = ioremap(range.cpu_addr,
729 /* Expect trouble if pci_addr is not 0 */
732 (unsigned long)hose->io_base_virt;
733 #endif /* CONFIG_PPC32 */
734 /* pci_io_size and io_base_phys always represent IO
735 * space starting at 0 so we factor in pci_addr
737 hose->pci_io_size = range.pci_addr + range.size;
738 hose->io_base_phys = range.cpu_addr - range.pci_addr;
741 res = &hose->io_resource;
742 range.cpu_addr = range.pci_addr;
746 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
747 range.cpu_addr, range.cpu_addr + range.size - 1,
749 (range.pci_space & 0x40000000) ?
752 /* We support only 3 memory ranges */
755 " \\--> Skipped (too many) !\n");
758 /* Handles ISA memory hole space here */
759 if (range.pci_addr == 0) {
760 if (primary || isa_mem_base == 0)
761 isa_mem_base = range.cpu_addr;
762 hose->isa_mem_phys = range.cpu_addr;
763 hose->isa_mem_size = range.size;
767 hose->mem_offset[memno] = range.cpu_addr -
769 res = &hose->mem_resources[memno++];
773 res->name = dev->full_name;
774 res->flags = range.flags;
775 res->start = range.cpu_addr;
776 res->end = range.cpu_addr + range.size - 1;
777 res->parent = res->child = res->sibling = NULL;
782 /* Decide whether to display the domain number in /proc */
783 int pci_proc_domain(struct pci_bus *bus)
785 struct pci_controller *hose = pci_bus_to_host(bus);
787 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS))
789 if (pci_has_flag(PCI_COMPAT_DOMAIN_0))
790 return hose->global_number != 0;
794 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
796 if (ppc_md.pcibios_root_bridge_prepare)
797 return ppc_md.pcibios_root_bridge_prepare(bridge);
802 /* This header fixup will do the resource fixup for all devices as they are
803 * probed, but not for bridge ranges
805 static void pcibios_fixup_resources(struct pci_dev *dev)
807 struct pci_controller *hose = pci_bus_to_host(dev->bus);
811 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
819 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
820 struct resource *res = dev->resource + i;
821 struct pci_bus_region reg;
825 /* If we're going to re-assign everything, we mark all resources
826 * as unset (and 0-base them). In addition, we mark BARs starting
827 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
828 * since in that case, we don't want to re-assign anything
830 pcibios_resource_to_bus(dev->bus, ®, res);
831 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
832 (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
833 /* Only print message if not re-assigning */
834 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
835 pr_debug("PCI:%s Resource %d %pR is unassigned\n",
836 pci_name(dev), i, res);
837 res->end -= res->start;
839 res->flags |= IORESOURCE_UNSET;
843 pr_debug("PCI:%s Resource %d %pR\n", pci_name(dev), i, res);
846 /* Call machine specific resource fixup */
847 if (ppc_md.pcibios_fixup_resources)
848 ppc_md.pcibios_fixup_resources(dev);
850 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
852 /* This function tries to figure out if a bridge resource has been initialized
853 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
854 * things go more smoothly when it gets it right. It should covers cases such
855 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
857 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
858 struct resource *res)
860 struct pci_controller *hose = pci_bus_to_host(bus);
861 struct pci_dev *dev = bus->self;
862 resource_size_t offset;
863 struct pci_bus_region region;
867 /* We don't do anything if PCI_PROBE_ONLY is set */
868 if (pci_has_flag(PCI_PROBE_ONLY))
871 /* Job is a bit different between memory and IO */
872 if (res->flags & IORESOURCE_MEM) {
873 pcibios_resource_to_bus(dev->bus, ®ion, res);
875 /* If the BAR is non-0 then it's probably been initialized */
876 if (region.start != 0)
879 /* The BAR is 0, let's check if memory decoding is enabled on
880 * the bridge. If not, we consider it unassigned
882 pci_read_config_word(dev, PCI_COMMAND, &command);
883 if ((command & PCI_COMMAND_MEMORY) == 0)
886 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
887 * resources covers that starting address (0 then it's good enough for
888 * us for memory space)
890 for (i = 0; i < 3; i++) {
891 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
892 hose->mem_resources[i].start == hose->mem_offset[i])
896 /* Well, it starts at 0 and we know it will collide so we may as
897 * well consider it as unassigned. That covers the Apple case.
901 /* If the BAR is non-0, then we consider it assigned */
902 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
903 if (((res->start - offset) & 0xfffffffful) != 0)
906 /* Here, we are a bit different than memory as typically IO space
907 * starting at low addresses -is- valid. What we do instead if that
908 * we consider as unassigned anything that doesn't have IO enabled
909 * in the PCI command register, and that's it.
911 pci_read_config_word(dev, PCI_COMMAND, &command);
912 if (command & PCI_COMMAND_IO)
915 /* It's starting at 0 and IO is disabled in the bridge, consider
922 /* Fixup resources of a PCI<->PCI bridge */
923 static void pcibios_fixup_bridge(struct pci_bus *bus)
925 struct resource *res;
928 struct pci_dev *dev = bus->self;
930 pci_bus_for_each_resource(bus, res, i) {
931 if (!res || !res->flags)
933 if (i >= 3 && bus->self->transparent)
936 /* If we're going to reassign everything, we can
937 * shrink the P2P resource to have size as being
938 * of 0 in order to save space.
940 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
941 res->flags |= IORESOURCE_UNSET;
947 pr_debug("PCI:%s Bus rsrc %d %pR\n", pci_name(dev), i, res);
949 /* Try to detect uninitialized P2P bridge resources,
950 * and clear them out so they get re-assigned later
952 if (pcibios_uninitialized_bridge_resource(bus, res)) {
954 pr_debug("PCI:%s (unassigned)\n", pci_name(dev));
959 void pcibios_setup_bus_self(struct pci_bus *bus)
961 struct pci_controller *phb;
963 /* Fix up the bus resources for P2P bridges */
964 if (bus->self != NULL)
965 pcibios_fixup_bridge(bus);
967 /* Platform specific bus fixups. This is currently only used
968 * by fsl_pci and I'm hoping to get rid of it at some point
970 if (ppc_md.pcibios_fixup_bus)
971 ppc_md.pcibios_fixup_bus(bus);
973 /* Setup bus DMA mappings */
974 phb = pci_bus_to_host(bus);
975 if (phb->controller_ops.dma_bus_setup)
976 phb->controller_ops.dma_bus_setup(bus);
979 static void pcibios_setup_device(struct pci_dev *dev)
981 struct pci_controller *phb;
982 /* Fixup NUMA node as it may not be setup yet by the generic
983 * code and is needed by the DMA init
985 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
987 /* Hook up default DMA ops */
988 set_dma_ops(&dev->dev, pci_dma_ops);
989 set_dma_offset(&dev->dev, PCI_DRAM_OFFSET);
991 /* Additional platform DMA/iommu setup */
992 phb = pci_bus_to_host(dev->bus);
993 if (phb->controller_ops.dma_dev_setup)
994 phb->controller_ops.dma_dev_setup(dev);
996 /* Read default IRQs and fixup if necessary */
997 pci_read_irq_line(dev);
998 if (ppc_md.pci_irq_fixup)
999 ppc_md.pci_irq_fixup(dev);
1002 int pcibios_add_device(struct pci_dev *dev)
1005 * We can only call pcibios_setup_device() after bus setup is complete,
1006 * since some of the platform specific DMA setup code depends on it.
1008 if (dev->bus->is_added)
1009 pcibios_setup_device(dev);
1011 #ifdef CONFIG_PCI_IOV
1012 if (ppc_md.pcibios_fixup_sriov)
1013 ppc_md.pcibios_fixup_sriov(dev);
1014 #endif /* CONFIG_PCI_IOV */
1019 void pcibios_setup_bus_devices(struct pci_bus *bus)
1021 struct pci_dev *dev;
1023 pr_debug("PCI: Fixup bus devices %d (%s)\n",
1024 bus->number, bus->self ? pci_name(bus->self) : "PHB");
1026 list_for_each_entry(dev, &bus->devices, bus_list) {
1027 /* Cardbus can call us to add new devices to a bus, so ignore
1028 * those who are already fully discovered
1033 pcibios_setup_device(dev);
1037 void pcibios_set_master(struct pci_dev *dev)
1039 /* No special bus mastering setup handling */
1042 void pcibios_fixup_bus(struct pci_bus *bus)
1044 /* When called from the generic PCI probe, read PCI<->PCI bridge
1045 * bases. This is -not- called when generating the PCI tree from
1046 * the OF device-tree.
1048 pci_read_bridge_bases(bus);
1050 /* Now fixup the bus bus */
1051 pcibios_setup_bus_self(bus);
1053 /* Now fixup devices on that bus */
1054 pcibios_setup_bus_devices(bus);
1056 EXPORT_SYMBOL(pcibios_fixup_bus);
1058 void pci_fixup_cardbus(struct pci_bus *bus)
1060 /* Now fixup devices on that bus */
1061 pcibios_setup_bus_devices(bus);
1065 static int skip_isa_ioresource_align(struct pci_dev *dev)
1067 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) &&
1068 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1074 * We need to avoid collisions with `mirrored' VGA ports
1075 * and other strange ISA hardware, so we always want the
1076 * addresses to be allocated in the 0x000-0x0ff region
1079 * Why? Because some silly external IO cards only decode
1080 * the low 10 bits of the IO address. The 0x00-0xff region
1081 * is reserved for motherboard devices that decode all 16
1082 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1083 * but we want to try to avoid allocating at 0x2900-0x2bff
1084 * which might have be mirrored at 0x0100-0x03ff..
1086 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1087 resource_size_t size, resource_size_t align)
1089 struct pci_dev *dev = data;
1090 resource_size_t start = res->start;
1092 if (res->flags & IORESOURCE_IO) {
1093 if (skip_isa_ioresource_align(dev))
1096 start = (start + 0x3ff) & ~0x3ff;
1101 EXPORT_SYMBOL(pcibios_align_resource);
1104 * Reparent resource children of pr that conflict with res
1105 * under res, and make res replace those children.
1107 static int reparent_resources(struct resource *parent,
1108 struct resource *res)
1110 struct resource *p, **pp;
1111 struct resource **firstpp = NULL;
1113 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1114 if (p->end < res->start)
1116 if (res->end < p->start)
1118 if (p->start < res->start || p->end > res->end)
1119 return -1; /* not completely contained */
1120 if (firstpp == NULL)
1123 if (firstpp == NULL)
1124 return -1; /* didn't find any conflicting entries? */
1125 res->parent = parent;
1126 res->child = *firstpp;
1130 for (p = res->child; p != NULL; p = p->sibling) {
1132 pr_debug("PCI: Reparented %s %pR under %s\n",
1133 p->name, p, res->name);
1139 * Handle resources of PCI devices. If the world were perfect, we could
1140 * just allocate all the resource regions and do nothing more. It isn't.
1141 * On the other hand, we cannot just re-allocate all devices, as it would
1142 * require us to know lots of host bridge internals. So we attempt to
1143 * keep as much of the original configuration as possible, but tweak it
1144 * when it's found to be wrong.
1146 * Known BIOS problems we have to work around:
1147 * - I/O or memory regions not configured
1148 * - regions configured, but not enabled in the command register
1149 * - bogus I/O addresses above 64K used
1150 * - expansion ROMs left enabled (this may sound harmless, but given
1151 * the fact the PCI specs explicitly allow address decoders to be
1152 * shared between expansion ROMs and other resource regions, it's
1153 * at least dangerous)
1156 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1157 * This gives us fixed barriers on where we can allocate.
1158 * (2) Allocate resources for all enabled devices. If there is
1159 * a collision, just mark the resource as unallocated. Also
1160 * disable expansion ROMs during this step.
1161 * (3) Try to allocate resources for disabled devices. If the
1162 * resources were assigned correctly, everything goes well,
1163 * if they weren't, they won't disturb allocation of other
1165 * (4) Assign new addresses to resources which were either
1166 * not configured at all or misconfigured. If explicitly
1167 * requested by the user, configure expansion ROM address
1171 static void pcibios_allocate_bus_resources(struct pci_bus *bus)
1175 struct resource *res, *pr;
1177 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1178 pci_domain_nr(bus), bus->number);
1180 pci_bus_for_each_resource(bus, res, i) {
1181 if (!res || !res->flags || res->start > res->end || res->parent)
1184 /* If the resource was left unset at this point, we clear it */
1185 if (res->flags & IORESOURCE_UNSET)
1186 goto clear_resource;
1188 if (bus->parent == NULL)
1189 pr = (res->flags & IORESOURCE_IO) ?
1190 &ioport_resource : &iomem_resource;
1192 pr = pci_find_parent_resource(bus->self, res);
1194 /* this happens when the generic PCI
1195 * code (wrongly) decides that this
1196 * bridge is transparent -- paulus
1202 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %pR, parent %p (%s)\n",
1203 bus->self ? pci_name(bus->self) : "PHB", bus->number,
1204 i, res, pr, (pr && pr->name) ? pr->name : "nil");
1206 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1207 struct pci_dev *dev = bus->self;
1209 if (request_resource(pr, res) == 0)
1212 * Must be a conflict with an existing entry.
1213 * Move that entry (or entries) under the
1214 * bridge resource and try again.
1216 if (reparent_resources(pr, res) == 0)
1219 if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
1220 pci_claim_bridge_resource(dev,
1221 i + PCI_BRIDGE_RESOURCES) == 0)
1224 pr_warning("PCI: Cannot allocate resource region "
1225 "%d of PCI bridge %d, will remap\n", i, bus->number);
1227 /* The resource might be figured out when doing
1228 * reassignment based on the resources required
1229 * by the downstream PCI devices. Here we set
1230 * the size of the resource to be 0 in order to
1238 list_for_each_entry(b, &bus->children, node)
1239 pcibios_allocate_bus_resources(b);
1242 static inline void alloc_resource(struct pci_dev *dev, int idx)
1244 struct resource *pr, *r = &dev->resource[idx];
1246 pr_debug("PCI: Allocating %s: Resource %d: %pR\n",
1247 pci_name(dev), idx, r);
1249 pr = pci_find_parent_resource(dev, r);
1250 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1251 request_resource(pr, r) < 0) {
1252 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1253 " of device %s, will remap\n", idx, pci_name(dev));
1255 pr_debug("PCI: parent is %p: %pR\n", pr, pr);
1256 /* We'll assign a new address later */
1257 r->flags |= IORESOURCE_UNSET;
1263 static void __init pcibios_allocate_resources(int pass)
1265 struct pci_dev *dev = NULL;
1270 for_each_pci_dev(dev) {
1271 pci_read_config_word(dev, PCI_COMMAND, &command);
1272 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1273 r = &dev->resource[idx];
1274 if (r->parent) /* Already allocated */
1276 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1277 continue; /* Not assigned at all */
1278 /* We only allocate ROMs on pass 1 just in case they
1279 * have been screwed up by firmware
1281 if (idx == PCI_ROM_RESOURCE )
1283 if (r->flags & IORESOURCE_IO)
1284 disabled = !(command & PCI_COMMAND_IO);
1286 disabled = !(command & PCI_COMMAND_MEMORY);
1287 if (pass == disabled)
1288 alloc_resource(dev, idx);
1292 r = &dev->resource[PCI_ROM_RESOURCE];
1294 /* Turn the ROM off, leave the resource region,
1295 * but keep it unregistered.
1298 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1299 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1300 pr_debug("PCI: Switching off ROM of %s\n",
1302 r->flags &= ~IORESOURCE_ROM_ENABLE;
1303 pci_write_config_dword(dev, dev->rom_base_reg,
1304 reg & ~PCI_ROM_ADDRESS_ENABLE);
1310 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1312 struct pci_controller *hose = pci_bus_to_host(bus);
1313 resource_size_t offset;
1314 struct resource *res, *pres;
1317 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
1320 if (!(hose->io_resource.flags & IORESOURCE_IO))
1322 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1323 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1324 BUG_ON(res == NULL);
1325 res->name = "Legacy IO";
1326 res->flags = IORESOURCE_IO;
1327 res->start = offset;
1328 res->end = (offset + 0xfff) & 0xfffffffful;
1329 pr_debug("Candidate legacy IO: %pR\n", res);
1330 if (request_resource(&hose->io_resource, res)) {
1332 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1333 pci_domain_nr(bus), bus->number, res);
1338 /* Check for memory */
1339 for (i = 0; i < 3; i++) {
1340 pres = &hose->mem_resources[i];
1341 offset = hose->mem_offset[i];
1342 if (!(pres->flags & IORESOURCE_MEM))
1344 pr_debug("hose mem res: %pR\n", pres);
1345 if ((pres->start - offset) <= 0xa0000 &&
1346 (pres->end - offset) >= 0xbffff)
1351 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1352 BUG_ON(res == NULL);
1353 res->name = "Legacy VGA memory";
1354 res->flags = IORESOURCE_MEM;
1355 res->start = 0xa0000 + offset;
1356 res->end = 0xbffff + offset;
1357 pr_debug("Candidate VGA memory: %pR\n", res);
1358 if (request_resource(pres, res)) {
1360 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1361 pci_domain_nr(bus), bus->number, res);
1366 void __init pcibios_resource_survey(void)
1370 /* Allocate and assign resources */
1371 list_for_each_entry(b, &pci_root_buses, node)
1372 pcibios_allocate_bus_resources(b);
1373 pcibios_allocate_resources(0);
1374 pcibios_allocate_resources(1);
1376 /* Before we start assigning unassigned resource, we try to reserve
1377 * the low IO area and the VGA memory area if they intersect the
1378 * bus available resources to avoid allocating things on top of them
1380 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1381 list_for_each_entry(b, &pci_root_buses, node)
1382 pcibios_reserve_legacy_regions(b);
1385 /* Now, if the platform didn't decide to blindly trust the firmware,
1386 * we proceed to assigning things that were left unassigned
1388 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1389 pr_debug("PCI: Assigning unassigned resources...\n");
1390 pci_assign_unassigned_resources();
1393 /* Call machine dependent fixup */
1394 if (ppc_md.pcibios_fixup)
1395 ppc_md.pcibios_fixup();
1398 /* This is used by the PCI hotplug driver to allocate resource
1399 * of newly plugged busses. We can try to consolidate with the
1400 * rest of the code later, for now, keep it as-is as our main
1401 * resource allocation function doesn't deal with sub-trees yet.
1403 void pcibios_claim_one_bus(struct pci_bus *bus)
1405 struct pci_dev *dev;
1406 struct pci_bus *child_bus;
1408 list_for_each_entry(dev, &bus->devices, bus_list) {
1411 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1412 struct resource *r = &dev->resource[i];
1414 if (r->parent || !r->start || !r->flags)
1417 pr_debug("PCI: Claiming %s: Resource %d: %pR\n",
1418 pci_name(dev), i, r);
1420 if (pci_claim_resource(dev, i) == 0)
1423 pci_claim_bridge_resource(dev, i);
1427 list_for_each_entry(child_bus, &bus->children, node)
1428 pcibios_claim_one_bus(child_bus);
1430 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1433 /* pcibios_finish_adding_to_bus
1435 * This is to be called by the hotplug code after devices have been
1436 * added to a bus, this include calling it for a PHB that is just
1439 void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1441 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1442 pci_domain_nr(bus), bus->number);
1444 /* Allocate bus and devices resources */
1445 pcibios_allocate_bus_resources(bus);
1446 pcibios_claim_one_bus(bus);
1447 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1449 pci_assign_unassigned_bridge_resources(bus->self);
1451 pci_assign_unassigned_bus_resources(bus);
1455 eeh_add_device_tree_late(bus);
1457 /* Add new devices to global lists. Register in proc, sysfs. */
1458 pci_bus_add_devices(bus);
1460 /* sysfs files should only be added after devices are added */
1461 eeh_add_sysfs_files(bus);
1463 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1465 int pcibios_enable_device(struct pci_dev *dev, int mask)
1467 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1469 if (phb->controller_ops.enable_device_hook)
1470 if (!phb->controller_ops.enable_device_hook(dev))
1473 return pci_enable_resources(dev, mask);
1476 void pcibios_disable_device(struct pci_dev *dev)
1478 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1480 if (phb->controller_ops.disable_device)
1481 phb->controller_ops.disable_device(dev);
1484 resource_size_t pcibios_io_space_offset(struct pci_controller *hose)
1486 return (unsigned long) hose->io_base_virt - _IO_BASE;
1489 static void pcibios_setup_phb_resources(struct pci_controller *hose,
1490 struct list_head *resources)
1492 struct resource *res;
1493 resource_size_t offset;
1496 /* Hookup PHB IO resource */
1497 res = &hose->io_resource;
1500 pr_info("PCI: I/O resource not set for host"
1501 " bridge %s (domain %d)\n",
1502 hose->dn->full_name, hose->global_number);
1504 offset = pcibios_io_space_offset(hose);
1506 pr_debug("PCI: PHB IO resource = %pR off 0x%08llx\n",
1507 res, (unsigned long long)offset);
1508 pci_add_resource_offset(resources, res, offset);
1511 /* Hookup PHB Memory resources */
1512 for (i = 0; i < 3; ++i) {
1513 res = &hose->mem_resources[i];
1516 printk(KERN_ERR "PCI: Memory resource 0 not set for "
1517 "host bridge %s (domain %d)\n",
1518 hose->dn->full_name, hose->global_number);
1521 offset = hose->mem_offset[i];
1524 pr_debug("PCI: PHB MEM resource %d = %pR off 0x%08llx\n", i,
1525 res, (unsigned long long)offset);
1527 pci_add_resource_offset(resources, res, offset);
1532 * Null PCI config access functions, for the case when we can't
1535 #define NULL_PCI_OP(rw, size, type) \
1537 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1539 return PCIBIOS_DEVICE_NOT_FOUND; \
1543 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1546 return PCIBIOS_DEVICE_NOT_FOUND;
1550 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1553 return PCIBIOS_DEVICE_NOT_FOUND;
1556 static struct pci_ops null_pci_ops =
1558 .read = null_read_config,
1559 .write = null_write_config,
1563 * These functions are used early on before PCI scanning is done
1564 * and all of the pci_dev and pci_bus structures have been created.
1566 static struct pci_bus *
1567 fake_pci_bus(struct pci_controller *hose, int busnr)
1569 static struct pci_bus bus;
1572 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1576 bus.ops = hose? hose->ops: &null_pci_ops;
1580 #define EARLY_PCI_OP(rw, size, type) \
1581 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1582 int devfn, int offset, type value) \
1584 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1585 devfn, offset, value); \
1588 EARLY_PCI_OP(read, byte, u8 *)
1589 EARLY_PCI_OP(read, word, u16 *)
1590 EARLY_PCI_OP(read, dword, u32 *)
1591 EARLY_PCI_OP(write, byte, u8)
1592 EARLY_PCI_OP(write, word, u16)
1593 EARLY_PCI_OP(write, dword, u32)
1595 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1598 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1601 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1603 struct pci_controller *hose = bus->sysdata;
1605 return of_node_get(hose->dn);
1609 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1610 * @hose: Pointer to the PCI host controller instance structure
1612 void pcibios_scan_phb(struct pci_controller *hose)
1614 LIST_HEAD(resources);
1615 struct pci_bus *bus;
1616 struct device_node *node = hose->dn;
1619 pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node));
1621 /* Get some IO space for the new PHB */
1622 pcibios_setup_phb_io_space(hose);
1624 /* Wire up PHB bus resources */
1625 pcibios_setup_phb_resources(hose, &resources);
1627 hose->busn.start = hose->first_busno;
1628 hose->busn.end = hose->last_busno;
1629 hose->busn.flags = IORESOURCE_BUS;
1630 pci_add_resource(&resources, &hose->busn);
1632 /* Create an empty bus for the toplevel */
1633 bus = pci_create_root_bus(hose->parent, hose->first_busno,
1634 hose->ops, hose, &resources);
1636 pr_err("Failed to create bus for PCI domain %04x\n",
1637 hose->global_number);
1638 pci_free_resource_list(&resources);
1643 /* Get probe mode and perform scan */
1644 mode = PCI_PROBE_NORMAL;
1645 if (node && hose->controller_ops.probe_mode)
1646 mode = hose->controller_ops.probe_mode(bus);
1647 pr_debug(" probe mode: %d\n", mode);
1648 if (mode == PCI_PROBE_DEVTREE)
1649 of_scan_bus(node, bus);
1651 if (mode == PCI_PROBE_NORMAL) {
1652 pci_bus_update_busn_res_end(bus, 255);
1653 hose->last_busno = pci_scan_child_bus(bus);
1654 pci_bus_update_busn_res_end(bus, hose->last_busno);
1657 /* Platform gets a chance to do some global fixups before
1658 * we proceed to resource allocation
1660 if (ppc_md.pcibios_fixup_phb)
1661 ppc_md.pcibios_fixup_phb(hose);
1663 /* Configure PCI Express settings */
1664 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
1665 struct pci_bus *child;
1666 list_for_each_entry(child, &bus->children, node)
1667 pcie_bus_configure_settings(child);
1670 EXPORT_SYMBOL_GPL(pcibios_scan_phb);
1672 static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
1674 int i, class = dev->class >> 8;
1675 /* When configured as agent, programing interface = 1 */
1676 int prog_if = dev->class & 0xf;
1678 if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
1679 class == PCI_CLASS_BRIDGE_OTHER) &&
1680 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
1682 (dev->bus->parent == NULL)) {
1683 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1684 dev->resource[i].start = 0;
1685 dev->resource[i].end = 0;
1686 dev->resource[i].flags = 0;
1690 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1691 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1693 static void fixup_vga(struct pci_dev *pdev)
1697 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1698 if ((cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) || !vga_default_device())
1699 vga_set_default_device(pdev);
1702 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1703 PCI_CLASS_DISPLAY_VGA, 8, fixup_vga);