arch/powerpc/kernel/process.c

   1 /*
   2  *  Derived from "arch/i386/kernel/process.c"
   3  *    Copyright (C) 1995  Linus Torvalds
   4  *
   5  *  Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
   6  *  Paul Mackerras (paulus@cs.anu.edu.au)
   7  *
   8  *  PowerPC version
   9  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  10  *
  11  *  This program is free software; you can redistribute it and/or
  12  *  modify it under the terms of the GNU General Public License
  13  *  as published by the Free Software Foundation; either version
  14  *  2 of the License, or (at your option) any later version.
  15  */
  16
  17 #include <linux/errno.h>
  18 #include <linux/sched.h>
  19 #include <linux/kernel.h>
  20 #include <linux/mm.h>
  21 #include <linux/smp.h>
  22 #include <linux/stddef.h>
  23 #include <linux/unistd.h>
  24 #include <linux/ptrace.h>
  25 #include <linux/slab.h>
  26 #include <linux/user.h>
  27 #include <linux/elf.h>
  28 #include <linux/prctl.h>
  29 #include <linux/init_task.h>
  30 #include <linux/export.h>
  31 #include <linux/kallsyms.h>
  32 #include <linux/mqueue.h>
  33 #include <linux/hardirq.h>
  34 #include <linux/utsname.h>
  35 #include <linux/ftrace.h>
  36 #include <linux/kernel_stat.h>
  37 #include <linux/personality.h>
  38 #include <linux/random.h>
  39 #include <linux/hw_breakpoint.h>
  40 #include <linux/uaccess.h>
  41 #include <linux/elf-randomize.h>
  42
  43 #include <asm/pgtable.h>
  44 #include <asm/io.h>
  45 #include <asm/processor.h>
  46 #include <asm/mmu.h>
  47 #include <asm/prom.h>
  48 #include <asm/machdep.h>
  49 #include <asm/time.h>
  50 #include <asm/runlatch.h>
  51 #include <asm/syscalls.h>
  52 #include <asm/switch_to.h>
  53 #include <asm/tm.h>
  54 #include <asm/debug.h>
  55 #ifdef CONFIG_PPC64
  56 #include <asm/firmware.h>
  57 #endif
  58 #include <asm/code-patching.h>
  59 #include <asm/exec.h>
  60 #include <asm/livepatch.h>
  61
  62 #include <linux/kprobes.h>
  63 #include <linux/kdebug.h>
  64
  65 /* Transactional Memory debug */
  66 #ifdef TM_DEBUG_SW
  67 #define TM_DEBUG(x...) printk(KERN_INFO x)
  68 #else
  69 #define TM_DEBUG(x...) do { } while(0)
  70 #endif
  71
  72 extern unsigned long _get_SP(void);
  73
  74 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  75 static void check_if_tm_restore_required(struct task_struct *tsk)
  76 {
  77         /*
  78          * If we are saving the current thread's registers, and the
  79          * thread is in a transactional state, set the TIF_RESTORE_TM
  80          * bit so that we know to restore the registers before
  81          * returning to userspace.
  82          */
  83         if (tsk == current && tsk->thread.regs &&
  84             MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
  85             !test_thread_flag(TIF_RESTORE_TM)) {
  86                 tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr;
  87                 set_thread_flag(TIF_RESTORE_TM);
  88         }
  89 }
  90 #else
  91 static inline void check_if_tm_restore_required(struct task_struct *tsk) { }
  92 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
  93
  94 bool strict_msr_control;
  95 EXPORT_SYMBOL(strict_msr_control);
  96
  97 static int __init enable_strict_msr_control(char *str)
  98 {
  99         strict_msr_control = true;
 100         pr_info("Enabling strict facility control\n");
 101
 102         return 0;
 103 }
 104 early_param("ppc_strict_facility_enable", enable_strict_msr_control);
 105
 106 void msr_check_and_set(unsigned long bits)
 107 {
 108         unsigned long oldmsr = mfmsr();
 109         unsigned long newmsr;
 110
 111         newmsr = oldmsr | bits;
 112
 113 #ifdef CONFIG_VSX
 114         if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
 115                 newmsr |= MSR_VSX;
 116 #endif
 117
 118         if (oldmsr != newmsr)
 119                 mtmsr_isync(newmsr);
 120 }
 121
 122 void __msr_check_and_clear(unsigned long bits)
 123 {
 124         unsigned long oldmsr = mfmsr();
 125         unsigned long newmsr;
 126
 127         newmsr = oldmsr & ~bits;
 128
 129 #ifdef CONFIG_VSX
 130         if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
 131                 newmsr &= ~MSR_VSX;
 132 #endif
 133
 134         if (oldmsr != newmsr)
 135                 mtmsr_isync(newmsr);
 136 }
 137 EXPORT_SYMBOL(__msr_check_and_clear);
 138
 139 #ifdef CONFIG_PPC_FPU
 140 void __giveup_fpu(struct task_struct *tsk)
 141 {
 142         unsigned long msr;
 143
 144         save_fpu(tsk);
 145         msr = tsk->thread.regs->msr;
 146         msr &= ~MSR_FP;
 147 #ifdef CONFIG_VSX
 148         if (cpu_has_feature(CPU_FTR_VSX))
 149                 msr &= ~MSR_VSX;
 150 #endif
 151         tsk->thread.regs->msr = msr;
 152 }
 153
 154 void giveup_fpu(struct task_struct *tsk)
 155 {
 156         check_if_tm_restore_required(tsk);
 157
 158         msr_check_and_set(MSR_FP);
 159         __giveup_fpu(tsk);
 160         msr_check_and_clear(MSR_FP);
 161 }
 162 EXPORT_SYMBOL(giveup_fpu);
 163
 164 /*
 165  * Make sure the floating-point register state in the
 166  * the thread_struct is up to date for task tsk.
 167  */
 168 void flush_fp_to_thread(struct task_struct *tsk)
 169 {
 170         if (tsk->thread.regs) {
 171                 /*
 172                  * We need to disable preemption here because if we didn't,
 173                  * another process could get scheduled after the regs->msr
 174                  * test but before we have finished saving the FP registers
 175                  * to the thread_struct.  That process could take over the
 176                  * FPU, and then when we get scheduled again we would store
 177                  * bogus values for the remaining FP registers.
 178                  */
 179                 preempt_disable();
 180                 if (tsk->thread.regs->msr & MSR_FP) {
 181                         /*
 182                          * This should only ever be called for current or
 183                          * for a stopped child process.  Since we save away
 184                          * the FP register state on context switch,
 185                          * there is something wrong if a stopped child appears
 186                          * to still have its FP state in the CPU registers.
 187                          */
 188                         BUG_ON(tsk != current);
 189                         giveup_fpu(tsk);
 190                 }
 191                 preempt_enable();
 192         }
 193 }
 194 EXPORT_SYMBOL_GPL(flush_fp_to_thread);
 195
 196 void enable_kernel_fp(void)
 197 {
 198         WARN_ON(preemptible());
 199
 200         msr_check_and_set(MSR_FP);
 201
 202         if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) {
 203                 check_if_tm_restore_required(current);
 204                 __giveup_fpu(current);
 205         }
 206 }
 207 EXPORT_SYMBOL(enable_kernel_fp);
 208
 209 static int restore_fp(struct task_struct *tsk) {
 210         if (tsk->thread.load_fp) {
 211                 load_fp_state(&current->thread.fp_state);
 212                 current->thread.load_fp++;
 213                 return 1;
 214         }
 215         return 0;
 216 }
 217 #else
 218 static int restore_fp(struct task_struct *tsk) { return 0; }
 219 #endif /* CONFIG_PPC_FPU */
 220
 221 #ifdef CONFIG_ALTIVEC
 222 #define loadvec(thr) ((thr).load_vec)
 223
 224 static void __giveup_altivec(struct task_struct *tsk)
 225 {
 226         unsigned long msr;
 227
 228         save_altivec(tsk);
 229         msr = tsk->thread.regs->msr;
 230         msr &= ~MSR_VEC;
 231 #ifdef CONFIG_VSX
 232         if (cpu_has_feature(CPU_FTR_VSX))
 233                 msr &= ~MSR_VSX;
 234 #endif
 235         tsk->thread.regs->msr = msr;
 236 }
 237
 238 void giveup_altivec(struct task_struct *tsk)
 239 {
 240         check_if_tm_restore_required(tsk);
 241
 242         msr_check_and_set(MSR_VEC);
 243         __giveup_altivec(tsk);
 244         msr_check_and_clear(MSR_VEC);
 245 }
 246 EXPORT_SYMBOL(giveup_altivec);
 247
 248 void enable_kernel_altivec(void)
 249 {
 250         WARN_ON(preemptible());
 251
 252         msr_check_and_set(MSR_VEC);
 253
 254         if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) {
 255                 check_if_tm_restore_required(current);
 256                 __giveup_altivec(current);
 257         }
 258 }
 259 EXPORT_SYMBOL(enable_kernel_altivec);
 260
 261 /*
 262  * Make sure the VMX/Altivec register state in the
 263  * the thread_struct is up to date for task tsk.
 264  */
 265 void flush_altivec_to_thread(struct task_struct *tsk)
 266 {
 267         if (tsk->thread.regs) {
 268                 preempt_disable();
 269                 if (tsk->thread.regs->msr & MSR_VEC) {
 270                         BUG_ON(tsk != current);
 271                         giveup_altivec(tsk);
 272                 }
 273                 preempt_enable();
 274         }
 275 }
 276 EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
 277
 278 static int restore_altivec(struct task_struct *tsk)
 279 {
 280         if (cpu_has_feature(CPU_FTR_ALTIVEC) && tsk->thread.load_vec) {
 281                 load_vr_state(&tsk->thread.vr_state);
 282                 tsk->thread.used_vr = 1;
 283                 tsk->thread.load_vec++;
 284
 285                 return 1;
 286         }
 287         return 0;
 288 }
 289 #else
 290 #define loadvec(thr) 0
 291 static inline int restore_altivec(struct task_struct *tsk) { return 0; }
 292 #endif /* CONFIG_ALTIVEC */
 293
 294 #ifdef CONFIG_VSX
 295 static void __giveup_vsx(struct task_struct *tsk)
 296 {
 297         if (tsk->thread.regs->msr & MSR_FP)
 298                 __giveup_fpu(tsk);
 299         if (tsk->thread.regs->msr & MSR_VEC)
 300                 __giveup_altivec(tsk);
 301         tsk->thread.regs->msr &= ~MSR_VSX;
 302 }
 303
 304 static void giveup_vsx(struct task_struct *tsk)
 305 {
 306         check_if_tm_restore_required(tsk);
 307
 308         msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
 309         __giveup_vsx(tsk);
 310         msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX);
 311 }
 312
 313 static void save_vsx(struct task_struct *tsk)
 314 {
 315         if (tsk->thread.regs->msr & MSR_FP)
 316                 save_fpu(tsk);
 317         if (tsk->thread.regs->msr & MSR_VEC)
 318                 save_altivec(tsk);
 319 }
 320
 321 void enable_kernel_vsx(void)
 322 {
 323         WARN_ON(preemptible());
 324
 325         msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
 326
 327         if (current->thread.regs && (current->thread.regs->msr & MSR_VSX)) {
 328                 check_if_tm_restore_required(current);
 329                 if (current->thread.regs->msr & MSR_FP)
 330                         __giveup_fpu(current);
 331                 if (current->thread.regs->msr & MSR_VEC)
 332                         __giveup_altivec(current);
 333                 __giveup_vsx(current);
 334         }
 335 }
 336 EXPORT_SYMBOL(enable_kernel_vsx);
 337
 338 void flush_vsx_to_thread(struct task_struct *tsk)
 339 {
 340         if (tsk->thread.regs) {
 341                 preempt_disable();
 342                 if (tsk->thread.regs->msr & MSR_VSX) {
 343                         BUG_ON(tsk != current);
 344                         giveup_vsx(tsk);
 345                 }
 346                 preempt_enable();
 347         }
 348 }
 349 EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
 350
 351 static int restore_vsx(struct task_struct *tsk)
 352 {
 353         if (cpu_has_feature(CPU_FTR_VSX)) {
 354                 tsk->thread.used_vsr = 1;
 355                 return 1;
 356         }
 357
 358         return 0;
 359 }
 360 #else
 361 static inline int restore_vsx(struct task_struct *tsk) { return 0; }
 362 static inline void save_vsx(struct task_struct *tsk) { }
 363 #endif /* CONFIG_VSX */
 364
 365 #ifdef CONFIG_SPE
 366 void giveup_spe(struct task_struct *tsk)
 367 {
 368         check_if_tm_restore_required(tsk);
 369
 370         msr_check_and_set(MSR_SPE);
 371         __giveup_spe(tsk);
 372         msr_check_and_clear(MSR_SPE);
 373 }
 374 EXPORT_SYMBOL(giveup_spe);
 375
 376 void enable_kernel_spe(void)
 377 {
 378         WARN_ON(preemptible());
 379
 380         msr_check_and_set(MSR_SPE);
 381
 382         if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) {
 383                 check_if_tm_restore_required(current);
 384                 __giveup_spe(current);
 385         }
 386 }
 387 EXPORT_SYMBOL(enable_kernel_spe);
 388
 389 void flush_spe_to_thread(struct task_struct *tsk)
 390 {
 391         if (tsk->thread.regs) {
 392                 preempt_disable();
 393                 if (tsk->thread.regs->msr & MSR_SPE) {
 394                         BUG_ON(tsk != current);
 395                         tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
 396                         giveup_spe(tsk);
 397                 }
 398                 preempt_enable();
 399         }
 400 }
 401 #endif /* CONFIG_SPE */
 402
 403 static unsigned long msr_all_available;
 404
 405 static int __init init_msr_all_available(void)
 406 {
 407 #ifdef CONFIG_PPC_FPU
 408         msr_all_available |= MSR_FP;
 409 #endif
 410 #ifdef CONFIG_ALTIVEC
 411         if (cpu_has_feature(CPU_FTR_ALTIVEC))
 412                 msr_all_available |= MSR_VEC;
 413 #endif
 414 #ifdef CONFIG_VSX
 415         if (cpu_has_feature(CPU_FTR_VSX))
 416                 msr_all_available |= MSR_VSX;
 417 #endif
 418 #ifdef CONFIG_SPE
 419         if (cpu_has_feature(CPU_FTR_SPE))
 420                 msr_all_available |= MSR_SPE;
 421 #endif
 422
 423         return 0;
 424 }
 425 early_initcall(init_msr_all_available);
 426
 427 void giveup_all(struct task_struct *tsk)
 428 {
 429         unsigned long usermsr;
 430
 431         if (!tsk->thread.regs)
 432                 return;
 433
 434         usermsr = tsk->thread.regs->msr;
 435
 436         if ((usermsr & msr_all_available) == 0)
 437                 return;
 438
 439         msr_check_and_set(msr_all_available);
 440
 441 #ifdef CONFIG_PPC_FPU
 442         if (usermsr & MSR_FP)
 443                 __giveup_fpu(tsk);
 444 #endif
 445 #ifdef CONFIG_ALTIVEC
 446         if (usermsr & MSR_VEC)
 447                 __giveup_altivec(tsk);
 448 #endif
 449 #ifdef CONFIG_VSX
 450         if (usermsr & MSR_VSX)
 451                 __giveup_vsx(tsk);
 452 #endif
 453 #ifdef CONFIG_SPE
 454         if (usermsr & MSR_SPE)
 455                 __giveup_spe(tsk);
 456 #endif
 457
 458         msr_check_and_clear(msr_all_available);
 459 }
 460 EXPORT_SYMBOL(giveup_all);
 461
 462 void restore_math(struct pt_regs *regs)
 463 {
 464         unsigned long msr;
 465
 466         if (!current->thread.load_fp && !loadvec(current->thread))
 467                 return;
 468
 469         msr = regs->msr;
 470         msr_check_and_set(msr_all_available);
 471
 472         /*
 473          * Only reload if the bit is not set in the user MSR, the bit BEING set
 474          * indicates that the registers are hot
 475          */
 476         if ((!(msr & MSR_FP)) && restore_fp(current))
 477                 msr |= MSR_FP | current->thread.fpexc_mode;
 478
 479         if ((!(msr & MSR_VEC)) && restore_altivec(current))
 480                 msr |= MSR_VEC;
 481
 482         if ((msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC) &&
 483                         restore_vsx(current)) {
 484                 msr |= MSR_VSX;
 485         }
 486
 487         msr_check_and_clear(msr_all_available);
 488
 489         regs->msr = msr;
 490 }
 491
 492 void save_all(struct task_struct *tsk)
 493 {
 494         unsigned long usermsr;
 495
 496         if (!tsk->thread.regs)
 497                 return;
 498
 499         usermsr = tsk->thread.regs->msr;
 500
 501         if ((usermsr & msr_all_available) == 0)
 502                 return;
 503
 504         msr_check_and_set(msr_all_available);
 505
 506         /*
 507          * Saving the way the register space is in hardware, save_vsx boils
 508          * down to a save_fpu() and save_altivec()
 509          */
 510         if (usermsr & MSR_VSX) {
 511                 save_vsx(tsk);
 512         } else {
 513                 if (usermsr & MSR_FP)
 514                         save_fpu(tsk);
 515
 516                 if (usermsr & MSR_VEC)
 517                         save_altivec(tsk);
 518         }
 519
 520         if (usermsr & MSR_SPE)
 521                 __giveup_spe(tsk);
 522
 523         msr_check_and_clear(msr_all_available);
 524 }
 525
 526 void flush_all_to_thread(struct task_struct *tsk)
 527 {
 528         if (tsk->thread.regs) {
 529                 preempt_disable();
 530                 BUG_ON(tsk != current);
 531                 save_all(tsk);
 532
 533 #ifdef CONFIG_SPE
 534                 if (tsk->thread.regs->msr & MSR_SPE)
 535                         tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
 536 #endif
 537
 538                 preempt_enable();
 539         }
 540 }
 541 EXPORT_SYMBOL(flush_all_to_thread);
 542
 543 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 544 void do_send_trap(struct pt_regs *regs, unsigned long address,
 545                   unsigned long error_code, int signal_code, int breakpt)
 546 {
 547         siginfo_t info;
 548
 549         current->thread.trap_nr = signal_code;
 550         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 551                         11, SIGSEGV) == NOTIFY_STOP)
 552                 return;
 553
 554         /* Deliver the signal to userspace */
 555         info.si_signo = SIGTRAP;
 556         info.si_errno = breakpt;        /* breakpoint or watchpoint id */
 557         info.si_code = signal_code;
 558         info.si_addr = (void __user *)address;
 559         force_sig_info(SIGTRAP, &info, current);
 560 }
 561 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 562 void do_break (struct pt_regs *regs, unsigned long address,
 563                     unsigned long error_code)
 564 {
 565         siginfo_t info;
 566
 567         current->thread.trap_nr = TRAP_HWBKPT;
 568         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 569                         11, SIGSEGV) == NOTIFY_STOP)
 570                 return;
 571
 572         if (debugger_break_match(regs))
 573                 return;
 574
 575         /* Clear the breakpoint */
 576         hw_breakpoint_disable();
 577
 578         /* Deliver the signal to userspace */
 579         info.si_signo = SIGTRAP;
 580         info.si_errno = 0;
 581         info.si_code = TRAP_HWBKPT;
 582         info.si_addr = (void __user *)address;
 583         force_sig_info(SIGTRAP, &info, current);
 584 }
 585 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 586
 587 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk);
 588
 589 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 590 /*
 591  * Set the debug registers back to their default "safe" values.
 592  */
 593 static void set_debug_reg_defaults(struct thread_struct *thread)
 594 {
 595         thread->debug.iac1 = thread->debug.iac2 = 0;
 596 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 597         thread->debug.iac3 = thread->debug.iac4 = 0;
 598 #endif
 599         thread->debug.dac1 = thread->debug.dac2 = 0;
 600 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 601         thread->debug.dvc1 = thread->debug.dvc2 = 0;
 602 #endif
 603         thread->debug.dbcr0 = 0;
 604 #ifdef CONFIG_BOOKE
 605         /*
 606          * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
 607          */
 608         thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
 609                         DBCR1_IAC3US | DBCR1_IAC4US;
 610         /*
 611          * Force Data Address Compare User/Supervisor bits to be User-only
 612          * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
 613          */
 614         thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
 615 #else
 616         thread->debug.dbcr1 = 0;
 617 #endif
 618 }
 619
 620 static void prime_debug_regs(struct debug_reg *debug)
 621 {
 622         /*
 623          * We could have inherited MSR_DE from userspace, since
 624          * it doesn't get cleared on exception entry.  Make sure
 625          * MSR_DE is clear before we enable any debug events.
 626          */
 627         mtmsr(mfmsr() & ~MSR_DE);
 628
 629         mtspr(SPRN_IAC1, debug->iac1);
 630         mtspr(SPRN_IAC2, debug->iac2);
 631 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 632         mtspr(SPRN_IAC3, debug->iac3);
 633         mtspr(SPRN_IAC4, debug->iac4);
 634 #endif
 635         mtspr(SPRN_DAC1, debug->dac1);
 636         mtspr(SPRN_DAC2, debug->dac2);
 637 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 638         mtspr(SPRN_DVC1, debug->dvc1);
 639         mtspr(SPRN_DVC2, debug->dvc2);
 640 #endif
 641         mtspr(SPRN_DBCR0, debug->dbcr0);
 642         mtspr(SPRN_DBCR1, debug->dbcr1);
 643 #ifdef CONFIG_BOOKE
 644         mtspr(SPRN_DBCR2, debug->dbcr2);
 645 #endif
 646 }
 647 /*
 648  * Unless neither the old or new thread are making use of the
 649  * debug registers, set the debug registers from the values
 650  * stored in the new thread.
 651  */
 652 void switch_booke_debug_regs(struct debug_reg *new_debug)
 653 {
 654         if ((current->thread.debug.dbcr0 & DBCR0_IDM)
 655                 || (new_debug->dbcr0 & DBCR0_IDM))
 656                         prime_debug_regs(new_debug);
 657 }
 658 EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
 659 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 660 #ifndef CONFIG_HAVE_HW_BREAKPOINT
 661 static void set_debug_reg_defaults(struct thread_struct *thread)
 662 {
 663         thread->hw_brk.address = 0;
 664         thread->hw_brk.type = 0;
 665         set_breakpoint(&thread->hw_brk);
 666 }
 667 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
 668 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 669
 670 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 671 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 672 {
 673         mtspr(SPRN_DAC1, dabr);
 674 #ifdef CONFIG_PPC_47x
 675         isync();
 676 #endif
 677         return 0;
 678 }
 679 #elif defined(CONFIG_PPC_BOOK3S)
 680 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 681 {
 682         mtspr(SPRN_DABR, dabr);
 683         if (cpu_has_feature(CPU_FTR_DABRX))
 684                 mtspr(SPRN_DABRX, dabrx);
 685         return 0;
 686 }
 687 #else
 688 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 689 {
 690         return -EINVAL;
 691 }
 692 #endif
 693
 694 static inline int set_dabr(struct arch_hw_breakpoint *brk)
 695 {
 696         unsigned long dabr, dabrx;
 697
 698         dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
 699         dabrx = ((brk->type >> 3) & 0x7);
 700
 701         if (ppc_md.set_dabr)
 702                 return ppc_md.set_dabr(dabr, dabrx);
 703
 704         return __set_dabr(dabr, dabrx);
 705 }
 706
 707 static inline int set_dawr(struct arch_hw_breakpoint *brk)
 708 {
 709         unsigned long dawr, dawrx, mrd;
 710
 711         dawr = brk->address;
 712
 713         dawrx  = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \
 714                                    << (63 - 58); //* read/write bits */
 715         dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \
 716                                    << (63 - 59); //* translate */
 717         dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \
 718                                    >> 3; //* PRIM bits */
 719         /* dawr length is stored in field MDR bits 48:53.  Matches range in
 720            doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
 721            0b111111=64DW.
 722            brk->len is in bytes.
 723            This aligns up to double word size, shifts and does the bias.
 724         */
 725         mrd = ((brk->len + 7) >> 3) - 1;
 726         dawrx |= (mrd & 0x3f) << (63 - 53);
 727
 728         if (ppc_md.set_dawr)
 729                 return ppc_md.set_dawr(dawr, dawrx);
 730         mtspr(SPRN_DAWR, dawr);
 731         mtspr(SPRN_DAWRX, dawrx);
 732         return 0;
 733 }
 734
 735 void __set_breakpoint(struct arch_hw_breakpoint *brk)
 736 {
 737         memcpy(this_cpu_ptr(&current_brk), brk, sizeof(*brk));
 738
 739         if (cpu_has_feature(CPU_FTR_DAWR))
 740                 set_dawr(brk);
 741         else
 742                 set_dabr(brk);
 743 }
 744
 745 void set_breakpoint(struct arch_hw_breakpoint *brk)
 746 {
 747         preempt_disable();
 748         __set_breakpoint(brk);
 749         preempt_enable();
 750 }
 751
 752 #ifdef CONFIG_PPC64
 753 DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array);
 754 #endif
 755
 756 static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
 757                               struct arch_hw_breakpoint *b)
 758 {
 759         if (a->address != b->address)
 760                 return false;
 761         if (a->type != b->type)
 762                 return false;
 763         if (a->len != b->len)
 764                 return false;
 765         return true;
 766 }
 767
 768 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 769 static void tm_reclaim_thread(struct thread_struct *thr,
 770                               struct thread_info *ti, uint8_t cause)
 771 {
 772         unsigned long msr_diff = 0;
 773
 774         /*
 775          * If FP/VSX registers have been already saved to the
 776          * thread_struct, move them to the transact_fp array.
 777          * We clear the TIF_RESTORE_TM bit since after the reclaim
 778          * the thread will no longer be transactional.
 779          */
 780         if (test_ti_thread_flag(ti, TIF_RESTORE_TM)) {
 781                 msr_diff = thr->ckpt_regs.msr & ~thr->regs->msr;
 782                 if (msr_diff & MSR_FP)
 783                         memcpy(&thr->transact_fp, &thr->fp_state,
 784                                sizeof(struct thread_fp_state));
 785                 if (msr_diff & MSR_VEC)
 786                         memcpy(&thr->transact_vr, &thr->vr_state,
 787                                sizeof(struct thread_vr_state));
 788                 clear_ti_thread_flag(ti, TIF_RESTORE_TM);
 789                 msr_diff &= MSR_FP | MSR_VEC | MSR_VSX | MSR_FE0 | MSR_FE1;
 790         }
 791
 792         /*
 793          * Use the current MSR TM suspended bit to track if we have
 794          * checkpointed state outstanding.
 795          * On signal delivery, we'd normally reclaim the checkpointed
 796          * state to obtain stack pointer (see:get_tm_stackpointer()).
 797          * This will then directly return to userspace without going
 798          * through __switch_to(). However, if the stack frame is bad,
 799          * we need to exit this thread which calls __switch_to() which
 800          * will again attempt to reclaim the already saved tm state.
 801          * Hence we need to check that we've not already reclaimed
 802          * this state.
 803          * We do this using the current MSR, rather tracking it in
 804          * some specific thread_struct bit, as it has the additional
 805          * benefit of checking for a potential TM bad thing exception.
 806          */
 807         if (!MSR_TM_SUSPENDED(mfmsr()))
 808                 return;
 809
 810         tm_reclaim(thr, thr->regs->msr, cause);
 811
 812         /* Having done the reclaim, we now have the checkpointed
 813          * FP/VSX values in the registers.  These might be valid
 814          * even if we have previously called enable_kernel_fp() or
 815          * flush_fp_to_thread(), so update thr->regs->msr to
 816          * indicate their current validity.
 817          */
 818         thr->regs->msr |= msr_diff;
 819 }
 820
 821 void tm_reclaim_current(uint8_t cause)
 822 {
 823         tm_enable();
 824         tm_reclaim_thread(&current->thread, current_thread_info(), cause);
 825 }
 826
 827 static inline void tm_reclaim_task(struct task_struct *tsk)
 828 {
 829         /* We have to work out if we're switching from/to a task that's in the
 830          * middle of a transaction.
 831          *
 832          * In switching we need to maintain a 2nd register state as
 833          * oldtask->thread.ckpt_regs.  We tm_reclaim(oldproc); this saves the
 834          * checkpointed (tbegin) state in ckpt_regs and saves the transactional
 835          * (current) FPRs into oldtask->thread.transact_fpr[].
 836          *
 837          * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
 838          */
 839         struct thread_struct *thr = &tsk->thread;
 840
 841         if (!thr->regs)
 842                 return;
 843
 844         if (!MSR_TM_ACTIVE(thr->regs->msr))
 845                 goto out_and_saveregs;
 846
 847         /* Stash the original thread MSR, as giveup_fpu et al will
 848          * modify it.  We hold onto it to see whether the task used
 849          * FP & vector regs.  If the TIF_RESTORE_TM flag is set,
 850          * ckpt_regs.msr is already set.
 851          */
 852         if (!test_ti_thread_flag(task_thread_info(tsk), TIF_RESTORE_TM))
 853                 thr->ckpt_regs.msr = thr->regs->msr;
 854
 855         TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
 856                  "ccr=%lx, msr=%lx, trap=%lx)\n",
 857                  tsk->pid, thr->regs->nip,
 858                  thr->regs->ccr, thr->regs->msr,
 859                  thr->regs->trap);
 860
 861         tm_reclaim_thread(thr, task_thread_info(tsk), TM_CAUSE_RESCHED);
 862
 863         TM_DEBUG("--- tm_reclaim on pid %d complete\n",
 864                  tsk->pid);
 865
 866 out_and_saveregs:
 867         /* Always save the regs here, even if a transaction's not active.
 868          * This context-switches a thread's TM info SPRs.  We do it here to
 869          * be consistent with the restore path (in recheckpoint) which
 870          * cannot happen later in _switch().
 871          */
 872         tm_save_sprs(thr);
 873 }
 874
 875 extern void __tm_recheckpoint(struct thread_struct *thread,
 876                               unsigned long orig_msr);
 877
 878 void tm_recheckpoint(struct thread_struct *thread,
 879                      unsigned long orig_msr)
 880 {
 881         unsigned long flags;
 882
 883         /* We really can't be interrupted here as the TEXASR registers can't
 884          * change and later in the trecheckpoint code, we have a userspace R1.
 885          * So let's hard disable over this region.
 886          */
 887         local_irq_save(flags);
 888         hard_irq_disable();
 889
 890         /* The TM SPRs are restored here, so that TEXASR.FS can be set
 891          * before the trecheckpoint and no explosion occurs.
 892          */
 893         tm_restore_sprs(thread);
 894
 895         __tm_recheckpoint(thread, orig_msr);
 896
 897         local_irq_restore(flags);
 898 }
 899
 900 static inline void tm_recheckpoint_new_task(struct task_struct *new)
 901 {
 902         unsigned long msr;
 903
 904         if (!cpu_has_feature(CPU_FTR_TM))
 905                 return;
 906
 907         /* Recheckpoint the registers of the thread we're about to switch to.
 908          *
 909          * If the task was using FP, we non-lazily reload both the original and
 910          * the speculative FP register states.  This is because the kernel
 911          * doesn't see if/when a TM rollback occurs, so if we take an FP
 912          * unavoidable later, we are unable to determine which set of FP regs
 913          * need to be restored.
 914          */
 915         if (!new->thread.regs)
 916                 return;
 917
 918         if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
 919                 tm_restore_sprs(&new->thread);
 920                 return;
 921         }
 922         msr = new->thread.ckpt_regs.msr;
 923         /* Recheckpoint to restore original checkpointed register state. */
 924         TM_DEBUG("*** tm_recheckpoint of pid %d "
 925                  "(new->msr 0x%lx, new->origmsr 0x%lx)\n",
 926                  new->pid, new->thread.regs->msr, msr);
 927
 928         /* This loads the checkpointed FP/VEC state, if used */
 929         tm_recheckpoint(&new->thread, msr);
 930
 931         /* This loads the speculative FP/VEC state, if used */
 932         if (msr & MSR_FP) {
 933                 do_load_up_transact_fpu(&new->thread);
 934                 new->thread.regs->msr |=
 935                         (MSR_FP | new->thread.fpexc_mode);
 936         }
 937 #ifdef CONFIG_ALTIVEC
 938         if (msr & MSR_VEC) {
 939                 do_load_up_transact_altivec(&new->thread);
 940                 new->thread.regs->msr |= MSR_VEC;
 941         }
 942 #endif
 943         /* We may as well turn on VSX too since all the state is restored now */
 944         if (msr & MSR_VSX)
 945                 new->thread.regs->msr |= MSR_VSX;
 946
 947         TM_DEBUG("*** tm_recheckpoint of pid %d complete "
 948                  "(kernel msr 0x%lx)\n",
 949                  new->pid, mfmsr());
 950 }
 951
 952 static inline void __switch_to_tm(struct task_struct *prev)
 953 {
 954         if (cpu_has_feature(CPU_FTR_TM)) {
 955                 tm_enable();
 956                 tm_reclaim_task(prev);
 957         }
 958 }
 959
 960 /*
 961  * This is called if we are on the way out to userspace and the
 962  * TIF_RESTORE_TM flag is set.  It checks if we need to reload
 963  * FP and/or vector state and does so if necessary.
 964  * If userspace is inside a transaction (whether active or
 965  * suspended) and FP/VMX/VSX instructions have ever been enabled
 966  * inside that transaction, then we have to keep them enabled
 967  * and keep the FP/VMX/VSX state loaded while ever the transaction
 968  * continues.  The reason is that if we didn't, and subsequently
 969  * got a FP/VMX/VSX unavailable interrupt inside a transaction,
 970  * we don't know whether it's the same transaction, and thus we
 971  * don't know which of the checkpointed state and the transactional
 972  * state to use.
 973  */
 974 void restore_tm_state(struct pt_regs *regs)
 975 {
 976         unsigned long msr_diff;
 977
 978         clear_thread_flag(TIF_RESTORE_TM);
 979         if (!MSR_TM_ACTIVE(regs->msr))
 980                 return;
 981
 982         msr_diff = current->thread.ckpt_regs.msr & ~regs->msr;
 983         msr_diff &= MSR_FP | MSR_VEC | MSR_VSX;
 984
 985         restore_math(regs);
 986
 987         regs->msr |= msr_diff;
 988 }
 989
 990 #else
 991 #define tm_recheckpoint_new_task(new)
 992 #define __switch_to_tm(prev)
 993 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
 994
 995 static inline void save_sprs(struct thread_struct *t)
 996 {
 997 #ifdef CONFIG_ALTIVEC
 998         if (cpu_has_feature(CPU_FTR_ALTIVEC))
 999                 t->vrsave = mfspr(SPRN_VRSAVE);
1000 #endif
1001 #ifdef CONFIG_PPC_BOOK3S_64
1002         if (cpu_has_feature(CPU_FTR_DSCR))
1003                 t->dscr = mfspr(SPRN_DSCR);
1004
1005         if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1006                 t->bescr = mfspr(SPRN_BESCR);
1007                 t->ebbhr = mfspr(SPRN_EBBHR);
1008                 t->ebbrr = mfspr(SPRN_EBBRR);
1009
1010                 t->fscr = mfspr(SPRN_FSCR);
1011
1012                 /*
1013                  * Note that the TAR is not available for use in the kernel.
1014                  * (To provide this, the TAR should be backed up/restored on
1015                  * exception entry/exit instead, and be in pt_regs.  FIXME,
1016                  * this should be in pt_regs anyway (for debug).)
1017                  */
1018                 t->tar = mfspr(SPRN_TAR);
1019         }
1020
1021         if (cpu_has_feature(CPU_FTR_ARCH_300)) {
1022                 /* Conditionally save Load Monitor registers, if enabled */
1023                 if (t->fscr & FSCR_LM) {
1024                         t->lmrr = mfspr(SPRN_LMRR);
1025                         t->lmser = mfspr(SPRN_LMSER);
1026                 }
1027         }
1028 #endif
1029 }
1030
1031 static inline void restore_sprs(struct thread_struct *old_thread,
1032                                 struct thread_struct *new_thread)
1033 {
1034 #ifdef CONFIG_ALTIVEC
1035         if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
1036             old_thread->vrsave != new_thread->vrsave)
1037                 mtspr(SPRN_VRSAVE, new_thread->vrsave);
1038 #endif
1039 #ifdef CONFIG_PPC_BOOK3S_64
1040         if (cpu_has_feature(CPU_FTR_DSCR)) {
1041                 u64 dscr = get_paca()->dscr_default;
1042                 if (new_thread->dscr_inherit)
1043                         dscr = new_thread->dscr;
1044
1045                 if (old_thread->dscr != dscr)
1046                         mtspr(SPRN_DSCR, dscr);
1047         }
1048
1049         if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1050                 if (old_thread->bescr != new_thread->bescr)
1051                         mtspr(SPRN_BESCR, new_thread->bescr);
1052                 if (old_thread->ebbhr != new_thread->ebbhr)
1053                         mtspr(SPRN_EBBHR, new_thread->ebbhr);
1054                 if (old_thread->ebbrr != new_thread->ebbrr)
1055                         mtspr(SPRN_EBBRR, new_thread->ebbrr);
1056
1057                 if (old_thread->fscr != new_thread->fscr)
1058                         mtspr(SPRN_FSCR, new_thread->fscr);
1059
1060                 if (old_thread->tar != new_thread->tar)
1061                         mtspr(SPRN_TAR, new_thread->tar);
1062         }
1063
1064         if (cpu_has_feature(CPU_FTR_ARCH_300)) {
1065                 /* Conditionally restore Load Monitor registers, if enabled */
1066                 if (new_thread->fscr & FSCR_LM) {
1067                         if (old_thread->lmrr != new_thread->lmrr)
1068                                 mtspr(SPRN_LMRR, new_thread->lmrr);
1069                         if (old_thread->lmser != new_thread->lmser)
1070                                 mtspr(SPRN_LMSER, new_thread->lmser);
1071                 }
1072         }
1073 #endif
1074 }
1075
1076 struct task_struct *__switch_to(struct task_struct *prev,
1077         struct task_struct *new)
1078 {
1079         struct thread_struct *new_thread, *old_thread;
1080         struct task_struct *last;
1081 #ifdef CONFIG_PPC_BOOK3S_64
1082         struct ppc64_tlb_batch *batch;
1083 #endif
1084
1085         new_thread = &new->thread;
1086         old_thread = &current->thread;
1087
1088         WARN_ON(!irqs_disabled());
1089
1090 #ifdef CONFIG_PPC64
1091         /*
1092          * Collect processor utilization data per process
1093          */
1094         if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
1095                 struct cpu_usage *cu = this_cpu_ptr(&cpu_usage_array);
1096                 long unsigned start_tb, current_tb;
1097                 start_tb = old_thread->start_tb;
1098                 cu->current_tb = current_tb = mfspr(SPRN_PURR);
1099                 old_thread->accum_tb += (current_tb - start_tb);
1100                 new_thread->start_tb = current_tb;
1101         }
1102 #endif /* CONFIG_PPC64 */
1103
1104 #ifdef CONFIG_PPC_STD_MMU_64
1105         batch = this_cpu_ptr(&ppc64_tlb_batch);
1106         if (batch->active) {
1107                 current_thread_info()->local_flags |= _TLF_LAZY_MMU;
1108                 if (batch->index)
1109                         __flush_tlb_pending(batch);
1110                 batch->active = 0;
1111         }
1112 #endif /* CONFIG_PPC_STD_MMU_64 */
1113
1114 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1115         switch_booke_debug_regs(&new->thread.debug);
1116 #else
1117 /*
1118  * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
1119  * schedule DABR
1120  */
1121 #ifndef CONFIG_HAVE_HW_BREAKPOINT
1122         if (unlikely(!hw_brk_match(this_cpu_ptr(&current_brk), &new->thread.hw_brk)))
1123                 __set_breakpoint(&new->thread.hw_brk);
1124 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1125 #endif
1126
1127         /*
1128          * We need to save SPRs before treclaim/trecheckpoint as these will
1129          * change a number of them.
1130          */
1131         save_sprs(&prev->thread);
1132
1133         __switch_to_tm(prev);
1134
1135         /* Save FPU, Altivec, VSX and SPE state */
1136         giveup_all(prev);
1137
1138         /*
1139          * We can't take a PMU exception inside _switch() since there is a
1140          * window where the kernel stack SLB and the kernel stack are out
1141          * of sync. Hard disable here.
1142          */
1143         hard_irq_disable();
1144
1145         tm_recheckpoint_new_task(new);
1146
1147         /*
1148          * Call restore_sprs() before calling _switch(). If we move it after
1149          * _switch() then we miss out on calling it for new tasks. The reason
1150          * for this is we manually create a stack frame for new tasks that
1151          * directly returns through ret_from_fork() or
1152          * ret_from_kernel_thread(). See copy_thread() for details.
1153          */
1154         restore_sprs(old_thread, new_thread);
1155
1156         last = _switch(old_thread, new_thread);
1157
1158 #ifdef CONFIG_PPC_STD_MMU_64
1159         if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
1160                 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
1161                 batch = this_cpu_ptr(&ppc64_tlb_batch);
1162                 batch->active = 1;
1163         }
1164
1165         if (current_thread_info()->task->thread.regs)
1166                 restore_math(current_thread_info()->task->thread.regs);
1167 #endif /* CONFIG_PPC_STD_MMU_64 */
1168
1169         return last;
1170 }
1171
1172 static int instructions_to_print = 16;
1173
1174 static void show_instructions(struct pt_regs *regs)
1175 {
1176         int i;
1177         unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 *
1178                         sizeof(int));
1179
1180         printk("Instruction dump:");
1181
1182         for (i = 0; i < instructions_to_print; i++) {
1183                 int instr;
1184
1185                 if (!(i % 8))
1186                         printk("\n");
1187
1188 #if !defined(CONFIG_BOOKE)
1189                 /* If executing with the IMMU off, adjust pc rather
1190                  * than print XXXXXXXX.
1191                  */
1192                 if (!(regs->msr & MSR_IR))
1193                         pc = (unsigned long)phys_to_virt(pc);
1194 #endif
1195
1196                 if (!__kernel_text_address(pc) ||
1197                      probe_kernel_address((unsigned int __user *)pc, instr)) {
1198                         printk(KERN_CONT "XXXXXXXX ");
1199                 } else {
1200                         if (regs->nip == pc)
1201                                 printk(KERN_CONT "<%08x> ", instr);
1202                         else
1203                                 printk(KERN_CONT "%08x ", instr);
1204                 }
1205
1206                 pc += sizeof(int);
1207         }
1208
1209         printk("\n");
1210 }
1211
1212 struct regbit {
1213         unsigned long bit;
1214         const char *name;
1215 };
1216
1217 static struct regbit msr_bits[] = {
1218 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
1219         {MSR_SF,        "SF"},
1220         {MSR_HV,        "HV"},
1221 #endif
1222         {MSR_VEC,       "VEC"},
1223         {MSR_VSX,       "VSX"},
1224 #ifdef CONFIG_BOOKE
1225         {MSR_CE,        "CE"},
1226 #endif
1227         {MSR_EE,        "EE"},
1228         {MSR_PR,        "PR"},
1229         {MSR_FP,        "FP"},
1230         {MSR_ME,        "ME"},
1231 #ifdef CONFIG_BOOKE
1232         {MSR_DE,        "DE"},
1233 #else
1234         {MSR_SE,        "SE"},
1235         {MSR_BE,        "BE"},
1236 #endif
1237         {MSR_IR,        "IR"},
1238         {MSR_DR,        "DR"},
1239         {MSR_PMM,       "PMM"},
1240 #ifndef CONFIG_BOOKE
1241         {MSR_RI,        "RI"},
1242         {MSR_LE,        "LE"},
1243 #endif
1244         {0,             NULL}
1245 };
1246
1247 static void print_bits(unsigned long val, struct regbit *bits, const char *sep)
1248 {
1249         const char *s = "";
1250
1251         for (; bits->bit; ++bits)
1252                 if (val & bits->bit) {
1253                         printk("%s%s", s, bits->name);
1254                         s = sep;
1255                 }
1256 }
1257
1258 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1259 static struct regbit msr_tm_bits[] = {
1260         {MSR_TS_T,      "T"},
1261         {MSR_TS_S,      "S"},
1262         {MSR_TM,        "E"},
1263         {0,             NULL}
1264 };
1265
1266 static void print_tm_bits(unsigned long val)
1267 {
1268 /*
1269  * This only prints something if at least one of the TM bit is set.
1270  * Inside the TM[], the output means:
1271  *   E: Enabled         (bit 32)
1272  *   S: Suspended       (bit 33)
1273  *   T: Transactional   (bit 34)
1274  */
1275         if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) {
1276                 printk(",TM[");
1277                 print_bits(val, msr_tm_bits, "");
1278                 printk("]");
1279         }
1280 }
1281 #else
1282 static void print_tm_bits(unsigned long val) {}
1283 #endif
1284
1285 static void print_msr_bits(unsigned long val)
1286 {
1287         printk("<");
1288         print_bits(val, msr_bits, ",");
1289         print_tm_bits(val);
1290         printk(">");
1291 }
1292
1293 #ifdef CONFIG_PPC64
1294 #define REG             "%016lx"
1295 #define REGS_PER_LINE   4
1296 #define LAST_VOLATILE   13
1297 #else
1298 #define REG             "%08lx"
1299 #define REGS_PER_LINE   8
1300 #define LAST_VOLATILE   12
1301 #endif
1302
1303 void show_regs(struct pt_regs * regs)
1304 {
1305         int i, trap;
1306
1307         show_regs_print_info(KERN_DEFAULT);
1308
1309         printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
1310                regs->nip, regs->link, regs->ctr);
1311         printk("REGS: %p TRAP: %04lx   %s  (%s)\n",
1312                regs, regs->trap, print_tainted(), init_utsname()->release);
1313         printk("MSR: "REG" ", regs->msr);
1314         print_msr_bits(regs->msr);
1315         printk("  CR: %08lx  XER: %08lx\n", regs->ccr, regs->xer);
1316         trap = TRAP(regs);
1317         if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
1318                 printk("CFAR: "REG" ", regs->orig_gpr3);
1319         if (trap == 0x200 || trap == 0x300 || trap == 0x600)
1320 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1321                 printk("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
1322 #else
1323                 printk("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
1324 #endif
1325 #ifdef CONFIG_PPC64
1326         printk("SOFTE: %ld ", regs->softe);
1327 #endif
1328 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1329         if (MSR_TM_ACTIVE(regs->msr))
1330                 printk("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
1331 #endif
1332
1333         for (i = 0;  i < 32;  i++) {
1334                 if ((i % REGS_PER_LINE) == 0)
1335                         printk("\nGPR%02d: ", i);
1336                 printk(REG " ", regs->gpr[i]);
1337                 if (i == LAST_VOLATILE && !FULL_REGS(regs))
1338                         break;
1339         }
1340         printk("\n");
1341 #ifdef CONFIG_KALLSYMS
1342         /*
1343          * Lookup NIP late so we have the best change of getting the
1344          * above info out without failing
1345          */
1346         printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
1347         printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
1348 #endif
1349         show_stack(current, (unsigned long *) regs->gpr[1]);
1350         if (!user_mode(regs))
1351                 show_instructions(regs);
1352 }
1353
1354 void flush_thread(void)
1355 {
1356 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1357         flush_ptrace_hw_breakpoint(current);
1358 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1359         set_debug_reg_defaults(&current->thread);
1360 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1361 }
1362
1363 void
1364 release_thread(struct task_struct *t)
1365 {
1366 }
1367
1368 /*
1369  * this gets called so that we can store coprocessor state into memory and
1370  * copy the current task into the new thread.
1371  */
1372 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
1373 {
1374         flush_all_to_thread(src);
1375         /*
1376          * Flush TM state out so we can copy it.  __switch_to_tm() does this
1377          * flush but it removes the checkpointed state from the current CPU and
1378          * transitions the CPU out of TM mode.  Hence we need to call
1379          * tm_recheckpoint_new_task() (on the same task) to restore the
1380          * checkpointed state back and the TM mode.
1381          */
1382         __switch_to_tm(src);
1383         tm_recheckpoint_new_task(src);
1384
1385         *dst = *src;
1386
1387         clear_task_ebb(dst);
1388
1389         return 0;
1390 }
1391
1392 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
1393 {
1394 #ifdef CONFIG_PPC_STD_MMU_64
1395         unsigned long sp_vsid;
1396         unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
1397
1398         if (radix_enabled())
1399                 return;
1400
1401         if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1402                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
1403                         << SLB_VSID_SHIFT_1T;
1404         else
1405                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
1406                         << SLB_VSID_SHIFT;
1407         sp_vsid |= SLB_VSID_KERNEL | llp;
1408         p->thread.ksp_vsid = sp_vsid;
1409 #endif
1410 }
1411
1412 /*
1413  * Copy a thread..
1414  */
1415
1416 /*
1417  * Copy architecture-specific thread state
1418  */
1419 int copy_thread(unsigned long clone_flags, unsigned long usp,
1420                 unsigned long kthread_arg, struct task_struct *p)
1421 {
1422         struct pt_regs *childregs, *kregs;
1423         extern void ret_from_fork(void);
1424         extern void ret_from_kernel_thread(void);
1425         void (*f)(void);
1426         unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
1427         struct thread_info *ti = task_thread_info(p);
1428
1429         klp_init_thread_info(ti);
1430
1431         /* Copy registers */
1432         sp -= sizeof(struct pt_regs);
1433         childregs = (struct pt_regs *) sp;
1434         if (unlikely(p->flags & PF_KTHREAD)) {
1435                 /* kernel thread */
1436                 memset(childregs, 0, sizeof(struct pt_regs));
1437                 childregs->gpr[1] = sp + sizeof(struct pt_regs);
1438                 /* function */
1439                 if (usp)
1440                         childregs->gpr[14] = ppc_function_entry((void *)usp);
1441 #ifdef CONFIG_PPC64
1442                 clear_tsk_thread_flag(p, TIF_32BIT);
1443                 childregs->softe = 1;
1444 #endif
1445                 childregs->gpr[15] = kthread_arg;
1446                 p->thread.regs = NULL;  /* no user register state */
1447                 ti->flags |= _TIF_RESTOREALL;
1448                 f = ret_from_kernel_thread;
1449         } else {
1450                 /* user thread */
1451                 struct pt_regs *regs = current_pt_regs();
1452                 CHECK_FULL_REGS(regs);
1453                 *childregs = *regs;
1454                 if (usp)
1455                         childregs->gpr[1] = usp;
1456                 p->thread.regs = childregs;
1457                 childregs->gpr[3] = 0;  /* Result from fork() */
1458                 if (clone_flags & CLONE_SETTLS) {
1459 #ifdef CONFIG_PPC64
1460                         if (!is_32bit_task())
1461                                 childregs->gpr[13] = childregs->gpr[6];
1462                         else
1463 #endif
1464                                 childregs->gpr[2] = childregs->gpr[6];
1465                 }
1466
1467                 f = ret_from_fork;
1468         }
1469         childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX);
1470         sp -= STACK_FRAME_OVERHEAD;
1471
1472         /*
1473          * The way this works is that at some point in the future
1474          * some task will call _switch to switch to the new task.
1475          * That will pop off the stack frame created below and start
1476          * the new task running at ret_from_fork.  The new task will
1477          * do some house keeping and then return from the fork or clone
1478          * system call, using the stack frame created above.
1479          */
1480         ((unsigned long *)sp)[0] = 0;
1481         sp -= sizeof(struct pt_regs);
1482         kregs = (struct pt_regs *) sp;
1483         sp -= STACK_FRAME_OVERHEAD;
1484         p->thread.ksp = sp;
1485 #ifdef CONFIG_PPC32
1486         p->thread.ksp_limit = (unsigned long)task_stack_page(p) +
1487                                 _ALIGN_UP(sizeof(struct thread_info), 16);
1488 #endif
1489 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1490         p->thread.ptrace_bps[0] = NULL;
1491 #endif
1492
1493         p->thread.fp_save_area = NULL;
1494 #ifdef CONFIG_ALTIVEC
1495         p->thread.vr_save_area = NULL;
1496 #endif
1497
1498         setup_ksp_vsid(p, sp);
1499
1500 #ifdef CONFIG_PPC64
1501         if (cpu_has_feature(CPU_FTR_DSCR)) {
1502                 p->thread.dscr_inherit = current->thread.dscr_inherit;
1503                 p->thread.dscr = mfspr(SPRN_DSCR);
1504         }
1505         if (cpu_has_feature(CPU_FTR_HAS_PPR))
1506                 p->thread.ppr = INIT_PPR;
1507 #endif
1508         kregs->nip = ppc_function_entry(f);
1509         return 0;
1510 }
1511
1512 /*
1513  * Set up a thread for executing a new program
1514  */
1515 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
1516 {
1517 #ifdef CONFIG_PPC64
1518         unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
1519 #endif
1520
1521         /*
1522          * If we exec out of a kernel thread then thread.regs will not be
1523          * set.  Do it now.
1524          */
1525         if (!current->thread.regs) {
1526                 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
1527                 current->thread.regs = regs - 1;
1528         }
1529
1530 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1531         /*
1532          * Clear any transactional state, we're exec()ing. The cause is
1533          * not important as there will never be a recheckpoint so it's not
1534          * user visible.
1535          */
1536         if (MSR_TM_SUSPENDED(mfmsr()))
1537                 tm_reclaim_current(0);
1538 #endif
1539
1540         memset(regs->gpr, 0, sizeof(regs->gpr));
1541         regs->ctr = 0;
1542         regs->link = 0;
1543         regs->xer = 0;
1544         regs->ccr = 0;
1545         regs->gpr[1] = sp;
1546
1547         /*
1548          * We have just cleared all the nonvolatile GPRs, so make
1549          * FULL_REGS(regs) return true.  This is necessary to allow
1550          * ptrace to examine the thread immediately after exec.
1551          */
1552         regs->trap &= ~1UL;
1553
1554 #ifdef CONFIG_PPC32
1555         regs->mq = 0;
1556         regs->nip = start;
1557         regs->msr = MSR_USER;
1558 #else
1559         if (!is_32bit_task()) {
1560                 unsigned long entry;
1561
1562                 if (is_elf2_task()) {
1563                         /* Look ma, no function descriptors! */
1564                         entry = start;
1565
1566                         /*
1567                          * Ulrich says:
1568                          *   The latest iteration of the ABI requires that when
1569                          *   calling a function (at its global entry point),
1570                          *   the caller must ensure r12 holds the entry point
1571                          *   address (so that the function can quickly
1572                          *   establish addressability).
1573                          */
1574                         regs->gpr[12] = start;
1575                         /* Make sure that's restored on entry to userspace. */
1576                         set_thread_flag(TIF_RESTOREALL);
1577                 } else {
1578                         unsigned long toc;
1579
1580                         /* start is a relocated pointer to the function
1581                          * descriptor for the elf _start routine.  The first
1582                          * entry in the function descriptor is the entry
1583                          * address of _start and the second entry is the TOC
1584                          * value we need to use.
1585                          */
1586                         __get_user(entry, (unsigned long __user *)start);
1587                         __get_user(toc, (unsigned long __user *)start+1);
1588
1589                         /* Check whether the e_entry function descriptor entries
1590                          * need to be relocated before we can use them.
1591                          */
1592                         if (load_addr != 0) {
1593                                 entry += load_addr;
1594                                 toc   += load_addr;
1595                         }
1596                         regs->gpr[2] = toc;
1597                 }
1598                 regs->nip = entry;
1599                 regs->msr = MSR_USER64;
1600         } else {
1601                 regs->nip = start;
1602                 regs->gpr[2] = 0;
1603                 regs->msr = MSR_USER32;
1604         }
1605 #endif
1606 #ifdef CONFIG_VSX
1607         current->thread.used_vsr = 0;
1608 #endif
1609         memset(&current->thread.fp_state, 0, sizeof(current->thread.fp_state));
1610         current->thread.fp_save_area = NULL;
1611 #ifdef CONFIG_ALTIVEC
1612         memset(&current->thread.vr_state, 0, sizeof(current->thread.vr_state));
1613         current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */
1614         current->thread.vr_save_area = NULL;
1615         current->thread.vrsave = 0;
1616         current->thread.used_vr = 0;
1617 #endif /* CONFIG_ALTIVEC */
1618 #ifdef CONFIG_SPE
1619         memset(current->thread.evr, 0, sizeof(current->thread.evr));
1620         current->thread.acc = 0;
1621         current->thread.spefscr = 0;
1622         current->thread.used_spe = 0;
1623 #endif /* CONFIG_SPE */
1624 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1625         if (cpu_has_feature(CPU_FTR_TM))
1626                 regs->msr |= MSR_TM;
1627         current->thread.tm_tfhar = 0;
1628         current->thread.tm_texasr = 0;
1629         current->thread.tm_tfiar = 0;
1630 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1631 }
1632 EXPORT_SYMBOL(start_thread);
1633
1634 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1635                 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1636
1637 int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
1638 {
1639         struct pt_regs *regs = tsk->thread.regs;
1640
1641         /* This is a bit hairy.  If we are an SPE enabled  processor
1642          * (have embedded fp) we store the IEEE exception enable flags in
1643          * fpexc_mode.  fpexc_mode is also used for setting FP exception
1644          * mode (asyn, precise, disabled) for 'Classic' FP. */
1645         if (val & PR_FP_EXC_SW_ENABLE) {
1646 #ifdef CONFIG_SPE
1647                 if (cpu_has_feature(CPU_FTR_SPE)) {
1648                         /*
1649                          * When the sticky exception bits are set
1650                          * directly by userspace, it must call prctl
1651                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1652                          * in the existing prctl settings) or
1653                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1654                          * the bits being set).  <fenv.h> functions
1655                          * saving and restoring the whole
1656                          * floating-point environment need to do so
1657                          * anyway to restore the prctl settings from
1658                          * the saved environment.
1659                          */
1660                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1661                         tsk->thread.fpexc_mode = val &
1662                                 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
1663                         return 0;
1664                 } else {
1665                         return -EINVAL;
1666                 }
1667 #else
1668                 return -EINVAL;
1669 #endif
1670         }
1671
1672         /* on a CONFIG_SPE this does not hurt us.  The bits that
1673          * __pack_fe01 use do not overlap with bits used for
1674          * PR_FP_EXC_SW_ENABLE.  Additionally, the MSR[FE0,FE1] bits
1675          * on CONFIG_SPE implementations are reserved so writing to
1676          * them does not change anything */
1677         if (val > PR_FP_EXC_PRECISE)
1678                 return -EINVAL;
1679         tsk->thread.fpexc_mode = __pack_fe01(val);
1680         if (regs != NULL && (regs->msr & MSR_FP) != 0)
1681                 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
1682                         | tsk->thread.fpexc_mode;
1683         return 0;
1684 }
1685
1686 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
1687 {
1688         unsigned int val;
1689
1690         if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
1691 #ifdef CONFIG_SPE
1692                 if (cpu_has_feature(CPU_FTR_SPE)) {
1693                         /*
1694                          * When the sticky exception bits are set
1695                          * directly by userspace, it must call prctl
1696                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1697                          * in the existing prctl settings) or
1698                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1699                          * the bits being set).  <fenv.h> functions
1700                          * saving and restoring the whole
1701                          * floating-point environment need to do so
1702                          * anyway to restore the prctl settings from
1703                          * the saved environment.
1704                          */
1705                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1706                         val = tsk->thread.fpexc_mode;
1707                 } else
1708                         return -EINVAL;
1709 #else
1710                 return -EINVAL;
1711 #endif
1712         else
1713                 val = __unpack_fe01(tsk->thread.fpexc_mode);
1714         return put_user(val, (unsigned int __user *) adr);
1715 }
1716
1717 int set_endian(struct task_struct *tsk, unsigned int val)
1718 {
1719         struct pt_regs *regs = tsk->thread.regs;
1720
1721         if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
1722             (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
1723                 return -EINVAL;
1724
1725         if (regs == NULL)
1726                 return -EINVAL;
1727
1728         if (val == PR_ENDIAN_BIG)
1729                 regs->msr &= ~MSR_LE;
1730         else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
1731                 regs->msr |= MSR_LE;
1732         else
1733                 return -EINVAL;
1734
1735         return 0;
1736 }
1737
1738 int get_endian(struct task_struct *tsk, unsigned long adr)
1739 {
1740         struct pt_regs *regs = tsk->thread.regs;
1741         unsigned int val;
1742
1743         if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
1744             !cpu_has_feature(CPU_FTR_REAL_LE))
1745                 return -EINVAL;
1746
1747         if (regs == NULL)
1748                 return -EINVAL;
1749
1750         if (regs->msr & MSR_LE) {
1751                 if (cpu_has_feature(CPU_FTR_REAL_LE))
1752                         val = PR_ENDIAN_LITTLE;
1753                 else
1754                         val = PR_ENDIAN_PPC_LITTLE;
1755         } else
1756                 val = PR_ENDIAN_BIG;
1757
1758         return put_user(val, (unsigned int __user *)adr);
1759 }
1760
1761 int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
1762 {
1763         tsk->thread.align_ctl = val;
1764         return 0;
1765 }
1766
1767 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
1768 {
1769         return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
1770 }
1771
1772 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
1773                                   unsigned long nbytes)
1774 {
1775         unsigned long stack_page;
1776         unsigned long cpu = task_cpu(p);
1777
1778         /*
1779          * Avoid crashing if the stack has overflowed and corrupted
1780          * task_cpu(p), which is in the thread_info struct.
1781          */
1782         if (cpu < NR_CPUS && cpu_possible(cpu)) {
1783                 stack_page = (unsigned long) hardirq_ctx[cpu];
1784                 if (sp >= stack_page + sizeof(struct thread_struct)
1785                     && sp <= stack_page + THREAD_SIZE - nbytes)
1786                         return 1;
1787
1788                 stack_page = (unsigned long) softirq_ctx[cpu];
1789                 if (sp >= stack_page + sizeof(struct thread_struct)
1790                     && sp <= stack_page + THREAD_SIZE - nbytes)
1791                         return 1;
1792         }
1793         return 0;
1794 }
1795
1796 int validate_sp(unsigned long sp, struct task_struct *p,
1797                        unsigned long nbytes)
1798 {
1799         unsigned long stack_page = (unsigned long)task_stack_page(p);
1800
1801         if (sp >= stack_page + sizeof(struct thread_struct)
1802             && sp <= stack_page + THREAD_SIZE - nbytes)
1803                 return 1;
1804
1805         return valid_irq_stack(sp, p, nbytes);
1806 }
1807
1808 EXPORT_SYMBOL(validate_sp);
1809
1810 unsigned long get_wchan(struct task_struct *p)
1811 {
1812         unsigned long ip, sp;
1813         int count = 0;
1814
1815         if (!p || p == current || p->state == TASK_RUNNING)
1816                 return 0;
1817
1818         sp = p->thread.ksp;
1819         if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1820                 return 0;
1821
1822         do {
1823                 sp = *(unsigned long *)sp;
1824                 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1825                         return 0;
1826                 if (count > 0) {
1827                         ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
1828                         if (!in_sched_functions(ip))
1829                                 return ip;
1830                 }
1831         } while (count++ < 16);
1832         return 0;
1833 }
1834
1835 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
1836
1837 void show_stack(struct task_struct *tsk, unsigned long *stack)
1838 {
1839         unsigned long sp, ip, lr, newsp;
1840         int count = 0;
1841         int firstframe = 1;
1842 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1843         int curr_frame = current->curr_ret_stack;
1844         extern void return_to_handler(void);
1845         unsigned long rth = (unsigned long)return_to_handler;
1846 #endif
1847
1848         sp = (unsigned long) stack;
1849         if (tsk == NULL)
1850                 tsk = current;
1851         if (sp == 0) {
1852                 if (tsk == current)
1853                         sp = current_stack_pointer();
1854                 else
1855                         sp = tsk->thread.ksp;
1856         }
1857
1858         lr = 0;
1859         printk("Call Trace:\n");
1860         do {
1861                 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
1862                         return;
1863
1864                 stack = (unsigned long *) sp;
1865                 newsp = stack[0];
1866                 ip = stack[STACK_FRAME_LR_SAVE];
1867                 if (!firstframe || ip != lr) {
1868                         printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
1869 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1870                         if ((ip == rth) && curr_frame >= 0) {
1871                                 printk(" (%pS)",
1872                                        (void *)current->ret_stack[curr_frame].ret);
1873                                 curr_frame--;
1874                         }
1875 #endif
1876                         if (firstframe)
1877                                 printk(" (unreliable)");
1878                         printk("\n");
1879                 }
1880                 firstframe = 0;
1881
1882                 /*
1883                  * See if this is an exception frame.
1884                  * We look for the "regshere" marker in the current frame.
1885                  */
1886                 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
1887                     && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
1888                         struct pt_regs *regs = (struct pt_regs *)
1889                                 (sp + STACK_FRAME_OVERHEAD);
1890                         lr = regs->link;
1891                         printk("--- interrupt: %lx at %pS\n    LR = %pS\n",
1892                                regs->trap, (void *)regs->nip, (void *)lr);
1893                         firstframe = 1;
1894                 }
1895
1896                 sp = newsp;
1897         } while (count++ < kstack_depth_to_print);
1898 }
1899
1900 #ifdef CONFIG_PPC64
1901 /* Called with hard IRQs off */
1902 void notrace __ppc64_runlatch_on(void)
1903 {
1904         struct thread_info *ti = current_thread_info();
1905         unsigned long ctrl;
1906
1907         ctrl = mfspr(SPRN_CTRLF);
1908         ctrl |= CTRL_RUNLATCH;
1909         mtspr(SPRN_CTRLT, ctrl);
1910
1911         ti->local_flags |= _TLF_RUNLATCH;
1912 }
1913
1914 /* Called with hard IRQs off */
1915 void notrace __ppc64_runlatch_off(void)
1916 {
1917         struct thread_info *ti = current_thread_info();
1918         unsigned long ctrl;
1919
1920         ti->local_flags &= ~_TLF_RUNLATCH;
1921
1922         ctrl = mfspr(SPRN_CTRLF);
1923         ctrl &= ~CTRL_RUNLATCH;
1924         mtspr(SPRN_CTRLT, ctrl);
1925 }
1926 #endif /* CONFIG_PPC64 */
1927
1928 unsigned long arch_align_stack(unsigned long sp)
1929 {
1930         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
1931                 sp -= get_random_int() & ~PAGE_MASK;
1932         return sp & ~0xf;
1933 }
1934
1935 static inline unsigned long brk_rnd(void)
1936 {
1937         unsigned long rnd = 0;
1938
1939         /* 8MB for 32bit, 1GB for 64bit */
1940         if (is_32bit_task())
1941                 rnd = (get_random_long() % (1UL<<(23-PAGE_SHIFT)));
1942         else
1943                 rnd = (get_random_long() % (1UL<<(30-PAGE_SHIFT)));
1944
1945         return rnd << PAGE_SHIFT;
1946 }
1947
1948 unsigned long arch_randomize_brk(struct mm_struct *mm)
1949 {
1950         unsigned long base = mm->brk;
1951         unsigned long ret;
1952
1953 #ifdef CONFIG_PPC_STD_MMU_64
1954         /*
1955          * If we are using 1TB segments and we are allowed to randomise
1956          * the heap, we can put it above 1TB so it is backed by a 1TB
1957          * segment. Otherwise the heap will be in the bottom 1TB
1958          * which always uses 256MB segments and this may result in a
1959          * performance penalty. We don't need to worry about radix. For
1960          * radix, mmu_highuser_ssize remains unchanged from 256MB.
1961          */
1962         if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
1963                 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
1964 #endif
1965
1966         ret = PAGE_ALIGN(base + brk_rnd());
1967
1968         if (ret < mm->brk)
1969                 return mm->brk;
1970
1971         return ret;
1972 }
1973