2 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
3 * {mikejc|engebret}@us.ibm.com
5 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
7 * SMP scalability work:
8 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
13 * PowerPC Hashed Page Table functions
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/sched.h>
27 #include <linux/proc_fs.h>
28 #include <linux/stat.h>
29 #include <linux/sysctl.h>
30 #include <linux/export.h>
31 #include <linux/ctype.h>
32 #include <linux/cache.h>
33 #include <linux/init.h>
34 #include <linux/signal.h>
35 #include <linux/memblock.h>
36 #include <linux/context_tracking.h>
37 #include <linux/libfdt.h>
39 #include <asm/processor.h>
40 #include <asm/pgtable.h>
42 #include <asm/mmu_context.h>
44 #include <asm/types.h>
45 #include <asm/uaccess.h>
46 #include <asm/machdep.h>
48 #include <asm/tlbflush.h>
52 #include <asm/cacheflush.h>
53 #include <asm/cputable.h>
54 #include <asm/sections.h>
55 #include <asm/copro.h>
57 #include <asm/code-patching.h>
58 #include <asm/fadump.h>
59 #include <asm/firmware.h>
61 #include <asm/trace.h>
65 #define DBG(fmt...) udbg_printf(fmt)
71 #define DBG_LOW(fmt...) udbg_printf(fmt)
73 #define DBG_LOW(fmt...)
81 * Note: pte --> Linux PTE
82 * HPTE --> PowerPC Hashed Page Table Entry
85 * htab_initialize is called with the MMU off (of course), but
86 * the kernel has been copied down to zero so it can directly
87 * reference global data. At this point it is very difficult
88 * to print debug info.
92 static unsigned long _SDR1;
93 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
94 EXPORT_SYMBOL_GPL(mmu_psize_defs);
96 u8 hpte_page_sizes[1 << LP_BITS];
97 EXPORT_SYMBOL_GPL(hpte_page_sizes);
99 struct hash_pte *htab_address;
100 unsigned long htab_size_bytes;
101 unsigned long htab_hash_mask;
102 EXPORT_SYMBOL_GPL(htab_hash_mask);
103 int mmu_linear_psize = MMU_PAGE_4K;
104 EXPORT_SYMBOL_GPL(mmu_linear_psize);
105 int mmu_virtual_psize = MMU_PAGE_4K;
106 int mmu_vmalloc_psize = MMU_PAGE_4K;
107 #ifdef CONFIG_SPARSEMEM_VMEMMAP
108 int mmu_vmemmap_psize = MMU_PAGE_4K;
110 int mmu_io_psize = MMU_PAGE_4K;
111 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
112 EXPORT_SYMBOL_GPL(mmu_kernel_ssize);
113 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
114 u16 mmu_slb_size = 64;
115 EXPORT_SYMBOL_GPL(mmu_slb_size);
116 #ifdef CONFIG_PPC_64K_PAGES
117 int mmu_ci_restrictions;
119 #ifdef CONFIG_DEBUG_PAGEALLOC
120 static u8 *linear_map_hash_slots;
121 static unsigned long linear_map_hash_count;
122 static DEFINE_SPINLOCK(linear_map_hash_lock);
123 #endif /* CONFIG_DEBUG_PAGEALLOC */
124 struct mmu_hash_ops mmu_hash_ops;
125 EXPORT_SYMBOL(mmu_hash_ops);
127 /* There are definitions of page sizes arrays to be used when none
128 * is provided by the firmware.
131 /* Pre-POWER4 CPUs (4k pages only)
133 static struct mmu_psize_def mmu_psize_defaults_old[] = {
137 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
143 /* POWER4, GPUL, POWER5
145 * Support for 16Mb large pages
147 static struct mmu_psize_def mmu_psize_defaults_gp[] = {
151 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
158 .penc = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0,
159 [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 },
166 * 'R' and 'C' update notes:
167 * - Under pHyp or KVM, the updatepp path will not set C, thus it *will*
168 * create writeable HPTEs without C set, because the hcall H_PROTECT
169 * that we use in that case will not update C
170 * - The above is however not a problem, because we also don't do that
171 * fancy "no flush" variant of eviction and we use H_REMOVE which will
172 * do the right thing and thus we don't have the race I described earlier
174 * - Under bare metal, we do have the race, so we need R and C set
175 * - We make sure R is always set and never lost
176 * - C is _PAGE_DIRTY, and *should* always be set for a writeable mapping
178 unsigned long htab_convert_pte_flags(unsigned long pteflags)
180 unsigned long rflags = 0;
182 /* _PAGE_EXEC -> NOEXEC */
183 if ((pteflags & _PAGE_EXEC) == 0)
187 * Linux uses slb key 0 for kernel and 1 for user.
188 * kernel RW areas are mapped with PPP=0b000
189 * User area is mapped with PPP=0b010 for read/write
190 * or PPP=0b011 for read-only (including writeable but clean pages).
192 if (pteflags & _PAGE_PRIVILEGED) {
194 * Kernel read only mapped with ppp bits 0b110
196 if (!(pteflags & _PAGE_WRITE))
197 rflags |= (HPTE_R_PP0 | 0x2);
199 if (pteflags & _PAGE_RWX)
201 if (!((pteflags & _PAGE_WRITE) && (pteflags & _PAGE_DIRTY)))
205 * We can't allow hardware to update hpte bits. Hence always
206 * set 'R' bit and set 'C' if it is a write fault
210 if (pteflags & _PAGE_DIRTY)
216 if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_TOLERANT)
218 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT)
219 rflags |= (HPTE_R_I | HPTE_R_G);
220 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_SAO)
221 rflags |= (HPTE_R_W | HPTE_R_I | HPTE_R_M);
224 * Add memory coherence if cache inhibited is not set
231 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
232 unsigned long pstart, unsigned long prot,
233 int psize, int ssize)
235 unsigned long vaddr, paddr;
236 unsigned int step, shift;
239 shift = mmu_psize_defs[psize].shift;
242 prot = htab_convert_pte_flags(prot);
244 DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
245 vstart, vend, pstart, prot, psize, ssize);
247 for (vaddr = vstart, paddr = pstart; vaddr < vend;
248 vaddr += step, paddr += step) {
249 unsigned long hash, hpteg;
250 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
251 unsigned long vpn = hpt_vpn(vaddr, vsid, ssize);
252 unsigned long tprot = prot;
255 * If we hit a bad address return error.
259 /* Make kernel text executable */
260 if (overlaps_kernel_text(vaddr, vaddr + step))
263 /* Make kvm guest trampolines executable */
264 if (overlaps_kvm_tmp(vaddr, vaddr + step))
268 * If relocatable, check if it overlaps interrupt vectors that
269 * are copied down to real 0. For relocatable kernel
270 * (e.g. kdump case) we copy interrupt vectors down to real
271 * address 0. Mark that region as executable. This is
272 * because on p8 system with relocation on exception feature
273 * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence
274 * in order to execute the interrupt handlers in virtual
275 * mode the vector region need to be marked as executable.
277 if ((PHYSICAL_START > MEMORY_START) &&
278 overlaps_interrupt_vector_text(vaddr, vaddr + step))
281 hash = hpt_hash(vpn, shift, ssize);
282 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
284 BUG_ON(!mmu_hash_ops.hpte_insert);
285 ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot,
286 HPTE_V_BOLTED, psize, psize,
292 #ifdef CONFIG_DEBUG_PAGEALLOC
293 if (debug_pagealloc_enabled() &&
294 (paddr >> PAGE_SHIFT) < linear_map_hash_count)
295 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
296 #endif /* CONFIG_DEBUG_PAGEALLOC */
298 return ret < 0 ? ret : 0;
301 int htab_remove_mapping(unsigned long vstart, unsigned long vend,
302 int psize, int ssize)
305 unsigned int step, shift;
309 shift = mmu_psize_defs[psize].shift;
312 if (!mmu_hash_ops.hpte_removebolted)
315 for (vaddr = vstart; vaddr < vend; vaddr += step) {
316 rc = mmu_hash_ops.hpte_removebolted(vaddr, psize, ssize);
328 static bool disable_1tb_segments = false;
330 static int __init parse_disable_1tb_segments(char *p)
332 disable_1tb_segments = true;
335 early_param("disable_1tb_segments", parse_disable_1tb_segments);
337 static int __init htab_dt_scan_seg_sizes(unsigned long node,
338 const char *uname, int depth,
341 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
345 /* We are scanning "cpu" nodes only */
346 if (type == NULL || strcmp(type, "cpu") != 0)
349 prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size);
352 for (; size >= 4; size -= 4, ++prop) {
353 if (be32_to_cpu(prop[0]) == 40) {
354 DBG("1T segment support detected\n");
356 if (disable_1tb_segments) {
357 DBG("1T segments disabled by command line\n");
361 cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT;
365 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
369 static int __init get_idx_from_shift(unsigned int shift)
393 static int __init htab_dt_scan_page_sizes(unsigned long node,
394 const char *uname, int depth,
397 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
401 /* We are scanning "cpu" nodes only */
402 if (type == NULL || strcmp(type, "cpu") != 0)
405 prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size);
409 pr_info("Page sizes from device-tree:\n");
411 cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
413 unsigned int base_shift = be32_to_cpu(prop[0]);
414 unsigned int slbenc = be32_to_cpu(prop[1]);
415 unsigned int lpnum = be32_to_cpu(prop[2]);
416 struct mmu_psize_def *def;
419 size -= 3; prop += 3;
420 base_idx = get_idx_from_shift(base_shift);
422 /* skip the pte encoding also */
423 prop += lpnum * 2; size -= lpnum * 2;
426 def = &mmu_psize_defs[base_idx];
427 if (base_idx == MMU_PAGE_16M)
428 cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
430 def->shift = base_shift;
431 if (base_shift <= 23)
434 def->avpnm = (1 << (base_shift - 23)) - 1;
437 * We don't know for sure what's up with tlbiel, so
438 * for now we only set it for 4K and 64K pages
440 if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K)
445 while (size > 0 && lpnum) {
446 unsigned int shift = be32_to_cpu(prop[0]);
447 int penc = be32_to_cpu(prop[1]);
449 prop += 2; size -= 2;
452 idx = get_idx_from_shift(shift);
457 pr_err("Invalid penc for base_shift=%d "
458 "shift=%d\n", base_shift, shift);
460 def->penc[idx] = penc;
461 pr_info("base_shift=%d: shift=%d, sllp=0x%04lx,"
462 " avpnm=0x%08lx, tlbiel=%d, penc=%d\n",
463 base_shift, shift, def->sllp,
464 def->avpnm, def->tlbiel, def->penc[idx]);
471 #ifdef CONFIG_HUGETLB_PAGE
472 /* Scan for 16G memory blocks that have been set aside for huge pages
473 * and reserve those blocks for 16G huge pages.
475 static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
476 const char *uname, int depth,
478 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
479 const __be64 *addr_prop;
480 const __be32 *page_count_prop;
481 unsigned int expected_pages;
482 long unsigned int phys_addr;
483 long unsigned int block_size;
485 /* We are scanning "memory" nodes only */
486 if (type == NULL || strcmp(type, "memory") != 0)
489 /* This property is the log base 2 of the number of virtual pages that
490 * will represent this memory block. */
491 page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
492 if (page_count_prop == NULL)
494 expected_pages = (1 << be32_to_cpu(page_count_prop[0]));
495 addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
496 if (addr_prop == NULL)
498 phys_addr = be64_to_cpu(addr_prop[0]);
499 block_size = be64_to_cpu(addr_prop[1]);
500 if (block_size != (16 * GB))
502 printk(KERN_INFO "Huge page(16GB) memory: "
503 "addr = 0x%lX size = 0x%lX pages = %d\n",
504 phys_addr, block_size, expected_pages);
505 if (phys_addr + (16 * GB) <= memblock_end_of_DRAM()) {
506 memblock_reserve(phys_addr, block_size * expected_pages);
507 add_gpage(phys_addr, block_size, expected_pages);
511 #endif /* CONFIG_HUGETLB_PAGE */
513 static void mmu_psize_set_default_penc(void)
516 for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++)
517 for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++)
518 mmu_psize_defs[bpsize].penc[apsize] = -1;
521 #ifdef CONFIG_PPC_64K_PAGES
523 static bool might_have_hea(void)
526 * The HEA ethernet adapter requires awareness of the
527 * GX bus. Without that awareness we can easily assume
528 * we will never see an HEA ethernet device.
530 #ifdef CONFIG_IBMEBUS
531 return !cpu_has_feature(CPU_FTR_ARCH_207S) &&
532 !firmware_has_feature(FW_FEATURE_SPLPAR);
538 #endif /* #ifdef CONFIG_PPC_64K_PAGES */
540 static void __init htab_scan_page_sizes(void)
544 /* se the invalid penc to -1 */
545 mmu_psize_set_default_penc();
547 /* Default to 4K pages only */
548 memcpy(mmu_psize_defs, mmu_psize_defaults_old,
549 sizeof(mmu_psize_defaults_old));
552 * Try to find the available page sizes in the device-tree
554 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
555 if (rc == 0 && early_mmu_has_feature(MMU_FTR_16M_PAGE)) {
557 * Nothing in the device-tree, but the CPU supports 16M pages,
558 * so let's fallback on a known size list for 16M capable CPUs.
560 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
561 sizeof(mmu_psize_defaults_gp));
564 #ifdef CONFIG_HUGETLB_PAGE
565 /* Reserve 16G huge page memory sections for huge pages */
566 of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
567 #endif /* CONFIG_HUGETLB_PAGE */
571 * Fill in the hpte_page_sizes[] array.
572 * We go through the mmu_psize_defs[] array looking for all the
573 * supported base/actual page size combinations. Each combination
574 * has a unique pagesize encoding (penc) value in the low bits of
575 * the LP field of the HPTE. For actual page sizes less than 1MB,
576 * some of the upper LP bits are used for RPN bits, meaning that
577 * we need to fill in several entries in hpte_page_sizes[].
579 * In diagrammatic form, with r = RPN bits and z = page size bits:
580 * PTE LP actual page size
587 * The zzzz bits are implementation-specific but are chosen so that
588 * no encoding for a larger page size uses the same value in its
589 * low-order N bits as the encoding for the 2^(12+N) byte page size
592 static void init_hpte_page_sizes(void)
595 long int shift, penc;
597 for (bp = 0; bp < MMU_PAGE_COUNT; ++bp) {
598 if (!mmu_psize_defs[bp].shift)
599 continue; /* not a supported page size */
600 for (ap = bp; ap < MMU_PAGE_COUNT; ++ap) {
601 penc = mmu_psize_defs[bp].penc[ap];
604 shift = mmu_psize_defs[ap].shift - LP_SHIFT;
606 continue; /* should never happen */
608 * For page sizes less than 1MB, this loop
609 * replicates the entry for all possible values
612 while (penc < (1 << LP_BITS)) {
613 hpte_page_sizes[penc] = (ap << 4) | bp;
620 static void __init htab_init_page_sizes(void)
622 init_hpte_page_sizes();
624 if (!debug_pagealloc_enabled()) {
626 * Pick a size for the linear mapping. Currently, we only
627 * support 16M, 1M and 4K which is the default
629 if (mmu_psize_defs[MMU_PAGE_16M].shift)
630 mmu_linear_psize = MMU_PAGE_16M;
631 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
632 mmu_linear_psize = MMU_PAGE_1M;
635 #ifdef CONFIG_PPC_64K_PAGES
637 * Pick a size for the ordinary pages. Default is 4K, we support
638 * 64K for user mappings and vmalloc if supported by the processor.
639 * We only use 64k for ioremap if the processor
640 * (and firmware) support cache-inhibited large pages.
641 * If not, we use 4k and set mmu_ci_restrictions so that
642 * hash_page knows to switch processes that use cache-inhibited
643 * mappings to 4k pages.
645 if (mmu_psize_defs[MMU_PAGE_64K].shift) {
646 mmu_virtual_psize = MMU_PAGE_64K;
647 mmu_vmalloc_psize = MMU_PAGE_64K;
648 if (mmu_linear_psize == MMU_PAGE_4K)
649 mmu_linear_psize = MMU_PAGE_64K;
650 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
652 * When running on pSeries using 64k pages for ioremap
653 * would stop us accessing the HEA ethernet. So if we
654 * have the chance of ever seeing one, stay at 4k.
656 if (!might_have_hea())
657 mmu_io_psize = MMU_PAGE_64K;
659 mmu_ci_restrictions = 1;
661 #endif /* CONFIG_PPC_64K_PAGES */
663 #ifdef CONFIG_SPARSEMEM_VMEMMAP
664 /* We try to use 16M pages for vmemmap if that is supported
665 * and we have at least 1G of RAM at boot
667 if (mmu_psize_defs[MMU_PAGE_16M].shift &&
668 memblock_phys_mem_size() >= 0x40000000)
669 mmu_vmemmap_psize = MMU_PAGE_16M;
670 else if (mmu_psize_defs[MMU_PAGE_64K].shift)
671 mmu_vmemmap_psize = MMU_PAGE_64K;
673 mmu_vmemmap_psize = MMU_PAGE_4K;
674 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
676 printk(KERN_DEBUG "Page orders: linear mapping = %d, "
677 "virtual = %d, io = %d"
678 #ifdef CONFIG_SPARSEMEM_VMEMMAP
682 mmu_psize_defs[mmu_linear_psize].shift,
683 mmu_psize_defs[mmu_virtual_psize].shift,
684 mmu_psize_defs[mmu_io_psize].shift
685 #ifdef CONFIG_SPARSEMEM_VMEMMAP
686 ,mmu_psize_defs[mmu_vmemmap_psize].shift
691 static int __init htab_dt_scan_pftsize(unsigned long node,
692 const char *uname, int depth,
695 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
698 /* We are scanning "cpu" nodes only */
699 if (type == NULL || strcmp(type, "cpu") != 0)
702 prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
704 /* pft_size[0] is the NUMA CEC cookie */
705 ppc64_pft_size = be32_to_cpu(prop[1]);
711 unsigned htab_shift_for_mem_size(unsigned long mem_size)
713 unsigned memshift = __ilog2(mem_size);
714 unsigned pshift = mmu_psize_defs[mmu_virtual_psize].shift;
717 /* round mem_size up to next power of 2 */
718 if ((1UL << memshift) < mem_size)
721 /* aim for 2 pages / pteg */
722 pteg_shift = memshift - (pshift + 1);
725 * 2^11 PTEGS of 128 bytes each, ie. 2^18 bytes is the minimum htab
726 * size permitted by the architecture.
728 return max(pteg_shift + 7, 18U);
731 static unsigned long __init htab_get_table_size(void)
733 /* If hash size isn't already provided by the platform, we try to
734 * retrieve it from the device-tree. If it's not there neither, we
735 * calculate it now based on the total RAM size
737 if (ppc64_pft_size == 0)
738 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
740 return 1UL << ppc64_pft_size;
742 return 1UL << htab_shift_for_mem_size(memblock_phys_mem_size());
745 #ifdef CONFIG_MEMORY_HOTPLUG
746 int create_section_mapping(unsigned long start, unsigned long end)
748 int rc = htab_bolt_mapping(start, end, __pa(start),
749 pgprot_val(PAGE_KERNEL), mmu_linear_psize,
753 int rc2 = htab_remove_mapping(start, end, mmu_linear_psize,
755 BUG_ON(rc2 && (rc2 != -ENOENT));
760 int remove_section_mapping(unsigned long start, unsigned long end)
762 int rc = htab_remove_mapping(start, end, mmu_linear_psize,
767 #endif /* CONFIG_MEMORY_HOTPLUG */
769 static void update_hid_for_hash(void)
772 unsigned long rb = 3UL << PPC_BITLSHIFT(53); /* IS = 3 */
774 asm volatile("ptesync": : :"memory");
775 /* prs = 0, ric = 2, rs = 0, r = 1 is = 3 */
776 asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
777 : : "r"(rb), "i"(0), "i"(0), "i"(2), "r"(0) : "memory");
778 asm volatile("eieio; tlbsync; ptesync; isync; slbia": : :"memory");
782 hid0 = mfspr(SPRN_HID0);
783 hid0 &= ~HID0_POWER9_RADIX;
784 mtspr(SPRN_HID0, hid0);
785 asm volatile("isync": : :"memory");
787 /* Wait for it to happen */
788 while ((mfspr(SPRN_HID0) & HID0_POWER9_RADIX))
792 static void __init hash_init_partition_table(phys_addr_t hash_table,
793 unsigned long htab_size)
795 unsigned long ps_field;
796 unsigned long patb_size = 1UL << PATB_SIZE_SHIFT;
799 * slb llp encoding for the page size used in VPM real mode.
800 * We can ignore that for lpid 0
803 htab_size = __ilog2(htab_size) - 18;
805 BUILD_BUG_ON_MSG((PATB_SIZE_SHIFT > 24), "Partition table size too large.");
806 partition_tb = __va(memblock_alloc_base(patb_size, patb_size,
807 MEMBLOCK_ALLOC_ANYWHERE));
809 /* Initialize the Partition Table with no entries */
810 memset((void *)partition_tb, 0, patb_size);
811 partition_tb->patb0 = cpu_to_be64(ps_field | hash_table | htab_size);
813 * FIXME!! This should be done via update_partition table
814 * For now UPRT is 0 for us.
816 partition_tb->patb1 = 0;
817 pr_info("Partition table %p\n", partition_tb);
818 if (cpu_has_feature(CPU_FTR_POWER9_DD1))
819 update_hid_for_hash();
821 * update partition table control register,
824 mtspr(SPRN_PTCR, __pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
828 static void __init htab_initialize(void)
831 unsigned long pteg_count;
833 unsigned long base = 0, size = 0;
834 struct memblock_region *reg;
836 DBG(" -> htab_initialize()\n");
838 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
839 mmu_kernel_ssize = MMU_SEGSIZE_1T;
840 mmu_highuser_ssize = MMU_SEGSIZE_1T;
841 printk(KERN_INFO "Using 1TB segments\n");
845 * Calculate the required size of the htab. We want the number of
846 * PTEGs to equal one half the number of real pages.
848 htab_size_bytes = htab_get_table_size();
849 pteg_count = htab_size_bytes >> 7;
851 htab_hash_mask = pteg_count - 1;
853 if (firmware_has_feature(FW_FEATURE_LPAR) ||
854 firmware_has_feature(FW_FEATURE_PS3_LV1)) {
855 /* Using a hypervisor which owns the htab */
858 #ifdef CONFIG_FA_DUMP
860 * If firmware assisted dump is active firmware preserves
861 * the contents of htab along with entire partition memory.
862 * Clear the htab if firmware assisted dump is active so
863 * that we dont end up using old mappings.
865 if (is_fadump_active() && mmu_hash_ops.hpte_clear_all)
866 mmu_hash_ops.hpte_clear_all();
869 unsigned long limit = MEMBLOCK_ALLOC_ANYWHERE;
871 #ifdef CONFIG_PPC_CELL
873 * Cell may require the hash table down low when using the
874 * Axon IOMMU in order to fit the dynamic region over it, see
875 * comments in cell/iommu.c
877 if (fdt_subnode_offset(initial_boot_params, 0, "axon") > 0) {
879 pr_info("Hash table forced below 2G for Axon IOMMU\n");
881 #endif /* CONFIG_PPC_CELL */
883 table = memblock_alloc_base(htab_size_bytes, htab_size_bytes,
886 DBG("Hash table allocated at %lx, size: %lx\n", table,
889 htab_address = __va(table);
891 /* htab absolute addr + encoded htabsize */
892 _SDR1 = table + __ilog2(htab_size_bytes) - 18;
894 /* Initialize the HPT with no entries */
895 memset((void *)table, 0, htab_size_bytes);
897 if (!cpu_has_feature(CPU_FTR_ARCH_300))
899 mtspr(SPRN_SDR1, _SDR1);
901 hash_init_partition_table(table, htab_size_bytes);
904 prot = pgprot_val(PAGE_KERNEL);
906 #ifdef CONFIG_DEBUG_PAGEALLOC
907 if (debug_pagealloc_enabled()) {
908 linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT;
909 linear_map_hash_slots = __va(memblock_alloc_base(
910 linear_map_hash_count, 1, ppc64_rma_size));
911 memset(linear_map_hash_slots, 0, linear_map_hash_count);
913 #endif /* CONFIG_DEBUG_PAGEALLOC */
915 /* On U3 based machines, we need to reserve the DART area and
916 * _NOT_ map it to avoid cache paradoxes as it's remapped non
920 /* create bolted the linear mapping in the hash table */
921 for_each_memblock(memory, reg) {
922 base = (unsigned long)__va(reg->base);
925 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
928 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
929 prot, mmu_linear_psize, mmu_kernel_ssize));
931 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
934 * If we have a memory_limit and we've allocated TCEs then we need to
935 * explicitly map the TCE area at the top of RAM. We also cope with the
936 * case that the TCEs start below memory_limit.
937 * tce_alloc_start/end are 16MB aligned so the mapping should work
938 * for either 4K or 16MB pages.
940 if (tce_alloc_start) {
941 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
942 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
944 if (base + size >= tce_alloc_start)
945 tce_alloc_start = base + size + 1;
947 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
948 __pa(tce_alloc_start), prot,
949 mmu_linear_psize, mmu_kernel_ssize));
953 DBG(" <- htab_initialize()\n");
958 void __init hash__early_init_devtree(void)
960 /* Initialize segment sizes */
961 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
963 /* Initialize page sizes */
964 htab_scan_page_sizes();
967 void __init hash__early_init_mmu(void)
969 htab_init_page_sizes();
972 * initialize page table size
974 __pte_frag_nr = H_PTE_FRAG_NR;
975 __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT;
977 __pte_index_size = H_PTE_INDEX_SIZE;
978 __pmd_index_size = H_PMD_INDEX_SIZE;
979 __pud_index_size = H_PUD_INDEX_SIZE;
980 __pgd_index_size = H_PGD_INDEX_SIZE;
981 __pmd_cache_index = H_PMD_CACHE_INDEX;
982 __pte_table_size = H_PTE_TABLE_SIZE;
983 __pmd_table_size = H_PMD_TABLE_SIZE;
984 __pud_table_size = H_PUD_TABLE_SIZE;
985 __pgd_table_size = H_PGD_TABLE_SIZE;
987 * 4k use hugepd format, so for hash set then to
994 __kernel_virt_start = H_KERN_VIRT_START;
995 __kernel_virt_size = H_KERN_VIRT_SIZE;
996 __vmalloc_start = H_VMALLOC_START;
997 __vmalloc_end = H_VMALLOC_END;
998 vmemmap = (struct page *)H_VMEMMAP_BASE;
999 ioremap_bot = IOREMAP_BASE;
1002 pci_io_base = ISA_IO_BASE;
1005 /* Select appropriate backend */
1006 if (firmware_has_feature(FW_FEATURE_PS3_LV1))
1007 ps3_early_mm_init();
1008 else if (firmware_has_feature(FW_FEATURE_LPAR))
1009 hpte_init_pseries();
1010 else if (IS_ENABLED(CONFIG_PPC_NATIVE))
1013 if (!mmu_hash_ops.hpte_insert)
1014 panic("hash__early_init_mmu: No MMU hash ops defined!\n");
1016 /* Initialize the MMU Hash table and create the linear mapping
1017 * of memory. Has to be done before SLB initialization as this is
1018 * currently where the page size encoding is obtained.
1022 pr_info("Initializing hash mmu with SLB\n");
1023 /* Initialize SLB management */
1028 void hash__early_init_mmu_secondary(void)
1030 /* Initialize hash table for that CPU */
1031 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
1032 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1033 mtspr(SPRN_SDR1, _SDR1);
1036 __pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
1038 /* Initialize SLB */
1041 #endif /* CONFIG_SMP */
1044 * Called by asm hashtable.S for doing lazy icache flush
1046 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
1050 if (!pfn_valid(pte_pfn(pte)))
1053 page = pte_page(pte);
1056 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
1057 if (trap == 0x400) {
1058 flush_dcache_icache_page(page);
1059 set_bit(PG_arch_1, &page->flags);
1066 #ifdef CONFIG_PPC_MM_SLICES
1067 static unsigned int get_paca_psize(unsigned long addr)
1070 unsigned char *hpsizes;
1071 unsigned long index, mask_index;
1073 if (addr < SLICE_LOW_TOP) {
1074 lpsizes = get_paca()->mm_ctx_low_slices_psize;
1075 index = GET_LOW_SLICE_INDEX(addr);
1076 return (lpsizes >> (index * 4)) & 0xF;
1078 hpsizes = get_paca()->mm_ctx_high_slices_psize;
1079 index = GET_HIGH_SLICE_INDEX(addr);
1080 mask_index = index & 0x1;
1081 return (hpsizes[index >> 1] >> (mask_index * 4)) & 0xF;
1085 unsigned int get_paca_psize(unsigned long addr)
1087 return get_paca()->mm_ctx_user_psize;
1092 * Demote a segment to using 4k pages.
1093 * For now this makes the whole process use 4k pages.
1095 #ifdef CONFIG_PPC_64K_PAGES
1096 void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
1098 if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
1100 slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
1101 copro_flush_all_slbs(mm);
1102 if ((get_paca_psize(addr) != MMU_PAGE_4K) && (current->mm == mm)) {
1104 copy_mm_to_paca(&mm->context);
1105 slb_flush_and_rebolt();
1108 #endif /* CONFIG_PPC_64K_PAGES */
1110 #ifdef CONFIG_PPC_SUBPAGE_PROT
1112 * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
1113 * Userspace sets the subpage permissions using the subpage_prot system call.
1115 * Result is 0: full permissions, _PAGE_RW: read-only,
1116 * _PAGE_RWX: no access.
1118 static int subpage_protection(struct mm_struct *mm, unsigned long ea)
1120 struct subpage_prot_table *spt = &mm->context.spt;
1124 if (ea >= spt->maxaddr)
1126 if (ea < 0x100000000UL) {
1127 /* addresses below 4GB use spt->low_prot */
1128 sbpm = spt->low_prot;
1130 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
1134 sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
1137 spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
1139 /* extract 2-bit bitfield for this 4k subpage */
1140 spp >>= 30 - 2 * ((ea >> 12) & 0xf);
1143 * 0 -> full premission
1146 * We return the flag that need to be cleared.
1148 spp = ((spp & 2) ? _PAGE_RWX : 0) | ((spp & 1) ? _PAGE_WRITE : 0);
1152 #else /* CONFIG_PPC_SUBPAGE_PROT */
1153 static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
1159 void hash_failure_debug(unsigned long ea, unsigned long access,
1160 unsigned long vsid, unsigned long trap,
1161 int ssize, int psize, int lpsize, unsigned long pte)
1163 if (!printk_ratelimit())
1165 pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
1166 ea, access, current->comm);
1167 pr_info(" trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n",
1168 trap, vsid, ssize, psize, lpsize, pte);
1171 static void check_paca_psize(unsigned long ea, struct mm_struct *mm,
1172 int psize, bool user_region)
1175 if (psize != get_paca_psize(ea)) {
1176 copy_mm_to_paca(&mm->context);
1177 slb_flush_and_rebolt();
1179 } else if (get_paca()->vmalloc_sllp !=
1180 mmu_psize_defs[mmu_vmalloc_psize].sllp) {
1181 get_paca()->vmalloc_sllp =
1182 mmu_psize_defs[mmu_vmalloc_psize].sllp;
1183 slb_vmalloc_update();
1189 * 1 - normal page fault
1190 * -1 - critical hash insertion error
1191 * -2 - access not permitted by subpage protection mechanism
1193 int hash_page_mm(struct mm_struct *mm, unsigned long ea,
1194 unsigned long access, unsigned long trap,
1195 unsigned long flags)
1198 enum ctx_state prev_state = exception_enter();
1203 const struct cpumask *tmp;
1204 int rc, user_region = 0;
1207 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
1209 trace_hash_fault(ea, access, trap);
1211 /* Get region & vsid */
1212 switch (REGION_ID(ea)) {
1213 case USER_REGION_ID:
1216 DBG_LOW(" user region with no mm !\n");
1220 psize = get_slice_psize(mm, ea);
1221 ssize = user_segment_size(ea);
1222 vsid = get_vsid(mm->context.id, ea, ssize);
1224 case VMALLOC_REGION_ID:
1225 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1226 if (ea < VMALLOC_END)
1227 psize = mmu_vmalloc_psize;
1229 psize = mmu_io_psize;
1230 ssize = mmu_kernel_ssize;
1233 /* Not a valid range
1234 * Send the problem up to do_page_fault
1239 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
1243 DBG_LOW("Bad address!\n");
1249 if (pgdir == NULL) {
1254 /* Check CPU locality */
1255 tmp = cpumask_of(smp_processor_id());
1256 if (user_region && cpumask_equal(mm_cpumask(mm), tmp))
1257 flags |= HPTE_LOCAL_UPDATE;
1259 #ifndef CONFIG_PPC_64K_PAGES
1260 /* If we use 4K pages and our psize is not 4K, then we might
1261 * be hitting a special driver mapping, and need to align the
1262 * address before we fetch the PTE.
1264 * It could also be a hugepage mapping, in which case this is
1265 * not necessary, but it's not harmful, either.
1267 if (psize != MMU_PAGE_4K)
1268 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
1269 #endif /* CONFIG_PPC_64K_PAGES */
1271 /* Get PTE and page size from page tables */
1272 ptep = __find_linux_pte_or_hugepte(pgdir, ea, &is_thp, &hugeshift);
1273 if (ptep == NULL || !pte_present(*ptep)) {
1274 DBG_LOW(" no PTE !\n");
1279 /* Add _PAGE_PRESENT to the required access perm */
1280 access |= _PAGE_PRESENT;
1282 /* Pre-check access permissions (will be re-checked atomically
1283 * in __hash_page_XX but this pre-check is a fast path
1285 if (!check_pte_access(access, pte_val(*ptep))) {
1286 DBG_LOW(" no access !\n");
1293 rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep,
1294 trap, flags, ssize, psize);
1295 #ifdef CONFIG_HUGETLB_PAGE
1297 rc = __hash_page_huge(ea, access, vsid, ptep, trap,
1298 flags, ssize, hugeshift, psize);
1302 * if we have hugeshift, and is not transhuge with
1303 * hugetlb disabled, something is really wrong.
1309 if (current->mm == mm)
1310 check_paca_psize(ea, mm, psize, user_region);
1315 #ifndef CONFIG_PPC_64K_PAGES
1316 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
1318 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
1319 pte_val(*(ptep + PTRS_PER_PTE)));
1321 /* Do actual hashing */
1322 #ifdef CONFIG_PPC_64K_PAGES
1323 /* If H_PAGE_4K_PFN is set, make sure this is a 4k segment */
1324 if ((pte_val(*ptep) & H_PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
1325 demote_segment_4k(mm, ea);
1326 psize = MMU_PAGE_4K;
1329 /* If this PTE is non-cacheable and we have restrictions on
1330 * using non cacheable large pages, then we switch to 4k
1332 if (mmu_ci_restrictions && psize == MMU_PAGE_64K && pte_ci(*ptep)) {
1334 demote_segment_4k(mm, ea);
1335 psize = MMU_PAGE_4K;
1336 } else if (ea < VMALLOC_END) {
1338 * some driver did a non-cacheable mapping
1339 * in vmalloc space, so switch vmalloc
1342 printk(KERN_ALERT "Reducing vmalloc segment "
1343 "to 4kB pages because of "
1344 "non-cacheable mapping\n");
1345 psize = mmu_vmalloc_psize = MMU_PAGE_4K;
1346 copro_flush_all_slbs(mm);
1350 #endif /* CONFIG_PPC_64K_PAGES */
1352 if (current->mm == mm)
1353 check_paca_psize(ea, mm, psize, user_region);
1355 #ifdef CONFIG_PPC_64K_PAGES
1356 if (psize == MMU_PAGE_64K)
1357 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1360 #endif /* CONFIG_PPC_64K_PAGES */
1362 int spp = subpage_protection(mm, ea);
1366 rc = __hash_page_4K(ea, access, vsid, ptep, trap,
1370 /* Dump some info in case of hash insertion failure, they should
1371 * never happen so it is really useful to know if/when they do
1374 hash_failure_debug(ea, access, vsid, trap, ssize, psize,
1375 psize, pte_val(*ptep));
1376 #ifndef CONFIG_PPC_64K_PAGES
1377 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1379 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
1380 pte_val(*(ptep + PTRS_PER_PTE)));
1382 DBG_LOW(" -> rc=%d\n", rc);
1385 exception_exit(prev_state);
1388 EXPORT_SYMBOL_GPL(hash_page_mm);
1390 int hash_page(unsigned long ea, unsigned long access, unsigned long trap,
1391 unsigned long dsisr)
1393 unsigned long flags = 0;
1394 struct mm_struct *mm = current->mm;
1396 if (REGION_ID(ea) == VMALLOC_REGION_ID)
1399 if (dsisr & DSISR_NOHPTE)
1400 flags |= HPTE_NOHPTE_UPDATE;
1402 return hash_page_mm(mm, ea, access, trap, flags);
1404 EXPORT_SYMBOL_GPL(hash_page);
1406 int __hash_page(unsigned long ea, unsigned long msr, unsigned long trap,
1407 unsigned long dsisr)
1409 unsigned long access = _PAGE_PRESENT | _PAGE_READ;
1410 unsigned long flags = 0;
1411 struct mm_struct *mm = current->mm;
1413 if (REGION_ID(ea) == VMALLOC_REGION_ID)
1416 if (dsisr & DSISR_NOHPTE)
1417 flags |= HPTE_NOHPTE_UPDATE;
1419 if (dsisr & DSISR_ISSTORE)
1420 access |= _PAGE_WRITE;
1422 * We set _PAGE_PRIVILEGED only when
1423 * kernel mode access kernel space.
1425 * _PAGE_PRIVILEGED is NOT set
1426 * 1) when kernel mode access user space
1427 * 2) user space access kernel space.
1429 access |= _PAGE_PRIVILEGED;
1430 if ((msr & MSR_PR) || (REGION_ID(ea) == USER_REGION_ID))
1431 access &= ~_PAGE_PRIVILEGED;
1434 access |= _PAGE_EXEC;
1436 return hash_page_mm(mm, ea, access, trap, flags);
1439 #ifdef CONFIG_PPC_MM_SLICES
1440 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1442 int psize = get_slice_psize(mm, ea);
1444 /* We only prefault standard pages for now */
1445 if (unlikely(psize != mm->context.user_psize))
1449 * Don't prefault if subpage protection is enabled for the EA.
1451 if (unlikely((psize == MMU_PAGE_4K) && subpage_protection(mm, ea)))
1457 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1463 void hash_preload(struct mm_struct *mm, unsigned long ea,
1464 unsigned long access, unsigned long trap)
1470 unsigned long flags;
1471 int rc, ssize, update_flags = 0;
1473 BUG_ON(REGION_ID(ea) != USER_REGION_ID);
1475 if (!should_hash_preload(mm, ea))
1478 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1479 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1481 /* Get Linux PTE if available */
1487 ssize = user_segment_size(ea);
1488 vsid = get_vsid(mm->context.id, ea, ssize);
1492 * Hash doesn't like irqs. Walking linux page table with irq disabled
1493 * saves us from holding multiple locks.
1495 local_irq_save(flags);
1498 * THP pages use update_mmu_cache_pmd. We don't do
1499 * hash preload there. Hence can ignore THP here
1501 ptep = find_linux_pte_or_hugepte(pgdir, ea, NULL, &hugepage_shift);
1505 WARN_ON(hugepage_shift);
1506 #ifdef CONFIG_PPC_64K_PAGES
1507 /* If either H_PAGE_4K_PFN or cache inhibited is set (and we are on
1508 * a 64K kernel), then we don't preload, hash_page() will take
1509 * care of it once we actually try to access the page.
1510 * That way we don't have to duplicate all of the logic for segment
1511 * page size demotion here
1513 if ((pte_val(*ptep) & H_PAGE_4K_PFN) || pte_ci(*ptep))
1515 #endif /* CONFIG_PPC_64K_PAGES */
1517 /* Is that local to this CPU ? */
1518 if (cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id())))
1519 update_flags |= HPTE_LOCAL_UPDATE;
1522 #ifdef CONFIG_PPC_64K_PAGES
1523 if (mm->context.user_psize == MMU_PAGE_64K)
1524 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1525 update_flags, ssize);
1527 #endif /* CONFIG_PPC_64K_PAGES */
1528 rc = __hash_page_4K(ea, access, vsid, ptep, trap, update_flags,
1529 ssize, subpage_protection(mm, ea));
1531 /* Dump some info in case of hash insertion failure, they should
1532 * never happen so it is really useful to know if/when they do
1535 hash_failure_debug(ea, access, vsid, trap, ssize,
1536 mm->context.user_psize,
1537 mm->context.user_psize,
1540 local_irq_restore(flags);
1543 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1544 static inline void tm_flush_hash_page(int local)
1547 * Transactions are not aborted by tlbiel, only tlbie. Without, syncing a
1548 * page back to a block device w/PIO could pick up transactional data
1549 * (bad!) so we force an abort here. Before the sync the page will be
1550 * made read-only, which will flush_hash_page. BIG ISSUE here: if the
1551 * kernel uses a page from userspace without unmapping it first, it may
1552 * see the speculated version.
1554 if (local && cpu_has_feature(CPU_FTR_TM) && current->thread.regs &&
1555 MSR_TM_ACTIVE(current->thread.regs->msr)) {
1557 tm_abort(TM_CAUSE_TLBI);
1561 static inline void tm_flush_hash_page(int local)
1566 /* WARNING: This is called from hash_low_64.S, if you change this prototype,
1567 * do not forget to update the assembly call site !
1569 void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize,
1570 unsigned long flags)
1572 unsigned long hash, index, shift, hidx, slot;
1573 int local = flags & HPTE_LOCAL_UPDATE;
1575 DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn);
1576 pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
1577 hash = hpt_hash(vpn, shift, ssize);
1578 hidx = __rpte_to_hidx(pte, index);
1579 if (hidx & _PTEIDX_SECONDARY)
1581 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1582 slot += hidx & _PTEIDX_GROUP_IX;
1583 DBG_LOW(" sub %ld: hash=%lx, hidx=%lx\n", index, slot, hidx);
1585 * We use same base page size and actual psize, because we don't
1586 * use these functions for hugepage
1588 mmu_hash_ops.hpte_invalidate(slot, vpn, psize, psize,
1590 } pte_iterate_hashed_end();
1592 tm_flush_hash_page(local);
1595 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
1596 void flush_hash_hugepage(unsigned long vsid, unsigned long addr,
1597 pmd_t *pmdp, unsigned int psize, int ssize,
1598 unsigned long flags)
1600 int i, max_hpte_count, valid;
1601 unsigned long s_addr;
1602 unsigned char *hpte_slot_array;
1603 unsigned long hidx, shift, vpn, hash, slot;
1604 int local = flags & HPTE_LOCAL_UPDATE;
1606 s_addr = addr & HPAGE_PMD_MASK;
1607 hpte_slot_array = get_hpte_slot_array(pmdp);
1609 * IF we try to do a HUGE PTE update after a withdraw is done.
1610 * we will find the below NULL. This happens when we do
1611 * split_huge_page_pmd
1613 if (!hpte_slot_array)
1616 if (mmu_hash_ops.hugepage_invalidate) {
1617 mmu_hash_ops.hugepage_invalidate(vsid, s_addr, hpte_slot_array,
1618 psize, ssize, local);
1622 * No bluk hpte removal support, invalidate each entry
1624 shift = mmu_psize_defs[psize].shift;
1625 max_hpte_count = HPAGE_PMD_SIZE >> shift;
1626 for (i = 0; i < max_hpte_count; i++) {
1628 * 8 bits per each hpte entries
1629 * 000| [ secondary group (one bit) | hidx (3 bits) | valid bit]
1631 valid = hpte_valid(hpte_slot_array, i);
1634 hidx = hpte_hash_index(hpte_slot_array, i);
1637 addr = s_addr + (i * (1ul << shift));
1638 vpn = hpt_vpn(addr, vsid, ssize);
1639 hash = hpt_hash(vpn, shift, ssize);
1640 if (hidx & _PTEIDX_SECONDARY)
1643 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1644 slot += hidx & _PTEIDX_GROUP_IX;
1645 mmu_hash_ops.hpte_invalidate(slot, vpn, psize,
1646 MMU_PAGE_16M, ssize, local);
1649 tm_flush_hash_page(local);
1651 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1653 void flush_hash_range(unsigned long number, int local)
1655 if (mmu_hash_ops.flush_hash_range)
1656 mmu_hash_ops.flush_hash_range(number, local);
1659 struct ppc64_tlb_batch *batch =
1660 this_cpu_ptr(&ppc64_tlb_batch);
1662 for (i = 0; i < number; i++)
1663 flush_hash_page(batch->vpn[i], batch->pte[i],
1664 batch->psize, batch->ssize, local);
1669 * low_hash_fault is called when we the low level hash code failed
1670 * to instert a PTE due to an hypervisor error
1672 void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1674 enum ctx_state prev_state = exception_enter();
1676 if (user_mode(regs)) {
1677 #ifdef CONFIG_PPC_SUBPAGE_PROT
1679 _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1682 _exception(SIGBUS, regs, BUS_ADRERR, address);
1684 bad_page_fault(regs, address, SIGBUS);
1686 exception_exit(prev_state);
1689 long hpte_insert_repeating(unsigned long hash, unsigned long vpn,
1690 unsigned long pa, unsigned long rflags,
1691 unsigned long vflags, int psize, int ssize)
1693 unsigned long hpte_group;
1697 hpte_group = ((hash & htab_hash_mask) *
1698 HPTES_PER_GROUP) & ~0x7UL;
1700 /* Insert into the hash table, primary slot */
1701 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, vflags,
1702 psize, psize, ssize);
1704 /* Primary is full, try the secondary */
1705 if (unlikely(slot == -1)) {
1706 hpte_group = ((~hash & htab_hash_mask) *
1707 HPTES_PER_GROUP) & ~0x7UL;
1708 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags,
1709 vflags | HPTE_V_SECONDARY,
1710 psize, psize, ssize);
1713 hpte_group = ((hash & htab_hash_mask) *
1714 HPTES_PER_GROUP)&~0x7UL;
1716 mmu_hash_ops.hpte_remove(hpte_group);
1724 #ifdef CONFIG_DEBUG_PAGEALLOC
1725 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1728 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1729 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1730 unsigned long mode = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL));
1733 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1735 /* Don't create HPTE entries for bad address */
1739 ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode,
1741 mmu_linear_psize, mmu_kernel_ssize);
1744 spin_lock(&linear_map_hash_lock);
1745 BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1746 linear_map_hash_slots[lmi] = ret | 0x80;
1747 spin_unlock(&linear_map_hash_lock);
1750 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1752 unsigned long hash, hidx, slot;
1753 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1754 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1756 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1757 spin_lock(&linear_map_hash_lock);
1758 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1759 hidx = linear_map_hash_slots[lmi] & 0x7f;
1760 linear_map_hash_slots[lmi] = 0;
1761 spin_unlock(&linear_map_hash_lock);
1762 if (hidx & _PTEIDX_SECONDARY)
1764 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1765 slot += hidx & _PTEIDX_GROUP_IX;
1766 mmu_hash_ops.hpte_invalidate(slot, vpn, mmu_linear_psize,
1768 mmu_kernel_ssize, 0);
1771 void __kernel_map_pages(struct page *page, int numpages, int enable)
1773 unsigned long flags, vaddr, lmi;
1776 local_irq_save(flags);
1777 for (i = 0; i < numpages; i++, page++) {
1778 vaddr = (unsigned long)page_address(page);
1779 lmi = __pa(vaddr) >> PAGE_SHIFT;
1780 if (lmi >= linear_map_hash_count)
1783 kernel_map_linear_page(vaddr, lmi);
1785 kernel_unmap_linear_page(vaddr, lmi);
1787 local_irq_restore(flags);
1789 #endif /* CONFIG_DEBUG_PAGEALLOC */
1791 void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
1792 phys_addr_t first_memblock_size)
1794 /* We don't currently support the first MEMBLOCK not mapping 0
1795 * physical on those processors
1797 BUG_ON(first_memblock_base != 0);
1799 /* On LPAR systems, the first entry is our RMA region,
1800 * non-LPAR 64-bit hash MMU systems don't have a limitation
1801 * on real mode access, but using the first entry works well
1802 * enough. We also clamp it to 1G to avoid some funky things
1803 * such as RTAS bugs etc...
1805 ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);
1807 /* Finally limit subsequent allocations */
1808 memblock_set_current_limit(ppc64_rma_size);