2 * Support for PCI bridges found on Power Macintoshes.
4 * Copyright (C) 2003-2005 Benjamin Herrenschmuidt (benh@kernel.crashing.org)
5 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
13 #include <linux/kernel.h>
14 #include <linux/pci.h>
15 #include <linux/delay.h>
16 #include <linux/string.h>
17 #include <linux/init.h>
18 #include <linux/bootmem.h>
20 #include <asm/sections.h>
23 #include <asm/pci-bridge.h>
24 #include <asm/machdep.h>
25 #include <asm/pmac_feature.h>
26 #include <asm/grackle.h>
28 //#include <asm/iommu.h>
29 #include <asm/ppc-pci.h>
35 #define DBG(x...) printk(x)
40 static int add_bridge(struct device_node *dev);
42 /* XXX Could be per-controller, but I don't think we risk anything by
43 * assuming we won't have both UniNorth and Bandit */
44 static int has_uninorth;
46 static struct pci_controller *u3_agp;
47 static struct pci_controller *u4_pcie;
48 static struct pci_controller *u3_ht;
49 #define has_second_ohare 0
51 static int has_second_ohare;
52 #endif /* CONFIG_PPC64 */
54 extern u8 pci_cache_line_size;
55 extern int pcibios_assign_bus_offset;
57 struct device_node *k2_skiplist[2];
60 * Magic constants for enabling cache coherency in the bandit/PSX bridge.
62 #define BANDIT_DEVID_2 8
63 #define BANDIT_REVID 3
65 #define BANDIT_DEVNUM 11
66 #define BANDIT_MAGIC 0x50
67 #define BANDIT_COHERENT 0x40
69 static int __init fixup_one_level_bus_range(struct device_node *node, int higher)
71 for (; node != 0;node = node->sibling) {
73 unsigned int *class_code;
76 /* For PCI<->PCI bridges or CardBus bridges, we go down */
77 class_code = (unsigned int *) get_property(node, "class-code", NULL);
78 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
79 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
81 bus_range = (int *) get_property(node, "bus-range", &len);
82 if (bus_range != NULL && len > 2 * sizeof(int)) {
83 if (bus_range[1] > higher)
84 higher = bus_range[1];
86 higher = fixup_one_level_bus_range(node->child, higher);
91 /* This routine fixes the "bus-range" property of all bridges in the
92 * system since they tend to have their "last" member wrong on macs
94 * Note that the bus numbers manipulated here are OF bus numbers, they
95 * are not Linux bus numbers.
97 static void __init fixup_bus_range(struct device_node *bridge)
102 /* Lookup the "bus-range" property for the hose */
103 bus_range = (int *) get_property(bridge, "bus-range", &len);
104 if (bus_range == NULL || len < 2 * sizeof(int))
106 bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]);
110 * Apple MacRISC (U3, UniNorth, Bandit, Chaos) PCI controllers.
112 * The "Bandit" version is present in all early PCI PowerMacs,
113 * and up to the first ones using Grackle. Some machines may
114 * have 2 bandit controllers (2 PCI busses).
116 * "Chaos" is used in some "Bandit"-type machines as a bridge
117 * for the separate display bus. It is accessed the same
118 * way as bandit, but cannot be probed for devices. It therefore
119 * has its own config access functions.
121 * The "UniNorth" version is present in all Core99 machines
122 * (iBook, G4, new IMacs, and all the recent Apple machines).
123 * It contains 3 controllers in one ASIC.
125 * The U3 is the bridge used on G5 machines. It contains an
126 * AGP bus which is dealt with the old UniNorth access routines
127 * and a HyperTransport bus which uses its own set of access
131 #define MACRISC_CFA0(devfn, off) \
132 ((1 << (unsigned int)PCI_SLOT(dev_fn)) \
133 | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \
134 | (((unsigned int)(off)) & 0xFCUL))
136 #define MACRISC_CFA1(bus, devfn, off) \
137 ((((unsigned int)(bus)) << 16) \
138 |(((unsigned int)(devfn)) << 8) \
139 |(((unsigned int)(off)) & 0xFCUL) \
142 static volatile void __iomem *macrisc_cfg_access(struct pci_controller* hose,
143 u8 bus, u8 dev_fn, u8 offset)
147 if (bus == hose->first_busno) {
148 if (dev_fn < (11 << 3))
150 caddr = MACRISC_CFA0(dev_fn, offset);
152 caddr = MACRISC_CFA1(bus, dev_fn, offset);
154 /* Uninorth will return garbage if we don't read back the value ! */
156 out_le32(hose->cfg_addr, caddr);
157 } while (in_le32(hose->cfg_addr) != caddr);
159 offset &= has_uninorth ? 0x07 : 0x03;
160 return hose->cfg_data + offset;
163 static int macrisc_read_config(struct pci_bus *bus, unsigned int devfn,
164 int offset, int len, u32 *val)
166 struct pci_controller *hose;
167 volatile void __iomem *addr;
169 hose = pci_bus_to_host(bus);
171 return PCIBIOS_DEVICE_NOT_FOUND;
173 return PCIBIOS_BAD_REGISTER_NUMBER;
174 addr = macrisc_cfg_access(hose, bus->number, devfn, offset);
176 return PCIBIOS_DEVICE_NOT_FOUND;
178 * Note: the caller has already checked that offset is
179 * suitably aligned and that len is 1, 2 or 4.
186 *val = in_le16(addr);
189 *val = in_le32(addr);
192 return PCIBIOS_SUCCESSFUL;
195 static int macrisc_write_config(struct pci_bus *bus, unsigned int devfn,
196 int offset, int len, u32 val)
198 struct pci_controller *hose;
199 volatile void __iomem *addr;
201 hose = pci_bus_to_host(bus);
203 return PCIBIOS_DEVICE_NOT_FOUND;
205 return PCIBIOS_BAD_REGISTER_NUMBER;
206 addr = macrisc_cfg_access(hose, bus->number, devfn, offset);
208 return PCIBIOS_DEVICE_NOT_FOUND;
210 * Note: the caller has already checked that offset is
211 * suitably aligned and that len is 1, 2 or 4.
220 (void) in_le16(addr);
224 (void) in_le32(addr);
227 return PCIBIOS_SUCCESSFUL;
230 static struct pci_ops macrisc_pci_ops =
238 * Verify that a specific (bus, dev_fn) exists on chaos
240 static int chaos_validate_dev(struct pci_bus *bus, int devfn, int offset)
242 struct device_node *np;
243 u32 *vendor, *device;
246 return PCIBIOS_BAD_REGISTER_NUMBER;
247 np = pci_busdev_to_OF_node(bus, devfn);
249 return PCIBIOS_DEVICE_NOT_FOUND;
251 vendor = (u32 *)get_property(np, "vendor-id", NULL);
252 device = (u32 *)get_property(np, "device-id", NULL);
253 if (vendor == NULL || device == NULL)
254 return PCIBIOS_DEVICE_NOT_FOUND;
256 if ((*vendor == 0x106b) && (*device == 3) && (offset >= 0x10)
257 && (offset != 0x14) && (offset != 0x18) && (offset <= 0x24))
258 return PCIBIOS_BAD_REGISTER_NUMBER;
260 return PCIBIOS_SUCCESSFUL;
264 chaos_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
267 int result = chaos_validate_dev(bus, devfn, offset);
268 if (result == PCIBIOS_BAD_REGISTER_NUMBER)
270 if (result != PCIBIOS_SUCCESSFUL)
272 return macrisc_read_config(bus, devfn, offset, len, val);
276 chaos_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
279 int result = chaos_validate_dev(bus, devfn, offset);
280 if (result != PCIBIOS_SUCCESSFUL)
282 return macrisc_write_config(bus, devfn, offset, len, val);
285 static struct pci_ops chaos_pci_ops =
291 static void __init setup_chaos(struct pci_controller *hose,
292 struct resource *addr)
294 /* assume a `chaos' bridge */
295 hose->ops = &chaos_pci_ops;
296 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000);
297 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000);
299 #endif /* CONFIG_PPC32 */
303 * These versions of U3 HyperTransport config space access ops do not
304 * implement self-view of the HT host yet
308 * This function deals with some "special cases" devices.
310 * 0 -> No special case
311 * 1 -> Skip the device but act as if the access was successfull
312 * (return 0xff's on reads, eventually, cache config space
313 * accesses in a later version)
314 * -1 -> Hide the device (unsuccessful acess)
316 static int u3_ht_skip_device(struct pci_controller *hose,
317 struct pci_bus *bus, unsigned int devfn)
319 struct device_node *busdn, *dn;
322 /* We only allow config cycles to devices that are in OF device-tree
323 * as we are apparently having some weird things going on with some
324 * revs of K2 on recent G5s
327 busdn = pci_device_to_OF_node(bus->self);
329 busdn = hose->arch_data;
330 for (dn = busdn->child; dn; dn = dn->sibling)
331 if (PCI_DN(dn) && PCI_DN(dn)->devfn == devfn)
337 * When a device in K2 is powered down, we die on config
338 * cycle accesses. Fix that here.
341 if (k2_skiplist[i] == dn)
347 #define U3_HT_CFA0(devfn, off) \
348 ((((unsigned int)devfn) << 8) | offset)
349 #define U3_HT_CFA1(bus, devfn, off) \
350 (U3_HT_CFA0(devfn, off) \
351 + (((unsigned int)bus) << 16) \
354 static volatile void __iomem *u3_ht_cfg_access(struct pci_controller* hose,
355 u8 bus, u8 devfn, u8 offset)
357 if (bus == hose->first_busno) {
358 /* For now, we don't self probe U3 HT bridge */
359 if (PCI_SLOT(devfn) == 0)
361 return hose->cfg_data + U3_HT_CFA0(devfn, offset);
363 return hose->cfg_data + U3_HT_CFA1(bus, devfn, offset);
366 static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
367 int offset, int len, u32 *val)
369 struct pci_controller *hose;
370 volatile void __iomem *addr;
372 hose = pci_bus_to_host(bus);
374 return PCIBIOS_DEVICE_NOT_FOUND;
376 return PCIBIOS_BAD_REGISTER_NUMBER;
377 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
379 return PCIBIOS_DEVICE_NOT_FOUND;
381 switch (u3_ht_skip_device(hose, bus, devfn)) {
389 *val = 0xffff; break;
391 *val = 0xfffffffful; break;
393 return PCIBIOS_SUCCESSFUL;
395 return PCIBIOS_DEVICE_NOT_FOUND;
399 * Note: the caller has already checked that offset is
400 * suitably aligned and that len is 1, 2 or 4.
407 *val = in_le16(addr);
410 *val = in_le32(addr);
413 return PCIBIOS_SUCCESSFUL;
416 static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
417 int offset, int len, u32 val)
419 struct pci_controller *hose;
420 volatile void __iomem *addr;
422 hose = pci_bus_to_host(bus);
424 return PCIBIOS_DEVICE_NOT_FOUND;
426 return PCIBIOS_BAD_REGISTER_NUMBER;
427 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
429 return PCIBIOS_DEVICE_NOT_FOUND;
431 switch (u3_ht_skip_device(hose, bus, devfn)) {
435 return PCIBIOS_SUCCESSFUL;
437 return PCIBIOS_DEVICE_NOT_FOUND;
441 * Note: the caller has already checked that offset is
442 * suitably aligned and that len is 1, 2 or 4.
451 (void) in_le16(addr);
454 out_le32((u32 __iomem *)addr, val);
455 (void) in_le32(addr);
458 return PCIBIOS_SUCCESSFUL;
461 static struct pci_ops u3_ht_pci_ops =
467 #define U4_PCIE_CFA0(devfn, off) \
468 ((1 << ((unsigned int)PCI_SLOT(dev_fn))) \
469 | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \
470 | ((((unsigned int)(off)) >> 8) << 28) \
471 | (((unsigned int)(off)) & 0xfcU))
473 #define U4_PCIE_CFA1(bus, devfn, off) \
474 ((((unsigned int)(bus)) << 16) \
475 |(((unsigned int)(devfn)) << 8) \
476 | ((((unsigned int)(off)) >> 8) << 28) \
477 |(((unsigned int)(off)) & 0xfcU) \
480 static volatile void __iomem *u4_pcie_cfg_access(struct pci_controller* hose,
481 u8 bus, u8 dev_fn, int offset)
485 if (bus == hose->first_busno) {
486 caddr = U4_PCIE_CFA0(dev_fn, offset);
488 caddr = U4_PCIE_CFA1(bus, dev_fn, offset);
490 /* Uninorth will return garbage if we don't read back the value ! */
492 out_le32(hose->cfg_addr, caddr);
493 } while (in_le32(hose->cfg_addr) != caddr);
496 return hose->cfg_data + offset;
499 static int u4_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
500 int offset, int len, u32 *val)
502 struct pci_controller *hose;
503 volatile void __iomem *addr;
505 hose = pci_bus_to_host(bus);
507 return PCIBIOS_DEVICE_NOT_FOUND;
508 if (offset >= 0x1000)
509 return PCIBIOS_BAD_REGISTER_NUMBER;
510 addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset);
512 return PCIBIOS_DEVICE_NOT_FOUND;
514 * Note: the caller has already checked that offset is
515 * suitably aligned and that len is 1, 2 or 4.
522 *val = in_le16(addr);
525 *val = in_le32(addr);
528 return PCIBIOS_SUCCESSFUL;
531 static int u4_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
532 int offset, int len, u32 val)
534 struct pci_controller *hose;
535 volatile void __iomem *addr;
537 hose = pci_bus_to_host(bus);
539 return PCIBIOS_DEVICE_NOT_FOUND;
540 if (offset >= 0x1000)
541 return PCIBIOS_BAD_REGISTER_NUMBER;
542 addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset);
544 return PCIBIOS_DEVICE_NOT_FOUND;
546 * Note: the caller has already checked that offset is
547 * suitably aligned and that len is 1, 2 or 4.
556 (void) in_le16(addr);
560 (void) in_le32(addr);
563 return PCIBIOS_SUCCESSFUL;
566 static struct pci_ops u4_pcie_pci_ops =
572 #endif /* CONFIG_PPC64 */
576 * For a bandit bridge, turn on cache coherency if necessary.
577 * N.B. we could clean this up using the hose ops directly.
579 static void __init init_bandit(struct pci_controller *bp)
581 unsigned int vendev, magic;
584 /* read the word at offset 0 in config space for device 11 */
585 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + PCI_VENDOR_ID);
587 vendev = in_le32(bp->cfg_data);
588 if (vendev == (PCI_DEVICE_ID_APPLE_BANDIT << 16) +
589 PCI_VENDOR_ID_APPLE) {
590 /* read the revision id */
591 out_le32(bp->cfg_addr,
592 (1UL << BANDIT_DEVNUM) + PCI_REVISION_ID);
594 rev = in_8(bp->cfg_data);
595 if (rev != BANDIT_REVID)
597 "Unknown revision %d for bandit\n", rev);
598 } else if (vendev != (BANDIT_DEVID_2 << 16) + PCI_VENDOR_ID_APPLE) {
599 printk(KERN_WARNING "bandit isn't? (%x)\n", vendev);
603 /* read the word at offset 0x50 */
604 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + BANDIT_MAGIC);
606 magic = in_le32(bp->cfg_data);
607 if ((magic & BANDIT_COHERENT) != 0)
609 magic |= BANDIT_COHERENT;
611 out_le32(bp->cfg_data, magic);
612 printk(KERN_INFO "Cache coherency enabled for bandit/PSX\n");
616 * Tweak the PCI-PCI bridge chip on the blue & white G3s.
618 static void __init init_p2pbridge(void)
620 struct device_node *p2pbridge;
621 struct pci_controller* hose;
625 /* XXX it would be better here to identify the specific
626 PCI-PCI bridge chip we have. */
627 if ((p2pbridge = find_devices("pci-bridge")) == 0
628 || p2pbridge->parent == NULL
629 || strcmp(p2pbridge->parent->name, "pci") != 0)
631 if (pci_device_from_OF_node(p2pbridge, &bus, &devfn) < 0) {
632 DBG("Can't find PCI infos for PCI<->PCI bridge\n");
635 /* Warning: At this point, we have not yet renumbered all busses.
636 * So we must use OF walking to find out hose
638 hose = pci_find_hose_for_OF_device(p2pbridge);
640 DBG("Can't find hose for PCI<->PCI bridge\n");
643 if (early_read_config_word(hose, bus, devfn,
644 PCI_BRIDGE_CONTROL, &val) < 0) {
645 printk(KERN_ERR "init_p2pbridge: couldn't read bridge"
649 val &= ~PCI_BRIDGE_CTL_MASTER_ABORT;
650 early_write_config_word(hose, bus, devfn, PCI_BRIDGE_CONTROL, val);
653 static void __init init_second_ohare(void)
655 struct device_node *np = of_find_node_by_name(NULL, "pci106b,7");
656 unsigned char bus, devfn;
662 /* This must run before we initialize the PICs since the second
663 * ohare hosts a PIC that will be accessed there.
665 if (pci_device_from_OF_node(np, &bus, &devfn) == 0) {
666 struct pci_controller* hose =
667 pci_find_hose_for_OF_device(np);
669 printk(KERN_ERR "Can't find PCI hose for OHare2 !\n");
672 early_read_config_word(hose, bus, devfn, PCI_COMMAND, &cmd);
673 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
674 cmd &= ~PCI_COMMAND_IO;
675 early_write_config_word(hose, bus, devfn, PCI_COMMAND, cmd);
677 has_second_ohare = 1;
681 * Some Apple desktop machines have a NEC PD720100A USB2 controller
682 * on the motherboard. Open Firmware, on these, will disable the
683 * EHCI part of it so it behaves like a pair of OHCI's. This fixup
684 * code re-enables it ;)
686 static void __init fixup_nec_usb2(void)
688 struct device_node *nec;
690 for (nec = NULL; (nec = of_find_node_by_name(nec, "usb")) != NULL;) {
691 struct pci_controller *hose;
695 prop = (u32 *)get_property(nec, "vendor-id", NULL);
700 prop = (u32 *)get_property(nec, "device-id", NULL);
705 prop = (u32 *)get_property(nec, "reg", NULL);
708 devfn = (prop[0] >> 8) & 0xff;
709 bus = (prop[0] >> 16) & 0xff;
710 if (PCI_FUNC(devfn) != 0)
712 hose = pci_find_hose_for_OF_device(nec);
715 early_read_config_dword(hose, bus, devfn, 0xe4, &data);
717 printk("Found NEC PD720100A USB2 chip with disabled"
718 " EHCI, fixing up...\n");
720 early_write_config_dword(hose, bus, devfn, 0xe4, data);
725 static void __init setup_bandit(struct pci_controller *hose,
726 struct resource *addr)
728 hose->ops = ¯isc_pci_ops;
729 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000);
730 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000);
734 static int __init setup_uninorth(struct pci_controller *hose,
735 struct resource *addr)
737 pci_assign_all_buses = 1;
739 hose->ops = ¯isc_pci_ops;
740 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000);
741 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000);
742 /* We "know" that the bridge at f2000000 has the PCI slots. */
743 return addr->start == 0xf2000000;
745 #endif /* CONFIG_PPC32 */
748 static void __init setup_u3_agp(struct pci_controller* hose)
750 /* On G5, we move AGP up to high bus number so we don't need
751 * to reassign bus numbers for HT. If we ever have P2P bridges
752 * on AGP, we'll have to move pci_assign_all_busses to the
753 * pci_controller structure so we enable it for AGP and not for
755 * We hard code the address because of the different size of
756 * the reg address cell, we shall fix that by killing struct
757 * reg_property and using some accessor functions instead
759 hose->first_busno = 0xf0;
760 hose->last_busno = 0xff;
762 hose->ops = ¯isc_pci_ops;
763 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
764 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
768 static void __init setup_u4_pcie(struct pci_controller* hose)
770 /* We currently only implement the "non-atomic" config space, to
771 * be optimised later.
773 hose->ops = &u4_pcie_pci_ops;
774 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
775 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
777 /* The bus contains a bridge from root -> device, we need to
778 * make it visible on bus 0 so that we pick the right type
779 * of config cycles. If we didn't, we would have to force all
780 * config cycles to be type 1. So we override the "bus-range"
783 hose->first_busno = 0x00;
784 hose->last_busno = 0xff;
788 static void __init setup_u3_ht(struct pci_controller* hose)
790 struct device_node *np = (struct device_node *)hose->arch_data;
791 struct pci_controller *other = NULL;
795 hose->ops = &u3_ht_pci_ops;
797 /* We hard code the address because of the different size of
798 * the reg address cell, we shall fix that by killing struct
799 * reg_property and using some accessor functions instead
801 hose->cfg_data = ioremap(0xf2000000, 0x02000000);
804 * /ht node doesn't expose a "ranges" property, so we "remove"
805 * regions that have been allocated to AGP. So far, this version of
806 * the code doesn't assign any of the 0xfxxxxxxx "fine" memory regions
807 * to /ht. We need to fix that sooner or later by either parsing all
808 * child "ranges" properties or figuring out the U3 address space
809 * decoding logic and then read its configuration register (if any).
811 hose->io_base_phys = 0xf4000000;
812 hose->pci_io_size = 0x00400000;
813 hose->io_resource.name = np->full_name;
814 hose->io_resource.start = 0;
815 hose->io_resource.end = 0x003fffff;
816 hose->io_resource.flags = IORESOURCE_IO;
817 hose->pci_mem_offset = 0;
818 hose->first_busno = 0;
819 hose->last_busno = 0xef;
820 hose->mem_resources[0].name = np->full_name;
821 hose->mem_resources[0].start = 0x80000000;
822 hose->mem_resources[0].end = 0xefffffff;
823 hose->mem_resources[0].flags = IORESOURCE_MEM;
829 else if (u4_pcie != NULL)
833 DBG("U3/4 has no AGP/PCIE, using full resource range\n");
837 /* Fixup bus range vs. PCIE */
839 hose->last_busno = u4_pcie->first_busno - 1;
841 /* We "remove" the AGP resources from the resources allocated to HT,
842 * that is we create "holes". However, that code does assumptions
843 * that so far happen to be true (cross fingers...), typically that
844 * resources in the AGP node are properly ordered
847 for (i=0; i<3; i++) {
848 struct resource *res = &other->mem_resources[i];
849 if (res->flags != IORESOURCE_MEM)
851 /* We don't care about "fine" resources */
852 if (res->start >= 0xf0000000)
854 /* Check if it's just a matter of "shrinking" us in one
857 if (hose->mem_resources[cur].start == res->start) {
858 DBG("U3/HT: shrink start of %d, %08lx -> %08lx\n",
859 cur, hose->mem_resources[cur].start,
861 hose->mem_resources[cur].start = res->end + 1;
864 if (hose->mem_resources[cur].end == res->end) {
865 DBG("U3/HT: shrink end of %d, %08lx -> %08lx\n",
866 cur, hose->mem_resources[cur].end,
868 hose->mem_resources[cur].end = res->start - 1;
871 /* No, it's not the case, we need a hole */
873 /* not enough resources for a hole, we drop part
876 printk(KERN_WARNING "Running out of resources"
877 " for /ht host !\n");
878 hose->mem_resources[cur].end = res->start - 1;
882 DBG("U3/HT: hole, %d end at %08lx, %d start at %08lx\n",
883 cur-1, res->start - 1, cur, res->end + 1);
884 hose->mem_resources[cur].name = np->full_name;
885 hose->mem_resources[cur].flags = IORESOURCE_MEM;
886 hose->mem_resources[cur].start = res->end + 1;
887 hose->mem_resources[cur].end = hose->mem_resources[cur-1].end;
888 hose->mem_resources[cur-1].end = res->start - 1;
891 #endif /* CONFIG_PPC64 */
894 * We assume that if we have a G3 powermac, we have one bridge called
895 * "pci" (a MPC106) and no bandit or chaos bridges, and contrariwise,
896 * if we have one or more bandit or chaos bridges, we don't have a MPC106.
898 static int __init add_bridge(struct device_node *dev)
901 struct pci_controller *hose;
902 struct resource rsrc;
905 int primary = 1, has_address = 0;
907 DBG("Adding PCI host bridge %s\n", dev->full_name);
909 /* Fetch host bridge registers address */
910 has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
912 /* Get bus range if any */
913 bus_range = (int *) get_property(dev, "bus-range", &len);
914 if (bus_range == NULL || len < 2 * sizeof(int)) {
915 printk(KERN_WARNING "Can't get bus-range for %s, assume"
916 " bus 0\n", dev->full_name);
919 /* XXX Different prototypes, to be merged */
921 hose = pcibios_alloc_controller(dev);
923 hose = pcibios_alloc_controller();
927 hose->arch_data = dev;
928 hose->first_busno = bus_range ? bus_range[0] : 0;
929 hose->last_busno = bus_range ? bus_range[1] : 0xff;
933 /* 64 bits only bridges */
935 if (device_is_compatible(dev, "u3-agp")) {
937 disp_name = "U3-AGP";
939 } else if (device_is_compatible(dev, "u3-ht")) {
943 } else if (device_is_compatible(dev, "u4-pcie")) {
945 disp_name = "U4-PCIE";
948 printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number:"
949 " %d->%d\n", disp_name, hose->first_busno, hose->last_busno);
950 #endif /* CONFIG_PPC64 */
952 /* 32 bits only bridges */
954 if (device_is_compatible(dev, "uni-north")) {
955 primary = setup_uninorth(hose, &rsrc);
956 disp_name = "UniNorth";
957 } else if (strcmp(dev->name, "pci") == 0) {
958 /* XXX assume this is a mpc106 (grackle) */
960 disp_name = "Grackle (MPC106)";
961 } else if (strcmp(dev->name, "bandit") == 0) {
962 setup_bandit(hose, &rsrc);
963 disp_name = "Bandit";
964 } else if (strcmp(dev->name, "chaos") == 0) {
965 setup_chaos(hose, &rsrc);
969 printk(KERN_INFO "Found %s PCI host bridge at 0x%016llx. "
970 "Firmware bus number: %d->%d\n",
971 disp_name, (unsigned long long)rsrc.start, hose->first_busno,
973 #endif /* CONFIG_PPC32 */
975 DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
976 hose, hose->cfg_addr, hose->cfg_data);
978 /* Interpret the "ranges" property */
979 /* This also maps the I/O region and sets isa_io/mem_base */
980 pci_process_bridge_OF_ranges(hose, dev, primary);
982 /* Fixup "bus-range" OF property */
983 fixup_bus_range(dev);
988 void __init pmac_pcibios_fixup(void)
990 struct pci_dev* dev = NULL;
992 for_each_pci_dev(dev) {
993 /* Read interrupt from the device-tree */
994 pci_read_irq_line(dev);
996 /* Fixup interrupt for the modem/ethernet combo controller.
997 * on machines with a second ohare chip.
998 * The number in the device tree (27) is bogus (correct for
999 * the ethernet-only board but not the combo ethernet/modem
1000 * board). The real interrupt is 28 on the second controller
1003 if (has_second_ohare &&
1004 dev->vendor == PCI_VENDOR_ID_DEC &&
1005 dev->device == PCI_DEVICE_ID_DEC_TULIP_PLUS)
1006 dev->irq = irq_create_mapping(NULL, 60, 0);
1011 static void __init pmac_fixup_phb_resources(void)
1013 struct pci_controller *hose, *tmp;
1015 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1016 printk(KERN_INFO "PCI Host %d, io start: %lx; io end: %lx\n",
1017 hose->global_number,
1018 hose->io_resource.start, hose->io_resource.end);
1023 void __init pmac_pci_init(void)
1025 struct device_node *np, *root;
1026 struct device_node *ht = NULL;
1028 root = of_find_node_by_path("/");
1030 printk(KERN_CRIT "pmac_pci_init: can't find root "
1031 "of device tree\n");
1034 for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) {
1035 if (np->name == NULL)
1037 if (strcmp(np->name, "bandit") == 0
1038 || strcmp(np->name, "chaos") == 0
1039 || strcmp(np->name, "pci") == 0) {
1040 if (add_bridge(np) == 0)
1043 if (strcmp(np->name, "ht") == 0) {
1051 /* Probe HT last as it relies on the agp resources to be already
1054 if (ht && add_bridge(ht) != 0)
1058 * We need to call pci_setup_phb_io for the HT bridge first
1059 * so it gets the I/O port numbers starting at 0, and we
1060 * need to call it for the AGP bridge after that so it gets
1061 * small positive I/O port numbers.
1064 pci_setup_phb_io(u3_ht, 1);
1066 pci_setup_phb_io(u3_agp, 0);
1068 pci_setup_phb_io(u4_pcie, 0);
1071 * On ppc64, fixup the IO resources on our host bridges as
1072 * the common code does it only for children of the host bridges
1074 pmac_fixup_phb_resources();
1076 /* Setup the linkage between OF nodes and PHBs */
1077 pci_devs_phb_init();
1079 /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We
1080 * assume there is no P2P bridge on the AGP bus, which should be a
1081 * safe assumptions for now. We should do something better in the
1085 struct device_node *np = u3_agp->arch_data;
1086 PCI_DN(np)->busno = 0xf0;
1087 for (np = np->child; np; np = np->sibling)
1088 PCI_DN(np)->busno = 0xf0;
1090 /* pmac_check_ht_link(); */
1092 /* Tell pci.c to not use the common resource allocation mechanism */
1095 #else /* CONFIG_PPC64 */
1097 init_second_ohare();
1100 /* We are still having some issues with the Xserve G4, enabling
1101 * some offset between bus number and domains for now when we
1102 * assign all busses should help for now
1104 if (pci_assign_all_buses)
1105 pcibios_assign_bus_offset = 0x10;
1110 pmac_pci_enable_device_hook(struct pci_dev *dev, int initial)
1112 struct device_node* node;
1116 node = pci_device_to_OF_node(dev);
1118 /* We don't want to enable USB controllers absent from the OF tree
1119 * (iBook second controller)
1121 if (dev->vendor == PCI_VENDOR_ID_APPLE
1122 && dev->class == PCI_CLASS_SERIAL_USB_OHCI
1124 printk(KERN_INFO "Apple USB OHCI %s disabled by firmware\n",
1132 uninorth_child = node->parent &&
1133 device_is_compatible(node->parent, "uni-north");
1135 /* Firewire & GMAC were disabled after PCI probe, the driver is
1136 * claiming them, we must re-enable them now.
1138 if (uninorth_child && !strcmp(node->name, "firewire") &&
1139 (device_is_compatible(node, "pci106b,18") ||
1140 device_is_compatible(node, "pci106b,30") ||
1141 device_is_compatible(node, "pci11c1,5811"))) {
1142 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, node, 0, 1);
1143 pmac_call_feature(PMAC_FTR_1394_ENABLE, node, 0, 1);
1146 if (uninorth_child && !strcmp(node->name, "ethernet") &&
1147 device_is_compatible(node, "gmac")) {
1148 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, node, 0, 1);
1156 * Make sure PCI is correctly configured
1158 * We use old pci_bios versions of the function since, by
1159 * default, gmac is not powered up, and so will be absent
1160 * from the kernel initial PCI lookup.
1162 * Should be replaced by 2.4 new PCI mechanisms and really
1163 * register the device.
1165 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1166 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
1167 | PCI_COMMAND_INVALIDATE;
1168 pci_write_config_word(dev, PCI_COMMAND, cmd);
1169 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 16);
1170 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
1171 L1_CACHE_BYTES >> 2);
1177 /* We power down some devices after they have been probed. They'll
1178 * be powered back on later on
1180 void __init pmac_pcibios_after_init(void)
1182 struct device_node* nd;
1184 #ifdef CONFIG_BLK_DEV_IDE
1185 struct pci_dev *dev = NULL;
1187 /* OF fails to initialize IDE controllers on macs
1188 * (and maybe other machines)
1190 * Ideally, this should be moved to the IDE layer, but we need
1191 * to check specifically with Andre Hedrick how to do it cleanly
1192 * since the common IDE code seem to care about the fact that the
1193 * BIOS may have disabled a controller.
1197 for_each_pci_dev(dev) {
1198 if ((dev->class >> 16) == PCI_BASE_CLASS_STORAGE)
1199 pci_enable_device(dev);
1201 #endif /* CONFIG_BLK_DEV_IDE */
1203 nd = find_devices("firewire");
1205 if (nd->parent && (device_is_compatible(nd, "pci106b,18") ||
1206 device_is_compatible(nd, "pci106b,30") ||
1207 device_is_compatible(nd, "pci11c1,5811"))
1208 && device_is_compatible(nd->parent, "uni-north")) {
1209 pmac_call_feature(PMAC_FTR_1394_ENABLE, nd, 0, 0);
1210 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, nd, 0, 0);
1214 nd = find_devices("ethernet");
1216 if (nd->parent && device_is_compatible(nd, "gmac")
1217 && device_is_compatible(nd->parent, "uni-north"))
1218 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, nd, 0, 0);
1224 void pmac_pci_fixup_cardbus(struct pci_dev* dev)
1226 if (!machine_is(powermac))
1229 * Fix the interrupt routing on the various cardbus bridges
1230 * used on powerbooks
1232 if (dev->vendor != PCI_VENDOR_ID_TI)
1234 if (dev->device == PCI_DEVICE_ID_TI_1130 ||
1235 dev->device == PCI_DEVICE_ID_TI_1131) {
1237 /* Enable PCI interrupt */
1238 if (pci_read_config_byte(dev, 0x91, &val) == 0)
1239 pci_write_config_byte(dev, 0x91, val | 0x30);
1240 /* Disable ISA interrupt mode */
1241 if (pci_read_config_byte(dev, 0x92, &val) == 0)
1242 pci_write_config_byte(dev, 0x92, val & ~0x06);
1244 if (dev->device == PCI_DEVICE_ID_TI_1210 ||
1245 dev->device == PCI_DEVICE_ID_TI_1211 ||
1246 dev->device == PCI_DEVICE_ID_TI_1410 ||
1247 dev->device == PCI_DEVICE_ID_TI_1510) {
1249 /* 0x8c == TI122X_IRQMUX, 2 says to route the INTA
1250 signal out the MFUNC0 pin */
1251 if (pci_read_config_byte(dev, 0x8c, &val) == 0)
1252 pci_write_config_byte(dev, 0x8c, (val & ~0x0f) | 2);
1253 /* Disable ISA interrupt mode */
1254 if (pci_read_config_byte(dev, 0x92, &val) == 0)
1255 pci_write_config_byte(dev, 0x92, val & ~0x06);
1259 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_ANY_ID, pmac_pci_fixup_cardbus);
1261 void pmac_pci_fixup_pciata(struct pci_dev* dev)
1266 * On PowerMacs, we try to switch any PCI ATA controller to
1269 if (!machine_is(powermac))
1272 /* Some controllers don't have the class IDE */
1273 if (dev->vendor == PCI_VENDOR_ID_PROMISE)
1274 switch(dev->device) {
1275 case PCI_DEVICE_ID_PROMISE_20246:
1276 case PCI_DEVICE_ID_PROMISE_20262:
1277 case PCI_DEVICE_ID_PROMISE_20263:
1278 case PCI_DEVICE_ID_PROMISE_20265:
1279 case PCI_DEVICE_ID_PROMISE_20267:
1280 case PCI_DEVICE_ID_PROMISE_20268:
1281 case PCI_DEVICE_ID_PROMISE_20269:
1282 case PCI_DEVICE_ID_PROMISE_20270:
1283 case PCI_DEVICE_ID_PROMISE_20271:
1284 case PCI_DEVICE_ID_PROMISE_20275:
1285 case PCI_DEVICE_ID_PROMISE_20276:
1286 case PCI_DEVICE_ID_PROMISE_20277:
1289 /* Others, check PCI class */
1290 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
1293 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1294 if ((progif & 5) != 5) {
1295 printk(KERN_INFO "Forcing PCI IDE into native mode: %s\n",
1297 (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5);
1298 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) ||
1300 printk(KERN_ERR "Rewrite of PROGIF failed !\n");
1303 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pmac_pci_fixup_pciata);
1307 * Disable second function on K2-SATA, it's broken
1308 * and disable IO BARs on first one
1310 static void fixup_k2_sata(struct pci_dev* dev)
1315 if (PCI_FUNC(dev->devfn) > 0) {
1316 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1317 cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1318 pci_write_config_word(dev, PCI_COMMAND, cmd);
1319 for (i = 0; i < 6; i++) {
1320 dev->resource[i].start = dev->resource[i].end = 0;
1321 dev->resource[i].flags = 0;
1322 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i,
1326 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1327 cmd &= ~PCI_COMMAND_IO;
1328 pci_write_config_word(dev, PCI_COMMAND, cmd);
1329 for (i = 0; i < 5; i++) {
1330 dev->resource[i].start = dev->resource[i].end = 0;
1331 dev->resource[i].flags = 0;
1332 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i,
1337 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 0x0240, fixup_k2_sata);