arch/powerpc/platforms/powernv/eeh-powernv.c

   1 /*
   2  * The file intends to implement the platform dependent EEH operations on
   3  * powernv platform. Actually, the powernv was created in order to fully
   4  * hypervisor support.
   5  *
   6  * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/atomic.h>
  15 #include <linux/debugfs.h>
  16 #include <linux/delay.h>
  17 #include <linux/export.h>
  18 #include <linux/init.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/list.h>
  21 #include <linux/msi.h>
  22 #include <linux/of.h>
  23 #include <linux/pci.h>
  24 #include <linux/proc_fs.h>
  25 #include <linux/rbtree.h>
  26 #include <linux/sched.h>
  27 #include <linux/seq_file.h>
  28 #include <linux/spinlock.h>
  29
  30 #include <asm/eeh.h>
  31 #include <asm/eeh_event.h>
  32 #include <asm/firmware.h>
  33 #include <asm/io.h>
  34 #include <asm/iommu.h>
  35 #include <asm/machdep.h>
  36 #include <asm/msi_bitmap.h>
  37 #include <asm/opal.h>
  38 #include <asm/ppc-pci.h>
  39
  40 #include "powernv.h"
  41 #include "pci.h"
  42
  43 static bool pnv_eeh_nb_init = false;
  44 static int eeh_event_irq = -EINVAL;
  45
  46 static int pnv_eeh_init(void)
  47 {
  48         struct pci_controller *hose;
  49         struct pnv_phb *phb;
  50
  51         if (!firmware_has_feature(FW_FEATURE_OPAL)) {
  52                 pr_warn("%s: OPAL is required !\n",
  53                         __func__);
  54                 return -EINVAL;
  55         }
  56
  57         /* Set probe mode */
  58         eeh_add_flag(EEH_PROBE_MODE_DEV);
  59
  60         /*
  61          * P7IOC blocks PCI config access to frozen PE, but PHB3
  62          * doesn't do that. So we have to selectively enable I/O
  63          * prior to collecting error log.
  64          */
  65         list_for_each_entry(hose, &hose_list, list_node) {
  66                 phb = hose->private_data;
  67
  68                 if (phb->model == PNV_PHB_MODEL_P7IOC)
  69                         eeh_add_flag(EEH_ENABLE_IO_FOR_LOG);
  70
  71                 /*
  72                  * PE#0 should be regarded as valid by EEH core
  73                  * if it's not the reserved one. Currently, we
  74                  * have the reserved PE#255 and PE#127 for PHB3
  75                  * and P7IOC separately. So we should regard
  76                  * PE#0 as valid for PHB3 and P7IOC.
  77                  */
  78                 if (phb->ioda.reserved_pe_idx != 0)
  79                         eeh_add_flag(EEH_VALID_PE_ZERO);
  80
  81                 break;
  82         }
  83
  84         return 0;
  85 }
  86
  87 static irqreturn_t pnv_eeh_event(int irq, void *data)
  88 {
  89         /*
  90          * We simply send a special EEH event if EEH has been
  91          * enabled. We don't care about EEH events until we've
  92          * finished processing the outstanding ones. Event processing
  93          * gets unmasked in next_error() if EEH is enabled.
  94          */
  95         disable_irq_nosync(irq);
  96
  97         if (eeh_enabled())
  98                 eeh_send_failure_event(NULL);
  99
 100         return IRQ_HANDLED;
 101 }
 102
 103 #ifdef CONFIG_DEBUG_FS
 104 static ssize_t pnv_eeh_ei_write(struct file *filp,
 105                                 const char __user *user_buf,
 106                                 size_t count, loff_t *ppos)
 107 {
 108         struct pci_controller *hose = filp->private_data;
 109         struct eeh_dev *edev;
 110         struct eeh_pe *pe;
 111         int pe_no, type, func;
 112         unsigned long addr, mask;
 113         char buf[50];
 114         int ret;
 115
 116         if (!eeh_ops || !eeh_ops->err_inject)
 117                 return -ENXIO;
 118
 119         /* Copy over argument buffer */
 120         ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count);
 121         if (!ret)
 122                 return -EFAULT;
 123
 124         /* Retrieve parameters */
 125         ret = sscanf(buf, "%x:%x:%x:%lx:%lx",
 126                      &pe_no, &type, &func, &addr, &mask);
 127         if (ret != 5)
 128                 return -EINVAL;
 129
 130         /* Retrieve PE */
 131         edev = kzalloc(sizeof(*edev), GFP_KERNEL);
 132         if (!edev)
 133                 return -ENOMEM;
 134         edev->phb = hose;
 135         edev->pe_config_addr = pe_no;
 136         pe = eeh_pe_get(edev);
 137         kfree(edev);
 138         if (!pe)
 139                 return -ENODEV;
 140
 141         /* Do error injection */
 142         ret = eeh_ops->err_inject(pe, type, func, addr, mask);
 143         return ret < 0 ? ret : count;
 144 }
 145
 146 static const struct file_operations pnv_eeh_ei_fops = {
 147         .open   = simple_open,
 148         .llseek = no_llseek,
 149         .write  = pnv_eeh_ei_write,
 150 };
 151
 152 static int pnv_eeh_dbgfs_set(void *data, int offset, u64 val)
 153 {
 154         struct pci_controller *hose = data;
 155         struct pnv_phb *phb = hose->private_data;
 156
 157         out_be64(phb->regs + offset, val);
 158         return 0;
 159 }
 160
 161 static int pnv_eeh_dbgfs_get(void *data, int offset, u64 *val)
 162 {
 163         struct pci_controller *hose = data;
 164         struct pnv_phb *phb = hose->private_data;
 165
 166         *val = in_be64(phb->regs + offset);
 167         return 0;
 168 }
 169
 170 #define PNV_EEH_DBGFS_ENTRY(name, reg)                          \
 171 static int pnv_eeh_dbgfs_set_##name(void *data, u64 val)        \
 172 {                                                               \
 173         return pnv_eeh_dbgfs_set(data, reg, val);               \
 174 }                                                               \
 175                                                                 \
 176 static int pnv_eeh_dbgfs_get_##name(void *data, u64 *val)       \
 177 {                                                               \
 178         return pnv_eeh_dbgfs_get(data, reg, val);               \
 179 }                                                               \
 180                                                                 \
 181 DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_dbgfs_ops_##name,               \
 182                         pnv_eeh_dbgfs_get_##name,               \
 183                         pnv_eeh_dbgfs_set_##name,               \
 184                         "0x%llx\n")
 185
 186 PNV_EEH_DBGFS_ENTRY(outb, 0xD10);
 187 PNV_EEH_DBGFS_ENTRY(inbA, 0xD90);
 188 PNV_EEH_DBGFS_ENTRY(inbB, 0xE10);
 189
 190 #endif /* CONFIG_DEBUG_FS */
 191
 192 /**
 193  * pnv_eeh_post_init - EEH platform dependent post initialization
 194  *
 195  * EEH platform dependent post initialization on powernv. When
 196  * the function is called, the EEH PEs and devices should have
 197  * been built. If the I/O cache staff has been built, EEH is
 198  * ready to supply service.
 199  */
 200 static int pnv_eeh_post_init(void)
 201 {
 202         struct pci_controller *hose;
 203         struct pnv_phb *phb;
 204         int ret = 0;
 205
 206         /* Register OPAL event notifier */
 207         if (!pnv_eeh_nb_init) {
 208                 eeh_event_irq = opal_event_request(ilog2(OPAL_EVENT_PCI_ERROR));
 209                 if (eeh_event_irq < 0) {
 210                         pr_err("%s: Can't register OPAL event interrupt (%d)\n",
 211                                __func__, eeh_event_irq);
 212                         return eeh_event_irq;
 213                 }
 214
 215                 ret = request_irq(eeh_event_irq, pnv_eeh_event,
 216                                 IRQ_TYPE_LEVEL_HIGH, "opal-eeh", NULL);
 217                 if (ret < 0) {
 218                         irq_dispose_mapping(eeh_event_irq);
 219                         pr_err("%s: Can't request OPAL event interrupt (%d)\n",
 220                                __func__, eeh_event_irq);
 221                         return ret;
 222                 }
 223
 224                 pnv_eeh_nb_init = true;
 225         }
 226
 227         if (!eeh_enabled())
 228                 disable_irq(eeh_event_irq);
 229
 230         list_for_each_entry(hose, &hose_list, list_node) {
 231                 phb = hose->private_data;
 232
 233                 /*
 234                  * If EEH is enabled, we're going to rely on that.
 235                  * Otherwise, we restore to conventional mechanism
 236                  * to clear frozen PE during PCI config access.
 237                  */
 238                 if (eeh_enabled())
 239                         phb->flags |= PNV_PHB_FLAG_EEH;
 240                 else
 241                         phb->flags &= ~PNV_PHB_FLAG_EEH;
 242
 243                 /* Create debugfs entries */
 244 #ifdef CONFIG_DEBUG_FS
 245                 if (phb->has_dbgfs || !phb->dbgfs)
 246                         continue;
 247
 248                 phb->has_dbgfs = 1;
 249                 debugfs_create_file("err_injct", 0200,
 250                                     phb->dbgfs, hose,
 251                                     &pnv_eeh_ei_fops);
 252
 253                 debugfs_create_file("err_injct_outbound", 0600,
 254                                     phb->dbgfs, hose,
 255                                     &pnv_eeh_dbgfs_ops_outb);
 256                 debugfs_create_file("err_injct_inboundA", 0600,
 257                                     phb->dbgfs, hose,
 258                                     &pnv_eeh_dbgfs_ops_inbA);
 259                 debugfs_create_file("err_injct_inboundB", 0600,
 260                                     phb->dbgfs, hose,
 261                                     &pnv_eeh_dbgfs_ops_inbB);
 262 #endif /* CONFIG_DEBUG_FS */
 263         }
 264
 265         return ret;
 266 }
 267
 268 static int pnv_eeh_find_cap(struct pci_dn *pdn, int cap)
 269 {
 270         int pos = PCI_CAPABILITY_LIST;
 271         int cnt = 48;   /* Maximal number of capabilities */
 272         u32 status, id;
 273
 274         if (!pdn)
 275                 return 0;
 276
 277         /* Check if the device supports capabilities */
 278         pnv_pci_cfg_read(pdn, PCI_STATUS, 2, &status);
 279         if (!(status & PCI_STATUS_CAP_LIST))
 280                 return 0;
 281
 282         while (cnt--) {
 283                 pnv_pci_cfg_read(pdn, pos, 1, &pos);
 284                 if (pos < 0x40)
 285                         break;
 286
 287                 pos &= ~3;
 288                 pnv_pci_cfg_read(pdn, pos + PCI_CAP_LIST_ID, 1, &id);
 289                 if (id == 0xff)
 290                         break;
 291
 292                 /* Found */
 293                 if (id == cap)
 294                         return pos;
 295
 296                 /* Next one */
 297                 pos += PCI_CAP_LIST_NEXT;
 298         }
 299
 300         return 0;
 301 }
 302
 303 static int pnv_eeh_find_ecap(struct pci_dn *pdn, int cap)
 304 {
 305         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
 306         u32 header;
 307         int pos = 256, ttl = (4096 - 256) / 8;
 308
 309         if (!edev || !edev->pcie_cap)
 310                 return 0;
 311         if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
 312                 return 0;
 313         else if (!header)
 314                 return 0;
 315
 316         while (ttl-- > 0) {
 317                 if (PCI_EXT_CAP_ID(header) == cap && pos)
 318                         return pos;
 319
 320                 pos = PCI_EXT_CAP_NEXT(header);
 321                 if (pos < 256)
 322                         break;
 323
 324                 if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
 325                         break;
 326         }
 327
 328         return 0;
 329 }
 330
 331 /**
 332  * pnv_eeh_probe - Do probe on PCI device
 333  * @pdn: PCI device node
 334  * @data: unused
 335  *
 336  * When EEH module is installed during system boot, all PCI devices
 337  * are checked one by one to see if it supports EEH. The function
 338  * is introduced for the purpose. By default, EEH has been enabled
 339  * on all PCI devices. That's to say, we only need do necessary
 340  * initialization on the corresponding eeh device and create PE
 341  * accordingly.
 342  *
 343  * It's notable that's unsafe to retrieve the EEH device through
 344  * the corresponding PCI device. During the PCI device hotplug, which
 345  * was possiblly triggered by EEH core, the binding between EEH device
 346  * and the PCI device isn't built yet.
 347  */
 348 static void *pnv_eeh_probe(struct pci_dn *pdn, void *data)
 349 {
 350         struct pci_controller *hose = pdn->phb;
 351         struct pnv_phb *phb = hose->private_data;
 352         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
 353         uint32_t pcie_flags;
 354         int ret;
 355
 356         /*
 357          * When probing the root bridge, which doesn't have any
 358          * subordinate PCI devices. We don't have OF node for
 359          * the root bridge. So it's not reasonable to continue
 360          * the probing.
 361          */
 362         if (!edev || edev->pe)
 363                 return NULL;
 364
 365         /* Skip for PCI-ISA bridge */
 366         if ((pdn->class_code >> 8) == PCI_CLASS_BRIDGE_ISA)
 367                 return NULL;
 368
 369         /* Initialize eeh device */
 370         edev->class_code = pdn->class_code;
 371         edev->mode      &= 0xFFFFFF00;
 372         edev->pcix_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_PCIX);
 373         edev->pcie_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_EXP);
 374         edev->af_cap   = pnv_eeh_find_cap(pdn, PCI_CAP_ID_AF);
 375         edev->aer_cap  = pnv_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR);
 376         if ((edev->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) {
 377                 edev->mode |= EEH_DEV_BRIDGE;
 378                 if (edev->pcie_cap) {
 379                         pnv_pci_cfg_read(pdn, edev->pcie_cap + PCI_EXP_FLAGS,
 380                                          2, &pcie_flags);
 381                         pcie_flags = (pcie_flags & PCI_EXP_FLAGS_TYPE) >> 4;
 382                         if (pcie_flags == PCI_EXP_TYPE_ROOT_PORT)
 383                                 edev->mode |= EEH_DEV_ROOT_PORT;
 384                         else if (pcie_flags == PCI_EXP_TYPE_DOWNSTREAM)
 385                                 edev->mode |= EEH_DEV_DS_PORT;
 386                 }
 387         }
 388
 389         edev->config_addr    = (pdn->busno << 8) | (pdn->devfn);
 390         edev->pe_config_addr = phb->ioda.pe_rmap[edev->config_addr];
 391
 392         /* Create PE */
 393         ret = eeh_add_to_parent_pe(edev);
 394         if (ret) {
 395                 pr_warn("%s: Can't add PCI dev %04x:%02x:%02x.%01x to parent PE (%d)\n",
 396                         __func__, hose->global_number, pdn->busno,
 397                         PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn), ret);
 398                 return NULL;
 399         }
 400
 401         /*
 402          * If the PE contains any one of following adapters, the
 403          * PCI config space can't be accessed when dumping EEH log.
 404          * Otherwise, we will run into fenced PHB caused by shortage
 405          * of outbound credits in the adapter. The PCI config access
 406          * should be blocked until PE reset. MMIO access is dropped
 407          * by hardware certainly. In order to drop PCI config requests,
 408          * one more flag (EEH_PE_CFG_RESTRICTED) is introduced, which
 409          * will be checked in the backend for PE state retrival. If
 410          * the PE becomes frozen for the first time and the flag has
 411          * been set for the PE, we will set EEH_PE_CFG_BLOCKED for
 412          * that PE to block its config space.
 413          *
 414          * Broadcom Austin 4-ports NICs (14e4:1657)
 415          * Broadcom Shiner 4-ports 1G NICs (14e4:168a)
 416          * Broadcom Shiner 2-ports 10G NICs (14e4:168e)
 417          */
 418         if ((pdn->vendor_id == PCI_VENDOR_ID_BROADCOM &&
 419              pdn->device_id == 0x1657) ||
 420             (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM &&
 421              pdn->device_id == 0x168a) ||
 422             (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM &&
 423              pdn->device_id == 0x168e))
 424                 edev->pe->state |= EEH_PE_CFG_RESTRICTED;
 425
 426         /*
 427          * Cache the PE primary bus, which can't be fetched when
 428          * full hotplug is in progress. In that case, all child
 429          * PCI devices of the PE are expected to be removed prior
 430          * to PE reset.
 431          */
 432         if (!(edev->pe->state & EEH_PE_PRI_BUS)) {
 433                 edev->pe->bus = pci_find_bus(hose->global_number,
 434                                              pdn->busno);
 435                 if (edev->pe->bus)
 436                         edev->pe->state |= EEH_PE_PRI_BUS;
 437         }
 438
 439         /*
 440          * Enable EEH explicitly so that we will do EEH check
 441          * while accessing I/O stuff
 442          */
 443         eeh_add_flag(EEH_ENABLED);
 444
 445         /* Save memory bars */
 446         eeh_save_bars(edev);
 447
 448         return NULL;
 449 }
 450
 451 /**
 452  * pnv_eeh_set_option - Initialize EEH or MMIO/DMA reenable
 453  * @pe: EEH PE
 454  * @option: operation to be issued
 455  *
 456  * The function is used to control the EEH functionality globally.
 457  * Currently, following options are support according to PAPR:
 458  * Enable EEH, Disable EEH, Enable MMIO and Enable DMA
 459  */
 460 static int pnv_eeh_set_option(struct eeh_pe *pe, int option)
 461 {
 462         struct pci_controller *hose = pe->phb;
 463         struct pnv_phb *phb = hose->private_data;
 464         bool freeze_pe = false;
 465         int opt;
 466         s64 rc;
 467
 468         switch (option) {
 469         case EEH_OPT_DISABLE:
 470                 return -EPERM;
 471         case EEH_OPT_ENABLE:
 472                 return 0;
 473         case EEH_OPT_THAW_MMIO:
 474                 opt = OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO;
 475                 break;
 476         case EEH_OPT_THAW_DMA:
 477                 opt = OPAL_EEH_ACTION_CLEAR_FREEZE_DMA;
 478                 break;
 479         case EEH_OPT_FREEZE_PE:
 480                 freeze_pe = true;
 481                 opt = OPAL_EEH_ACTION_SET_FREEZE_ALL;
 482                 break;
 483         default:
 484                 pr_warn("%s: Invalid option %d\n", __func__, option);
 485                 return -EINVAL;
 486         }
 487
 488         /* Freeze master and slave PEs if PHB supports compound PEs */
 489         if (freeze_pe) {
 490                 if (phb->freeze_pe) {
 491                         phb->freeze_pe(phb, pe->addr);
 492                         return 0;
 493                 }
 494
 495                 rc = opal_pci_eeh_freeze_set(phb->opal_id, pe->addr, opt);
 496                 if (rc != OPAL_SUCCESS) {
 497                         pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
 498                                 __func__, rc, phb->hose->global_number,
 499                                 pe->addr);
 500                         return -EIO;
 501                 }
 502
 503                 return 0;
 504         }
 505
 506         /* Unfreeze master and slave PEs if PHB supports */
 507         if (phb->unfreeze_pe)
 508                 return phb->unfreeze_pe(phb, pe->addr, opt);
 509
 510         rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe->addr, opt);
 511         if (rc != OPAL_SUCCESS) {
 512                 pr_warn("%s: Failure %lld enable %d for PHB#%x-PE#%x\n",
 513                         __func__, rc, option, phb->hose->global_number,
 514                         pe->addr);
 515                 return -EIO;
 516         }
 517
 518         return 0;
 519 }
 520
 521 /**
 522  * pnv_eeh_get_pe_addr - Retrieve PE address
 523  * @pe: EEH PE
 524  *
 525  * Retrieve the PE address according to the given tranditional
 526  * PCI BDF (Bus/Device/Function) address.
 527  */
 528 static int pnv_eeh_get_pe_addr(struct eeh_pe *pe)
 529 {
 530         return pe->addr;
 531 }
 532
 533 static void pnv_eeh_get_phb_diag(struct eeh_pe *pe)
 534 {
 535         struct pnv_phb *phb = pe->phb->private_data;
 536         s64 rc;
 537
 538         rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data,
 539                                          PNV_PCI_DIAG_BUF_SIZE);
 540         if (rc != OPAL_SUCCESS)
 541                 pr_warn("%s: Failure %lld getting PHB#%x diag-data\n",
 542                         __func__, rc, pe->phb->global_number);
 543 }
 544
 545 static int pnv_eeh_get_phb_state(struct eeh_pe *pe)
 546 {
 547         struct pnv_phb *phb = pe->phb->private_data;
 548         u8 fstate;
 549         __be16 pcierr;
 550         s64 rc;
 551         int result = 0;
 552
 553         rc = opal_pci_eeh_freeze_status(phb->opal_id,
 554                                         pe->addr,
 555                                         &fstate,
 556                                         &pcierr,
 557                                         NULL);
 558         if (rc != OPAL_SUCCESS) {
 559                 pr_warn("%s: Failure %lld getting PHB#%x state\n",
 560                         __func__, rc, phb->hose->global_number);
 561                 return EEH_STATE_NOT_SUPPORT;
 562         }
 563
 564         /*
 565          * Check PHB state. If the PHB is frozen for the
 566          * first time, to dump the PHB diag-data.
 567          */
 568         if (be16_to_cpu(pcierr) != OPAL_EEH_PHB_ERROR) {
 569                 result = (EEH_STATE_MMIO_ACTIVE  |
 570                           EEH_STATE_DMA_ACTIVE   |
 571                           EEH_STATE_MMIO_ENABLED |
 572                           EEH_STATE_DMA_ENABLED);
 573         } else if (!(pe->state & EEH_PE_ISOLATED)) {
 574                 eeh_pe_state_mark(pe, EEH_PE_ISOLATED);
 575                 pnv_eeh_get_phb_diag(pe);
 576
 577                 if (eeh_has_flag(EEH_EARLY_DUMP_LOG))
 578                         pnv_pci_dump_phb_diag_data(pe->phb, pe->data);
 579         }
 580
 581         return result;
 582 }
 583
 584 static int pnv_eeh_get_pe_state(struct eeh_pe *pe)
 585 {
 586         struct pnv_phb *phb = pe->phb->private_data;
 587         u8 fstate;
 588         __be16 pcierr;
 589         s64 rc;
 590         int result;
 591
 592         /*
 593          * We don't clobber hardware frozen state until PE
 594          * reset is completed. In order to keep EEH core
 595          * moving forward, we have to return operational
 596          * state during PE reset.
 597          */
 598         if (pe->state & EEH_PE_RESET) {
 599                 result = (EEH_STATE_MMIO_ACTIVE  |
 600                           EEH_STATE_DMA_ACTIVE   |
 601                           EEH_STATE_MMIO_ENABLED |
 602                           EEH_STATE_DMA_ENABLED);
 603                 return result;
 604         }
 605
 606         /*
 607          * Fetch PE state from hardware. If the PHB
 608          * supports compound PE, let it handle that.
 609          */
 610         if (phb->get_pe_state) {
 611                 fstate = phb->get_pe_state(phb, pe->addr);
 612         } else {
 613                 rc = opal_pci_eeh_freeze_status(phb->opal_id,
 614                                                 pe->addr,
 615                                                 &fstate,
 616                                                 &pcierr,
 617                                                 NULL);
 618                 if (rc != OPAL_SUCCESS) {
 619                         pr_warn("%s: Failure %lld getting PHB#%x-PE%x state\n",
 620                                 __func__, rc, phb->hose->global_number,
 621                                 pe->addr);
 622                         return EEH_STATE_NOT_SUPPORT;
 623                 }
 624         }
 625
 626         /* Figure out state */
 627         switch (fstate) {
 628         case OPAL_EEH_STOPPED_NOT_FROZEN:
 629                 result = (EEH_STATE_MMIO_ACTIVE  |
 630                           EEH_STATE_DMA_ACTIVE   |
 631                           EEH_STATE_MMIO_ENABLED |
 632                           EEH_STATE_DMA_ENABLED);
 633                 break;
 634         case OPAL_EEH_STOPPED_MMIO_FREEZE:
 635                 result = (EEH_STATE_DMA_ACTIVE |
 636                           EEH_STATE_DMA_ENABLED);
 637                 break;
 638         case OPAL_EEH_STOPPED_DMA_FREEZE:
 639                 result = (EEH_STATE_MMIO_ACTIVE |
 640                           EEH_STATE_MMIO_ENABLED);
 641                 break;
 642         case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE:
 643                 result = 0;
 644                 break;
 645         case OPAL_EEH_STOPPED_RESET:
 646                 result = EEH_STATE_RESET_ACTIVE;
 647                 break;
 648         case OPAL_EEH_STOPPED_TEMP_UNAVAIL:
 649                 result = EEH_STATE_UNAVAILABLE;
 650                 break;
 651         case OPAL_EEH_STOPPED_PERM_UNAVAIL:
 652                 result = EEH_STATE_NOT_SUPPORT;
 653                 break;
 654         default:
 655                 result = EEH_STATE_NOT_SUPPORT;
 656                 pr_warn("%s: Invalid PHB#%x-PE#%x state %x\n",
 657                         __func__, phb->hose->global_number,
 658                         pe->addr, fstate);
 659         }
 660
 661         /*
 662          * If PHB supports compound PE, to freeze all
 663          * slave PEs for consistency.
 664          *
 665          * If the PE is switching to frozen state for the
 666          * first time, to dump the PHB diag-data.
 667          */
 668         if (!(result & EEH_STATE_NOT_SUPPORT) &&
 669             !(result & EEH_STATE_UNAVAILABLE) &&
 670             !(result & EEH_STATE_MMIO_ACTIVE) &&
 671             !(result & EEH_STATE_DMA_ACTIVE)  &&
 672             !(pe->state & EEH_PE_ISOLATED)) {
 673                 if (phb->freeze_pe)
 674                         phb->freeze_pe(phb, pe->addr);
 675
 676                 eeh_pe_state_mark(pe, EEH_PE_ISOLATED);
 677                 pnv_eeh_get_phb_diag(pe);
 678
 679                 if (eeh_has_flag(EEH_EARLY_DUMP_LOG))
 680                         pnv_pci_dump_phb_diag_data(pe->phb, pe->data);
 681         }
 682
 683         return result;
 684 }
 685
 686 /**
 687  * pnv_eeh_get_state - Retrieve PE state
 688  * @pe: EEH PE
 689  * @delay: delay while PE state is temporarily unavailable
 690  *
 691  * Retrieve the state of the specified PE. For IODA-compitable
 692  * platform, it should be retrieved from IODA table. Therefore,
 693  * we prefer passing down to hardware implementation to handle
 694  * it.
 695  */
 696 static int pnv_eeh_get_state(struct eeh_pe *pe, int *delay)
 697 {
 698         int ret;
 699
 700         if (pe->type & EEH_PE_PHB)
 701                 ret = pnv_eeh_get_phb_state(pe);
 702         else
 703                 ret = pnv_eeh_get_pe_state(pe);
 704
 705         if (!delay)
 706                 return ret;
 707
 708         /*
 709          * If the PE state is temporarily unavailable,
 710          * to inform the EEH core delay for default
 711          * period (1 second)
 712          */
 713         *delay = 0;
 714         if (ret & EEH_STATE_UNAVAILABLE)
 715                 *delay = 1000;
 716
 717         return ret;
 718 }
 719
 720 static s64 pnv_eeh_phb_poll(struct pnv_phb *phb)
 721 {
 722         s64 rc = OPAL_HARDWARE;
 723
 724         while (1) {
 725                 rc = opal_pci_poll(phb->opal_id);
 726                 if (rc <= 0)
 727                         break;
 728
 729                 if (system_state < SYSTEM_RUNNING)
 730                         udelay(1000 * rc);
 731                 else
 732                         msleep(rc);
 733         }
 734
 735         return rc;
 736 }
 737
 738 int pnv_eeh_phb_reset(struct pci_controller *hose, int option)
 739 {
 740         struct pnv_phb *phb = hose->private_data;
 741         s64 rc = OPAL_HARDWARE;
 742
 743         pr_debug("%s: Reset PHB#%x, option=%d\n",
 744                  __func__, hose->global_number, option);
 745
 746         /* Issue PHB complete reset request */
 747         if (option == EEH_RESET_FUNDAMENTAL ||
 748             option == EEH_RESET_HOT)
 749                 rc = opal_pci_reset(phb->opal_id,
 750                                     OPAL_RESET_PHB_COMPLETE,
 751                                     OPAL_ASSERT_RESET);
 752         else if (option == EEH_RESET_DEACTIVATE)
 753                 rc = opal_pci_reset(phb->opal_id,
 754                                     OPAL_RESET_PHB_COMPLETE,
 755                                     OPAL_DEASSERT_RESET);
 756         if (rc < 0)
 757                 goto out;
 758
 759         /*
 760          * Poll state of the PHB until the request is done
 761          * successfully. The PHB reset is usually PHB complete
 762          * reset followed by hot reset on root bus. So we also
 763          * need the PCI bus settlement delay.
 764          */
 765         rc = pnv_eeh_phb_poll(phb);
 766         if (option == EEH_RESET_DEACTIVATE) {
 767                 if (system_state < SYSTEM_RUNNING)
 768                         udelay(1000 * EEH_PE_RST_SETTLE_TIME);
 769                 else
 770                         msleep(EEH_PE_RST_SETTLE_TIME);
 771         }
 772 out:
 773         if (rc != OPAL_SUCCESS)
 774                 return -EIO;
 775
 776         return 0;
 777 }
 778
 779 static int pnv_eeh_root_reset(struct pci_controller *hose, int option)
 780 {
 781         struct pnv_phb *phb = hose->private_data;
 782         s64 rc = OPAL_HARDWARE;
 783
 784         pr_debug("%s: Reset PHB#%x, option=%d\n",
 785                  __func__, hose->global_number, option);
 786
 787         /*
 788          * During the reset deassert time, we needn't care
 789          * the reset scope because the firmware does nothing
 790          * for fundamental or hot reset during deassert phase.
 791          */
 792         if (option == EEH_RESET_FUNDAMENTAL)
 793                 rc = opal_pci_reset(phb->opal_id,
 794                                     OPAL_RESET_PCI_FUNDAMENTAL,
 795                                     OPAL_ASSERT_RESET);
 796         else if (option == EEH_RESET_HOT)
 797                 rc = opal_pci_reset(phb->opal_id,
 798                                     OPAL_RESET_PCI_HOT,
 799                                     OPAL_ASSERT_RESET);
 800         else if (option == EEH_RESET_DEACTIVATE)
 801                 rc = opal_pci_reset(phb->opal_id,
 802                                     OPAL_RESET_PCI_HOT,
 803                                     OPAL_DEASSERT_RESET);
 804         if (rc < 0)
 805                 goto out;
 806
 807         /* Poll state of the PHB until the request is done */
 808         rc = pnv_eeh_phb_poll(phb);
 809         if (option == EEH_RESET_DEACTIVATE)
 810                 msleep(EEH_PE_RST_SETTLE_TIME);
 811 out:
 812         if (rc != OPAL_SUCCESS)
 813                 return -EIO;
 814
 815         return 0;
 816 }
 817
 818 static int pnv_eeh_bridge_reset(struct pci_dev *dev, int option)
 819 {
 820         struct pci_dn *pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn);
 821         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
 822         int aer = edev ? edev->aer_cap : 0;
 823         u32 ctrl;
 824
 825         pr_debug("%s: Reset PCI bus %04x:%02x with option %d\n",
 826                  __func__, pci_domain_nr(dev->bus),
 827                  dev->bus->number, option);
 828
 829         switch (option) {
 830         case EEH_RESET_FUNDAMENTAL:
 831         case EEH_RESET_HOT:
 832                 /* Don't report linkDown event */
 833                 if (aer) {
 834                         eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK,
 835                                              4, &ctrl);
 836                         ctrl |= PCI_ERR_UNC_SURPDN;
 837                         eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK,
 838                                               4, ctrl);
 839                 }
 840
 841                 eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl);
 842                 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
 843                 eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl);
 844
 845                 msleep(EEH_PE_RST_HOLD_TIME);
 846                 break;
 847         case EEH_RESET_DEACTIVATE:
 848                 eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl);
 849                 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
 850                 eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl);
 851
 852                 msleep(EEH_PE_RST_SETTLE_TIME);
 853
 854                 /* Continue reporting linkDown event */
 855                 if (aer) {
 856                         eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK,
 857                                              4, &ctrl);
 858                         ctrl &= ~PCI_ERR_UNC_SURPDN;
 859                         eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK,
 860                                               4, ctrl);
 861                 }
 862
 863                 break;
 864         }
 865
 866         return 0;
 867 }
 868
 869 void pnv_pci_reset_secondary_bus(struct pci_dev *dev)
 870 {
 871         pnv_eeh_bridge_reset(dev, EEH_RESET_HOT);
 872         pnv_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE);
 873 }
 874
 875 static void pnv_eeh_wait_for_pending(struct pci_dn *pdn, const char *type,
 876                                      int pos, u16 mask)
 877 {
 878         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
 879         int i, status = 0;
 880
 881         /* Wait for Transaction Pending bit to be cleared */
 882         for (i = 0; i < 4; i++) {
 883                 eeh_ops->read_config(pdn, pos, 2, &status);
 884                 if (!(status & mask))
 885                         return;
 886
 887                 msleep((1 << i) * 100);
 888         }
 889
 890         pr_warn("%s: Pending transaction while issuing %sFLR to %04x:%02x:%02x.%01x\n",
 891                 __func__, type,
 892                 edev->phb->global_number, pdn->busno,
 893                 PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn));
 894 }
 895
 896 static int pnv_eeh_do_flr(struct pci_dn *pdn, int option)
 897 {
 898         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
 899         u32 reg = 0;
 900
 901         if (WARN_ON(!edev->pcie_cap))
 902                 return -ENOTTY;
 903
 904         eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCAP, 4, &reg);
 905         if (!(reg & PCI_EXP_DEVCAP_FLR))
 906                 return -ENOTTY;
 907
 908         switch (option) {
 909         case EEH_RESET_HOT:
 910         case EEH_RESET_FUNDAMENTAL:
 911                 pnv_eeh_wait_for_pending(pdn, "",
 912                                          edev->pcie_cap + PCI_EXP_DEVSTA,
 913                                          PCI_EXP_DEVSTA_TRPND);
 914                 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
 915                                      4, &reg);
 916                 reg |= PCI_EXP_DEVCTL_BCR_FLR;
 917                 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
 918                                       4, reg);
 919                 msleep(EEH_PE_RST_HOLD_TIME);
 920                 break;
 921         case EEH_RESET_DEACTIVATE:
 922                 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
 923                                      4, &reg);
 924                 reg &= ~PCI_EXP_DEVCTL_BCR_FLR;
 925                 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
 926                                       4, reg);
 927                 msleep(EEH_PE_RST_SETTLE_TIME);
 928                 break;
 929         }
 930
 931         return 0;
 932 }
 933
 934 static int pnv_eeh_do_af_flr(struct pci_dn *pdn, int option)
 935 {
 936         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
 937         u32 cap = 0;
 938
 939         if (WARN_ON(!edev->af_cap))
 940                 return -ENOTTY;
 941
 942         eeh_ops->read_config(pdn, edev->af_cap + PCI_AF_CAP, 1, &cap);
 943         if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
 944                 return -ENOTTY;
 945
 946         switch (option) {
 947         case EEH_RESET_HOT:
 948         case EEH_RESET_FUNDAMENTAL:
 949                 /*
 950                  * Wait for Transaction Pending bit to clear. A word-aligned
 951                  * test is used, so we use the conrol offset rather than status
 952                  * and shift the test bit to match.
 953                  */
 954                 pnv_eeh_wait_for_pending(pdn, "AF",
 955                                          edev->af_cap + PCI_AF_CTRL,
 956                                          PCI_AF_STATUS_TP << 8);
 957                 eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL,
 958                                       1, PCI_AF_CTRL_FLR);
 959                 msleep(EEH_PE_RST_HOLD_TIME);
 960                 break;
 961         case EEH_RESET_DEACTIVATE:
 962                 eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL, 1, 0);
 963                 msleep(EEH_PE_RST_SETTLE_TIME);
 964                 break;
 965         }
 966
 967         return 0;
 968 }
 969
 970 static int pnv_eeh_reset_vf_pe(struct eeh_pe *pe, int option)
 971 {
 972         struct eeh_dev *edev;
 973         struct pci_dn *pdn;
 974         int ret;
 975
 976         /* The VF PE should have only one child device */
 977         edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, list);
 978         pdn = eeh_dev_to_pdn(edev);
 979         if (!pdn)
 980                 return -ENXIO;
 981
 982         ret = pnv_eeh_do_flr(pdn, option);
 983         if (!ret)
 984                 return ret;
 985
 986         return pnv_eeh_do_af_flr(pdn, option);
 987 }
 988
 989 /**
 990  * pnv_eeh_reset - Reset the specified PE
 991  * @pe: EEH PE
 992  * @option: reset option
 993  *
 994  * Do reset on the indicated PE. For PCI bus sensitive PE,
 995  * we need to reset the parent p2p bridge. The PHB has to
 996  * be reinitialized if the p2p bridge is root bridge. For
 997  * PCI device sensitive PE, we will try to reset the device
 998  * through FLR. For now, we don't have OPAL APIs to do HARD
 999  * reset yet, so all reset would be SOFT (HOT) reset.
1000  */
1001 static int pnv_eeh_reset(struct eeh_pe *pe, int option)
1002 {
1003         struct pci_controller *hose = pe->phb;
1004         struct pnv_phb *phb;
1005         struct pci_bus *bus;
1006         int64_t rc;
1007
1008         /*
1009          * For PHB reset, we always have complete reset. For those PEs whose
1010          * primary bus derived from root complex (root bus) or root port
1011          * (usually bus#1), we apply hot or fundamental reset on the root port.
1012          * For other PEs, we always have hot reset on the PE primary bus.
1013          *
1014          * Here, we have different design to pHyp, which always clear the
1015          * frozen state during PE reset. However, the good idea here from
1016          * benh is to keep frozen state before we get PE reset done completely
1017          * (until BAR restore). With the frozen state, HW drops illegal IO
1018          * or MMIO access, which can incur recrusive frozen PE during PE
1019          * reset. The side effect is that EEH core has to clear the frozen
1020          * state explicitly after BAR restore.
1021          */
1022         if (pe->type & EEH_PE_PHB)
1023                 return pnv_eeh_phb_reset(hose, option);
1024
1025         /*
1026          * The frozen PE might be caused by PAPR error injection
1027          * registers, which are expected to be cleared after hitting
1028          * frozen PE as stated in the hardware spec. Unfortunately,
1029          * that's not true on P7IOC. So we have to clear it manually
1030          * to avoid recursive EEH errors during recovery.
1031          */
1032         phb = hose->private_data;
1033         if (phb->model == PNV_PHB_MODEL_P7IOC &&
1034             (option == EEH_RESET_HOT ||
1035              option == EEH_RESET_FUNDAMENTAL)) {
1036                 rc = opal_pci_reset(phb->opal_id,
1037                                     OPAL_RESET_PHB_ERROR,
1038                                     OPAL_ASSERT_RESET);
1039                 if (rc != OPAL_SUCCESS) {
1040                         pr_warn("%s: Failure %lld clearing error injection registers\n",
1041                                 __func__, rc);
1042                         return -EIO;
1043                 }
1044         }
1045
1046         bus = eeh_pe_bus_get(pe);
1047         if (pe->type & EEH_PE_VF)
1048                 return pnv_eeh_reset_vf_pe(pe, option);
1049
1050         if (pci_is_root_bus(bus) ||
1051             pci_is_root_bus(bus->parent))
1052                 return pnv_eeh_root_reset(hose, option);
1053
1054         return pnv_eeh_bridge_reset(bus->self, option);
1055 }
1056
1057 /**
1058  * pnv_eeh_wait_state - Wait for PE state
1059  * @pe: EEH PE
1060  * @max_wait: maximal period in millisecond
1061  *
1062  * Wait for the state of associated PE. It might take some time
1063  * to retrieve the PE's state.
1064  */
1065 static int pnv_eeh_wait_state(struct eeh_pe *pe, int max_wait)
1066 {
1067         int ret;
1068         int mwait;
1069
1070         while (1) {
1071                 ret = pnv_eeh_get_state(pe, &mwait);
1072
1073                 /*
1074                  * If the PE's state is temporarily unavailable,
1075                  * we have to wait for the specified time. Otherwise,
1076                  * the PE's state will be returned immediately.
1077                  */
1078                 if (ret != EEH_STATE_UNAVAILABLE)
1079                         return ret;
1080
1081                 if (max_wait <= 0) {
1082                         pr_warn("%s: Timeout getting PE#%x's state (%d)\n",
1083                                 __func__, pe->addr, max_wait);
1084                         return EEH_STATE_NOT_SUPPORT;
1085                 }
1086
1087                 max_wait -= mwait;
1088                 msleep(mwait);
1089         }
1090
1091         return EEH_STATE_NOT_SUPPORT;
1092 }
1093
1094 /**
1095  * pnv_eeh_get_log - Retrieve error log
1096  * @pe: EEH PE
1097  * @severity: temporary or permanent error log
1098  * @drv_log: driver log to be combined with retrieved error log
1099  * @len: length of driver log
1100  *
1101  * Retrieve the temporary or permanent error from the PE.
1102  */
1103 static int pnv_eeh_get_log(struct eeh_pe *pe, int severity,
1104                            char *drv_log, unsigned long len)
1105 {
1106         if (!eeh_has_flag(EEH_EARLY_DUMP_LOG))
1107                 pnv_pci_dump_phb_diag_data(pe->phb, pe->data);
1108
1109         return 0;
1110 }
1111
1112 /**
1113  * pnv_eeh_configure_bridge - Configure PCI bridges in the indicated PE
1114  * @pe: EEH PE
1115  *
1116  * The function will be called to reconfigure the bridges included
1117  * in the specified PE so that the mulfunctional PE would be recovered
1118  * again.
1119  */
1120 static int pnv_eeh_configure_bridge(struct eeh_pe *pe)
1121 {
1122         return 0;
1123 }
1124
1125 /**
1126  * pnv_pe_err_inject - Inject specified error to the indicated PE
1127  * @pe: the indicated PE
1128  * @type: error type
1129  * @func: specific error type
1130  * @addr: address
1131  * @mask: address mask
1132  *
1133  * The routine is called to inject specified error, which is
1134  * determined by @type and @func, to the indicated PE for
1135  * testing purpose.
1136  */
1137 static int pnv_eeh_err_inject(struct eeh_pe *pe, int type, int func,
1138                               unsigned long addr, unsigned long mask)
1139 {
1140         struct pci_controller *hose = pe->phb;
1141         struct pnv_phb *phb = hose->private_data;
1142         s64 rc;
1143
1144         if (type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR &&
1145             type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64) {
1146                 pr_warn("%s: Invalid error type %d\n",
1147                         __func__, type);
1148                 return -ERANGE;
1149         }
1150
1151         if (func < OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR ||
1152             func > OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET) {
1153                 pr_warn("%s: Invalid error function %d\n",
1154                         __func__, func);
1155                 return -ERANGE;
1156         }
1157
1158         /* Firmware supports error injection ? */
1159         if (!opal_check_token(OPAL_PCI_ERR_INJECT)) {
1160                 pr_warn("%s: Firmware doesn't support error injection\n",
1161                         __func__);
1162                 return -ENXIO;
1163         }
1164
1165         /* Do error injection */
1166         rc = opal_pci_err_inject(phb->opal_id, pe->addr,
1167                                  type, func, addr, mask);
1168         if (rc != OPAL_SUCCESS) {
1169                 pr_warn("%s: Failure %lld injecting error "
1170                         "%d-%d to PHB#%x-PE#%x\n",
1171                         __func__, rc, type, func,
1172                         hose->global_number, pe->addr);
1173                 return -EIO;
1174         }
1175
1176         return 0;
1177 }
1178
1179 static inline bool pnv_eeh_cfg_blocked(struct pci_dn *pdn)
1180 {
1181         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
1182
1183         if (!edev || !edev->pe)
1184                 return false;
1185
1186         /*
1187          * We will issue FLR or AF FLR to all VFs, which are contained
1188          * in VF PE. It relies on the EEH PCI config accessors. So we
1189          * can't block them during the window.
1190          */
1191         if (edev->physfn && (edev->pe->state & EEH_PE_RESET))
1192                 return false;
1193
1194         if (edev->pe->state & EEH_PE_CFG_BLOCKED)
1195                 return true;
1196
1197         return false;
1198 }
1199
1200 static int pnv_eeh_read_config(struct pci_dn *pdn,
1201                                int where, int size, u32 *val)
1202 {
1203         if (!pdn)
1204                 return PCIBIOS_DEVICE_NOT_FOUND;
1205
1206         if (pnv_eeh_cfg_blocked(pdn)) {
1207                 *val = 0xFFFFFFFF;
1208                 return PCIBIOS_SET_FAILED;
1209         }
1210
1211         return pnv_pci_cfg_read(pdn, where, size, val);
1212 }
1213
1214 static int pnv_eeh_write_config(struct pci_dn *pdn,
1215                                 int where, int size, u32 val)
1216 {
1217         if (!pdn)
1218                 return PCIBIOS_DEVICE_NOT_FOUND;
1219
1220         if (pnv_eeh_cfg_blocked(pdn))
1221                 return PCIBIOS_SET_FAILED;
1222
1223         return pnv_pci_cfg_write(pdn, where, size, val);
1224 }
1225
1226 static void pnv_eeh_dump_hub_diag_common(struct OpalIoP7IOCErrorData *data)
1227 {
1228         /* GEM */
1229         if (data->gemXfir || data->gemRfir ||
1230             data->gemRirqfir || data->gemMask || data->gemRwof)
1231                 pr_info("  GEM: %016llx %016llx %016llx %016llx %016llx\n",
1232                         be64_to_cpu(data->gemXfir),
1233                         be64_to_cpu(data->gemRfir),
1234                         be64_to_cpu(data->gemRirqfir),
1235                         be64_to_cpu(data->gemMask),
1236                         be64_to_cpu(data->gemRwof));
1237
1238         /* LEM */
1239         if (data->lemFir || data->lemErrMask ||
1240             data->lemAction0 || data->lemAction1 || data->lemWof)
1241                 pr_info("  LEM: %016llx %016llx %016llx %016llx %016llx\n",
1242                         be64_to_cpu(data->lemFir),
1243                         be64_to_cpu(data->lemErrMask),
1244                         be64_to_cpu(data->lemAction0),
1245                         be64_to_cpu(data->lemAction1),
1246                         be64_to_cpu(data->lemWof));
1247 }
1248
1249 static void pnv_eeh_get_and_dump_hub_diag(struct pci_controller *hose)
1250 {
1251         struct pnv_phb *phb = hose->private_data;
1252         struct OpalIoP7IOCErrorData *data = &phb->diag.hub_diag;
1253         long rc;
1254
1255         rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data));
1256         if (rc != OPAL_SUCCESS) {
1257                 pr_warn("%s: Failed to get HUB#%llx diag-data (%ld)\n",
1258                         __func__, phb->hub_id, rc);
1259                 return;
1260         }
1261
1262         switch (data->type) {
1263         case OPAL_P7IOC_DIAG_TYPE_RGC:
1264                 pr_info("P7IOC diag-data for RGC\n\n");
1265                 pnv_eeh_dump_hub_diag_common(data);
1266                 if (data->rgc.rgcStatus || data->rgc.rgcLdcp)
1267                         pr_info("  RGC: %016llx %016llx\n",
1268                                 be64_to_cpu(data->rgc.rgcStatus),
1269                                 be64_to_cpu(data->rgc.rgcLdcp));
1270                 break;
1271         case OPAL_P7IOC_DIAG_TYPE_BI:
1272                 pr_info("P7IOC diag-data for BI %s\n\n",
1273                         data->bi.biDownbound ? "Downbound" : "Upbound");
1274                 pnv_eeh_dump_hub_diag_common(data);
1275                 if (data->bi.biLdcp0 || data->bi.biLdcp1 ||
1276                     data->bi.biLdcp2 || data->bi.biFenceStatus)
1277                         pr_info("  BI:  %016llx %016llx %016llx %016llx\n",
1278                                 be64_to_cpu(data->bi.biLdcp0),
1279                                 be64_to_cpu(data->bi.biLdcp1),
1280                                 be64_to_cpu(data->bi.biLdcp2),
1281                                 be64_to_cpu(data->bi.biFenceStatus));
1282                 break;
1283         case OPAL_P7IOC_DIAG_TYPE_CI:
1284                 pr_info("P7IOC diag-data for CI Port %d\n\n",
1285                         data->ci.ciPort);
1286                 pnv_eeh_dump_hub_diag_common(data);
1287                 if (data->ci.ciPortStatus || data->ci.ciPortLdcp)
1288                         pr_info("  CI:  %016llx %016llx\n",
1289                                 be64_to_cpu(data->ci.ciPortStatus),
1290                                 be64_to_cpu(data->ci.ciPortLdcp));
1291                 break;
1292         case OPAL_P7IOC_DIAG_TYPE_MISC:
1293                 pr_info("P7IOC diag-data for MISC\n\n");
1294                 pnv_eeh_dump_hub_diag_common(data);
1295                 break;
1296         case OPAL_P7IOC_DIAG_TYPE_I2C:
1297                 pr_info("P7IOC diag-data for I2C\n\n");
1298                 pnv_eeh_dump_hub_diag_common(data);
1299                 break;
1300         default:
1301                 pr_warn("%s: Invalid type of HUB#%llx diag-data (%d)\n",
1302                         __func__, phb->hub_id, data->type);
1303         }
1304 }
1305
1306 static int pnv_eeh_get_pe(struct pci_controller *hose,
1307                           u16 pe_no, struct eeh_pe **pe)
1308 {
1309         struct pnv_phb *phb = hose->private_data;
1310         struct pnv_ioda_pe *pnv_pe;
1311         struct eeh_pe *dev_pe;
1312         struct eeh_dev edev;
1313
1314         /*
1315          * If PHB supports compound PE, to fetch
1316          * the master PE because slave PE is invisible
1317          * to EEH core.
1318          */
1319         pnv_pe = &phb->ioda.pe_array[pe_no];
1320         if (pnv_pe->flags & PNV_IODA_PE_SLAVE) {
1321                 pnv_pe = pnv_pe->master;
1322                 WARN_ON(!pnv_pe ||
1323                         !(pnv_pe->flags & PNV_IODA_PE_MASTER));
1324                 pe_no = pnv_pe->pe_number;
1325         }
1326
1327         /* Find the PE according to PE# */
1328         memset(&edev, 0, sizeof(struct eeh_dev));
1329         edev.phb = hose;
1330         edev.pe_config_addr = pe_no;
1331         dev_pe = eeh_pe_get(&edev);
1332         if (!dev_pe)
1333                 return -EEXIST;
1334
1335         /* Freeze the (compound) PE */
1336         *pe = dev_pe;
1337         if (!(dev_pe->state & EEH_PE_ISOLATED))
1338                 phb->freeze_pe(phb, pe_no);
1339
1340         /*
1341          * At this point, we're sure the (compound) PE should
1342          * have been frozen. However, we still need poke until
1343          * hitting the frozen PE on top level.
1344          */
1345         dev_pe = dev_pe->parent;
1346         while (dev_pe && !(dev_pe->type & EEH_PE_PHB)) {
1347                 int ret;
1348                 int active_flags = (EEH_STATE_MMIO_ACTIVE |
1349                                     EEH_STATE_DMA_ACTIVE);
1350
1351                 ret = eeh_ops->get_state(dev_pe, NULL);
1352                 if (ret <= 0 || (ret & active_flags) == active_flags) {
1353                         dev_pe = dev_pe->parent;
1354                         continue;
1355                 }
1356
1357                 /* Frozen parent PE */
1358                 *pe = dev_pe;
1359                 if (!(dev_pe->state & EEH_PE_ISOLATED))
1360                         phb->freeze_pe(phb, dev_pe->addr);
1361
1362                 /* Next one */
1363                 dev_pe = dev_pe->parent;
1364         }
1365
1366         return 0;
1367 }
1368
1369 /**
1370  * pnv_eeh_next_error - Retrieve next EEH error to handle
1371  * @pe: Affected PE
1372  *
1373  * The function is expected to be called by EEH core while it gets
1374  * special EEH event (without binding PE). The function calls to
1375  * OPAL APIs for next error to handle. The informational error is
1376  * handled internally by platform. However, the dead IOC, dead PHB,
1377  * fenced PHB and frozen PE should be handled by EEH core eventually.
1378  */
1379 static int pnv_eeh_next_error(struct eeh_pe **pe)
1380 {
1381         struct pci_controller *hose;
1382         struct pnv_phb *phb;
1383         struct eeh_pe *phb_pe, *parent_pe;
1384         __be64 frozen_pe_no;
1385         __be16 err_type, severity;
1386         int active_flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE);
1387         long rc;
1388         int state, ret = EEH_NEXT_ERR_NONE;
1389
1390         /*
1391          * While running here, it's safe to purge the event queue. The
1392          * event should still be masked.
1393          */
1394         eeh_remove_event(NULL, false);
1395
1396         list_for_each_entry(hose, &hose_list, list_node) {
1397                 /*
1398                  * If the subordinate PCI buses of the PHB has been
1399                  * removed or is exactly under error recovery, we
1400                  * needn't take care of it any more.
1401                  */
1402                 phb = hose->private_data;
1403                 phb_pe = eeh_phb_pe_get(hose);
1404                 if (!phb_pe || (phb_pe->state & EEH_PE_ISOLATED))
1405                         continue;
1406
1407                 rc = opal_pci_next_error(phb->opal_id,
1408                                          &frozen_pe_no, &err_type, &severity);
1409                 if (rc != OPAL_SUCCESS) {
1410                         pr_devel("%s: Invalid return value on "
1411                                  "PHB#%x (0x%lx) from opal_pci_next_error",
1412                                  __func__, hose->global_number, rc);
1413                         continue;
1414                 }
1415
1416                 /* If the PHB doesn't have error, stop processing */
1417                 if (be16_to_cpu(err_type) == OPAL_EEH_NO_ERROR ||
1418                     be16_to_cpu(severity) == OPAL_EEH_SEV_NO_ERROR) {
1419                         pr_devel("%s: No error found on PHB#%x\n",
1420                                  __func__, hose->global_number);
1421                         continue;
1422                 }
1423
1424                 /*
1425                  * Processing the error. We're expecting the error with
1426                  * highest priority reported upon multiple errors on the
1427                  * specific PHB.
1428                  */
1429                 pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n",
1430                         __func__, be16_to_cpu(err_type),
1431                         be16_to_cpu(severity), be64_to_cpu(frozen_pe_no),
1432                         hose->global_number);
1433                 switch (be16_to_cpu(err_type)) {
1434                 case OPAL_EEH_IOC_ERROR:
1435                         if (be16_to_cpu(severity) == OPAL_EEH_SEV_IOC_DEAD) {
1436                                 pr_err("EEH: dead IOC detected\n");
1437                                 ret = EEH_NEXT_ERR_DEAD_IOC;
1438                         } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) {
1439                                 pr_info("EEH: IOC informative error "
1440                                         "detected\n");
1441                                 pnv_eeh_get_and_dump_hub_diag(hose);
1442                                 ret = EEH_NEXT_ERR_NONE;
1443                         }
1444
1445                         break;
1446                 case OPAL_EEH_PHB_ERROR:
1447                         if (be16_to_cpu(severity) == OPAL_EEH_SEV_PHB_DEAD) {
1448                                 *pe = phb_pe;
1449                                 pr_err("EEH: dead PHB#%x detected, "
1450                                        "location: %s\n",
1451                                         hose->global_number,
1452                                         eeh_pe_loc_get(phb_pe));
1453                                 ret = EEH_NEXT_ERR_DEAD_PHB;
1454                         } else if (be16_to_cpu(severity) ==
1455                                    OPAL_EEH_SEV_PHB_FENCED) {
1456                                 *pe = phb_pe;
1457                                 pr_err("EEH: Fenced PHB#%x detected, "
1458                                        "location: %s\n",
1459                                         hose->global_number,
1460                                         eeh_pe_loc_get(phb_pe));
1461                                 ret = EEH_NEXT_ERR_FENCED_PHB;
1462                         } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) {
1463                                 pr_info("EEH: PHB#%x informative error "
1464                                         "detected, location: %s\n",
1465                                         hose->global_number,
1466                                         eeh_pe_loc_get(phb_pe));
1467                                 pnv_eeh_get_phb_diag(phb_pe);
1468                                 pnv_pci_dump_phb_diag_data(hose, phb_pe->data);
1469                                 ret = EEH_NEXT_ERR_NONE;
1470                         }
1471
1472                         break;
1473                 case OPAL_EEH_PE_ERROR:
1474                         /*
1475                          * If we can't find the corresponding PE, we
1476                          * just try to unfreeze.
1477                          */
1478                         if (pnv_eeh_get_pe(hose,
1479                                 be64_to_cpu(frozen_pe_no), pe)) {
1480                                 pr_info("EEH: Clear non-existing PHB#%x-PE#%llx\n",
1481                                         hose->global_number, be64_to_cpu(frozen_pe_no));
1482                                 pr_info("EEH: PHB location: %s\n",
1483                                         eeh_pe_loc_get(phb_pe));
1484
1485                                 /* Dump PHB diag-data */
1486                                 rc = opal_pci_get_phb_diag_data2(phb->opal_id,
1487                                         phb->diag.blob, PNV_PCI_DIAG_BUF_SIZE);
1488                                 if (rc == OPAL_SUCCESS)
1489                                         pnv_pci_dump_phb_diag_data(hose,
1490                                                         phb->diag.blob);
1491
1492                                 /* Try best to clear it */
1493                                 opal_pci_eeh_freeze_clear(phb->opal_id,
1494                                         frozen_pe_no,
1495                                         OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
1496                                 ret = EEH_NEXT_ERR_NONE;
1497                         } else if ((*pe)->state & EEH_PE_ISOLATED ||
1498                                    eeh_pe_passed(*pe)) {
1499                                 ret = EEH_NEXT_ERR_NONE;
1500                         } else {
1501                                 pr_err("EEH: Frozen PE#%x "
1502                                        "on PHB#%x detected\n",
1503                                        (*pe)->addr,
1504                                         (*pe)->phb->global_number);
1505                                 pr_err("EEH: PE location: %s, "
1506                                        "PHB location: %s\n",
1507                                        eeh_pe_loc_get(*pe),
1508                                        eeh_pe_loc_get(phb_pe));
1509                                 ret = EEH_NEXT_ERR_FROZEN_PE;
1510                         }
1511
1512                         break;
1513                 default:
1514                         pr_warn("%s: Unexpected error type %d\n",
1515                                 __func__, be16_to_cpu(err_type));
1516                 }
1517
1518                 /*
1519                  * EEH core will try recover from fenced PHB or
1520                  * frozen PE. In the time for frozen PE, EEH core
1521                  * enable IO path for that before collecting logs,
1522                  * but it ruins the site. So we have to dump the
1523                  * log in advance here.
1524                  */
1525                 if ((ret == EEH_NEXT_ERR_FROZEN_PE  ||
1526                     ret == EEH_NEXT_ERR_FENCED_PHB) &&
1527                     !((*pe)->state & EEH_PE_ISOLATED)) {
1528                         eeh_pe_state_mark(*pe, EEH_PE_ISOLATED);
1529                         pnv_eeh_get_phb_diag(*pe);
1530
1531                         if (eeh_has_flag(EEH_EARLY_DUMP_LOG))
1532                                 pnv_pci_dump_phb_diag_data((*pe)->phb,
1533                                                            (*pe)->data);
1534                 }
1535
1536                 /*
1537                  * We probably have the frozen parent PE out there and
1538                  * we need have to handle frozen parent PE firstly.
1539                  */
1540                 if (ret == EEH_NEXT_ERR_FROZEN_PE) {
1541                         parent_pe = (*pe)->parent;
1542                         while (parent_pe) {
1543                                 /* Hit the ceiling ? */
1544                                 if (parent_pe->type & EEH_PE_PHB)
1545                                         break;
1546
1547                                 /* Frozen parent PE ? */
1548                                 state = eeh_ops->get_state(parent_pe, NULL);
1549                                 if (state > 0 &&
1550                                     (state & active_flags) != active_flags)
1551                                         *pe = parent_pe;
1552
1553                                 /* Next parent level */
1554                                 parent_pe = parent_pe->parent;
1555                         }
1556
1557                         /* We possibly migrate to another PE */
1558                         eeh_pe_state_mark(*pe, EEH_PE_ISOLATED);
1559                 }
1560
1561                 /*
1562                  * If we have no errors on the specific PHB or only
1563                  * informative error there, we continue poking it.
1564                  * Otherwise, we need actions to be taken by upper
1565                  * layer.
1566                  */
1567                 if (ret > EEH_NEXT_ERR_INF)
1568                         break;
1569         }
1570
1571         /* Unmask the event */
1572         if (ret == EEH_NEXT_ERR_NONE && eeh_enabled())
1573                 enable_irq(eeh_event_irq);
1574
1575         return ret;
1576 }
1577
1578 static int pnv_eeh_restore_vf_config(struct pci_dn *pdn)
1579 {
1580         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
1581         u32 devctl, cmd, cap2, aer_capctl;
1582         int old_mps;
1583
1584         if (edev->pcie_cap) {
1585                 /* Restore MPS */
1586                 old_mps = (ffs(pdn->mps) - 8) << 5;
1587                 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
1588                                      2, &devctl);
1589                 devctl &= ~PCI_EXP_DEVCTL_PAYLOAD;
1590                 devctl |= old_mps;
1591                 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
1592                                       2, devctl);
1593
1594                 /* Disable Completion Timeout */
1595                 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCAP2,
1596                                      4, &cap2);
1597                 if (cap2 & 0x10) {
1598                         eeh_ops->read_config(pdn,
1599                                              edev->pcie_cap + PCI_EXP_DEVCTL2,
1600                                              4, &cap2);
1601                         cap2 |= 0x10;
1602                         eeh_ops->write_config(pdn,
1603                                               edev->pcie_cap + PCI_EXP_DEVCTL2,
1604                                               4, cap2);
1605                 }
1606         }
1607
1608         /* Enable SERR and parity checking */
1609         eeh_ops->read_config(pdn, PCI_COMMAND, 2, &cmd);
1610         cmd |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1611         eeh_ops->write_config(pdn, PCI_COMMAND, 2, cmd);
1612
1613         /* Enable report various errors */
1614         if (edev->pcie_cap) {
1615                 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
1616                                      2, &devctl);
1617                 devctl &= ~PCI_EXP_DEVCTL_CERE;
1618                 devctl |= (PCI_EXP_DEVCTL_NFERE |
1619                            PCI_EXP_DEVCTL_FERE |
1620                            PCI_EXP_DEVCTL_URRE);
1621                 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
1622                                       2, devctl);
1623         }
1624
1625         /* Enable ECRC generation and check */
1626         if (edev->pcie_cap && edev->aer_cap) {
1627                 eeh_ops->read_config(pdn, edev->aer_cap + PCI_ERR_CAP,
1628                                      4, &aer_capctl);
1629                 aer_capctl |= (PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE);
1630                 eeh_ops->write_config(pdn, edev->aer_cap + PCI_ERR_CAP,
1631                                       4, aer_capctl);
1632         }
1633
1634         return 0;
1635 }
1636
1637 static int pnv_eeh_restore_config(struct pci_dn *pdn)
1638 {
1639         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
1640         struct pnv_phb *phb;
1641         s64 ret;
1642
1643         if (!edev)
1644                 return -EEXIST;
1645
1646         /*
1647          * We have to restore the PCI config space after reset since the
1648          * firmware can't see SRIOV VFs.
1649          *
1650          * FIXME: The MPS, error routing rules, timeout setting are worthy
1651          * to be exported by firmware in extendible way.
1652          */
1653         if (edev->physfn) {
1654                 ret = pnv_eeh_restore_vf_config(pdn);
1655         } else {
1656                 phb = edev->phb->private_data;
1657                 ret = opal_pci_reinit(phb->opal_id,
1658                                       OPAL_REINIT_PCI_DEV, edev->config_addr);
1659         }
1660
1661         if (ret) {
1662                 pr_warn("%s: Can't reinit PCI dev 0x%x (%lld)\n",
1663                         __func__, edev->config_addr, ret);
1664                 return -EIO;
1665         }
1666
1667         return 0;
1668 }
1669
1670 static struct eeh_ops pnv_eeh_ops = {
1671         .name                   = "powernv",
1672         .init                   = pnv_eeh_init,
1673         .post_init              = pnv_eeh_post_init,
1674         .probe                  = pnv_eeh_probe,
1675         .set_option             = pnv_eeh_set_option,
1676         .get_pe_addr            = pnv_eeh_get_pe_addr,
1677         .get_state              = pnv_eeh_get_state,
1678         .reset                  = pnv_eeh_reset,
1679         .wait_state             = pnv_eeh_wait_state,
1680         .get_log                = pnv_eeh_get_log,
1681         .configure_bridge       = pnv_eeh_configure_bridge,
1682         .err_inject             = pnv_eeh_err_inject,
1683         .read_config            = pnv_eeh_read_config,
1684         .write_config           = pnv_eeh_write_config,
1685         .next_error             = pnv_eeh_next_error,
1686         .restore_config         = pnv_eeh_restore_config
1687 };
1688
1689 void pcibios_bus_add_device(struct pci_dev *pdev)
1690 {
1691         struct pci_dn *pdn = pci_get_pdn(pdev);
1692
1693         if (!pdev->is_virtfn)
1694                 return;
1695
1696         /*
1697          * The following operations will fail if VF's sysfs files
1698          * aren't created or its resources aren't finalized.
1699          */
1700         eeh_add_device_early(pdn);
1701         eeh_add_device_late(pdev);
1702         eeh_sysfs_add_device(pdev);
1703 }
1704
1705 #ifdef CONFIG_PCI_IOV
1706 static void pnv_pci_fixup_vf_mps(struct pci_dev *pdev)
1707 {
1708         struct pci_dn *pdn = pci_get_pdn(pdev);
1709         int parent_mps;
1710
1711         if (!pdev->is_virtfn)
1712                 return;
1713
1714         /* Synchronize MPS for VF and PF */
1715         parent_mps = pcie_get_mps(pdev->physfn);
1716         if ((128 << pdev->pcie_mpss) >= parent_mps)
1717                 pcie_set_mps(pdev, parent_mps);
1718         pdn->mps = pcie_get_mps(pdev);
1719 }
1720 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pnv_pci_fixup_vf_mps);
1721 #endif /* CONFIG_PCI_IOV */
1722
1723 /**
1724  * eeh_powernv_init - Register platform dependent EEH operations
1725  *
1726  * EEH initialization on powernv platform. This function should be
1727  * called before any EEH related functions.
1728  */
1729 static int __init eeh_powernv_init(void)
1730 {
1731         int ret = -EINVAL;
1732
1733         eeh_set_pe_aux_size(PNV_PCI_DIAG_BUF_SIZE);
1734         ret = eeh_ops_register(&pnv_eeh_ops);
1735         if (!ret)
1736                 pr_info("EEH: PowerNV platform initialized\n");
1737         else
1738                 pr_info("EEH: Failed to initialize PowerNV platform (%d)\n", ret);
1739
1740         return ret;
1741 }
1742 machine_early_initcall(powernv, eeh_powernv_init);