arch/powerpc/platforms/powernv/pci-ioda.c

   1 /*
   2  * Support PCI/PCIe on PowerNV platforms
   3  *
   4  * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #undef DEBUG
  13
  14 #include <linux/kernel.h>
  15 #include <linux/pci.h>
  16 #include <linux/crash_dump.h>
  17 #include <linux/debugfs.h>
  18 #include <linux/delay.h>
  19 #include <linux/string.h>
  20 #include <linux/init.h>
  21 #include <linux/bootmem.h>
  22 #include <linux/irq.h>
  23 #include <linux/io.h>
  24 #include <linux/msi.h>
  25 #include <linux/memblock.h>
  26 #include <linux/iommu.h>
  27 #include <linux/rculist.h>
  28 #include <linux/sizes.h>
  29
  30 #include <asm/sections.h>
  31 #include <asm/io.h>
  32 #include <asm/prom.h>
  33 #include <asm/pci-bridge.h>
  34 #include <asm/machdep.h>
  35 #include <asm/msi_bitmap.h>
  36 #include <asm/ppc-pci.h>
  37 #include <asm/opal.h>
  38 #include <asm/iommu.h>
  39 #include <asm/tce.h>
  40 #include <asm/xics.h>
  41 #include <asm/debug.h>
  42 #include <asm/firmware.h>
  43 #include <asm/pnv-pci.h>
  44 #include <asm/mmzone.h>
  45
  46 #include <misc/cxl-base.h>
  47
  48 #include "powernv.h"
  49 #include "pci.h"
  50
  51 #define PNV_IODA1_M64_NUM       16      /* Number of M64 BARs   */
  52 #define PNV_IODA1_M64_SEGS      8       /* Segments per M64 BAR */
  53 #define PNV_IODA1_DMA32_SEGSIZE 0x10000000
  54
  55 #define POWERNV_IOMMU_DEFAULT_LEVELS    1
  56 #define POWERNV_IOMMU_MAX_LEVELS        5
  57
  58 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl);
  59
  60 void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
  61                             const char *fmt, ...)
  62 {
  63         struct va_format vaf;
  64         va_list args;
  65         char pfix[32];
  66
  67         va_start(args, fmt);
  68
  69         vaf.fmt = fmt;
  70         vaf.va = &args;
  71
  72         if (pe->flags & PNV_IODA_PE_DEV)
  73                 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
  74         else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
  75                 sprintf(pfix, "%04x:%02x     ",
  76                         pci_domain_nr(pe->pbus), pe->pbus->number);
  77 #ifdef CONFIG_PCI_IOV
  78         else if (pe->flags & PNV_IODA_PE_VF)
  79                 sprintf(pfix, "%04x:%02x:%2x.%d",
  80                         pci_domain_nr(pe->parent_dev->bus),
  81                         (pe->rid & 0xff00) >> 8,
  82                         PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
  83 #endif /* CONFIG_PCI_IOV*/
  84
  85         printk("%spci %s: [PE# %.3d] %pV",
  86                level, pfix, pe->pe_number, &vaf);
  87
  88         va_end(args);
  89 }
  90
  91 static bool pnv_iommu_bypass_disabled __read_mostly;
  92
  93 static int __init iommu_setup(char *str)
  94 {
  95         if (!str)
  96                 return -EINVAL;
  97
  98         while (*str) {
  99                 if (!strncmp(str, "nobypass", 8)) {
 100                         pnv_iommu_bypass_disabled = true;
 101                         pr_info("PowerNV: IOMMU bypass window disabled.\n");
 102                         break;
 103                 }
 104                 str += strcspn(str, ",");
 105                 if (*str == ',')
 106                         str++;
 107         }
 108
 109         return 0;
 110 }
 111 early_param("iommu", iommu_setup);
 112
 113 static inline bool pnv_pci_is_mem_pref_64(unsigned long flags)
 114 {
 115         return ((flags & (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)) ==
 116                 (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH));
 117 }
 118
 119 static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no)
 120 {
 121         phb->ioda.pe_array[pe_no].phb = phb;
 122         phb->ioda.pe_array[pe_no].pe_number = pe_no;
 123
 124         return &phb->ioda.pe_array[pe_no];
 125 }
 126
 127 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
 128 {
 129         if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) {
 130                 pr_warn("%s: Invalid PE %d on PHB#%x\n",
 131                         __func__, pe_no, phb->hose->global_number);
 132                 return;
 133         }
 134
 135         if (test_and_set_bit(pe_no, phb->ioda.pe_alloc))
 136                 pr_debug("%s: PE %d was reserved on PHB#%x\n",
 137                          __func__, pe_no, phb->hose->global_number);
 138
 139         pnv_ioda_init_pe(phb, pe_no);
 140 }
 141
 142 static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb)
 143 {
 144         unsigned long pe;
 145
 146         do {
 147                 pe = find_next_zero_bit(phb->ioda.pe_alloc,
 148                                         phb->ioda.total_pe_num, 0);
 149                 if (pe >= phb->ioda.total_pe_num)
 150                         return NULL;
 151         } while(test_and_set_bit(pe, phb->ioda.pe_alloc));
 152
 153         return pnv_ioda_init_pe(phb, pe);
 154 }
 155
 156 static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe)
 157 {
 158         struct pnv_phb *phb = pe->phb;
 159
 160         WARN_ON(pe->pdev);
 161
 162         memset(pe, 0, sizeof(struct pnv_ioda_pe));
 163         clear_bit(pe->pe_number, phb->ioda.pe_alloc);
 164 }
 165
 166 /* The default M64 BAR is shared by all PEs */
 167 static int pnv_ioda2_init_m64(struct pnv_phb *phb)
 168 {
 169         const char *desc;
 170         struct resource *r;
 171         s64 rc;
 172
 173         /* Configure the default M64 BAR */
 174         rc = opal_pci_set_phb_mem_window(phb->opal_id,
 175                                          OPAL_M64_WINDOW_TYPE,
 176                                          phb->ioda.m64_bar_idx,
 177                                          phb->ioda.m64_base,
 178                                          0, /* unused */
 179                                          phb->ioda.m64_size);
 180         if (rc != OPAL_SUCCESS) {
 181                 desc = "configuring";
 182                 goto fail;
 183         }
 184
 185         /* Enable the default M64 BAR */
 186         rc = opal_pci_phb_mmio_enable(phb->opal_id,
 187                                       OPAL_M64_WINDOW_TYPE,
 188                                       phb->ioda.m64_bar_idx,
 189                                       OPAL_ENABLE_M64_SPLIT);
 190         if (rc != OPAL_SUCCESS) {
 191                 desc = "enabling";
 192                 goto fail;
 193         }
 194
 195         /* Mark the M64 BAR assigned */
 196         set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc);
 197
 198         /*
 199          * Strip off the segment used by the reserved PE, which is
 200          * expected to be 0 or last one of PE capability.
 201          */
 202         r = &phb->hose->mem_resources[1];
 203         if (phb->ioda.reserved_pe_idx == 0)
 204                 r->start += phb->ioda.m64_segsize;
 205         else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
 206                 r->end -= phb->ioda.m64_segsize;
 207         else
 208                 pr_warn("  Cannot strip M64 segment for reserved PE#%d\n",
 209                         phb->ioda.reserved_pe_idx);
 210
 211         return 0;
 212
 213 fail:
 214         pr_warn("  Failure %lld %s M64 BAR#%d\n",
 215                 rc, desc, phb->ioda.m64_bar_idx);
 216         opal_pci_phb_mmio_enable(phb->opal_id,
 217                                  OPAL_M64_WINDOW_TYPE,
 218                                  phb->ioda.m64_bar_idx,
 219                                  OPAL_DISABLE_M64);
 220         return -EIO;
 221 }
 222
 223 static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev,
 224                                          unsigned long *pe_bitmap)
 225 {
 226         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
 227         struct pnv_phb *phb = hose->private_data;
 228         struct resource *r;
 229         resource_size_t base, sgsz, start, end;
 230         int segno, i;
 231
 232         base = phb->ioda.m64_base;
 233         sgsz = phb->ioda.m64_segsize;
 234         for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
 235                 r = &pdev->resource[i];
 236                 if (!r->parent || !pnv_pci_is_mem_pref_64(r->flags))
 237                         continue;
 238
 239                 start = _ALIGN_DOWN(r->start - base, sgsz);
 240                 end = _ALIGN_UP(r->end - base, sgsz);
 241                 for (segno = start / sgsz; segno < end / sgsz; segno++) {
 242                         if (pe_bitmap)
 243                                 set_bit(segno, pe_bitmap);
 244                         else
 245                                 pnv_ioda_reserve_pe(phb, segno);
 246                 }
 247         }
 248 }
 249
 250 static int pnv_ioda1_init_m64(struct pnv_phb *phb)
 251 {
 252         struct resource *r;
 253         int index;
 254
 255         /*
 256          * There are 16 M64 BARs, each of which has 8 segments. So
 257          * there are as many M64 segments as the maximum number of
 258          * PEs, which is 128.
 259          */
 260         for (index = 0; index < PNV_IODA1_M64_NUM; index++) {
 261                 unsigned long base, segsz = phb->ioda.m64_segsize;
 262                 int64_t rc;
 263
 264                 base = phb->ioda.m64_base +
 265                        index * PNV_IODA1_M64_SEGS * segsz;
 266                 rc = opal_pci_set_phb_mem_window(phb->opal_id,
 267                                 OPAL_M64_WINDOW_TYPE, index, base, 0,
 268                                 PNV_IODA1_M64_SEGS * segsz);
 269                 if (rc != OPAL_SUCCESS) {
 270                         pr_warn("  Error %lld setting M64 PHB#%d-BAR#%d\n",
 271                                 rc, phb->hose->global_number, index);
 272                         goto fail;
 273                 }
 274
 275                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
 276                                 OPAL_M64_WINDOW_TYPE, index,
 277                                 OPAL_ENABLE_M64_SPLIT);
 278                 if (rc != OPAL_SUCCESS) {
 279                         pr_warn("  Error %lld enabling M64 PHB#%d-BAR#%d\n",
 280                                 rc, phb->hose->global_number, index);
 281                         goto fail;
 282                 }
 283         }
 284
 285         /*
 286          * Exclude the segment used by the reserved PE, which
 287          * is expected to be 0 or last supported PE#.
 288          */
 289         r = &phb->hose->mem_resources[1];
 290         if (phb->ioda.reserved_pe_idx == 0)
 291                 r->start += phb->ioda.m64_segsize;
 292         else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
 293                 r->end -= phb->ioda.m64_segsize;
 294         else
 295                 WARN(1, "Wrong reserved PE#%d on PHB#%d\n",
 296                      phb->ioda.reserved_pe_idx, phb->hose->global_number);
 297
 298         return 0;
 299
 300 fail:
 301         for ( ; index >= 0; index--)
 302                 opal_pci_phb_mmio_enable(phb->opal_id,
 303                         OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64);
 304
 305         return -EIO;
 306 }
 307
 308 static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus,
 309                                     unsigned long *pe_bitmap,
 310                                     bool all)
 311 {
 312         struct pci_dev *pdev;
 313
 314         list_for_each_entry(pdev, &bus->devices, bus_list) {
 315                 pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap);
 316
 317                 if (all && pdev->subordinate)
 318                         pnv_ioda_reserve_m64_pe(pdev->subordinate,
 319                                                 pe_bitmap, all);
 320         }
 321 }
 322
 323 static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all)
 324 {
 325         struct pci_controller *hose = pci_bus_to_host(bus);
 326         struct pnv_phb *phb = hose->private_data;
 327         struct pnv_ioda_pe *master_pe, *pe;
 328         unsigned long size, *pe_alloc;
 329         int i;
 330
 331         /* Root bus shouldn't use M64 */
 332         if (pci_is_root_bus(bus))
 333                 return NULL;
 334
 335         /* Allocate bitmap */
 336         size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long));
 337         pe_alloc = kzalloc(size, GFP_KERNEL);
 338         if (!pe_alloc) {
 339                 pr_warn("%s: Out of memory !\n",
 340                         __func__);
 341                 return NULL;
 342         }
 343
 344         /* Figure out reserved PE numbers by the PE */
 345         pnv_ioda_reserve_m64_pe(bus, pe_alloc, all);
 346
 347         /*
 348          * the current bus might not own M64 window and that's all
 349          * contributed by its child buses. For the case, we needn't
 350          * pick M64 dependent PE#.
 351          */
 352         if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) {
 353                 kfree(pe_alloc);
 354                 return NULL;
 355         }
 356
 357         /*
 358          * Figure out the master PE and put all slave PEs to master
 359          * PE's list to form compound PE.
 360          */
 361         master_pe = NULL;
 362         i = -1;
 363         while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) <
 364                 phb->ioda.total_pe_num) {
 365                 pe = &phb->ioda.pe_array[i];
 366
 367                 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number;
 368                 if (!master_pe) {
 369                         pe->flags |= PNV_IODA_PE_MASTER;
 370                         INIT_LIST_HEAD(&pe->slaves);
 371                         master_pe = pe;
 372                 } else {
 373                         pe->flags |= PNV_IODA_PE_SLAVE;
 374                         pe->master = master_pe;
 375                         list_add_tail(&pe->list, &master_pe->slaves);
 376                 }
 377
 378                 /*
 379                  * P7IOC supports M64DT, which helps mapping M64 segment
 380                  * to one particular PE#. However, PHB3 has fixed mapping
 381                  * between M64 segment and PE#. In order to have same logic
 382                  * for P7IOC and PHB3, we enforce fixed mapping between M64
 383                  * segment and PE# on P7IOC.
 384                  */
 385                 if (phb->type == PNV_PHB_IODA1) {
 386                         int64_t rc;
 387
 388                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
 389                                         pe->pe_number, OPAL_M64_WINDOW_TYPE,
 390                                         pe->pe_number / PNV_IODA1_M64_SEGS,
 391                                         pe->pe_number % PNV_IODA1_M64_SEGS);
 392                         if (rc != OPAL_SUCCESS)
 393                                 pr_warn("%s: Error %lld mapping M64 for PHB#%d-PE#%d\n",
 394                                         __func__, rc, phb->hose->global_number,
 395                                         pe->pe_number);
 396                 }
 397         }
 398
 399         kfree(pe_alloc);
 400         return master_pe;
 401 }
 402
 403 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
 404 {
 405         struct pci_controller *hose = phb->hose;
 406         struct device_node *dn = hose->dn;
 407         struct resource *res;
 408         const u32 *r;
 409         u64 pci_addr;
 410
 411         if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) {
 412                 pr_info("  Not support M64 window\n");
 413                 return;
 414         }
 415
 416         if (!firmware_has_feature(FW_FEATURE_OPAL)) {
 417                 pr_info("  Firmware too old to support M64 window\n");
 418                 return;
 419         }
 420
 421         r = of_get_property(dn, "ibm,opal-m64-window", NULL);
 422         if (!r) {
 423                 pr_info("  No <ibm,opal-m64-window> on %s\n",
 424                         dn->full_name);
 425                 return;
 426         }
 427
 428         res = &hose->mem_resources[1];
 429         res->name = dn->full_name;
 430         res->start = of_translate_address(dn, r + 2);
 431         res->end = res->start + of_read_number(r + 4, 2) - 1;
 432         res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
 433         pci_addr = of_read_number(r, 2);
 434         hose->mem_offset[1] = res->start - pci_addr;
 435
 436         phb->ioda.m64_size = resource_size(res);
 437         phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num;
 438         phb->ioda.m64_base = pci_addr;
 439
 440         pr_info(" MEM64 0x%016llx..0x%016llx -> 0x%016llx\n",
 441                         res->start, res->end, pci_addr);
 442
 443         /* Use last M64 BAR to cover M64 window */
 444         phb->ioda.m64_bar_idx = 15;
 445         if (phb->type == PNV_PHB_IODA1)
 446                 phb->init_m64 = pnv_ioda1_init_m64;
 447         else
 448                 phb->init_m64 = pnv_ioda2_init_m64;
 449         phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe;
 450         phb->pick_m64_pe = pnv_ioda_pick_m64_pe;
 451 }
 452
 453 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
 454 {
 455         struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
 456         struct pnv_ioda_pe *slave;
 457         s64 rc;
 458
 459         /* Fetch master PE */
 460         if (pe->flags & PNV_IODA_PE_SLAVE) {
 461                 pe = pe->master;
 462                 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
 463                         return;
 464
 465                 pe_no = pe->pe_number;
 466         }
 467
 468         /* Freeze master PE */
 469         rc = opal_pci_eeh_freeze_set(phb->opal_id,
 470                                      pe_no,
 471                                      OPAL_EEH_ACTION_SET_FREEZE_ALL);
 472         if (rc != OPAL_SUCCESS) {
 473                 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
 474                         __func__, rc, phb->hose->global_number, pe_no);
 475                 return;
 476         }
 477
 478         /* Freeze slave PEs */
 479         if (!(pe->flags & PNV_IODA_PE_MASTER))
 480                 return;
 481
 482         list_for_each_entry(slave, &pe->slaves, list) {
 483                 rc = opal_pci_eeh_freeze_set(phb->opal_id,
 484                                              slave->pe_number,
 485                                              OPAL_EEH_ACTION_SET_FREEZE_ALL);
 486                 if (rc != OPAL_SUCCESS)
 487                         pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
 488                                 __func__, rc, phb->hose->global_number,
 489                                 slave->pe_number);
 490         }
 491 }
 492
 493 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
 494 {
 495         struct pnv_ioda_pe *pe, *slave;
 496         s64 rc;
 497
 498         /* Find master PE */
 499         pe = &phb->ioda.pe_array[pe_no];
 500         if (pe->flags & PNV_IODA_PE_SLAVE) {
 501                 pe = pe->master;
 502                 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
 503                 pe_no = pe->pe_number;
 504         }
 505
 506         /* Clear frozen state for master PE */
 507         rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
 508         if (rc != OPAL_SUCCESS) {
 509                 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
 510                         __func__, rc, opt, phb->hose->global_number, pe_no);
 511                 return -EIO;
 512         }
 513
 514         if (!(pe->flags & PNV_IODA_PE_MASTER))
 515                 return 0;
 516
 517         /* Clear frozen state for slave PEs */
 518         list_for_each_entry(slave, &pe->slaves, list) {
 519                 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
 520                                              slave->pe_number,
 521                                              opt);
 522                 if (rc != OPAL_SUCCESS) {
 523                         pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
 524                                 __func__, rc, opt, phb->hose->global_number,
 525                                 slave->pe_number);
 526                         return -EIO;
 527                 }
 528         }
 529
 530         return 0;
 531 }
 532
 533 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
 534 {
 535         struct pnv_ioda_pe *slave, *pe;
 536         u8 fstate, state;
 537         __be16 pcierr;
 538         s64 rc;
 539
 540         /* Sanity check on PE number */
 541         if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num)
 542                 return OPAL_EEH_STOPPED_PERM_UNAVAIL;
 543
 544         /*
 545          * Fetch the master PE and the PE instance might be
 546          * not initialized yet.
 547          */
 548         pe = &phb->ioda.pe_array[pe_no];
 549         if (pe->flags & PNV_IODA_PE_SLAVE) {
 550                 pe = pe->master;
 551                 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
 552                 pe_no = pe->pe_number;
 553         }
 554
 555         /* Check the master PE */
 556         rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
 557                                         &state, &pcierr, NULL);
 558         if (rc != OPAL_SUCCESS) {
 559                 pr_warn("%s: Failure %lld getting "
 560                         "PHB#%x-PE#%x state\n",
 561                         __func__, rc,
 562                         phb->hose->global_number, pe_no);
 563                 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
 564         }
 565
 566         /* Check the slave PE */
 567         if (!(pe->flags & PNV_IODA_PE_MASTER))
 568                 return state;
 569
 570         list_for_each_entry(slave, &pe->slaves, list) {
 571                 rc = opal_pci_eeh_freeze_status(phb->opal_id,
 572                                                 slave->pe_number,
 573                                                 &fstate,
 574                                                 &pcierr,
 575                                                 NULL);
 576                 if (rc != OPAL_SUCCESS) {
 577                         pr_warn("%s: Failure %lld getting "
 578                                 "PHB#%x-PE#%x state\n",
 579                                 __func__, rc,
 580                                 phb->hose->global_number, slave->pe_number);
 581                         return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
 582                 }
 583
 584                 /*
 585                  * Override the result based on the ascending
 586                  * priority.
 587                  */
 588                 if (fstate > state)
 589                         state = fstate;
 590         }
 591
 592         return state;
 593 }
 594
 595 /* Currently those 2 are only used when MSIs are enabled, this will change
 596  * but in the meantime, we need to protect them to avoid warnings
 597  */
 598 #ifdef CONFIG_PCI_MSI
 599 static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
 600 {
 601         struct pci_controller *hose = pci_bus_to_host(dev->bus);
 602         struct pnv_phb *phb = hose->private_data;
 603         struct pci_dn *pdn = pci_get_pdn(dev);
 604
 605         if (!pdn)
 606                 return NULL;
 607         if (pdn->pe_number == IODA_INVALID_PE)
 608                 return NULL;
 609         return &phb->ioda.pe_array[pdn->pe_number];
 610 }
 611 #endif /* CONFIG_PCI_MSI */
 612
 613 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
 614                                   struct pnv_ioda_pe *parent,
 615                                   struct pnv_ioda_pe *child,
 616                                   bool is_add)
 617 {
 618         const char *desc = is_add ? "adding" : "removing";
 619         uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
 620                               OPAL_REMOVE_PE_FROM_DOMAIN;
 621         struct pnv_ioda_pe *slave;
 622         long rc;
 623
 624         /* Parent PE affects child PE */
 625         rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
 626                                 child->pe_number, op);
 627         if (rc != OPAL_SUCCESS) {
 628                 pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
 629                         rc, desc);
 630                 return -ENXIO;
 631         }
 632
 633         if (!(child->flags & PNV_IODA_PE_MASTER))
 634                 return 0;
 635
 636         /* Compound case: parent PE affects slave PEs */
 637         list_for_each_entry(slave, &child->slaves, list) {
 638                 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
 639                                         slave->pe_number, op);
 640                 if (rc != OPAL_SUCCESS) {
 641                         pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
 642                                 rc, desc);
 643                         return -ENXIO;
 644                 }
 645         }
 646
 647         return 0;
 648 }
 649
 650 static int pnv_ioda_set_peltv(struct pnv_phb *phb,
 651                               struct pnv_ioda_pe *pe,
 652                               bool is_add)
 653 {
 654         struct pnv_ioda_pe *slave;
 655         struct pci_dev *pdev = NULL;
 656         int ret;
 657
 658         /*
 659          * Clear PE frozen state. If it's master PE, we need
 660          * clear slave PE frozen state as well.
 661          */
 662         if (is_add) {
 663                 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
 664                                           OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 665                 if (pe->flags & PNV_IODA_PE_MASTER) {
 666                         list_for_each_entry(slave, &pe->slaves, list)
 667                                 opal_pci_eeh_freeze_clear(phb->opal_id,
 668                                                           slave->pe_number,
 669                                                           OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 670                 }
 671         }
 672
 673         /*
 674          * Associate PE in PELT. We need add the PE into the
 675          * corresponding PELT-V as well. Otherwise, the error
 676          * originated from the PE might contribute to other
 677          * PEs.
 678          */
 679         ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
 680         if (ret)
 681                 return ret;
 682
 683         /* For compound PEs, any one affects all of them */
 684         if (pe->flags & PNV_IODA_PE_MASTER) {
 685                 list_for_each_entry(slave, &pe->slaves, list) {
 686                         ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
 687                         if (ret)
 688                                 return ret;
 689                 }
 690         }
 691
 692         if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
 693                 pdev = pe->pbus->self;
 694         else if (pe->flags & PNV_IODA_PE_DEV)
 695                 pdev = pe->pdev->bus->self;
 696 #ifdef CONFIG_PCI_IOV
 697         else if (pe->flags & PNV_IODA_PE_VF)
 698                 pdev = pe->parent_dev;
 699 #endif /* CONFIG_PCI_IOV */
 700         while (pdev) {
 701                 struct pci_dn *pdn = pci_get_pdn(pdev);
 702                 struct pnv_ioda_pe *parent;
 703
 704                 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
 705                         parent = &phb->ioda.pe_array[pdn->pe_number];
 706                         ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
 707                         if (ret)
 708                                 return ret;
 709                 }
 710
 711                 pdev = pdev->bus->self;
 712         }
 713
 714         return 0;
 715 }
 716
 717 #ifdef CONFIG_PCI_IOV
 718 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
 719 {
 720         struct pci_dev *parent;
 721         uint8_t bcomp, dcomp, fcomp;
 722         int64_t rc;
 723         long rid_end, rid;
 724
 725         /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
 726         if (pe->pbus) {
 727                 int count;
 728
 729                 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
 730                 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
 731                 parent = pe->pbus->self;
 732                 if (pe->flags & PNV_IODA_PE_BUS_ALL)
 733                         count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
 734                 else
 735                         count = 1;
 736
 737                 switch(count) {
 738                 case  1: bcomp = OpalPciBusAll;         break;
 739                 case  2: bcomp = OpalPciBus7Bits;       break;
 740                 case  4: bcomp = OpalPciBus6Bits;       break;
 741                 case  8: bcomp = OpalPciBus5Bits;       break;
 742                 case 16: bcomp = OpalPciBus4Bits;       break;
 743                 case 32: bcomp = OpalPciBus3Bits;       break;
 744                 default:
 745                         dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
 746                                 count);
 747                         /* Do an exact match only */
 748                         bcomp = OpalPciBusAll;
 749                 }
 750                 rid_end = pe->rid + (count << 8);
 751         } else {
 752                 if (pe->flags & PNV_IODA_PE_VF)
 753                         parent = pe->parent_dev;
 754                 else
 755                         parent = pe->pdev->bus->self;
 756                 bcomp = OpalPciBusAll;
 757                 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
 758                 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
 759                 rid_end = pe->rid + 1;
 760         }
 761
 762         /* Clear the reverse map */
 763         for (rid = pe->rid; rid < rid_end; rid++)
 764                 phb->ioda.pe_rmap[rid] = IODA_INVALID_PE;
 765
 766         /* Release from all parents PELT-V */
 767         while (parent) {
 768                 struct pci_dn *pdn = pci_get_pdn(parent);
 769                 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
 770                         rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
 771                                                 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
 772                         /* XXX What to do in case of error ? */
 773                 }
 774                 parent = parent->bus->self;
 775         }
 776
 777         opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
 778                                   OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 779
 780         /* Disassociate PE in PELT */
 781         rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
 782                                 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
 783         if (rc)
 784                 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc);
 785         rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
 786                              bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
 787         if (rc)
 788                 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
 789
 790         pe->pbus = NULL;
 791         pe->pdev = NULL;
 792         pe->parent_dev = NULL;
 793
 794         return 0;
 795 }
 796 #endif /* CONFIG_PCI_IOV */
 797
 798 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
 799 {
 800         struct pci_dev *parent;
 801         uint8_t bcomp, dcomp, fcomp;
 802         long rc, rid_end, rid;
 803
 804         /* Bus validation ? */
 805         if (pe->pbus) {
 806                 int count;
 807
 808                 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
 809                 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
 810                 parent = pe->pbus->self;
 811                 if (pe->flags & PNV_IODA_PE_BUS_ALL)
 812                         count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
 813                 else
 814                         count = 1;
 815
 816                 switch(count) {
 817                 case  1: bcomp = OpalPciBusAll;         break;
 818                 case  2: bcomp = OpalPciBus7Bits;       break;
 819                 case  4: bcomp = OpalPciBus6Bits;       break;
 820                 case  8: bcomp = OpalPciBus5Bits;       break;
 821                 case 16: bcomp = OpalPciBus4Bits;       break;
 822                 case 32: bcomp = OpalPciBus3Bits;       break;
 823                 default:
 824                         dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
 825                                 count);
 826                         /* Do an exact match only */
 827                         bcomp = OpalPciBusAll;
 828                 }
 829                 rid_end = pe->rid + (count << 8);
 830         } else {
 831 #ifdef CONFIG_PCI_IOV
 832                 if (pe->flags & PNV_IODA_PE_VF)
 833                         parent = pe->parent_dev;
 834                 else
 835 #endif /* CONFIG_PCI_IOV */
 836                         parent = pe->pdev->bus->self;
 837                 bcomp = OpalPciBusAll;
 838                 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
 839                 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
 840                 rid_end = pe->rid + 1;
 841         }
 842
 843         /*
 844          * Associate PE in PELT. We need add the PE into the
 845          * corresponding PELT-V as well. Otherwise, the error
 846          * originated from the PE might contribute to other
 847          * PEs.
 848          */
 849         rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
 850                              bcomp, dcomp, fcomp, OPAL_MAP_PE);
 851         if (rc) {
 852                 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
 853                 return -ENXIO;
 854         }
 855
 856         /*
 857          * Configure PELTV. NPUs don't have a PELTV table so skip
 858          * configuration on them.
 859          */
 860         if (phb->type != PNV_PHB_NPU)
 861                 pnv_ioda_set_peltv(phb, pe, true);
 862
 863         /* Setup reverse map */
 864         for (rid = pe->rid; rid < rid_end; rid++)
 865                 phb->ioda.pe_rmap[rid] = pe->pe_number;
 866
 867         /* Setup one MVTs on IODA1 */
 868         if (phb->type != PNV_PHB_IODA1) {
 869                 pe->mve_number = 0;
 870                 goto out;
 871         }
 872
 873         pe->mve_number = pe->pe_number;
 874         rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
 875         if (rc != OPAL_SUCCESS) {
 876                 pe_err(pe, "OPAL error %ld setting up MVE %d\n",
 877                        rc, pe->mve_number);
 878                 pe->mve_number = -1;
 879         } else {
 880                 rc = opal_pci_set_mve_enable(phb->opal_id,
 881                                              pe->mve_number, OPAL_ENABLE_MVE);
 882                 if (rc) {
 883                         pe_err(pe, "OPAL error %ld enabling MVE %d\n",
 884                                rc, pe->mve_number);
 885                         pe->mve_number = -1;
 886                 }
 887         }
 888
 889 out:
 890         return 0;
 891 }
 892
 893 #ifdef CONFIG_PCI_IOV
 894 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
 895 {
 896         struct pci_dn *pdn = pci_get_pdn(dev);
 897         int i;
 898         struct resource *res, res2;
 899         resource_size_t size;
 900         u16 num_vfs;
 901
 902         if (!dev->is_physfn)
 903                 return -EINVAL;
 904
 905         /*
 906          * "offset" is in VFs.  The M64 windows are sized so that when they
 907          * are segmented, each segment is the same size as the IOV BAR.
 908          * Each segment is in a separate PE, and the high order bits of the
 909          * address are the PE number.  Therefore, each VF's BAR is in a
 910          * separate PE, and changing the IOV BAR start address changes the
 911          * range of PEs the VFs are in.
 912          */
 913         num_vfs = pdn->num_vfs;
 914         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
 915                 res = &dev->resource[i + PCI_IOV_RESOURCES];
 916                 if (!res->flags || !res->parent)
 917                         continue;
 918
 919                 /*
 920                  * The actual IOV BAR range is determined by the start address
 921                  * and the actual size for num_vfs VFs BAR.  This check is to
 922                  * make sure that after shifting, the range will not overlap
 923                  * with another device.
 924                  */
 925                 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
 926                 res2.flags = res->flags;
 927                 res2.start = res->start + (size * offset);
 928                 res2.end = res2.start + (size * num_vfs) - 1;
 929
 930                 if (res2.end > res->end) {
 931                         dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
 932                                 i, &res2, res, num_vfs, offset);
 933                         return -EBUSY;
 934                 }
 935         }
 936
 937         /*
 938          * After doing so, there would be a "hole" in the /proc/iomem when
 939          * offset is a positive value. It looks like the device return some
 940          * mmio back to the system, which actually no one could use it.
 941          */
 942         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
 943                 res = &dev->resource[i + PCI_IOV_RESOURCES];
 944                 if (!res->flags || !res->parent)
 945                         continue;
 946
 947                 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
 948                 res2 = *res;
 949                 res->start += size * offset;
 950
 951                 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",
 952                          i, &res2, res, (offset > 0) ? "En" : "Dis",
 953                          num_vfs, offset);
 954                 pci_update_resource(dev, i + PCI_IOV_RESOURCES);
 955         }
 956         return 0;
 957 }
 958 #endif /* CONFIG_PCI_IOV */
 959
 960 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
 961 {
 962         struct pci_controller *hose = pci_bus_to_host(dev->bus);
 963         struct pnv_phb *phb = hose->private_data;
 964         struct pci_dn *pdn = pci_get_pdn(dev);
 965         struct pnv_ioda_pe *pe;
 966
 967         if (!pdn) {
 968                 pr_err("%s: Device tree node not associated properly\n",
 969                            pci_name(dev));
 970                 return NULL;
 971         }
 972         if (pdn->pe_number != IODA_INVALID_PE)
 973                 return NULL;
 974
 975         pe = pnv_ioda_alloc_pe(phb);
 976         if (!pe) {
 977                 pr_warning("%s: Not enough PE# available, disabling device\n",
 978                            pci_name(dev));
 979                 return NULL;
 980         }
 981
 982         /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
 983          * pointer in the PE data structure, both should be destroyed at the
 984          * same time. However, this needs to be looked at more closely again
 985          * once we actually start removing things (Hotplug, SR-IOV, ...)
 986          *
 987          * At some point we want to remove the PDN completely anyways
 988          */
 989         pci_dev_get(dev);
 990         pdn->pcidev = dev;
 991         pdn->pe_number = pe->pe_number;
 992         pe->flags = PNV_IODA_PE_DEV;
 993         pe->pdev = dev;
 994         pe->pbus = NULL;
 995         pe->mve_number = -1;
 996         pe->rid = dev->bus->number << 8 | pdn->devfn;
 997
 998         pe_info(pe, "Associated device to PE\n");
 999
1000         if (pnv_ioda_configure_pe(phb, pe)) {
1001                 /* XXX What do we do here ? */
1002                 pnv_ioda_free_pe(pe);
1003                 pdn->pe_number = IODA_INVALID_PE;
1004                 pe->pdev = NULL;
1005                 pci_dev_put(dev);
1006                 return NULL;
1007         }
1008
1009         /* Put PE to the list */
1010         list_add_tail(&pe->list, &phb->ioda.pe_list);
1011
1012         return pe;
1013 }
1014
1015 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
1016 {
1017         struct pci_dev *dev;
1018
1019         list_for_each_entry(dev, &bus->devices, bus_list) {
1020                 struct pci_dn *pdn = pci_get_pdn(dev);
1021
1022                 if (pdn == NULL) {
1023                         pr_warn("%s: No device node associated with device !\n",
1024                                 pci_name(dev));
1025                         continue;
1026                 }
1027                 pdn->pcidev = dev;
1028                 pdn->pe_number = pe->pe_number;
1029                 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1030                         pnv_ioda_setup_same_PE(dev->subordinate, pe);
1031         }
1032 }
1033
1034 /*
1035  * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1036  * single PCI bus. Another one that contains the primary PCI bus and its
1037  * subordinate PCI devices and buses. The second type of PE is normally
1038  * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1039  */
1040 static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
1041 {
1042         struct pci_controller *hose = pci_bus_to_host(bus);
1043         struct pnv_phb *phb = hose->private_data;
1044         struct pnv_ioda_pe *pe = NULL;
1045
1046         /* Check if PE is determined by M64 */
1047         if (phb->pick_m64_pe)
1048                 pe = phb->pick_m64_pe(bus, all);
1049
1050         /* The PE number isn't pinned by M64 */
1051         if (!pe)
1052                 pe = pnv_ioda_alloc_pe(phb);
1053
1054         if (!pe) {
1055                 pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1056                         __func__, pci_domain_nr(bus), bus->number);
1057                 return NULL;
1058         }
1059
1060         pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
1061         pe->pbus = bus;
1062         pe->pdev = NULL;
1063         pe->mve_number = -1;
1064         pe->rid = bus->busn_res.start << 8;
1065
1066         if (all)
1067                 pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n",
1068                         bus->busn_res.start, bus->busn_res.end, pe->pe_number);
1069         else
1070                 pe_info(pe, "Secondary bus %d associated with PE#%d\n",
1071                         bus->busn_res.start, pe->pe_number);
1072
1073         if (pnv_ioda_configure_pe(phb, pe)) {
1074                 /* XXX What do we do here ? */
1075                 pnv_ioda_free_pe(pe);
1076                 pe->pbus = NULL;
1077                 return NULL;
1078         }
1079
1080         /* Associate it with all child devices */
1081         pnv_ioda_setup_same_PE(bus, pe);
1082
1083         /* Put PE to the list */
1084         list_add_tail(&pe->list, &phb->ioda.pe_list);
1085
1086         return pe;
1087 }
1088
1089 static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev)
1090 {
1091         int pe_num, found_pe = false, rc;
1092         long rid;
1093         struct pnv_ioda_pe *pe;
1094         struct pci_dev *gpu_pdev;
1095         struct pci_dn *npu_pdn;
1096         struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus);
1097         struct pnv_phb *phb = hose->private_data;
1098
1099         /*
1100          * Due to a hardware errata PE#0 on the NPU is reserved for
1101          * error handling. This means we only have three PEs remaining
1102          * which need to be assigned to four links, implying some
1103          * links must share PEs.
1104          *
1105          * To achieve this we assign PEs such that NPUs linking the
1106          * same GPU get assigned the same PE.
1107          */
1108         gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev);
1109         for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) {
1110                 pe = &phb->ioda.pe_array[pe_num];
1111                 if (!pe->pdev)
1112                         continue;
1113
1114                 if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) {
1115                         /*
1116                          * This device has the same peer GPU so should
1117                          * be assigned the same PE as the existing
1118                          * peer NPU.
1119                          */
1120                         dev_info(&npu_pdev->dev,
1121                                 "Associating to existing PE %d\n", pe_num);
1122                         pci_dev_get(npu_pdev);
1123                         npu_pdn = pci_get_pdn(npu_pdev);
1124                         rid = npu_pdev->bus->number << 8 | npu_pdn->devfn;
1125                         npu_pdn->pcidev = npu_pdev;
1126                         npu_pdn->pe_number = pe_num;
1127                         phb->ioda.pe_rmap[rid] = pe->pe_number;
1128
1129                         /* Map the PE to this link */
1130                         rc = opal_pci_set_pe(phb->opal_id, pe_num, rid,
1131                                         OpalPciBusAll,
1132                                         OPAL_COMPARE_RID_DEVICE_NUMBER,
1133                                         OPAL_COMPARE_RID_FUNCTION_NUMBER,
1134                                         OPAL_MAP_PE);
1135                         WARN_ON(rc != OPAL_SUCCESS);
1136                         found_pe = true;
1137                         break;
1138                 }
1139         }
1140
1141         if (!found_pe)
1142                 /*
1143                  * Could not find an existing PE so allocate a new
1144                  * one.
1145                  */
1146                 return pnv_ioda_setup_dev_PE(npu_pdev);
1147         else
1148                 return pe;
1149 }
1150
1151 static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus)
1152 {
1153         struct pci_dev *pdev;
1154
1155         list_for_each_entry(pdev, &bus->devices, bus_list)
1156                 pnv_ioda_setup_npu_PE(pdev);
1157 }
1158
1159 static void pnv_ioda_setup_PEs(struct pci_bus *bus)
1160 {
1161         struct pci_dev *dev;
1162
1163         pnv_ioda_setup_bus_PE(bus, false);
1164
1165         list_for_each_entry(dev, &bus->devices, bus_list) {
1166                 if (dev->subordinate) {
1167                         if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE)
1168                                 pnv_ioda_setup_bus_PE(dev->subordinate, true);
1169                         else
1170                                 pnv_ioda_setup_PEs(dev->subordinate);
1171                 }
1172         }
1173 }
1174
1175 /*
1176  * Configure PEs so that the downstream PCI buses and devices
1177  * could have their associated PE#. Unfortunately, we didn't
1178  * figure out the way to identify the PLX bridge yet. So we
1179  * simply put the PCI bus and the subordinate behind the root
1180  * port to PE# here. The game rule here is expected to be changed
1181  * as soon as we can detected PLX bridge correctly.
1182  */
1183 static void pnv_pci_ioda_setup_PEs(void)
1184 {
1185         struct pci_controller *hose, *tmp;
1186         struct pnv_phb *phb;
1187
1188         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1189                 phb = hose->private_data;
1190
1191                 /* M64 layout might affect PE allocation */
1192                 if (phb->reserve_m64_pe)
1193                         phb->reserve_m64_pe(hose->bus, NULL, true);
1194
1195                 /*
1196                  * On NPU PHB, we expect separate PEs for individual PCI
1197                  * functions. PCI bus dependent PEs are required for the
1198                  * remaining types of PHBs.
1199                  */
1200                 if (phb->type == PNV_PHB_NPU) {
1201                         /* PE#0 is needed for error reporting */
1202                         pnv_ioda_reserve_pe(phb, 0);
1203                         pnv_ioda_setup_npu_PEs(hose->bus);
1204                 } else
1205                         pnv_ioda_setup_PEs(hose->bus);
1206         }
1207 }
1208
1209 #ifdef CONFIG_PCI_IOV
1210 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs)
1211 {
1212         struct pci_bus        *bus;
1213         struct pci_controller *hose;
1214         struct pnv_phb        *phb;
1215         struct pci_dn         *pdn;
1216         int                    i, j;
1217         int                    m64_bars;
1218
1219         bus = pdev->bus;
1220         hose = pci_bus_to_host(bus);
1221         phb = hose->private_data;
1222         pdn = pci_get_pdn(pdev);
1223
1224         if (pdn->m64_single_mode)
1225                 m64_bars = num_vfs;
1226         else
1227                 m64_bars = 1;
1228
1229         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1230                 for (j = 0; j < m64_bars; j++) {
1231                         if (pdn->m64_map[j][i] == IODA_INVALID_M64)
1232                                 continue;
1233                         opal_pci_phb_mmio_enable(phb->opal_id,
1234                                 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0);
1235                         clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc);
1236                         pdn->m64_map[j][i] = IODA_INVALID_M64;
1237                 }
1238
1239         kfree(pdn->m64_map);
1240         return 0;
1241 }
1242
1243 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
1244 {
1245         struct pci_bus        *bus;
1246         struct pci_controller *hose;
1247         struct pnv_phb        *phb;
1248         struct pci_dn         *pdn;
1249         unsigned int           win;
1250         struct resource       *res;
1251         int                    i, j;
1252         int64_t                rc;
1253         int                    total_vfs;
1254         resource_size_t        size, start;
1255         int                    pe_num;
1256         int                    m64_bars;
1257
1258         bus = pdev->bus;
1259         hose = pci_bus_to_host(bus);
1260         phb = hose->private_data;
1261         pdn = pci_get_pdn(pdev);
1262         total_vfs = pci_sriov_get_totalvfs(pdev);
1263
1264         if (pdn->m64_single_mode)
1265                 m64_bars = num_vfs;
1266         else
1267                 m64_bars = 1;
1268
1269         pdn->m64_map = kmalloc(sizeof(*pdn->m64_map) * m64_bars, GFP_KERNEL);
1270         if (!pdn->m64_map)
1271                 return -ENOMEM;
1272         /* Initialize the m64_map to IODA_INVALID_M64 */
1273         for (i = 0; i < m64_bars ; i++)
1274                 for (j = 0; j < PCI_SRIOV_NUM_BARS; j++)
1275                         pdn->m64_map[i][j] = IODA_INVALID_M64;
1276
1277
1278         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1279                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
1280                 if (!res->flags || !res->parent)
1281                         continue;
1282
1283                 for (j = 0; j < m64_bars; j++) {
1284                         do {
1285                                 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
1286                                                 phb->ioda.m64_bar_idx + 1, 0);
1287
1288                                 if (win >= phb->ioda.m64_bar_idx + 1)
1289                                         goto m64_failed;
1290                         } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
1291
1292                         pdn->m64_map[j][i] = win;
1293
1294                         if (pdn->m64_single_mode) {
1295                                 size = pci_iov_resource_size(pdev,
1296                                                         PCI_IOV_RESOURCES + i);
1297                                 start = res->start + size * j;
1298                         } else {
1299                                 size = resource_size(res);
1300                                 start = res->start;
1301                         }
1302
1303                         /* Map the M64 here */
1304                         if (pdn->m64_single_mode) {
1305                                 pe_num = pdn->pe_num_map[j];
1306                                 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1307                                                 pe_num, OPAL_M64_WINDOW_TYPE,
1308                                                 pdn->m64_map[j][i], 0);
1309                         }
1310
1311                         rc = opal_pci_set_phb_mem_window(phb->opal_id,
1312                                                  OPAL_M64_WINDOW_TYPE,
1313                                                  pdn->m64_map[j][i],
1314                                                  start,
1315                                                  0, /* unused */
1316                                                  size);
1317
1318
1319                         if (rc != OPAL_SUCCESS) {
1320                                 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n",
1321                                         win, rc);
1322                                 goto m64_failed;
1323                         }
1324
1325                         if (pdn->m64_single_mode)
1326                                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1327                                      OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2);
1328                         else
1329                                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1330                                      OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1);
1331
1332                         if (rc != OPAL_SUCCESS) {
1333                                 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n",
1334                                         win, rc);
1335                                 goto m64_failed;
1336                         }
1337                 }
1338         }
1339         return 0;
1340
1341 m64_failed:
1342         pnv_pci_vf_release_m64(pdev, num_vfs);
1343         return -EBUSY;
1344 }
1345
1346 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
1347                 int num);
1348 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
1349
1350 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe)
1351 {
1352         struct iommu_table    *tbl;
1353         int64_t               rc;
1354
1355         tbl = pe->table_group.tables[0];
1356         rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
1357         if (rc)
1358                 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
1359
1360         pnv_pci_ioda2_set_bypass(pe, false);
1361         if (pe->table_group.group) {
1362                 iommu_group_put(pe->table_group.group);
1363                 BUG_ON(pe->table_group.group);
1364         }
1365         pnv_pci_ioda2_table_free_pages(tbl);
1366         iommu_free_table(tbl, of_node_full_name(dev->dev.of_node));
1367 }
1368
1369 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev)
1370 {
1371         struct pci_bus        *bus;
1372         struct pci_controller *hose;
1373         struct pnv_phb        *phb;
1374         struct pnv_ioda_pe    *pe, *pe_n;
1375         struct pci_dn         *pdn;
1376
1377         bus = pdev->bus;
1378         hose = pci_bus_to_host(bus);
1379         phb = hose->private_data;
1380         pdn = pci_get_pdn(pdev);
1381
1382         if (!pdev->is_physfn)
1383                 return;
1384
1385         list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
1386                 if (pe->parent_dev != pdev)
1387                         continue;
1388
1389                 pnv_pci_ioda2_release_dma_pe(pdev, pe);
1390
1391                 /* Remove from list */
1392                 mutex_lock(&phb->ioda.pe_list_mutex);
1393                 list_del(&pe->list);
1394                 mutex_unlock(&phb->ioda.pe_list_mutex);
1395
1396                 pnv_ioda_deconfigure_pe(phb, pe);
1397
1398                 pnv_ioda_free_pe(pe);
1399         }
1400 }
1401
1402 void pnv_pci_sriov_disable(struct pci_dev *pdev)
1403 {
1404         struct pci_bus        *bus;
1405         struct pci_controller *hose;
1406         struct pnv_phb        *phb;
1407         struct pnv_ioda_pe    *pe;
1408         struct pci_dn         *pdn;
1409         struct pci_sriov      *iov;
1410         u16                    num_vfs, i;
1411
1412         bus = pdev->bus;
1413         hose = pci_bus_to_host(bus);
1414         phb = hose->private_data;
1415         pdn = pci_get_pdn(pdev);
1416         iov = pdev->sriov;
1417         num_vfs = pdn->num_vfs;
1418
1419         /* Release VF PEs */
1420         pnv_ioda_release_vf_PE(pdev);
1421
1422         if (phb->type == PNV_PHB_IODA2) {
1423                 if (!pdn->m64_single_mode)
1424                         pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map);
1425
1426                 /* Release M64 windows */
1427                 pnv_pci_vf_release_m64(pdev, num_vfs);
1428
1429                 /* Release PE numbers */
1430                 if (pdn->m64_single_mode) {
1431                         for (i = 0; i < num_vfs; i++) {
1432                                 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1433                                         continue;
1434
1435                                 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1436                                 pnv_ioda_free_pe(pe);
1437                         }
1438                 } else
1439                         bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1440                 /* Releasing pe_num_map */
1441                 kfree(pdn->pe_num_map);
1442         }
1443 }
1444
1445 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1446                                        struct pnv_ioda_pe *pe);
1447 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1448 {
1449         struct pci_bus        *bus;
1450         struct pci_controller *hose;
1451         struct pnv_phb        *phb;
1452         struct pnv_ioda_pe    *pe;
1453         int                    pe_num;
1454         u16                    vf_index;
1455         struct pci_dn         *pdn;
1456
1457         bus = pdev->bus;
1458         hose = pci_bus_to_host(bus);
1459         phb = hose->private_data;
1460         pdn = pci_get_pdn(pdev);
1461
1462         if (!pdev->is_physfn)
1463                 return;
1464
1465         /* Reserve PE for each VF */
1466         for (vf_index = 0; vf_index < num_vfs; vf_index++) {
1467                 if (pdn->m64_single_mode)
1468                         pe_num = pdn->pe_num_map[vf_index];
1469                 else
1470                         pe_num = *pdn->pe_num_map + vf_index;
1471
1472                 pe = &phb->ioda.pe_array[pe_num];
1473                 pe->pe_number = pe_num;
1474                 pe->phb = phb;
1475                 pe->flags = PNV_IODA_PE_VF;
1476                 pe->pbus = NULL;
1477                 pe->parent_dev = pdev;
1478                 pe->mve_number = -1;
1479                 pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) |
1480                            pci_iov_virtfn_devfn(pdev, vf_index);
1481
1482                 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n",
1483                         hose->global_number, pdev->bus->number,
1484                         PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)),
1485                         PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num);
1486
1487                 if (pnv_ioda_configure_pe(phb, pe)) {
1488                         /* XXX What do we do here ? */
1489                         pnv_ioda_free_pe(pe);
1490                         pe->pdev = NULL;
1491                         continue;
1492                 }
1493
1494                 /* Put PE to the list */
1495                 mutex_lock(&phb->ioda.pe_list_mutex);
1496                 list_add_tail(&pe->list, &phb->ioda.pe_list);
1497                 mutex_unlock(&phb->ioda.pe_list_mutex);
1498
1499                 pnv_pci_ioda2_setup_dma_pe(phb, pe);
1500         }
1501 }
1502
1503 int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1504 {
1505         struct pci_bus        *bus;
1506         struct pci_controller *hose;
1507         struct pnv_phb        *phb;
1508         struct pnv_ioda_pe    *pe;
1509         struct pci_dn         *pdn;
1510         int                    ret;
1511         u16                    i;
1512
1513         bus = pdev->bus;
1514         hose = pci_bus_to_host(bus);
1515         phb = hose->private_data;
1516         pdn = pci_get_pdn(pdev);
1517
1518         if (phb->type == PNV_PHB_IODA2) {
1519                 if (!pdn->vfs_expanded) {
1520                         dev_info(&pdev->dev, "don't support this SRIOV device"
1521                                 " with non 64bit-prefetchable IOV BAR\n");
1522                         return -ENOSPC;
1523                 }
1524
1525                 /*
1526                  * When M64 BARs functions in Single PE mode, the number of VFs
1527                  * could be enabled must be less than the number of M64 BARs.
1528                  */
1529                 if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) {
1530                         dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n");
1531                         return -EBUSY;
1532                 }
1533
1534                 /* Allocating pe_num_map */
1535                 if (pdn->m64_single_mode)
1536                         pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map) * num_vfs,
1537                                         GFP_KERNEL);
1538                 else
1539                         pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL);
1540
1541                 if (!pdn->pe_num_map)
1542                         return -ENOMEM;
1543
1544                 if (pdn->m64_single_mode)
1545                         for (i = 0; i < num_vfs; i++)
1546                                 pdn->pe_num_map[i] = IODA_INVALID_PE;
1547
1548                 /* Calculate available PE for required VFs */
1549                 if (pdn->m64_single_mode) {
1550                         for (i = 0; i < num_vfs; i++) {
1551                                 pe = pnv_ioda_alloc_pe(phb);
1552                                 if (!pe) {
1553                                         ret = -EBUSY;
1554                                         goto m64_failed;
1555                                 }
1556
1557                                 pdn->pe_num_map[i] = pe->pe_number;
1558                         }
1559                 } else {
1560                         mutex_lock(&phb->ioda.pe_alloc_mutex);
1561                         *pdn->pe_num_map = bitmap_find_next_zero_area(
1562                                 phb->ioda.pe_alloc, phb->ioda.total_pe_num,
1563                                 0, num_vfs, 0);
1564                         if (*pdn->pe_num_map >= phb->ioda.total_pe_num) {
1565                                 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1566                                 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs);
1567                                 kfree(pdn->pe_num_map);
1568                                 return -EBUSY;
1569                         }
1570                         bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1571                         mutex_unlock(&phb->ioda.pe_alloc_mutex);
1572                 }
1573                 pdn->num_vfs = num_vfs;
1574
1575                 /* Assign M64 window accordingly */
1576                 ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
1577                 if (ret) {
1578                         dev_info(&pdev->dev, "Not enough M64 window resources\n");
1579                         goto m64_failed;
1580                 }
1581
1582                 /*
1583                  * When using one M64 BAR to map one IOV BAR, we need to shift
1584                  * the IOV BAR according to the PE# allocated to the VFs.
1585                  * Otherwise, the PE# for the VF will conflict with others.
1586                  */
1587                 if (!pdn->m64_single_mode) {
1588                         ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map);
1589                         if (ret)
1590                                 goto m64_failed;
1591                 }
1592         }
1593
1594         /* Setup VF PEs */
1595         pnv_ioda_setup_vf_PE(pdev, num_vfs);
1596
1597         return 0;
1598
1599 m64_failed:
1600         if (pdn->m64_single_mode) {
1601                 for (i = 0; i < num_vfs; i++) {
1602                         if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1603                                 continue;
1604
1605                         pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1606                         pnv_ioda_free_pe(pe);
1607                 }
1608         } else
1609                 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1610
1611         /* Releasing pe_num_map */
1612         kfree(pdn->pe_num_map);
1613
1614         return ret;
1615 }
1616
1617 int pcibios_sriov_disable(struct pci_dev *pdev)
1618 {
1619         pnv_pci_sriov_disable(pdev);
1620
1621         /* Release PCI data */
1622         remove_dev_pci_data(pdev);
1623         return 0;
1624 }
1625
1626 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1627 {
1628         /* Allocate PCI data */
1629         add_dev_pci_data(pdev);
1630
1631         return pnv_pci_sriov_enable(pdev, num_vfs);
1632 }
1633 #endif /* CONFIG_PCI_IOV */
1634
1635 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
1636 {
1637         struct pci_dn *pdn = pci_get_pdn(pdev);
1638         struct pnv_ioda_pe *pe;
1639
1640         /*
1641          * The function can be called while the PE#
1642          * hasn't been assigned. Do nothing for the
1643          * case.
1644          */
1645         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1646                 return;
1647
1648         pe = &phb->ioda.pe_array[pdn->pe_number];
1649         WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
1650         set_dma_offset(&pdev->dev, pe->tce_bypass_base);
1651         set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
1652         /*
1653          * Note: iommu_add_device() will fail here as
1654          * for physical PE: the device is already added by now;
1655          * for virtual PE: sysfs entries are not ready yet and
1656          * tce_iommu_bus_notifier will add the device to a group later.
1657          */
1658 }
1659
1660 static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
1661 {
1662         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1663         struct pnv_phb *phb = hose->private_data;
1664         struct pci_dn *pdn = pci_get_pdn(pdev);
1665         struct pnv_ioda_pe *pe;
1666         uint64_t top;
1667         bool bypass = false;
1668
1669         if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1670                 return -ENODEV;;
1671
1672         pe = &phb->ioda.pe_array[pdn->pe_number];
1673         if (pe->tce_bypass_enabled) {
1674                 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1675                 bypass = (dma_mask >= top);
1676         }
1677
1678         if (bypass) {
1679                 dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");
1680                 set_dma_ops(&pdev->dev, &dma_direct_ops);
1681         } else {
1682                 dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");
1683                 set_dma_ops(&pdev->dev, &dma_iommu_ops);
1684         }
1685         *pdev->dev.dma_mask = dma_mask;
1686
1687         /* Update peer npu devices */
1688         pnv_npu_try_dma_set_bypass(pdev, bypass);
1689
1690         return 0;
1691 }
1692
1693 static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev)
1694 {
1695         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1696         struct pnv_phb *phb = hose->private_data;
1697         struct pci_dn *pdn = pci_get_pdn(pdev);
1698         struct pnv_ioda_pe *pe;
1699         u64 end, mask;
1700
1701         if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1702                 return 0;
1703
1704         pe = &phb->ioda.pe_array[pdn->pe_number];
1705         if (!pe->tce_bypass_enabled)
1706                 return __dma_get_required_mask(&pdev->dev);
1707
1708
1709         end = pe->tce_bypass_base + memblock_end_of_DRAM();
1710         mask = 1ULL << (fls64(end) - 1);
1711         mask += mask - 1;
1712
1713         return mask;
1714 }
1715
1716 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe,
1717                                    struct pci_bus *bus)
1718 {
1719         struct pci_dev *dev;
1720
1721         list_for_each_entry(dev, &bus->devices, bus_list) {
1722                 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
1723                 set_dma_offset(&dev->dev, pe->tce_bypass_base);
1724                 iommu_add_device(&dev->dev);
1725
1726                 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1727                         pnv_ioda_setup_bus_dma(pe, dev->subordinate);
1728         }
1729 }
1730
1731 static void pnv_pci_ioda1_tce_invalidate(struct iommu_table *tbl,
1732                 unsigned long index, unsigned long npages, bool rm)
1733 {
1734         struct iommu_table_group_link *tgl = list_first_entry_or_null(
1735                         &tbl->it_group_list, struct iommu_table_group_link,
1736                         next);
1737         struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1738                         struct pnv_ioda_pe, table_group);
1739         __be64 __iomem *invalidate = rm ?
1740                 (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys :
1741                 pe->phb->ioda.tce_inval_reg;
1742         unsigned long start, end, inc;
1743         const unsigned shift = tbl->it_page_shift;
1744
1745         start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset);
1746         end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset +
1747                         npages - 1);
1748
1749         /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */
1750         if (tbl->it_busno) {
1751                 start <<= shift;
1752                 end <<= shift;
1753                 inc = 128ull << shift;
1754                 start |= tbl->it_busno;
1755                 end |= tbl->it_busno;
1756         } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) {
1757                 /* p7ioc-style invalidation, 2 TCEs per write */
1758                 start |= (1ull << 63);
1759                 end |= (1ull << 63);
1760                 inc = 16;
1761         } else {
1762                 /* Default (older HW) */
1763                 inc = 128;
1764         }
1765
1766         end |= inc - 1; /* round up end to be different than start */
1767
1768         mb(); /* Ensure above stores are visible */
1769         while (start <= end) {
1770                 if (rm)
1771                         __raw_rm_writeq(cpu_to_be64(start), invalidate);
1772                 else
1773                         __raw_writeq(cpu_to_be64(start), invalidate);
1774                 start += inc;
1775         }
1776
1777         /*
1778          * The iommu layer will do another mb() for us on build()
1779          * and we don't care on free()
1780          */
1781 }
1782
1783 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
1784                 long npages, unsigned long uaddr,
1785                 enum dma_data_direction direction,
1786                 struct dma_attrs *attrs)
1787 {
1788         int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1789                         attrs);
1790
1791         if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE))
1792                 pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false);
1793
1794         return ret;
1795 }
1796
1797 #ifdef CONFIG_IOMMU_API
1798 static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index,
1799                 unsigned long *hpa, enum dma_data_direction *direction)
1800 {
1801         long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1802
1803         if (!ret && (tbl->it_type &
1804                         (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE)))
1805                 pnv_pci_ioda1_tce_invalidate(tbl, index, 1, false);
1806
1807         return ret;
1808 }
1809 #endif
1810
1811 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
1812                 long npages)
1813 {
1814         pnv_tce_free(tbl, index, npages);
1815
1816         if (tbl->it_type & TCE_PCI_SWINV_FREE)
1817                 pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false);
1818 }
1819
1820 static struct iommu_table_ops pnv_ioda1_iommu_ops = {
1821         .set = pnv_ioda1_tce_build,
1822 #ifdef CONFIG_IOMMU_API
1823         .exchange = pnv_ioda1_tce_xchg,
1824 #endif
1825         .clear = pnv_ioda1_tce_free,
1826         .get = pnv_tce_get,
1827 };
1828
1829 #define TCE_KILL_INVAL_ALL  PPC_BIT(0)
1830 #define TCE_KILL_INVAL_PE   PPC_BIT(1)
1831 #define TCE_KILL_INVAL_TCE  PPC_BIT(2)
1832
1833 void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
1834 {
1835         const unsigned long val = TCE_KILL_INVAL_ALL;
1836
1837         mb(); /* Ensure previous TCE table stores are visible */
1838         if (rm)
1839                 __raw_rm_writeq(cpu_to_be64(val),
1840                                 (__be64 __iomem *)
1841                                 phb->ioda.tce_inval_reg_phys);
1842         else
1843                 __raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg);
1844 }
1845
1846 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe)
1847 {
1848         /* 01xb - invalidate TCEs that match the specified PE# */
1849         unsigned long val = TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF);
1850         struct pnv_phb *phb = pe->phb;
1851
1852         if (!phb->ioda.tce_inval_reg)
1853                 return;
1854
1855         mb(); /* Ensure above stores are visible */
1856         __raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg);
1857 }
1858
1859 static void pnv_pci_ioda2_do_tce_invalidate(unsigned pe_number, bool rm,
1860                 __be64 __iomem *invalidate, unsigned shift,
1861                 unsigned long index, unsigned long npages)
1862 {
1863         unsigned long start, end, inc;
1864
1865         /* We'll invalidate DMA address in PE scope */
1866         start = TCE_KILL_INVAL_TCE;
1867         start |= (pe_number & 0xFF);
1868         end = start;
1869
1870         /* Figure out the start, end and step */
1871         start |= (index << shift);
1872         end |= ((index + npages - 1) << shift);
1873         inc = (0x1ull << shift);
1874         mb();
1875
1876         while (start <= end) {
1877                 if (rm)
1878                         __raw_rm_writeq(cpu_to_be64(start), invalidate);
1879                 else
1880                         __raw_writeq(cpu_to_be64(start), invalidate);
1881                 start += inc;
1882         }
1883 }
1884
1885 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
1886                 unsigned long index, unsigned long npages, bool rm)
1887 {
1888         struct iommu_table_group_link *tgl;
1889
1890         list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) {
1891                 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1892                                 struct pnv_ioda_pe, table_group);
1893                 __be64 __iomem *invalidate = rm ?
1894                         (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys :
1895                         pe->phb->ioda.tce_inval_reg;
1896
1897                 if (pe->phb->type == PNV_PHB_NPU) {
1898                         /*
1899                          * The NVLink hardware does not support TCE kill
1900                          * per TCE entry so we have to invalidate
1901                          * the entire cache for it.
1902                          */
1903                         pnv_pci_ioda2_tce_invalidate_entire(pe->phb, rm);
1904                         continue;
1905                 }
1906                 pnv_pci_ioda2_do_tce_invalidate(pe->pe_number, rm,
1907                         invalidate, tbl->it_page_shift,
1908                         index, npages);
1909         }
1910 }
1911
1912 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
1913                 long npages, unsigned long uaddr,
1914                 enum dma_data_direction direction,
1915                 struct dma_attrs *attrs)
1916 {
1917         int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1918                         attrs);
1919
1920         if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE))
1921                 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
1922
1923         return ret;
1924 }
1925
1926 #ifdef CONFIG_IOMMU_API
1927 static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index,
1928                 unsigned long *hpa, enum dma_data_direction *direction)
1929 {
1930         long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1931
1932         if (!ret && (tbl->it_type &
1933                         (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE)))
1934                 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false);
1935
1936         return ret;
1937 }
1938 #endif
1939
1940 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
1941                 long npages)
1942 {
1943         pnv_tce_free(tbl, index, npages);
1944
1945         if (tbl->it_type & TCE_PCI_SWINV_FREE)
1946                 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
1947 }
1948
1949 static void pnv_ioda2_table_free(struct iommu_table *tbl)
1950 {
1951         pnv_pci_ioda2_table_free_pages(tbl);
1952         iommu_free_table(tbl, "pnv");
1953 }
1954
1955 static struct iommu_table_ops pnv_ioda2_iommu_ops = {
1956         .set = pnv_ioda2_tce_build,
1957 #ifdef CONFIG_IOMMU_API
1958         .exchange = pnv_ioda2_tce_xchg,
1959 #endif
1960         .clear = pnv_ioda2_tce_free,
1961         .get = pnv_tce_get,
1962         .free = pnv_ioda2_table_free,
1963 };
1964
1965 static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data)
1966 {
1967         unsigned int *weight = (unsigned int *)data;
1968
1969         /* This is quite simplistic. The "base" weight of a device
1970          * is 10. 0 means no DMA is to be accounted for it.
1971          */
1972         if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
1973                 return 0;
1974
1975         if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
1976             dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
1977             dev->class == PCI_CLASS_SERIAL_USB_EHCI)
1978                 *weight += 3;
1979         else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
1980                 *weight += 15;
1981         else
1982                 *weight += 10;
1983
1984         return 0;
1985 }
1986
1987 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe)
1988 {
1989         unsigned int weight = 0;
1990
1991         /* SRIOV VF has same DMA32 weight as its PF */
1992 #ifdef CONFIG_PCI_IOV
1993         if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) {
1994                 pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight);
1995                 return weight;
1996         }
1997 #endif
1998
1999         if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) {
2000                 pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight);
2001         } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) {
2002                 struct pci_dev *pdev;
2003
2004                 list_for_each_entry(pdev, &pe->pbus->devices, bus_list)
2005                         pnv_pci_ioda_dev_dma_weight(pdev, &weight);
2006         } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) {
2007                 pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight);
2008         }
2009
2010         return weight;
2011 }
2012
2013 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb,
2014                                        struct pnv_ioda_pe *pe)
2015 {
2016
2017         struct page *tce_mem = NULL;
2018         struct iommu_table *tbl;
2019         unsigned int weight, total_weight = 0;
2020         unsigned int tce32_segsz, base, segs, avail, i;
2021         int64_t rc;
2022         void *addr;
2023
2024         /* XXX FIXME: Handle 64-bit only DMA devices */
2025         /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
2026         /* XXX FIXME: Allocate multi-level tables on PHB3 */
2027         weight = pnv_pci_ioda_pe_dma_weight(pe);
2028         if (!weight)
2029                 return;
2030
2031         pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight,
2032                      &total_weight);
2033         segs = (weight * phb->ioda.dma32_count) / total_weight;
2034         if (!segs)
2035                 segs = 1;
2036
2037         /*
2038          * Allocate contiguous DMA32 segments. We begin with the expected
2039          * number of segments. With one more attempt, the number of DMA32
2040          * segments to be allocated is decreased by one until one segment
2041          * is allocated successfully.
2042          */
2043         do {
2044                 for (base = 0; base <= phb->ioda.dma32_count - segs; base++) {
2045                         for (avail = 0, i = base; i < base + segs; i++) {
2046                                 if (phb->ioda.dma32_segmap[i] ==
2047                                     IODA_INVALID_PE)
2048                                         avail++;
2049                         }
2050
2051                         if (avail == segs)
2052                                 goto found;
2053                 }
2054         } while (--segs);
2055
2056         if (!segs) {
2057                 pe_warn(pe, "No available DMA32 segments\n");
2058                 return;
2059         }
2060
2061 found:
2062         tbl = pnv_pci_table_alloc(phb->hose->node);
2063         iommu_register_group(&pe->table_group, phb->hose->global_number,
2064                         pe->pe_number);
2065         pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
2066
2067         /* Grab a 32-bit TCE table */
2068         pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n",
2069                 weight, total_weight, base, segs);
2070         pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
2071                 base * PNV_IODA1_DMA32_SEGSIZE,
2072                 (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1);
2073
2074         /* XXX Currently, we allocate one big contiguous table for the
2075          * TCEs. We only really need one chunk per 256M of TCE space
2076          * (ie per segment) but that's an optimization for later, it
2077          * requires some added smarts with our get/put_tce implementation
2078          *
2079          * Each TCE page is 4KB in size and each TCE entry occupies 8
2080          * bytes
2081          */
2082         tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3);
2083         tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
2084                                    get_order(tce32_segsz * segs));
2085         if (!tce_mem) {
2086                 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
2087                 goto fail;
2088         }
2089         addr = page_address(tce_mem);
2090         memset(addr, 0, tce32_segsz * segs);
2091
2092         /* Configure HW */
2093         for (i = 0; i < segs; i++) {
2094                 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2095                                               pe->pe_number,
2096                                               base + i, 1,
2097                                               __pa(addr) + tce32_segsz * i,
2098                                               tce32_segsz, IOMMU_PAGE_SIZE_4K);
2099                 if (rc) {
2100                         pe_err(pe, " Failed to configure 32-bit TCE table,"
2101                                " err %ld\n", rc);
2102                         goto fail;
2103                 }
2104         }
2105
2106         /* Setup DMA32 segment mapping */
2107         for (i = base; i < base + segs; i++)
2108                 phb->ioda.dma32_segmap[i] = pe->pe_number;
2109
2110         /* Setup linux iommu table */
2111         pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs,
2112                                   base * PNV_IODA1_DMA32_SEGSIZE,
2113                                   IOMMU_PAGE_SHIFT_4K);
2114
2115         /* OPAL variant of P7IOC SW invalidated TCEs */
2116         if (phb->ioda.tce_inval_reg)
2117                 tbl->it_type |= (TCE_PCI_SWINV_CREATE |
2118                                  TCE_PCI_SWINV_FREE   |
2119                                  TCE_PCI_SWINV_PAIR);
2120
2121         tbl->it_ops = &pnv_ioda1_iommu_ops;
2122         pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
2123         pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
2124         iommu_init_table(tbl, phb->hose->node);
2125
2126         if (pe->flags & PNV_IODA_PE_DEV) {
2127                 /*
2128                  * Setting table base here only for carrying iommu_group
2129                  * further down to let iommu_add_device() do the job.
2130                  * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2131                  */
2132                 set_iommu_table_base(&pe->pdev->dev, tbl);
2133                 iommu_add_device(&pe->pdev->dev);
2134         } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2135                 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2136
2137         return;
2138  fail:
2139         /* XXX Failure: Try to fallback to 64-bit only ? */
2140         if (tce_mem)
2141                 __free_pages(tce_mem, get_order(tce32_segsz * segs));
2142         if (tbl) {
2143                 pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
2144                 iommu_free_table(tbl, "pnv");
2145         }
2146 }
2147
2148 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
2149                 int num, struct iommu_table *tbl)
2150 {
2151         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2152                         table_group);
2153         struct pnv_phb *phb = pe->phb;
2154         int64_t rc;
2155         const unsigned long size = tbl->it_indirect_levels ?
2156                         tbl->it_level_size : tbl->it_size;
2157         const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
2158         const __u64 win_size = tbl->it_size << tbl->it_page_shift;
2159
2160         pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num,
2161                         start_addr, start_addr + win_size - 1,
2162                         IOMMU_PAGE_SIZE(tbl));
2163
2164         /*
2165          * Map TCE table through TVT. The TVE index is the PE number
2166          * shifted by 1 bit for 32-bits DMA space.
2167          */
2168         rc = opal_pci_map_pe_dma_window(phb->opal_id,
2169                         pe->pe_number,
2170                         (pe->pe_number << 1) + num,
2171                         tbl->it_indirect_levels + 1,
2172                         __pa(tbl->it_base),
2173                         size << 3,
2174                         IOMMU_PAGE_SIZE(tbl));
2175         if (rc) {
2176                 pe_err(pe, "Failed to configure TCE table, err %ld\n", rc);
2177                 return rc;
2178         }
2179
2180         pnv_pci_link_table_and_group(phb->hose->node, num,
2181                         tbl, &pe->table_group);
2182         pnv_pci_ioda2_tce_invalidate_pe(pe);
2183
2184         return 0;
2185 }
2186
2187 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
2188 {
2189         uint16_t window_id = (pe->pe_number << 1 ) + 1;
2190         int64_t rc;
2191
2192         pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
2193         if (enable) {
2194                 phys_addr_t top = memblock_end_of_DRAM();
2195
2196                 top = roundup_pow_of_two(top);
2197                 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2198                                                      pe->pe_number,
2199                                                      window_id,
2200                                                      pe->tce_bypass_base,
2201                                                      top);
2202         } else {
2203                 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2204                                                      pe->pe_number,
2205                                                      window_id,
2206                                                      pe->tce_bypass_base,
2207                                                      0);
2208         }
2209         if (rc)
2210                 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
2211         else
2212                 pe->tce_bypass_enabled = enable;
2213 }
2214
2215 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2216                 __u32 page_shift, __u64 window_size, __u32 levels,
2217                 struct iommu_table *tbl);
2218
2219 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
2220                 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2221                 struct iommu_table **ptbl)
2222 {
2223         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2224                         table_group);
2225         int nid = pe->phb->hose->node;
2226         __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
2227         long ret;
2228         struct iommu_table *tbl;
2229
2230         tbl = pnv_pci_table_alloc(nid);
2231         if (!tbl)
2232                 return -ENOMEM;
2233
2234         ret = pnv_pci_ioda2_table_alloc_pages(nid,
2235                         bus_offset, page_shift, window_size,
2236                         levels, tbl);
2237         if (ret) {
2238                 iommu_free_table(tbl, "pnv");
2239                 return ret;
2240         }
2241
2242         tbl->it_ops = &pnv_ioda2_iommu_ops;
2243         if (pe->phb->ioda.tce_inval_reg)
2244                 tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE);
2245
2246         *ptbl = tbl;
2247
2248         return 0;
2249 }
2250
2251 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
2252 {
2253         struct iommu_table *tbl = NULL;
2254         long rc;
2255
2256         /*
2257          * crashkernel= specifies the kdump kernel's maximum memory at
2258          * some offset and there is no guaranteed the result is a power
2259          * of 2, which will cause errors later.
2260          */
2261         const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max());
2262
2263         /*
2264          * In memory constrained environments, e.g. kdump kernel, the
2265          * DMA window can be larger than available memory, which will
2266          * cause errors later.
2267          */
2268         const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory);
2269
2270         rc = pnv_pci_ioda2_create_table(&pe->table_group, 0,
2271                         IOMMU_PAGE_SHIFT_4K,
2272                         window_size,
2273                         POWERNV_IOMMU_DEFAULT_LEVELS, &tbl);
2274         if (rc) {
2275                 pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
2276                                 rc);
2277                 return rc;
2278         }
2279
2280         iommu_init_table(tbl, pe->phb->hose->node);
2281
2282         rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
2283         if (rc) {
2284                 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n",
2285                                 rc);
2286                 pnv_ioda2_table_free(tbl);
2287                 return rc;
2288         }
2289
2290         if (!pnv_iommu_bypass_disabled)
2291                 pnv_pci_ioda2_set_bypass(pe, true);
2292
2293         /* OPAL variant of PHB3 invalidated TCEs */
2294         if (pe->phb->ioda.tce_inval_reg)
2295                 tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE);
2296
2297         /*
2298          * Setting table base here only for carrying iommu_group
2299          * further down to let iommu_add_device() do the job.
2300          * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2301          */
2302         if (pe->flags & PNV_IODA_PE_DEV)
2303                 set_iommu_table_base(&pe->pdev->dev, tbl);
2304
2305         return 0;
2306 }
2307
2308 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV)
2309 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
2310                 int num)
2311 {
2312         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2313                         table_group);
2314         struct pnv_phb *phb = pe->phb;
2315         long ret;
2316
2317         pe_info(pe, "Removing DMA window #%d\n", num);
2318
2319         ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
2320                         (pe->pe_number << 1) + num,
2321                         0/* levels */, 0/* table address */,
2322                         0/* table size */, 0/* page size */);
2323         if (ret)
2324                 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
2325         else
2326                 pnv_pci_ioda2_tce_invalidate_pe(pe);
2327
2328         pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
2329
2330         return ret;
2331 }
2332 #endif
2333
2334 #ifdef CONFIG_IOMMU_API
2335 static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
2336                 __u64 window_size, __u32 levels)
2337 {
2338         unsigned long bytes = 0;
2339         const unsigned window_shift = ilog2(window_size);
2340         unsigned entries_shift = window_shift - page_shift;
2341         unsigned table_shift = entries_shift + 3;
2342         unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift);
2343         unsigned long direct_table_size;
2344
2345         if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
2346                         (window_size > memory_hotplug_max()) ||
2347                         !is_power_of_2(window_size))
2348                 return 0;
2349
2350         /* Calculate a direct table size from window_size and levels */
2351         entries_shift = (entries_shift + levels - 1) / levels;
2352         table_shift = entries_shift + 3;
2353         table_shift = max_t(unsigned, table_shift, PAGE_SHIFT);
2354         direct_table_size =  1UL << table_shift;
2355
2356         for ( ; levels; --levels) {
2357                 bytes += _ALIGN_UP(tce_table_size, direct_table_size);
2358
2359                 tce_table_size /= direct_table_size;
2360                 tce_table_size <<= 3;
2361                 tce_table_size = _ALIGN_UP(tce_table_size, direct_table_size);
2362         }
2363
2364         return bytes;
2365 }
2366
2367 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
2368 {
2369         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2370                                                 table_group);
2371         /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
2372         struct iommu_table *tbl = pe->table_group.tables[0];
2373
2374         pnv_pci_ioda2_set_bypass(pe, false);
2375         pnv_pci_ioda2_unset_window(&pe->table_group, 0);
2376         pnv_ioda2_table_free(tbl);
2377 }
2378
2379 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
2380 {
2381         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2382                                                 table_group);
2383
2384         pnv_pci_ioda2_setup_default_config(pe);
2385 }
2386
2387 static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
2388         .get_table_size = pnv_pci_ioda2_get_table_size,
2389         .create_table = pnv_pci_ioda2_create_table,
2390         .set_window = pnv_pci_ioda2_set_window,
2391         .unset_window = pnv_pci_ioda2_unset_window,
2392         .take_ownership = pnv_ioda2_take_ownership,
2393         .release_ownership = pnv_ioda2_release_ownership,
2394 };
2395
2396 static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque)
2397 {
2398         struct pci_controller *hose;
2399         struct pnv_phb *phb;
2400         struct pnv_ioda_pe **ptmppe = opaque;
2401         struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
2402         struct pci_dn *pdn = pci_get_pdn(pdev);
2403
2404         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
2405                 return 0;
2406
2407         hose = pci_bus_to_host(pdev->bus);
2408         phb = hose->private_data;
2409         if (phb->type != PNV_PHB_NPU)
2410                 return 0;
2411
2412         *ptmppe = &phb->ioda.pe_array[pdn->pe_number];
2413
2414         return 1;
2415 }
2416
2417 /*
2418  * This returns PE of associated NPU.
2419  * This assumes that NPU is in the same IOMMU group with GPU and there is
2420  * no other PEs.
2421  */
2422 static struct pnv_ioda_pe *gpe_table_group_to_npe(
2423                 struct iommu_table_group *table_group)
2424 {
2425         struct pnv_ioda_pe *npe = NULL;
2426         int ret = iommu_group_for_each_dev(table_group->group, &npe,
2427                         gpe_table_group_to_npe_cb);
2428
2429         BUG_ON(!ret || !npe);
2430
2431         return npe;
2432 }
2433
2434 static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group,
2435                 int num, struct iommu_table *tbl)
2436 {
2437         long ret = pnv_pci_ioda2_set_window(table_group, num, tbl);
2438
2439         if (ret)
2440                 return ret;
2441
2442         ret = pnv_npu_set_window(gpe_table_group_to_npe(table_group), num, tbl);
2443         if (ret)
2444                 pnv_pci_ioda2_unset_window(table_group, num);
2445
2446         return ret;
2447 }
2448
2449 static long pnv_pci_ioda2_npu_unset_window(
2450                 struct iommu_table_group *table_group,
2451                 int num)
2452 {
2453         long ret = pnv_pci_ioda2_unset_window(table_group, num);
2454
2455         if (ret)
2456                 return ret;
2457
2458         return pnv_npu_unset_window(gpe_table_group_to_npe(table_group), num);
2459 }
2460
2461 static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group)
2462 {
2463         /*
2464          * Detach NPU first as pnv_ioda2_take_ownership() will destroy
2465          * the iommu_table if 32bit DMA is enabled.
2466          */
2467         pnv_npu_take_ownership(gpe_table_group_to_npe(table_group));
2468         pnv_ioda2_take_ownership(table_group);
2469 }
2470
2471 static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = {
2472         .get_table_size = pnv_pci_ioda2_get_table_size,
2473         .create_table = pnv_pci_ioda2_create_table,
2474         .set_window = pnv_pci_ioda2_npu_set_window,
2475         .unset_window = pnv_pci_ioda2_npu_unset_window,
2476         .take_ownership = pnv_ioda2_npu_take_ownership,
2477         .release_ownership = pnv_ioda2_release_ownership,
2478 };
2479
2480 static void pnv_pci_ioda_setup_iommu_api(void)
2481 {
2482         struct pci_controller *hose, *tmp;
2483         struct pnv_phb *phb;
2484         struct pnv_ioda_pe *pe, *gpe;
2485
2486         /*
2487          * Now we have all PHBs discovered, time to add NPU devices to
2488          * the corresponding IOMMU groups.
2489          */
2490         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
2491                 phb = hose->private_data;
2492
2493                 if (phb->type != PNV_PHB_NPU)
2494                         continue;
2495
2496                 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2497                         gpe = pnv_pci_npu_setup_iommu(pe);
2498                         if (gpe)
2499                                 gpe->table_group.ops = &pnv_pci_ioda2_npu_ops;
2500                 }
2501         }
2502 }
2503 #else /* !CONFIG_IOMMU_API */
2504 static void pnv_pci_ioda_setup_iommu_api(void) { };
2505 #endif
2506
2507 static void pnv_pci_ioda_setup_opal_tce_kill(struct pnv_phb *phb)
2508 {
2509         const __be64 *swinvp;
2510
2511         /* OPAL variant of PHB3 invalidated TCEs */
2512         swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL);
2513         if (!swinvp)
2514                 return;
2515
2516         phb->ioda.tce_inval_reg_phys = be64_to_cpup(swinvp);
2517         phb->ioda.tce_inval_reg = ioremap(phb->ioda.tce_inval_reg_phys, 8);
2518 }
2519
2520 static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift,
2521                 unsigned levels, unsigned long limit,
2522                 unsigned long *current_offset, unsigned long *total_allocated)
2523 {
2524         struct page *tce_mem = NULL;
2525         __be64 *addr, *tmp;
2526         unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT;
2527         unsigned long allocated = 1UL << (order + PAGE_SHIFT);
2528         unsigned entries = 1UL << (shift - 3);
2529         long i;
2530
2531         tce_mem = alloc_pages_node(nid, GFP_KERNEL, order);
2532         if (!tce_mem) {
2533                 pr_err("Failed to allocate a TCE memory, order=%d\n", order);
2534                 return NULL;
2535         }
2536         addr = page_address(tce_mem);
2537         memset(addr, 0, allocated);
2538         *total_allocated += allocated;
2539
2540         --levels;
2541         if (!levels) {
2542                 *current_offset += allocated;
2543                 return addr;
2544         }
2545
2546         for (i = 0; i < entries; ++i) {
2547                 tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift,
2548                                 levels, limit, current_offset, total_allocated);
2549                 if (!tmp)
2550                         break;
2551
2552                 addr[i] = cpu_to_be64(__pa(tmp) |
2553                                 TCE_PCI_READ | TCE_PCI_WRITE);
2554
2555                 if (*current_offset >= limit)
2556                         break;
2557         }
2558
2559         return addr;
2560 }
2561
2562 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2563                 unsigned long size, unsigned level);
2564
2565 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2566                 __u32 page_shift, __u64 window_size, __u32 levels,
2567                 struct iommu_table *tbl)
2568 {
2569         void *addr;
2570         unsigned long offset = 0, level_shift, total_allocated = 0;
2571         const unsigned window_shift = ilog2(window_size);
2572         unsigned entries_shift = window_shift - page_shift;
2573         unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT);
2574         const unsigned long tce_table_size = 1UL << table_shift;
2575
2576         if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS))
2577                 return -EINVAL;
2578
2579         if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size))
2580                 return -EINVAL;
2581
2582         /* Adjust direct table size from window_size and levels */
2583         entries_shift = (entries_shift + levels - 1) / levels;
2584         level_shift = entries_shift + 3;
2585         level_shift = max_t(unsigned, level_shift, PAGE_SHIFT);
2586
2587         /* Allocate TCE table */
2588         addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift,
2589                         levels, tce_table_size, &offset, &total_allocated);
2590
2591         /* addr==NULL means that the first level allocation failed */
2592         if (!addr)
2593                 return -ENOMEM;
2594
2595         /*
2596          * First level was allocated but some lower level failed as
2597          * we did not allocate as much as we wanted,
2598          * release partially allocated table.
2599          */
2600         if (offset < tce_table_size) {
2601                 pnv_pci_ioda2_table_do_free_pages(addr,
2602                                 1ULL << (level_shift - 3), levels - 1);
2603                 return -ENOMEM;
2604         }
2605
2606         /* Setup linux iommu table */
2607         pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset,
2608                         page_shift);
2609         tbl->it_level_size = 1ULL << (level_shift - 3);
2610         tbl->it_indirect_levels = levels - 1;
2611         tbl->it_allocated_size = total_allocated;
2612
2613         pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n",
2614                         window_size, tce_table_size, bus_offset);
2615
2616         return 0;
2617 }
2618
2619 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2620                 unsigned long size, unsigned level)
2621 {
2622         const unsigned long addr_ul = (unsigned long) addr &
2623                         ~(TCE_PCI_READ | TCE_PCI_WRITE);
2624
2625         if (level) {
2626                 long i;
2627                 u64 *tmp = (u64 *) addr_ul;
2628
2629                 for (i = 0; i < size; ++i) {
2630                         unsigned long hpa = be64_to_cpu(tmp[i]);
2631
2632                         if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE)))
2633                                 continue;
2634
2635                         pnv_pci_ioda2_table_do_free_pages(__va(hpa), size,
2636                                         level - 1);
2637                 }
2638         }
2639
2640         free_pages(addr_ul, get_order(size << 3));
2641 }
2642
2643 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl)
2644 {
2645         const unsigned long size = tbl->it_indirect_levels ?
2646                         tbl->it_level_size : tbl->it_size;
2647
2648         if (!tbl->it_size)
2649                 return;
2650
2651         pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size,
2652                         tbl->it_indirect_levels);
2653 }
2654
2655 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
2656                                        struct pnv_ioda_pe *pe)
2657 {
2658         int64_t rc;
2659
2660         /* TVE #1 is selected by PCI address bit 59 */
2661         pe->tce_bypass_base = 1ull << 59;
2662
2663         iommu_register_group(&pe->table_group, phb->hose->global_number,
2664                         pe->pe_number);
2665
2666         /* The PE will reserve all possible 32-bits space */
2667         pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
2668                 phb->ioda.m32_pci_base);
2669
2670         /* Setup linux iommu table */
2671         pe->table_group.tce32_start = 0;
2672         pe->table_group.tce32_size = phb->ioda.m32_pci_base;
2673         pe->table_group.max_dynamic_windows_supported =
2674                         IOMMU_TABLE_GROUP_MAX_TABLES;
2675         pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
2676         pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M;
2677 #ifdef CONFIG_IOMMU_API
2678         pe->table_group.ops = &pnv_pci_ioda2_ops;
2679 #endif
2680
2681         rc = pnv_pci_ioda2_setup_default_config(pe);
2682         if (rc)
2683                 return;
2684
2685         if (pe->flags & PNV_IODA_PE_DEV)
2686                 iommu_add_device(&pe->pdev->dev);
2687         else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2688                 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2689 }
2690
2691 static void pnv_ioda_setup_dma(struct pnv_phb *phb)
2692 {
2693         struct pci_controller *hose = phb->hose;
2694         struct pnv_ioda_pe *pe;
2695         unsigned int weight;
2696
2697         /* If we have more PE# than segments available, hand out one
2698          * per PE until we run out and let the rest fail. If not,
2699          * then we assign at least one segment per PE, plus more based
2700          * on the amount of devices under that PE
2701          */
2702         pr_info("PCI: Domain %04x has %d available 32-bit DMA segments\n",
2703                 hose->global_number, phb->ioda.dma32_count);
2704
2705         /* Walk our PE list and configure their DMA segments */
2706         list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2707                 weight = pnv_pci_ioda_pe_dma_weight(pe);
2708                 if (!weight)
2709                         continue;
2710
2711                 /*
2712                  * For IODA2 compliant PHB3, we needn't care about the weight.
2713                  * The all available 32-bits DMA space will be assigned to
2714                  * the specific PE.
2715                  */
2716                 if (phb->type == PNV_PHB_IODA1) {
2717                         pnv_pci_ioda1_setup_dma_pe(phb, pe);
2718                 } else if (phb->type == PNV_PHB_IODA2) {
2719                         pe_info(pe, "Assign DMA32 space\n");
2720                         pnv_pci_ioda2_setup_dma_pe(phb, pe);
2721                 } else if (phb->type == PNV_PHB_NPU) {
2722                         /*
2723                          * We initialise the DMA space for an NPU PHB
2724                          * after setup of the PHB is complete as we
2725                          * point the NPU TVT to the the same location
2726                          * as the PHB3 TVT.
2727                          */
2728                 }
2729         }
2730 }
2731
2732 #ifdef CONFIG_PCI_MSI
2733 static void pnv_ioda2_msi_eoi(struct irq_data *d)
2734 {
2735         unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
2736         struct irq_chip *chip = irq_data_get_irq_chip(d);
2737         struct pnv_phb *phb = container_of(chip, struct pnv_phb,
2738                                            ioda.irq_chip);
2739         int64_t rc;
2740
2741         rc = opal_pci_msi_eoi(phb->opal_id, hw_irq);
2742         WARN_ON_ONCE(rc);
2743
2744         icp_native_eoi(d);
2745 }
2746
2747
2748 static void set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
2749 {
2750         struct irq_data *idata;
2751         struct irq_chip *ichip;
2752
2753         if (phb->type != PNV_PHB_IODA2)
2754                 return;
2755
2756         if (!phb->ioda.irq_chip_init) {
2757                 /*
2758                  * First time we setup an MSI IRQ, we need to setup the
2759                  * corresponding IRQ chip to route correctly.
2760                  */
2761                 idata = irq_get_irq_data(virq);
2762                 ichip = irq_data_get_irq_chip(idata);
2763                 phb->ioda.irq_chip_init = 1;
2764                 phb->ioda.irq_chip = *ichip;
2765                 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
2766         }
2767         irq_set_chip(virq, &phb->ioda.irq_chip);
2768 }
2769
2770 #ifdef CONFIG_CXL_BASE
2771
2772 struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev)
2773 {
2774         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2775
2776         return of_node_get(hose->dn);
2777 }
2778 EXPORT_SYMBOL(pnv_pci_get_phb_node);
2779
2780 int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode)
2781 {
2782         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2783         struct pnv_phb *phb = hose->private_data;
2784         struct pnv_ioda_pe *pe;
2785         int rc;
2786
2787         pe = pnv_ioda_get_pe(dev);
2788         if (!pe)
2789                 return -ENODEV;
2790
2791         pe_info(pe, "Switching PHB to CXL\n");
2792
2793         rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number);
2794         if (rc == OPAL_UNSUPPORTED)
2795                 dev_err(&dev->dev, "Required cxl mode not supported by firmware - update skiboot\n");
2796         else if (rc)
2797                 dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc);
2798
2799         return rc;
2800 }
2801 EXPORT_SYMBOL(pnv_phb_to_cxl_mode);
2802
2803 /* Find PHB for cxl dev and allocate MSI hwirqs?
2804  * Returns the absolute hardware IRQ number
2805  */
2806 int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num)
2807 {
2808         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2809         struct pnv_phb *phb = hose->private_data;
2810         int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num);
2811
2812         if (hwirq < 0) {
2813                 dev_warn(&dev->dev, "Failed to find a free MSI\n");
2814                 return -ENOSPC;
2815         }
2816
2817         return phb->msi_base + hwirq;
2818 }
2819 EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs);
2820
2821 void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num)
2822 {
2823         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2824         struct pnv_phb *phb = hose->private_data;
2825
2826         msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num);
2827 }
2828 EXPORT_SYMBOL(pnv_cxl_release_hwirqs);
2829
2830 void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs,
2831                                   struct pci_dev *dev)
2832 {
2833         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2834         struct pnv_phb *phb = hose->private_data;
2835         int i, hwirq;
2836
2837         for (i = 1; i < CXL_IRQ_RANGES; i++) {
2838                 if (!irqs->range[i])
2839                         continue;
2840                 pr_devel("cxl release irq range 0x%x: offset: 0x%lx  limit: %ld\n",
2841                          i, irqs->offset[i],
2842                          irqs->range[i]);
2843                 hwirq = irqs->offset[i] - phb->msi_base;
2844                 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq,
2845                                        irqs->range[i]);
2846         }
2847 }
2848 EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges);
2849
2850 int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs,
2851                                struct pci_dev *dev, int num)
2852 {
2853         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2854         struct pnv_phb *phb = hose->private_data;
2855         int i, hwirq, try;
2856
2857         memset(irqs, 0, sizeof(struct cxl_irq_ranges));
2858
2859         /* 0 is reserved for the multiplexed PSL DSI interrupt */
2860         for (i = 1; i < CXL_IRQ_RANGES && num; i++) {
2861                 try = num;
2862                 while (try) {
2863                         hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try);
2864                         if (hwirq >= 0)
2865                                 break;
2866                         try /= 2;
2867                 }
2868                 if (!try)
2869                         goto fail;
2870
2871                 irqs->offset[i] = phb->msi_base + hwirq;
2872                 irqs->range[i] = try;
2873                 pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx  limit: %li\n",
2874                          i, irqs->offset[i], irqs->range[i]);
2875                 num -= try;
2876         }
2877         if (num)
2878                 goto fail;
2879
2880         return 0;
2881 fail:
2882         pnv_cxl_release_hwirq_ranges(irqs, dev);
2883         return -ENOSPC;
2884 }
2885 EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges);
2886
2887 int pnv_cxl_get_irq_count(struct pci_dev *dev)
2888 {
2889         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2890         struct pnv_phb *phb = hose->private_data;
2891
2892         return phb->msi_bmp.irq_count;
2893 }
2894 EXPORT_SYMBOL(pnv_cxl_get_irq_count);
2895
2896 int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq,
2897                            unsigned int virq)
2898 {
2899         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2900         struct pnv_phb *phb = hose->private_data;
2901         unsigned int xive_num = hwirq - phb->msi_base;
2902         struct pnv_ioda_pe *pe;
2903         int rc;
2904
2905         if (!(pe = pnv_ioda_get_pe(dev)))
2906                 return -ENODEV;
2907
2908         /* Assign XIVE to PE */
2909         rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2910         if (rc) {
2911                 pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x "
2912                         "hwirq 0x%x XIVE 0x%x PE\n",
2913                         pci_name(dev), rc, phb->msi_base, hwirq, xive_num);
2914                 return -EIO;
2915         }
2916         set_msi_irq_chip(phb, virq);
2917
2918         return 0;
2919 }
2920 EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup);
2921 #endif
2922
2923 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
2924                                   unsigned int hwirq, unsigned int virq,
2925                                   unsigned int is_64, struct msi_msg *msg)
2926 {
2927         struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
2928         unsigned int xive_num = hwirq - phb->msi_base;
2929         __be32 data;
2930         int rc;
2931
2932         /* No PE assigned ? bail out ... no MSI for you ! */
2933         if (pe == NULL)
2934                 return -ENXIO;
2935
2936         /* Check if we have an MVE */
2937         if (pe->mve_number < 0)
2938                 return -ENXIO;
2939
2940         /* Force 32-bit MSI on some broken devices */
2941         if (dev->no_64bit_msi)
2942                 is_64 = 0;
2943
2944         /* Assign XIVE to PE */
2945         rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2946         if (rc) {
2947                 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2948                         pci_name(dev), rc, xive_num);
2949                 return -EIO;
2950         }
2951
2952         if (is_64) {
2953                 __be64 addr64;
2954
2955                 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
2956                                      &addr64, &data);
2957                 if (rc) {
2958                         pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2959                                 pci_name(dev), rc);
2960                         return -EIO;
2961                 }
2962                 msg->address_hi = be64_to_cpu(addr64) >> 32;
2963                 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
2964         } else {
2965                 __be32 addr32;
2966
2967                 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
2968                                      &addr32, &data);
2969                 if (rc) {
2970                         pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2971                                 pci_name(dev), rc);
2972                         return -EIO;
2973                 }
2974                 msg->address_hi = 0;
2975                 msg->address_lo = be32_to_cpu(addr32);
2976         }
2977         msg->data = be32_to_cpu(data);
2978
2979         set_msi_irq_chip(phb, virq);
2980
2981         pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
2982                  " address=%x_%08x data=%x PE# %d\n",
2983                  pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
2984                  msg->address_hi, msg->address_lo, data, pe->pe_number);
2985
2986         return 0;
2987 }
2988
2989 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
2990 {
2991         unsigned int count;
2992         const __be32 *prop = of_get_property(phb->hose->dn,
2993                                              "ibm,opal-msi-ranges", NULL);
2994         if (!prop) {
2995                 /* BML Fallback */
2996                 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
2997         }
2998         if (!prop)
2999                 return;
3000
3001         phb->msi_base = be32_to_cpup(prop);
3002         count = be32_to_cpup(prop + 1);
3003         if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
3004                 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
3005                        phb->hose->global_number);
3006                 return;
3007         }
3008
3009         phb->msi_setup = pnv_pci_ioda_msi_setup;
3010         phb->msi32_support = 1;
3011         pr_info("  Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
3012                 count, phb->msi_base);
3013 }
3014 #else
3015 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
3016 #endif /* CONFIG_PCI_MSI */
3017
3018 #ifdef CONFIG_PCI_IOV
3019 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
3020 {
3021         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3022         struct pnv_phb *phb = hose->private_data;
3023         const resource_size_t gate = phb->ioda.m64_segsize >> 2;
3024         struct resource *res;
3025         int i;
3026         resource_size_t size, total_vf_bar_sz;
3027         struct pci_dn *pdn;
3028         int mul, total_vfs;
3029
3030         if (!pdev->is_physfn || pdev->is_added)
3031                 return;
3032
3033         pdn = pci_get_pdn(pdev);
3034         pdn->vfs_expanded = 0;
3035         pdn->m64_single_mode = false;
3036
3037         total_vfs = pci_sriov_get_totalvfs(pdev);
3038         mul = phb->ioda.total_pe_num;
3039         total_vf_bar_sz = 0;
3040
3041         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
3042                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
3043                 if (!res->flags || res->parent)
3044                         continue;
3045                 if (!pnv_pci_is_mem_pref_64(res->flags)) {
3046                         dev_warn(&pdev->dev, "Don't support SR-IOV with"
3047                                         " non M64 VF BAR%d: %pR. \n",
3048                                  i, res);
3049                         goto truncate_iov;
3050                 }
3051
3052                 total_vf_bar_sz += pci_iov_resource_size(pdev,
3053                                 i + PCI_IOV_RESOURCES);
3054
3055                 /*
3056                  * If bigger than quarter of M64 segment size, just round up
3057                  * power of two.
3058                  *
3059                  * Generally, one M64 BAR maps one IOV BAR. To avoid conflict
3060                  * with other devices, IOV BAR size is expanded to be
3061                  * (total_pe * VF_BAR_size).  When VF_BAR_size is half of M64
3062                  * segment size , the expanded size would equal to half of the
3063                  * whole M64 space size, which will exhaust the M64 Space and
3064                  * limit the system flexibility.  This is a design decision to
3065                  * set the boundary to quarter of the M64 segment size.
3066                  */
3067                 if (total_vf_bar_sz > gate) {
3068                         mul = roundup_pow_of_two(total_vfs);
3069                         dev_info(&pdev->dev,
3070                                 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n",
3071                                 total_vf_bar_sz, gate, mul);
3072                         pdn->m64_single_mode = true;
3073                         break;
3074                 }
3075         }
3076
3077         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
3078                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
3079                 if (!res->flags || res->parent)
3080                         continue;
3081
3082                 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
3083                 /*
3084                  * On PHB3, the minimum size alignment of M64 BAR in single
3085                  * mode is 32MB.
3086                  */
3087                 if (pdn->m64_single_mode && (size < SZ_32M))
3088                         goto truncate_iov;
3089                 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res);
3090                 res->end = res->start + size * mul - 1;
3091                 dev_dbg(&pdev->dev, "                       %pR\n", res);
3092                 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
3093                          i, res, mul);
3094         }
3095         pdn->vfs_expanded = mul;
3096
3097         return;
3098
3099 truncate_iov:
3100         /* To save MMIO space, IOV BAR is truncated. */
3101         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
3102                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
3103                 res->flags = 0;
3104                 res->end = res->start - 1;
3105         }
3106 }
3107 #endif /* CONFIG_PCI_IOV */
3108
3109 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe,
3110                                   struct resource *res)
3111 {
3112         struct pnv_phb *phb = pe->phb;
3113         struct pci_bus_region region;
3114         int index;
3115         int64_t rc;
3116
3117         if (!res || !res->flags || res->start > res->end)
3118                 return;
3119
3120         if (res->flags & IORESOURCE_IO) {
3121                 region.start = res->start - phb->ioda.io_pci_base;
3122                 region.end   = res->end - phb->ioda.io_pci_base;
3123                 index = region.start / phb->ioda.io_segsize;
3124
3125                 while (index < phb->ioda.total_pe_num &&
3126                        region.start <= region.end) {
3127                         phb->ioda.io_segmap[index] = pe->pe_number;
3128                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3129                                 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
3130                         if (rc != OPAL_SUCCESS) {
3131                                 pr_err("%s: Error %lld mapping IO segment#%d to PE#%d\n",
3132                                        __func__, rc, index, pe->pe_number);
3133                                 break;
3134                         }
3135
3136                         region.start += phb->ioda.io_segsize;
3137                         index++;
3138                 }
3139         } else if ((res->flags & IORESOURCE_MEM) &&
3140                    !pnv_pci_is_mem_pref_64(res->flags)) {
3141                 region.start = res->start -
3142                                phb->hose->mem_offset[0] -
3143                                phb->ioda.m32_pci_base;
3144                 region.end   = res->end -
3145                                phb->hose->mem_offset[0] -
3146                                phb->ioda.m32_pci_base;
3147                 index = region.start / phb->ioda.m32_segsize;
3148
3149                 while (index < phb->ioda.total_pe_num &&
3150                        region.start <= region.end) {
3151                         phb->ioda.m32_segmap[index] = pe->pe_number;
3152                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3153                                 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
3154                         if (rc != OPAL_SUCCESS) {
3155                                 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%d",
3156                                        __func__, rc, index, pe->pe_number);
3157                                 break;
3158                         }
3159
3160                         region.start += phb->ioda.m32_segsize;
3161                         index++;
3162                 }
3163         }
3164 }
3165
3166 /*
3167  * This function is supposed to be called on basis of PE from top
3168  * to bottom style. So the the I/O or MMIO segment assigned to
3169  * parent PE could be overrided by its child PEs if necessary.
3170  */
3171 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe)
3172 {
3173         struct pci_dev *pdev;
3174         int i;
3175
3176         /*
3177          * NOTE: We only care PCI bus based PE for now. For PCI
3178          * device based PE, for example SRIOV sensitive VF should
3179          * be figured out later.
3180          */
3181         BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
3182
3183         list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
3184                 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
3185                         pnv_ioda_setup_pe_res(pe, &pdev->resource[i]);
3186
3187                 /*
3188                  * If the PE contains all subordinate PCI buses, the
3189                  * windows of the child bridges should be mapped to
3190                  * the PE as well.
3191                  */
3192                 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev))
3193                         continue;
3194                 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
3195                         pnv_ioda_setup_pe_res(pe,
3196                                 &pdev->resource[PCI_BRIDGE_RESOURCES + i]);
3197         }
3198 }
3199
3200 static void pnv_pci_ioda_setup_seg(void)
3201 {
3202         struct pci_controller *tmp, *hose;
3203         struct pnv_phb *phb;
3204         struct pnv_ioda_pe *pe;
3205
3206         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3207                 phb = hose->private_data;
3208
3209                 /* NPU PHB does not support IO or MMIO segmentation */
3210                 if (phb->type == PNV_PHB_NPU)
3211                         continue;
3212
3213                 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
3214                         pnv_ioda_setup_pe_seg(pe);
3215                 }
3216         }
3217 }
3218
3219 static void pnv_pci_ioda_setup_DMA(void)
3220 {
3221         struct pci_controller *hose, *tmp;
3222         struct pnv_phb *phb;
3223
3224         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3225                 pnv_ioda_setup_dma(hose->private_data);
3226
3227                 /* Mark the PHB initialization done */
3228                 phb = hose->private_data;
3229                 phb->initialized = 1;
3230         }
3231
3232         pnv_pci_ioda_setup_iommu_api();
3233 }
3234
3235 static void pnv_pci_ioda_create_dbgfs(void)
3236 {
3237 #ifdef CONFIG_DEBUG_FS
3238         struct pci_controller *hose, *tmp;
3239         struct pnv_phb *phb;
3240         char name[16];
3241
3242         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3243                 phb = hose->private_data;
3244
3245                 sprintf(name, "PCI%04x", hose->global_number);
3246                 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
3247                 if (!phb->dbgfs)
3248                         pr_warning("%s: Error on creating debugfs on PHB#%x\n",
3249                                 __func__, hose->global_number);
3250         }
3251 #endif /* CONFIG_DEBUG_FS */
3252 }
3253
3254 static void pnv_pci_ioda_fixup(void)
3255 {
3256         pnv_pci_ioda_setup_PEs();
3257         pnv_pci_ioda_setup_seg();
3258         pnv_pci_ioda_setup_DMA();
3259
3260         pnv_pci_ioda_create_dbgfs();
3261
3262 #ifdef CONFIG_EEH
3263         eeh_init();
3264         eeh_addr_cache_build();
3265 #endif
3266 }
3267
3268 /*
3269  * Returns the alignment for I/O or memory windows for P2P
3270  * bridges. That actually depends on how PEs are segmented.
3271  * For now, we return I/O or M32 segment size for PE sensitive
3272  * P2P bridges. Otherwise, the default values (4KiB for I/O,
3273  * 1MiB for memory) will be returned.
3274  *
3275  * The current PCI bus might be put into one PE, which was
3276  * create against the parent PCI bridge. For that case, we
3277  * needn't enlarge the alignment so that we can save some
3278  * resources.
3279  */
3280 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
3281                                                 unsigned long type)
3282 {
3283         struct pci_dev *bridge;
3284         struct pci_controller *hose = pci_bus_to_host(bus);
3285         struct pnv_phb *phb = hose->private_data;
3286         int num_pci_bridges = 0;
3287
3288         bridge = bus->self;
3289         while (bridge) {
3290                 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
3291                         num_pci_bridges++;
3292                         if (num_pci_bridges >= 2)
3293                                 return 1;
3294                 }
3295
3296                 bridge = bridge->bus->self;
3297         }
3298
3299         /* We fail back to M32 if M64 isn't supported */
3300         if (phb->ioda.m64_segsize &&
3301             pnv_pci_is_mem_pref_64(type))
3302                 return phb->ioda.m64_segsize;
3303         if (type & IORESOURCE_MEM)
3304                 return phb->ioda.m32_segsize;
3305
3306         return phb->ioda.io_segsize;
3307 }
3308
3309 #ifdef CONFIG_PCI_IOV
3310 static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
3311                                                       int resno)
3312 {
3313         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3314         struct pnv_phb *phb = hose->private_data;
3315         struct pci_dn *pdn = pci_get_pdn(pdev);
3316         resource_size_t align;
3317
3318         /*
3319          * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the
3320          * SR-IOV. While from hardware perspective, the range mapped by M64
3321          * BAR should be size aligned.
3322          *
3323          * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra
3324          * powernv-specific hardware restriction is gone. But if just use the
3325          * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with
3326          * in one segment of M64 #15, which introduces the PE conflict between
3327          * PF and VF. Based on this, the minimum alignment of an IOV BAR is
3328          * m64_segsize.
3329          *
3330          * This function returns the total IOV BAR size if M64 BAR is in
3331          * Shared PE mode or just VF BAR size if not.
3332          * If the M64 BAR is in Single PE mode, return the VF BAR size or
3333          * M64 segment size if IOV BAR size is less.
3334          */
3335         align = pci_iov_resource_size(pdev, resno);
3336         if (!pdn->vfs_expanded)
3337                 return align;
3338         if (pdn->m64_single_mode)
3339                 return max(align, (resource_size_t)phb->ioda.m64_segsize);
3340
3341         return pdn->vfs_expanded * align;
3342 }
3343 #endif /* CONFIG_PCI_IOV */
3344
3345 /* Prevent enabling devices for which we couldn't properly
3346  * assign a PE
3347  */
3348 static bool pnv_pci_enable_device_hook(struct pci_dev *dev)
3349 {
3350         struct pci_controller *hose = pci_bus_to_host(dev->bus);
3351         struct pnv_phb *phb = hose->private_data;
3352         struct pci_dn *pdn;
3353
3354         /* The function is probably called while the PEs have
3355          * not be created yet. For example, resource reassignment
3356          * during PCI probe period. We just skip the check if
3357          * PEs isn't ready.
3358          */
3359         if (!phb->initialized)
3360                 return true;
3361
3362         pdn = pci_get_pdn(dev);
3363         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3364                 return false;
3365
3366         return true;
3367 }
3368
3369 static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
3370 {
3371         struct pnv_phb *phb = hose->private_data;
3372
3373         opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
3374                        OPAL_ASSERT_RESET);
3375 }
3376
3377 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
3378         .dma_dev_setup          = pnv_pci_dma_dev_setup,
3379         .dma_bus_setup          = pnv_pci_dma_bus_setup,
3380 #ifdef CONFIG_PCI_MSI
3381         .setup_msi_irqs         = pnv_setup_msi_irqs,
3382         .teardown_msi_irqs      = pnv_teardown_msi_irqs,
3383 #endif
3384         .enable_device_hook     = pnv_pci_enable_device_hook,
3385         .window_alignment       = pnv_pci_window_alignment,
3386         .reset_secondary_bus    = pnv_pci_reset_secondary_bus,
3387         .dma_set_mask           = pnv_pci_ioda_dma_set_mask,
3388         .dma_get_required_mask  = pnv_pci_ioda_dma_get_required_mask,
3389         .shutdown               = pnv_pci_ioda_shutdown,
3390 };
3391
3392 static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask)
3393 {
3394         dev_err_once(&npdev->dev,
3395                         "%s operation unsupported for NVLink devices\n",
3396                         __func__);
3397         return -EPERM;
3398 }
3399
3400 static const struct pci_controller_ops pnv_npu_ioda_controller_ops = {
3401         .dma_dev_setup          = pnv_pci_dma_dev_setup,
3402 #ifdef CONFIG_PCI_MSI
3403         .setup_msi_irqs         = pnv_setup_msi_irqs,
3404         .teardown_msi_irqs      = pnv_teardown_msi_irqs,
3405 #endif
3406         .enable_device_hook     = pnv_pci_enable_device_hook,
3407         .window_alignment       = pnv_pci_window_alignment,
3408         .reset_secondary_bus    = pnv_pci_reset_secondary_bus,
3409         .dma_set_mask           = pnv_npu_dma_set_mask,
3410         .shutdown               = pnv_pci_ioda_shutdown,
3411 };
3412
3413 static void __init pnv_pci_init_ioda_phb(struct device_node *np,
3414                                          u64 hub_id, int ioda_type)
3415 {
3416         struct pci_controller *hose;
3417         struct pnv_phb *phb;
3418         unsigned long size, m64map_off, m32map_off, pemap_off;
3419         unsigned long iomap_off = 0, dma32map_off = 0;
3420         const __be64 *prop64;
3421         const __be32 *prop32;
3422         int len;
3423         unsigned int segno;
3424         u64 phb_id;
3425         void *aux;
3426         long rc;
3427
3428         pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name);
3429
3430         prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
3431         if (!prop64) {
3432                 pr_err("  Missing \"ibm,opal-phbid\" property !\n");
3433                 return;
3434         }
3435         phb_id = be64_to_cpup(prop64);
3436         pr_debug("  PHB-ID  : 0x%016llx\n", phb_id);
3437
3438         phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0);
3439
3440         /* Allocate PCI controller */
3441         phb->hose = hose = pcibios_alloc_controller(np);
3442         if (!phb->hose) {
3443                 pr_err("  Can't allocate PCI controller for %s\n",
3444                        np->full_name);
3445                 memblock_free(__pa(phb), sizeof(struct pnv_phb));
3446                 return;
3447         }
3448
3449         spin_lock_init(&phb->lock);
3450         prop32 = of_get_property(np, "bus-range", &len);
3451         if (prop32 && len == 8) {
3452                 hose->first_busno = be32_to_cpu(prop32[0]);
3453                 hose->last_busno = be32_to_cpu(prop32[1]);
3454         } else {
3455                 pr_warn("  Broken <bus-range> on %s\n", np->full_name);
3456                 hose->first_busno = 0;
3457                 hose->last_busno = 0xff;
3458         }
3459         hose->private_data = phb;
3460         phb->hub_id = hub_id;
3461         phb->opal_id = phb_id;
3462         phb->type = ioda_type;
3463         mutex_init(&phb->ioda.pe_alloc_mutex);
3464
3465         /* Detect specific models for error handling */
3466         if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
3467                 phb->model = PNV_PHB_MODEL_P7IOC;
3468         else if (of_device_is_compatible(np, "ibm,power8-pciex"))
3469                 phb->model = PNV_PHB_MODEL_PHB3;
3470         else if (of_device_is_compatible(np, "ibm,power8-npu-pciex"))
3471                 phb->model = PNV_PHB_MODEL_NPU;
3472         else
3473                 phb->model = PNV_PHB_MODEL_UNKNOWN;
3474
3475         /* Parse 32-bit and IO ranges (if any) */
3476         pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
3477
3478         /* Get registers */
3479         phb->regs = of_iomap(np, 0);
3480         if (phb->regs == NULL)
3481                 pr_err("  Failed to map registers !\n");
3482
3483         /* Initialize TCE kill register */
3484         pnv_pci_ioda_setup_opal_tce_kill(phb);
3485
3486         /* Initialize more IODA stuff */
3487         phb->ioda.total_pe_num = 1;
3488         prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
3489         if (prop32)
3490                 phb->ioda.total_pe_num = be32_to_cpup(prop32);
3491         prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
3492         if (prop32)
3493                 phb->ioda.reserved_pe_idx = be32_to_cpup(prop32);
3494
3495         /* Invalidate RID to PE# mapping */
3496         for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++)
3497                 phb->ioda.pe_rmap[segno] = IODA_INVALID_PE;
3498
3499         /* Parse 64-bit MMIO range */
3500         pnv_ioda_parse_m64_window(phb);
3501
3502         phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
3503         /* FW Has already off top 64k of M32 space (MSI space) */
3504         phb->ioda.m32_size += 0x10000;
3505
3506         phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num;
3507         phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
3508         phb->ioda.io_size = hose->pci_io_size;
3509         phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num;
3510         phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
3511
3512         /* Calculate how many 32-bit TCE segments we have */
3513         phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3514                                 PNV_IODA1_DMA32_SEGSIZE;
3515
3516         /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
3517         size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8,
3518                         sizeof(unsigned long));
3519         m64map_off = size;
3520         size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]);
3521         m32map_off = size;
3522         size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]);
3523         if (phb->type == PNV_PHB_IODA1) {
3524                 iomap_off = size;
3525                 size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]);
3526                 dma32map_off = size;
3527                 size += phb->ioda.dma32_count *
3528                         sizeof(phb->ioda.dma32_segmap[0]);
3529         }
3530         pemap_off = size;
3531         size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe);
3532         aux = memblock_virt_alloc(size, 0);
3533         phb->ioda.pe_alloc = aux;
3534         phb->ioda.m64_segmap = aux + m64map_off;
3535         phb->ioda.m32_segmap = aux + m32map_off;
3536         for (segno = 0; segno < phb->ioda.total_pe_num; segno++) {
3537                 phb->ioda.m64_segmap[segno] = IODA_INVALID_PE;
3538                 phb->ioda.m32_segmap[segno] = IODA_INVALID_PE;
3539         }
3540         if (phb->type == PNV_PHB_IODA1) {
3541                 phb->ioda.io_segmap = aux + iomap_off;
3542                 for (segno = 0; segno < phb->ioda.total_pe_num; segno++)
3543                         phb->ioda.io_segmap[segno] = IODA_INVALID_PE;
3544
3545                 phb->ioda.dma32_segmap = aux + dma32map_off;
3546                 for (segno = 0; segno < phb->ioda.dma32_count; segno++)
3547                         phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE;
3548         }
3549         phb->ioda.pe_array = aux + pemap_off;
3550         set_bit(phb->ioda.reserved_pe_idx, phb->ioda.pe_alloc);
3551
3552         INIT_LIST_HEAD(&phb->ioda.pe_list);
3553         mutex_init(&phb->ioda.pe_list_mutex);
3554
3555         /* Calculate how many 32-bit TCE segments we have */
3556         phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3557                                 PNV_IODA1_DMA32_SEGSIZE;
3558
3559 #if 0 /* We should really do that ... */
3560         rc = opal_pci_set_phb_mem_window(opal->phb_id,
3561                                          window_type,
3562                                          window_num,
3563                                          starting_real_address,
3564                                          starting_pci_address,
3565                                          segment_size);
3566 #endif
3567
3568         pr_info("  %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
3569                 phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx,
3570                 phb->ioda.m32_size, phb->ioda.m32_segsize);
3571         if (phb->ioda.m64_size)
3572                 pr_info("                 M64: 0x%lx [segment=0x%lx]\n",
3573                         phb->ioda.m64_size, phb->ioda.m64_segsize);
3574         if (phb->ioda.io_size)
3575                 pr_info("                  IO: 0x%x [segment=0x%x]\n",
3576                         phb->ioda.io_size, phb->ioda.io_segsize);
3577
3578
3579         phb->hose->ops = &pnv_pci_ops;
3580         phb->get_pe_state = pnv_ioda_get_pe_state;
3581         phb->freeze_pe = pnv_ioda_freeze_pe;
3582         phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
3583
3584         /* Setup MSI support */
3585         pnv_pci_init_ioda_msis(phb);
3586
3587         /*
3588          * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
3589          * to let the PCI core do resource assignment. It's supposed
3590          * that the PCI core will do correct I/O and MMIO alignment
3591          * for the P2P bridge bars so that each PCI bus (excluding
3592          * the child P2P bridges) can form individual PE.
3593          */
3594         ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
3595
3596         if (phb->type == PNV_PHB_NPU) {
3597                 hose->controller_ops = pnv_npu_ioda_controller_ops;
3598         } else {
3599                 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
3600                 hose->controller_ops = pnv_pci_ioda_controller_ops;
3601         }
3602
3603 #ifdef CONFIG_PCI_IOV
3604         ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources;
3605         ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
3606 #endif
3607
3608         pci_add_flags(PCI_REASSIGN_ALL_RSRC);
3609
3610         /* Reset IODA tables to a clean state */
3611         rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
3612         if (rc)
3613                 pr_warning("  OPAL Error %ld performing IODA table reset !\n", rc);
3614
3615         /* If we're running in kdump kerenl, the previous kerenl never
3616          * shutdown PCI devices correctly. We already got IODA table
3617          * cleaned out. So we have to issue PHB reset to stop all PCI
3618          * transactions from previous kerenl.
3619          */
3620         if (is_kdump_kernel()) {
3621                 pr_info("  Issue PHB reset ...\n");
3622                 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
3623                 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
3624         }
3625
3626         /* Remove M64 resource if we can't configure it successfully */
3627         if (!phb->init_m64 || phb->init_m64(phb))
3628                 hose->mem_resources[1].flags = 0;
3629 }
3630
3631 void __init pnv_pci_init_ioda2_phb(struct device_node *np)
3632 {
3633         pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
3634 }
3635
3636 void __init pnv_pci_init_npu_phb(struct device_node *np)
3637 {
3638         pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU);
3639 }
3640
3641 void __init pnv_pci_init_ioda_hub(struct device_node *np)
3642 {
3643         struct device_node *phbn;
3644         const __be64 *prop64;
3645         u64 hub_id;
3646
3647         pr_info("Probing IODA IO-Hub %s\n", np->full_name);
3648
3649         prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
3650         if (!prop64) {
3651                 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
3652                 return;
3653         }
3654         hub_id = be64_to_cpup(prop64);
3655         pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
3656
3657         /* Count child PHBs */
3658         for_each_child_of_node(np, phbn) {
3659                 /* Look for IODA1 PHBs */
3660                 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
3661                         pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);
3662         }
3663 }