2 * Support PCI/PCIe on PowerNV platforms
4 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
14 #include <linux/kernel.h>
15 #include <linux/pci.h>
16 #include <linux/crash_dump.h>
17 #include <linux/debugfs.h>
18 #include <linux/delay.h>
19 #include <linux/string.h>
20 #include <linux/init.h>
21 #include <linux/bootmem.h>
22 #include <linux/irq.h>
24 #include <linux/msi.h>
25 #include <linux/memblock.h>
26 #include <linux/iommu.h>
27 #include <linux/rculist.h>
28 #include <linux/sizes.h>
30 #include <asm/sections.h>
33 #include <asm/pci-bridge.h>
34 #include <asm/machdep.h>
35 #include <asm/msi_bitmap.h>
36 #include <asm/ppc-pci.h>
38 #include <asm/iommu.h>
41 #include <asm/debug.h>
42 #include <asm/firmware.h>
43 #include <asm/pnv-pci.h>
44 #include <asm/mmzone.h>
46 #include <misc/cxl-base.h>
51 #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */
52 #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */
53 #define PNV_IODA1_DMA32_SEGSIZE 0x10000000
55 #define POWERNV_IOMMU_DEFAULT_LEVELS 1
56 #define POWERNV_IOMMU_MAX_LEVELS 5
58 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl);
60 void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
72 if (pe->flags & PNV_IODA_PE_DEV)
73 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
74 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
75 sprintf(pfix, "%04x:%02x ",
76 pci_domain_nr(pe->pbus), pe->pbus->number);
78 else if (pe->flags & PNV_IODA_PE_VF)
79 sprintf(pfix, "%04x:%02x:%2x.%d",
80 pci_domain_nr(pe->parent_dev->bus),
81 (pe->rid & 0xff00) >> 8,
82 PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
83 #endif /* CONFIG_PCI_IOV*/
85 printk("%spci %s: [PE# %.3d] %pV",
86 level, pfix, pe->pe_number, &vaf);
91 static bool pnv_iommu_bypass_disabled __read_mostly;
93 static int __init iommu_setup(char *str)
99 if (!strncmp(str, "nobypass", 8)) {
100 pnv_iommu_bypass_disabled = true;
101 pr_info("PowerNV: IOMMU bypass window disabled.\n");
104 str += strcspn(str, ",");
111 early_param("iommu", iommu_setup);
113 static inline bool pnv_pci_is_mem_pref_64(unsigned long flags)
115 return ((flags & (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)) ==
116 (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH));
119 static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no)
121 phb->ioda.pe_array[pe_no].phb = phb;
122 phb->ioda.pe_array[pe_no].pe_number = pe_no;
124 return &phb->ioda.pe_array[pe_no];
127 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
129 if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) {
130 pr_warn("%s: Invalid PE %d on PHB#%x\n",
131 __func__, pe_no, phb->hose->global_number);
135 if (test_and_set_bit(pe_no, phb->ioda.pe_alloc))
136 pr_debug("%s: PE %d was reserved on PHB#%x\n",
137 __func__, pe_no, phb->hose->global_number);
139 pnv_ioda_init_pe(phb, pe_no);
142 static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb)
144 unsigned long pe = phb->ioda.total_pe_num - 1;
146 for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) {
147 if (!test_and_set_bit(pe, phb->ioda.pe_alloc))
148 return pnv_ioda_init_pe(phb, pe);
154 static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe)
156 struct pnv_phb *phb = pe->phb;
160 memset(pe, 0, sizeof(struct pnv_ioda_pe));
161 clear_bit(pe->pe_number, phb->ioda.pe_alloc);
164 /* The default M64 BAR is shared by all PEs */
165 static int pnv_ioda2_init_m64(struct pnv_phb *phb)
171 /* Configure the default M64 BAR */
172 rc = opal_pci_set_phb_mem_window(phb->opal_id,
173 OPAL_M64_WINDOW_TYPE,
174 phb->ioda.m64_bar_idx,
178 if (rc != OPAL_SUCCESS) {
179 desc = "configuring";
183 /* Enable the default M64 BAR */
184 rc = opal_pci_phb_mmio_enable(phb->opal_id,
185 OPAL_M64_WINDOW_TYPE,
186 phb->ioda.m64_bar_idx,
187 OPAL_ENABLE_M64_SPLIT);
188 if (rc != OPAL_SUCCESS) {
193 /* Mark the M64 BAR assigned */
194 set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc);
197 * Exclude the segments for reserved and root bus PE, which
198 * are first or last two PEs.
200 r = &phb->hose->mem_resources[1];
201 if (phb->ioda.reserved_pe_idx == 0)
202 r->start += (2 * phb->ioda.m64_segsize);
203 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
204 r->end -= (2 * phb->ioda.m64_segsize);
206 pr_warn(" Cannot strip M64 segment for reserved PE#%d\n",
207 phb->ioda.reserved_pe_idx);
212 pr_warn(" Failure %lld %s M64 BAR#%d\n",
213 rc, desc, phb->ioda.m64_bar_idx);
214 opal_pci_phb_mmio_enable(phb->opal_id,
215 OPAL_M64_WINDOW_TYPE,
216 phb->ioda.m64_bar_idx,
221 static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev,
222 unsigned long *pe_bitmap)
224 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
225 struct pnv_phb *phb = hose->private_data;
227 resource_size_t base, sgsz, start, end;
230 base = phb->ioda.m64_base;
231 sgsz = phb->ioda.m64_segsize;
232 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
233 r = &pdev->resource[i];
234 if (!r->parent || !pnv_pci_is_mem_pref_64(r->flags))
237 start = _ALIGN_DOWN(r->start - base, sgsz);
238 end = _ALIGN_UP(r->end - base, sgsz);
239 for (segno = start / sgsz; segno < end / sgsz; segno++) {
241 set_bit(segno, pe_bitmap);
243 pnv_ioda_reserve_pe(phb, segno);
248 static int pnv_ioda1_init_m64(struct pnv_phb *phb)
254 * There are 16 M64 BARs, each of which has 8 segments. So
255 * there are as many M64 segments as the maximum number of
258 for (index = 0; index < PNV_IODA1_M64_NUM; index++) {
259 unsigned long base, segsz = phb->ioda.m64_segsize;
262 base = phb->ioda.m64_base +
263 index * PNV_IODA1_M64_SEGS * segsz;
264 rc = opal_pci_set_phb_mem_window(phb->opal_id,
265 OPAL_M64_WINDOW_TYPE, index, base, 0,
266 PNV_IODA1_M64_SEGS * segsz);
267 if (rc != OPAL_SUCCESS) {
268 pr_warn(" Error %lld setting M64 PHB#%d-BAR#%d\n",
269 rc, phb->hose->global_number, index);
273 rc = opal_pci_phb_mmio_enable(phb->opal_id,
274 OPAL_M64_WINDOW_TYPE, index,
275 OPAL_ENABLE_M64_SPLIT);
276 if (rc != OPAL_SUCCESS) {
277 pr_warn(" Error %lld enabling M64 PHB#%d-BAR#%d\n",
278 rc, phb->hose->global_number, index);
284 * Exclude the segments for reserved and root bus PE, which
285 * are first or last two PEs.
287 r = &phb->hose->mem_resources[1];
288 if (phb->ioda.reserved_pe_idx == 0)
289 r->start += (2 * phb->ioda.m64_segsize);
290 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
291 r->end -= (2 * phb->ioda.m64_segsize);
293 WARN(1, "Wrong reserved PE#%d on PHB#%d\n",
294 phb->ioda.reserved_pe_idx, phb->hose->global_number);
299 for ( ; index >= 0; index--)
300 opal_pci_phb_mmio_enable(phb->opal_id,
301 OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64);
306 static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus,
307 unsigned long *pe_bitmap,
310 struct pci_dev *pdev;
312 list_for_each_entry(pdev, &bus->devices, bus_list) {
313 pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap);
315 if (all && pdev->subordinate)
316 pnv_ioda_reserve_m64_pe(pdev->subordinate,
321 static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all)
323 struct pci_controller *hose = pci_bus_to_host(bus);
324 struct pnv_phb *phb = hose->private_data;
325 struct pnv_ioda_pe *master_pe, *pe;
326 unsigned long size, *pe_alloc;
329 /* Root bus shouldn't use M64 */
330 if (pci_is_root_bus(bus))
333 /* Allocate bitmap */
334 size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long));
335 pe_alloc = kzalloc(size, GFP_KERNEL);
337 pr_warn("%s: Out of memory !\n",
342 /* Figure out reserved PE numbers by the PE */
343 pnv_ioda_reserve_m64_pe(bus, pe_alloc, all);
346 * the current bus might not own M64 window and that's all
347 * contributed by its child buses. For the case, we needn't
348 * pick M64 dependent PE#.
350 if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) {
356 * Figure out the master PE and put all slave PEs to master
357 * PE's list to form compound PE.
361 while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) <
362 phb->ioda.total_pe_num) {
363 pe = &phb->ioda.pe_array[i];
365 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number;
367 pe->flags |= PNV_IODA_PE_MASTER;
368 INIT_LIST_HEAD(&pe->slaves);
371 pe->flags |= PNV_IODA_PE_SLAVE;
372 pe->master = master_pe;
373 list_add_tail(&pe->list, &master_pe->slaves);
377 * P7IOC supports M64DT, which helps mapping M64 segment
378 * to one particular PE#. However, PHB3 has fixed mapping
379 * between M64 segment and PE#. In order to have same logic
380 * for P7IOC and PHB3, we enforce fixed mapping between M64
381 * segment and PE# on P7IOC.
383 if (phb->type == PNV_PHB_IODA1) {
386 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
387 pe->pe_number, OPAL_M64_WINDOW_TYPE,
388 pe->pe_number / PNV_IODA1_M64_SEGS,
389 pe->pe_number % PNV_IODA1_M64_SEGS);
390 if (rc != OPAL_SUCCESS)
391 pr_warn("%s: Error %lld mapping M64 for PHB#%d-PE#%d\n",
392 __func__, rc, phb->hose->global_number,
401 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
403 struct pci_controller *hose = phb->hose;
404 struct device_node *dn = hose->dn;
405 struct resource *res;
409 if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) {
410 pr_info(" Not support M64 window\n");
414 if (!firmware_has_feature(FW_FEATURE_OPAL)) {
415 pr_info(" Firmware too old to support M64 window\n");
419 r = of_get_property(dn, "ibm,opal-m64-window", NULL);
421 pr_info(" No <ibm,opal-m64-window> on %s\n",
426 res = &hose->mem_resources[1];
427 res->name = dn->full_name;
428 res->start = of_translate_address(dn, r + 2);
429 res->end = res->start + of_read_number(r + 4, 2) - 1;
430 res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
431 pci_addr = of_read_number(r, 2);
432 hose->mem_offset[1] = res->start - pci_addr;
434 phb->ioda.m64_size = resource_size(res);
435 phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num;
436 phb->ioda.m64_base = pci_addr;
438 pr_info(" MEM64 0x%016llx..0x%016llx -> 0x%016llx\n",
439 res->start, res->end, pci_addr);
441 /* Use last M64 BAR to cover M64 window */
442 phb->ioda.m64_bar_idx = 15;
443 if (phb->type == PNV_PHB_IODA1)
444 phb->init_m64 = pnv_ioda1_init_m64;
446 phb->init_m64 = pnv_ioda2_init_m64;
447 phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe;
448 phb->pick_m64_pe = pnv_ioda_pick_m64_pe;
451 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
453 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
454 struct pnv_ioda_pe *slave;
457 /* Fetch master PE */
458 if (pe->flags & PNV_IODA_PE_SLAVE) {
460 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
463 pe_no = pe->pe_number;
466 /* Freeze master PE */
467 rc = opal_pci_eeh_freeze_set(phb->opal_id,
469 OPAL_EEH_ACTION_SET_FREEZE_ALL);
470 if (rc != OPAL_SUCCESS) {
471 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
472 __func__, rc, phb->hose->global_number, pe_no);
476 /* Freeze slave PEs */
477 if (!(pe->flags & PNV_IODA_PE_MASTER))
480 list_for_each_entry(slave, &pe->slaves, list) {
481 rc = opal_pci_eeh_freeze_set(phb->opal_id,
483 OPAL_EEH_ACTION_SET_FREEZE_ALL);
484 if (rc != OPAL_SUCCESS)
485 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
486 __func__, rc, phb->hose->global_number,
491 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
493 struct pnv_ioda_pe *pe, *slave;
497 pe = &phb->ioda.pe_array[pe_no];
498 if (pe->flags & PNV_IODA_PE_SLAVE) {
500 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
501 pe_no = pe->pe_number;
504 /* Clear frozen state for master PE */
505 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
506 if (rc != OPAL_SUCCESS) {
507 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
508 __func__, rc, opt, phb->hose->global_number, pe_no);
512 if (!(pe->flags & PNV_IODA_PE_MASTER))
515 /* Clear frozen state for slave PEs */
516 list_for_each_entry(slave, &pe->slaves, list) {
517 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
520 if (rc != OPAL_SUCCESS) {
521 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
522 __func__, rc, opt, phb->hose->global_number,
531 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
533 struct pnv_ioda_pe *slave, *pe;
538 /* Sanity check on PE number */
539 if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num)
540 return OPAL_EEH_STOPPED_PERM_UNAVAIL;
543 * Fetch the master PE and the PE instance might be
544 * not initialized yet.
546 pe = &phb->ioda.pe_array[pe_no];
547 if (pe->flags & PNV_IODA_PE_SLAVE) {
549 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
550 pe_no = pe->pe_number;
553 /* Check the master PE */
554 rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
555 &state, &pcierr, NULL);
556 if (rc != OPAL_SUCCESS) {
557 pr_warn("%s: Failure %lld getting "
558 "PHB#%x-PE#%x state\n",
560 phb->hose->global_number, pe_no);
561 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
564 /* Check the slave PE */
565 if (!(pe->flags & PNV_IODA_PE_MASTER))
568 list_for_each_entry(slave, &pe->slaves, list) {
569 rc = opal_pci_eeh_freeze_status(phb->opal_id,
574 if (rc != OPAL_SUCCESS) {
575 pr_warn("%s: Failure %lld getting "
576 "PHB#%x-PE#%x state\n",
578 phb->hose->global_number, slave->pe_number);
579 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
583 * Override the result based on the ascending
593 /* Currently those 2 are only used when MSIs are enabled, this will change
594 * but in the meantime, we need to protect them to avoid warnings
596 #ifdef CONFIG_PCI_MSI
597 static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
599 struct pci_controller *hose = pci_bus_to_host(dev->bus);
600 struct pnv_phb *phb = hose->private_data;
601 struct pci_dn *pdn = pci_get_pdn(dev);
605 if (pdn->pe_number == IODA_INVALID_PE)
607 return &phb->ioda.pe_array[pdn->pe_number];
609 #endif /* CONFIG_PCI_MSI */
611 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
612 struct pnv_ioda_pe *parent,
613 struct pnv_ioda_pe *child,
616 const char *desc = is_add ? "adding" : "removing";
617 uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
618 OPAL_REMOVE_PE_FROM_DOMAIN;
619 struct pnv_ioda_pe *slave;
622 /* Parent PE affects child PE */
623 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
624 child->pe_number, op);
625 if (rc != OPAL_SUCCESS) {
626 pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
631 if (!(child->flags & PNV_IODA_PE_MASTER))
634 /* Compound case: parent PE affects slave PEs */
635 list_for_each_entry(slave, &child->slaves, list) {
636 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
637 slave->pe_number, op);
638 if (rc != OPAL_SUCCESS) {
639 pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
648 static int pnv_ioda_set_peltv(struct pnv_phb *phb,
649 struct pnv_ioda_pe *pe,
652 struct pnv_ioda_pe *slave;
653 struct pci_dev *pdev = NULL;
657 * Clear PE frozen state. If it's master PE, we need
658 * clear slave PE frozen state as well.
661 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
662 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
663 if (pe->flags & PNV_IODA_PE_MASTER) {
664 list_for_each_entry(slave, &pe->slaves, list)
665 opal_pci_eeh_freeze_clear(phb->opal_id,
667 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
672 * Associate PE in PELT. We need add the PE into the
673 * corresponding PELT-V as well. Otherwise, the error
674 * originated from the PE might contribute to other
677 ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
681 /* For compound PEs, any one affects all of them */
682 if (pe->flags & PNV_IODA_PE_MASTER) {
683 list_for_each_entry(slave, &pe->slaves, list) {
684 ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
690 if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
691 pdev = pe->pbus->self;
692 else if (pe->flags & PNV_IODA_PE_DEV)
693 pdev = pe->pdev->bus->self;
694 #ifdef CONFIG_PCI_IOV
695 else if (pe->flags & PNV_IODA_PE_VF)
696 pdev = pe->parent_dev;
697 #endif /* CONFIG_PCI_IOV */
699 struct pci_dn *pdn = pci_get_pdn(pdev);
700 struct pnv_ioda_pe *parent;
702 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
703 parent = &phb->ioda.pe_array[pdn->pe_number];
704 ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
709 pdev = pdev->bus->self;
715 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
717 struct pci_dev *parent;
718 uint8_t bcomp, dcomp, fcomp;
722 /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
726 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
727 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
728 parent = pe->pbus->self;
729 if (pe->flags & PNV_IODA_PE_BUS_ALL)
730 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
735 case 1: bcomp = OpalPciBusAll; break;
736 case 2: bcomp = OpalPciBus7Bits; break;
737 case 4: bcomp = OpalPciBus6Bits; break;
738 case 8: bcomp = OpalPciBus5Bits; break;
739 case 16: bcomp = OpalPciBus4Bits; break;
740 case 32: bcomp = OpalPciBus3Bits; break;
742 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
744 /* Do an exact match only */
745 bcomp = OpalPciBusAll;
747 rid_end = pe->rid + (count << 8);
749 #ifdef CONFIG_PCI_IOV
750 if (pe->flags & PNV_IODA_PE_VF)
751 parent = pe->parent_dev;
754 parent = pe->pdev->bus->self;
755 bcomp = OpalPciBusAll;
756 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
757 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
758 rid_end = pe->rid + 1;
761 /* Clear the reverse map */
762 for (rid = pe->rid; rid < rid_end; rid++)
763 phb->ioda.pe_rmap[rid] = IODA_INVALID_PE;
765 /* Release from all parents PELT-V */
767 struct pci_dn *pdn = pci_get_pdn(parent);
768 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
769 rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
770 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
771 /* XXX What to do in case of error ? */
773 parent = parent->bus->self;
776 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
777 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
779 /* Disassociate PE in PELT */
780 rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
781 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
783 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc);
784 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
785 bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
787 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
791 #ifdef CONFIG_PCI_IOV
792 pe->parent_dev = NULL;
798 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
800 struct pci_dev *parent;
801 uint8_t bcomp, dcomp, fcomp;
802 long rc, rid_end, rid;
804 /* Bus validation ? */
808 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
809 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
810 parent = pe->pbus->self;
811 if (pe->flags & PNV_IODA_PE_BUS_ALL)
812 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
817 case 1: bcomp = OpalPciBusAll; break;
818 case 2: bcomp = OpalPciBus7Bits; break;
819 case 4: bcomp = OpalPciBus6Bits; break;
820 case 8: bcomp = OpalPciBus5Bits; break;
821 case 16: bcomp = OpalPciBus4Bits; break;
822 case 32: bcomp = OpalPciBus3Bits; break;
824 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
826 /* Do an exact match only */
827 bcomp = OpalPciBusAll;
829 rid_end = pe->rid + (count << 8);
831 #ifdef CONFIG_PCI_IOV
832 if (pe->flags & PNV_IODA_PE_VF)
833 parent = pe->parent_dev;
835 #endif /* CONFIG_PCI_IOV */
836 parent = pe->pdev->bus->self;
837 bcomp = OpalPciBusAll;
838 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
839 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
840 rid_end = pe->rid + 1;
844 * Associate PE in PELT. We need add the PE into the
845 * corresponding PELT-V as well. Otherwise, the error
846 * originated from the PE might contribute to other
849 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
850 bcomp, dcomp, fcomp, OPAL_MAP_PE);
852 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
857 * Configure PELTV. NPUs don't have a PELTV table so skip
858 * configuration on them.
860 if (phb->type != PNV_PHB_NPU)
861 pnv_ioda_set_peltv(phb, pe, true);
863 /* Setup reverse map */
864 for (rid = pe->rid; rid < rid_end; rid++)
865 phb->ioda.pe_rmap[rid] = pe->pe_number;
867 /* Setup one MVTs on IODA1 */
868 if (phb->type != PNV_PHB_IODA1) {
873 pe->mve_number = pe->pe_number;
874 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
875 if (rc != OPAL_SUCCESS) {
876 pe_err(pe, "OPAL error %ld setting up MVE %d\n",
880 rc = opal_pci_set_mve_enable(phb->opal_id,
881 pe->mve_number, OPAL_ENABLE_MVE);
883 pe_err(pe, "OPAL error %ld enabling MVE %d\n",
893 #ifdef CONFIG_PCI_IOV
894 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
896 struct pci_dn *pdn = pci_get_pdn(dev);
898 struct resource *res, res2;
899 resource_size_t size;
906 * "offset" is in VFs. The M64 windows are sized so that when they
907 * are segmented, each segment is the same size as the IOV BAR.
908 * Each segment is in a separate PE, and the high order bits of the
909 * address are the PE number. Therefore, each VF's BAR is in a
910 * separate PE, and changing the IOV BAR start address changes the
911 * range of PEs the VFs are in.
913 num_vfs = pdn->num_vfs;
914 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
915 res = &dev->resource[i + PCI_IOV_RESOURCES];
916 if (!res->flags || !res->parent)
920 * The actual IOV BAR range is determined by the start address
921 * and the actual size for num_vfs VFs BAR. This check is to
922 * make sure that after shifting, the range will not overlap
923 * with another device.
925 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
926 res2.flags = res->flags;
927 res2.start = res->start + (size * offset);
928 res2.end = res2.start + (size * num_vfs) - 1;
930 if (res2.end > res->end) {
931 dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
932 i, &res2, res, num_vfs, offset);
938 * After doing so, there would be a "hole" in the /proc/iomem when
939 * offset is a positive value. It looks like the device return some
940 * mmio back to the system, which actually no one could use it.
942 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
943 res = &dev->resource[i + PCI_IOV_RESOURCES];
944 if (!res->flags || !res->parent)
947 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
949 res->start += size * offset;
951 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",
952 i, &res2, res, (offset > 0) ? "En" : "Dis",
954 pci_update_resource(dev, i + PCI_IOV_RESOURCES);
958 #endif /* CONFIG_PCI_IOV */
960 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
962 struct pci_controller *hose = pci_bus_to_host(dev->bus);
963 struct pnv_phb *phb = hose->private_data;
964 struct pci_dn *pdn = pci_get_pdn(dev);
965 struct pnv_ioda_pe *pe;
968 pr_err("%s: Device tree node not associated properly\n",
972 if (pdn->pe_number != IODA_INVALID_PE)
975 pe = pnv_ioda_alloc_pe(phb);
977 pr_warning("%s: Not enough PE# available, disabling device\n",
982 /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
983 * pointer in the PE data structure, both should be destroyed at the
984 * same time. However, this needs to be looked at more closely again
985 * once we actually start removing things (Hotplug, SR-IOV, ...)
987 * At some point we want to remove the PDN completely anyways
991 pdn->pe_number = pe->pe_number;
992 pe->flags = PNV_IODA_PE_DEV;
996 pe->rid = dev->bus->number << 8 | pdn->devfn;
998 pe_info(pe, "Associated device to PE\n");
1000 if (pnv_ioda_configure_pe(phb, pe)) {
1001 /* XXX What do we do here ? */
1002 pnv_ioda_free_pe(pe);
1003 pdn->pe_number = IODA_INVALID_PE;
1009 /* Put PE to the list */
1010 list_add_tail(&pe->list, &phb->ioda.pe_list);
1015 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
1017 struct pci_dev *dev;
1019 list_for_each_entry(dev, &bus->devices, bus_list) {
1020 struct pci_dn *pdn = pci_get_pdn(dev);
1023 pr_warn("%s: No device node associated with device !\n",
1029 * In partial hotplug case, the PCI device might be still
1030 * associated with the PE and needn't attach it to the PE
1033 if (pdn->pe_number != IODA_INVALID_PE)
1038 pdn->pe_number = pe->pe_number;
1039 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1040 pnv_ioda_setup_same_PE(dev->subordinate, pe);
1045 * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1046 * single PCI bus. Another one that contains the primary PCI bus and its
1047 * subordinate PCI devices and buses. The second type of PE is normally
1048 * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1050 static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
1052 struct pci_controller *hose = pci_bus_to_host(bus);
1053 struct pnv_phb *phb = hose->private_data;
1054 struct pnv_ioda_pe *pe = NULL;
1055 unsigned int pe_num;
1058 * In partial hotplug case, the PE instance might be still alive.
1059 * We should reuse it instead of allocating a new one.
1061 pe_num = phb->ioda.pe_rmap[bus->number << 8];
1062 if (pe_num != IODA_INVALID_PE) {
1063 pe = &phb->ioda.pe_array[pe_num];
1064 pnv_ioda_setup_same_PE(bus, pe);
1068 /* PE number for root bus should have been reserved */
1069 if (pci_is_root_bus(bus) &&
1070 phb->ioda.root_pe_idx != IODA_INVALID_PE)
1071 pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx];
1073 /* Check if PE is determined by M64 */
1074 if (!pe && phb->pick_m64_pe)
1075 pe = phb->pick_m64_pe(bus, all);
1077 /* The PE number isn't pinned by M64 */
1079 pe = pnv_ioda_alloc_pe(phb);
1082 pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1083 __func__, pci_domain_nr(bus), bus->number);
1087 pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
1090 pe->mve_number = -1;
1091 pe->rid = bus->busn_res.start << 8;
1094 pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n",
1095 bus->busn_res.start, bus->busn_res.end, pe->pe_number);
1097 pe_info(pe, "Secondary bus %d associated with PE#%d\n",
1098 bus->busn_res.start, pe->pe_number);
1100 if (pnv_ioda_configure_pe(phb, pe)) {
1101 /* XXX What do we do here ? */
1102 pnv_ioda_free_pe(pe);
1107 /* Associate it with all child devices */
1108 pnv_ioda_setup_same_PE(bus, pe);
1110 /* Put PE to the list */
1111 list_add_tail(&pe->list, &phb->ioda.pe_list);
1116 static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev)
1118 int pe_num, found_pe = false, rc;
1120 struct pnv_ioda_pe *pe;
1121 struct pci_dev *gpu_pdev;
1122 struct pci_dn *npu_pdn;
1123 struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus);
1124 struct pnv_phb *phb = hose->private_data;
1127 * Due to a hardware errata PE#0 on the NPU is reserved for
1128 * error handling. This means we only have three PEs remaining
1129 * which need to be assigned to four links, implying some
1130 * links must share PEs.
1132 * To achieve this we assign PEs such that NPUs linking the
1133 * same GPU get assigned the same PE.
1135 gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev);
1136 for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) {
1137 pe = &phb->ioda.pe_array[pe_num];
1141 if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) {
1143 * This device has the same peer GPU so should
1144 * be assigned the same PE as the existing
1147 dev_info(&npu_pdev->dev,
1148 "Associating to existing PE %d\n", pe_num);
1149 pci_dev_get(npu_pdev);
1150 npu_pdn = pci_get_pdn(npu_pdev);
1151 rid = npu_pdev->bus->number << 8 | npu_pdn->devfn;
1152 npu_pdn->pcidev = npu_pdev;
1153 npu_pdn->pe_number = pe_num;
1154 phb->ioda.pe_rmap[rid] = pe->pe_number;
1156 /* Map the PE to this link */
1157 rc = opal_pci_set_pe(phb->opal_id, pe_num, rid,
1159 OPAL_COMPARE_RID_DEVICE_NUMBER,
1160 OPAL_COMPARE_RID_FUNCTION_NUMBER,
1162 WARN_ON(rc != OPAL_SUCCESS);
1170 * Could not find an existing PE so allocate a new
1173 return pnv_ioda_setup_dev_PE(npu_pdev);
1178 static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus)
1180 struct pci_dev *pdev;
1182 list_for_each_entry(pdev, &bus->devices, bus_list)
1183 pnv_ioda_setup_npu_PE(pdev);
1186 static void pnv_pci_ioda_setup_PEs(void)
1188 struct pci_controller *hose, *tmp;
1189 struct pnv_phb *phb;
1191 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1192 phb = hose->private_data;
1193 if (phb->type == PNV_PHB_NPU) {
1194 /* PE#0 is needed for error reporting */
1195 pnv_ioda_reserve_pe(phb, 0);
1196 pnv_ioda_setup_npu_PEs(hose->bus);
1201 #ifdef CONFIG_PCI_IOV
1202 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs)
1204 struct pci_bus *bus;
1205 struct pci_controller *hose;
1206 struct pnv_phb *phb;
1212 hose = pci_bus_to_host(bus);
1213 phb = hose->private_data;
1214 pdn = pci_get_pdn(pdev);
1216 if (pdn->m64_single_mode)
1221 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1222 for (j = 0; j < m64_bars; j++) {
1223 if (pdn->m64_map[j][i] == IODA_INVALID_M64)
1225 opal_pci_phb_mmio_enable(phb->opal_id,
1226 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0);
1227 clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc);
1228 pdn->m64_map[j][i] = IODA_INVALID_M64;
1231 kfree(pdn->m64_map);
1235 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
1237 struct pci_bus *bus;
1238 struct pci_controller *hose;
1239 struct pnv_phb *phb;
1242 struct resource *res;
1246 resource_size_t size, start;
1251 hose = pci_bus_to_host(bus);
1252 phb = hose->private_data;
1253 pdn = pci_get_pdn(pdev);
1254 total_vfs = pci_sriov_get_totalvfs(pdev);
1256 if (pdn->m64_single_mode)
1261 pdn->m64_map = kmalloc(sizeof(*pdn->m64_map) * m64_bars, GFP_KERNEL);
1264 /* Initialize the m64_map to IODA_INVALID_M64 */
1265 for (i = 0; i < m64_bars ; i++)
1266 for (j = 0; j < PCI_SRIOV_NUM_BARS; j++)
1267 pdn->m64_map[i][j] = IODA_INVALID_M64;
1270 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1271 res = &pdev->resource[i + PCI_IOV_RESOURCES];
1272 if (!res->flags || !res->parent)
1275 for (j = 0; j < m64_bars; j++) {
1277 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
1278 phb->ioda.m64_bar_idx + 1, 0);
1280 if (win >= phb->ioda.m64_bar_idx + 1)
1282 } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
1284 pdn->m64_map[j][i] = win;
1286 if (pdn->m64_single_mode) {
1287 size = pci_iov_resource_size(pdev,
1288 PCI_IOV_RESOURCES + i);
1289 start = res->start + size * j;
1291 size = resource_size(res);
1295 /* Map the M64 here */
1296 if (pdn->m64_single_mode) {
1297 pe_num = pdn->pe_num_map[j];
1298 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1299 pe_num, OPAL_M64_WINDOW_TYPE,
1300 pdn->m64_map[j][i], 0);
1303 rc = opal_pci_set_phb_mem_window(phb->opal_id,
1304 OPAL_M64_WINDOW_TYPE,
1311 if (rc != OPAL_SUCCESS) {
1312 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n",
1317 if (pdn->m64_single_mode)
1318 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1319 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2);
1321 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1322 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1);
1324 if (rc != OPAL_SUCCESS) {
1325 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n",
1334 pnv_pci_vf_release_m64(pdev, num_vfs);
1338 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
1340 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
1342 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe)
1344 struct iommu_table *tbl;
1347 tbl = pe->table_group.tables[0];
1348 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
1350 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
1352 pnv_pci_ioda2_set_bypass(pe, false);
1353 if (pe->table_group.group) {
1354 iommu_group_put(pe->table_group.group);
1355 BUG_ON(pe->table_group.group);
1357 pnv_pci_ioda2_table_free_pages(tbl);
1358 iommu_free_table(tbl, of_node_full_name(dev->dev.of_node));
1361 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev)
1363 struct pci_bus *bus;
1364 struct pci_controller *hose;
1365 struct pnv_phb *phb;
1366 struct pnv_ioda_pe *pe, *pe_n;
1370 hose = pci_bus_to_host(bus);
1371 phb = hose->private_data;
1372 pdn = pci_get_pdn(pdev);
1374 if (!pdev->is_physfn)
1377 list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
1378 if (pe->parent_dev != pdev)
1381 pnv_pci_ioda2_release_dma_pe(pdev, pe);
1383 /* Remove from list */
1384 mutex_lock(&phb->ioda.pe_list_mutex);
1385 list_del(&pe->list);
1386 mutex_unlock(&phb->ioda.pe_list_mutex);
1388 pnv_ioda_deconfigure_pe(phb, pe);
1390 pnv_ioda_free_pe(pe);
1394 void pnv_pci_sriov_disable(struct pci_dev *pdev)
1396 struct pci_bus *bus;
1397 struct pci_controller *hose;
1398 struct pnv_phb *phb;
1399 struct pnv_ioda_pe *pe;
1401 struct pci_sriov *iov;
1405 hose = pci_bus_to_host(bus);
1406 phb = hose->private_data;
1407 pdn = pci_get_pdn(pdev);
1409 num_vfs = pdn->num_vfs;
1411 /* Release VF PEs */
1412 pnv_ioda_release_vf_PE(pdev);
1414 if (phb->type == PNV_PHB_IODA2) {
1415 if (!pdn->m64_single_mode)
1416 pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map);
1418 /* Release M64 windows */
1419 pnv_pci_vf_release_m64(pdev, num_vfs);
1421 /* Release PE numbers */
1422 if (pdn->m64_single_mode) {
1423 for (i = 0; i < num_vfs; i++) {
1424 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1427 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1428 pnv_ioda_free_pe(pe);
1431 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1432 /* Releasing pe_num_map */
1433 kfree(pdn->pe_num_map);
1437 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1438 struct pnv_ioda_pe *pe);
1439 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1441 struct pci_bus *bus;
1442 struct pci_controller *hose;
1443 struct pnv_phb *phb;
1444 struct pnv_ioda_pe *pe;
1450 hose = pci_bus_to_host(bus);
1451 phb = hose->private_data;
1452 pdn = pci_get_pdn(pdev);
1454 if (!pdev->is_physfn)
1457 /* Reserve PE for each VF */
1458 for (vf_index = 0; vf_index < num_vfs; vf_index++) {
1459 if (pdn->m64_single_mode)
1460 pe_num = pdn->pe_num_map[vf_index];
1462 pe_num = *pdn->pe_num_map + vf_index;
1464 pe = &phb->ioda.pe_array[pe_num];
1465 pe->pe_number = pe_num;
1467 pe->flags = PNV_IODA_PE_VF;
1469 pe->parent_dev = pdev;
1470 pe->mve_number = -1;
1471 pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) |
1472 pci_iov_virtfn_devfn(pdev, vf_index);
1474 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n",
1475 hose->global_number, pdev->bus->number,
1476 PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)),
1477 PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num);
1479 if (pnv_ioda_configure_pe(phb, pe)) {
1480 /* XXX What do we do here ? */
1481 pnv_ioda_free_pe(pe);
1486 /* Put PE to the list */
1487 mutex_lock(&phb->ioda.pe_list_mutex);
1488 list_add_tail(&pe->list, &phb->ioda.pe_list);
1489 mutex_unlock(&phb->ioda.pe_list_mutex);
1491 pnv_pci_ioda2_setup_dma_pe(phb, pe);
1495 int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1497 struct pci_bus *bus;
1498 struct pci_controller *hose;
1499 struct pnv_phb *phb;
1500 struct pnv_ioda_pe *pe;
1506 hose = pci_bus_to_host(bus);
1507 phb = hose->private_data;
1508 pdn = pci_get_pdn(pdev);
1510 if (phb->type == PNV_PHB_IODA2) {
1511 if (!pdn->vfs_expanded) {
1512 dev_info(&pdev->dev, "don't support this SRIOV device"
1513 " with non 64bit-prefetchable IOV BAR\n");
1518 * When M64 BARs functions in Single PE mode, the number of VFs
1519 * could be enabled must be less than the number of M64 BARs.
1521 if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) {
1522 dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n");
1526 /* Allocating pe_num_map */
1527 if (pdn->m64_single_mode)
1528 pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map) * num_vfs,
1531 pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL);
1533 if (!pdn->pe_num_map)
1536 if (pdn->m64_single_mode)
1537 for (i = 0; i < num_vfs; i++)
1538 pdn->pe_num_map[i] = IODA_INVALID_PE;
1540 /* Calculate available PE for required VFs */
1541 if (pdn->m64_single_mode) {
1542 for (i = 0; i < num_vfs; i++) {
1543 pe = pnv_ioda_alloc_pe(phb);
1549 pdn->pe_num_map[i] = pe->pe_number;
1552 mutex_lock(&phb->ioda.pe_alloc_mutex);
1553 *pdn->pe_num_map = bitmap_find_next_zero_area(
1554 phb->ioda.pe_alloc, phb->ioda.total_pe_num,
1556 if (*pdn->pe_num_map >= phb->ioda.total_pe_num) {
1557 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1558 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs);
1559 kfree(pdn->pe_num_map);
1562 bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1563 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1565 pdn->num_vfs = num_vfs;
1567 /* Assign M64 window accordingly */
1568 ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
1570 dev_info(&pdev->dev, "Not enough M64 window resources\n");
1575 * When using one M64 BAR to map one IOV BAR, we need to shift
1576 * the IOV BAR according to the PE# allocated to the VFs.
1577 * Otherwise, the PE# for the VF will conflict with others.
1579 if (!pdn->m64_single_mode) {
1580 ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map);
1587 pnv_ioda_setup_vf_PE(pdev, num_vfs);
1592 if (pdn->m64_single_mode) {
1593 for (i = 0; i < num_vfs; i++) {
1594 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1597 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1598 pnv_ioda_free_pe(pe);
1601 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1603 /* Releasing pe_num_map */
1604 kfree(pdn->pe_num_map);
1609 int pcibios_sriov_disable(struct pci_dev *pdev)
1611 pnv_pci_sriov_disable(pdev);
1613 /* Release PCI data */
1614 remove_dev_pci_data(pdev);
1618 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1620 /* Allocate PCI data */
1621 add_dev_pci_data(pdev);
1623 return pnv_pci_sriov_enable(pdev, num_vfs);
1625 #endif /* CONFIG_PCI_IOV */
1627 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
1629 struct pci_dn *pdn = pci_get_pdn(pdev);
1630 struct pnv_ioda_pe *pe;
1633 * The function can be called while the PE#
1634 * hasn't been assigned. Do nothing for the
1637 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1640 pe = &phb->ioda.pe_array[pdn->pe_number];
1641 WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
1642 set_dma_offset(&pdev->dev, pe->tce_bypass_base);
1643 set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
1645 * Note: iommu_add_device() will fail here as
1646 * for physical PE: the device is already added by now;
1647 * for virtual PE: sysfs entries are not ready yet and
1648 * tce_iommu_bus_notifier will add the device to a group later.
1652 static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
1654 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1655 struct pnv_phb *phb = hose->private_data;
1656 struct pci_dn *pdn = pci_get_pdn(pdev);
1657 struct pnv_ioda_pe *pe;
1659 bool bypass = false;
1661 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1664 pe = &phb->ioda.pe_array[pdn->pe_number];
1665 if (pe->tce_bypass_enabled) {
1666 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1667 bypass = (dma_mask >= top);
1671 dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");
1672 set_dma_ops(&pdev->dev, &dma_direct_ops);
1674 dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");
1675 set_dma_ops(&pdev->dev, &dma_iommu_ops);
1677 *pdev->dev.dma_mask = dma_mask;
1679 /* Update peer npu devices */
1680 pnv_npu_try_dma_set_bypass(pdev, bypass);
1685 static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev)
1687 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1688 struct pnv_phb *phb = hose->private_data;
1689 struct pci_dn *pdn = pci_get_pdn(pdev);
1690 struct pnv_ioda_pe *pe;
1693 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1696 pe = &phb->ioda.pe_array[pdn->pe_number];
1697 if (!pe->tce_bypass_enabled)
1698 return __dma_get_required_mask(&pdev->dev);
1701 end = pe->tce_bypass_base + memblock_end_of_DRAM();
1702 mask = 1ULL << (fls64(end) - 1);
1708 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe,
1709 struct pci_bus *bus)
1711 struct pci_dev *dev;
1713 list_for_each_entry(dev, &bus->devices, bus_list) {
1714 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
1715 set_dma_offset(&dev->dev, pe->tce_bypass_base);
1716 iommu_add_device(&dev->dev);
1718 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1719 pnv_ioda_setup_bus_dma(pe, dev->subordinate);
1723 static void pnv_pci_ioda1_tce_invalidate(struct iommu_table *tbl,
1724 unsigned long index, unsigned long npages, bool rm)
1726 struct iommu_table_group_link *tgl = list_first_entry_or_null(
1727 &tbl->it_group_list, struct iommu_table_group_link,
1729 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1730 struct pnv_ioda_pe, table_group);
1731 __be64 __iomem *invalidate = rm ?
1732 (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys :
1733 pe->phb->ioda.tce_inval_reg;
1734 unsigned long start, end, inc;
1735 const unsigned shift = tbl->it_page_shift;
1737 start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset);
1738 end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset +
1741 /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */
1742 if (tbl->it_busno) {
1745 inc = 128ull << shift;
1746 start |= tbl->it_busno;
1747 end |= tbl->it_busno;
1748 } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) {
1749 /* p7ioc-style invalidation, 2 TCEs per write */
1750 start |= (1ull << 63);
1751 end |= (1ull << 63);
1754 /* Default (older HW) */
1758 end |= inc - 1; /* round up end to be different than start */
1760 mb(); /* Ensure above stores are visible */
1761 while (start <= end) {
1763 __raw_rm_writeq(cpu_to_be64(start), invalidate);
1765 __raw_writeq(cpu_to_be64(start), invalidate);
1770 * The iommu layer will do another mb() for us on build()
1771 * and we don't care on free()
1775 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
1776 long npages, unsigned long uaddr,
1777 enum dma_data_direction direction,
1778 struct dma_attrs *attrs)
1780 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1783 if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE))
1784 pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false);
1789 #ifdef CONFIG_IOMMU_API
1790 static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index,
1791 unsigned long *hpa, enum dma_data_direction *direction)
1793 long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1795 if (!ret && (tbl->it_type &
1796 (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE)))
1797 pnv_pci_ioda1_tce_invalidate(tbl, index, 1, false);
1803 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
1806 pnv_tce_free(tbl, index, npages);
1808 if (tbl->it_type & TCE_PCI_SWINV_FREE)
1809 pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false);
1812 static struct iommu_table_ops pnv_ioda1_iommu_ops = {
1813 .set = pnv_ioda1_tce_build,
1814 #ifdef CONFIG_IOMMU_API
1815 .exchange = pnv_ioda1_tce_xchg,
1817 .clear = pnv_ioda1_tce_free,
1821 #define TCE_KILL_INVAL_ALL PPC_BIT(0)
1822 #define TCE_KILL_INVAL_PE PPC_BIT(1)
1823 #define TCE_KILL_INVAL_TCE PPC_BIT(2)
1825 void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
1827 const unsigned long val = TCE_KILL_INVAL_ALL;
1829 mb(); /* Ensure previous TCE table stores are visible */
1831 __raw_rm_writeq(cpu_to_be64(val),
1833 phb->ioda.tce_inval_reg_phys);
1835 __raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg);
1838 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe)
1840 /* 01xb - invalidate TCEs that match the specified PE# */
1841 unsigned long val = TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF);
1842 struct pnv_phb *phb = pe->phb;
1844 if (!phb->ioda.tce_inval_reg)
1847 mb(); /* Ensure above stores are visible */
1848 __raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg);
1851 static void pnv_pci_ioda2_do_tce_invalidate(unsigned pe_number, bool rm,
1852 __be64 __iomem *invalidate, unsigned shift,
1853 unsigned long index, unsigned long npages)
1855 unsigned long start, end, inc;
1857 /* We'll invalidate DMA address in PE scope */
1858 start = TCE_KILL_INVAL_TCE;
1859 start |= (pe_number & 0xFF);
1862 /* Figure out the start, end and step */
1863 start |= (index << shift);
1864 end |= ((index + npages - 1) << shift);
1865 inc = (0x1ull << shift);
1868 while (start <= end) {
1870 __raw_rm_writeq(cpu_to_be64(start), invalidate);
1872 __raw_writeq(cpu_to_be64(start), invalidate);
1877 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
1878 unsigned long index, unsigned long npages, bool rm)
1880 struct iommu_table_group_link *tgl;
1882 list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) {
1883 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1884 struct pnv_ioda_pe, table_group);
1885 __be64 __iomem *invalidate = rm ?
1886 (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys :
1887 pe->phb->ioda.tce_inval_reg;
1889 if (pe->phb->type == PNV_PHB_NPU) {
1891 * The NVLink hardware does not support TCE kill
1892 * per TCE entry so we have to invalidate
1893 * the entire cache for it.
1895 pnv_pci_ioda2_tce_invalidate_entire(pe->phb, rm);
1898 pnv_pci_ioda2_do_tce_invalidate(pe->pe_number, rm,
1899 invalidate, tbl->it_page_shift,
1904 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
1905 long npages, unsigned long uaddr,
1906 enum dma_data_direction direction,
1907 struct dma_attrs *attrs)
1909 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1912 if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE))
1913 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
1918 #ifdef CONFIG_IOMMU_API
1919 static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index,
1920 unsigned long *hpa, enum dma_data_direction *direction)
1922 long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1924 if (!ret && (tbl->it_type &
1925 (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE)))
1926 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false);
1932 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
1935 pnv_tce_free(tbl, index, npages);
1937 if (tbl->it_type & TCE_PCI_SWINV_FREE)
1938 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
1941 static void pnv_ioda2_table_free(struct iommu_table *tbl)
1943 pnv_pci_ioda2_table_free_pages(tbl);
1944 iommu_free_table(tbl, "pnv");
1947 static struct iommu_table_ops pnv_ioda2_iommu_ops = {
1948 .set = pnv_ioda2_tce_build,
1949 #ifdef CONFIG_IOMMU_API
1950 .exchange = pnv_ioda2_tce_xchg,
1952 .clear = pnv_ioda2_tce_free,
1954 .free = pnv_ioda2_table_free,
1957 static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data)
1959 unsigned int *weight = (unsigned int *)data;
1961 /* This is quite simplistic. The "base" weight of a device
1962 * is 10. 0 means no DMA is to be accounted for it.
1964 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
1967 if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
1968 dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
1969 dev->class == PCI_CLASS_SERIAL_USB_EHCI)
1971 else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
1979 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe)
1981 unsigned int weight = 0;
1983 /* SRIOV VF has same DMA32 weight as its PF */
1984 #ifdef CONFIG_PCI_IOV
1985 if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) {
1986 pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight);
1991 if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) {
1992 pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight);
1993 } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) {
1994 struct pci_dev *pdev;
1996 list_for_each_entry(pdev, &pe->pbus->devices, bus_list)
1997 pnv_pci_ioda_dev_dma_weight(pdev, &weight);
1998 } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) {
1999 pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight);
2005 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb,
2006 struct pnv_ioda_pe *pe)
2009 struct page *tce_mem = NULL;
2010 struct iommu_table *tbl;
2011 unsigned int weight, total_weight = 0;
2012 unsigned int tce32_segsz, base, segs, avail, i;
2016 /* XXX FIXME: Handle 64-bit only DMA devices */
2017 /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
2018 /* XXX FIXME: Allocate multi-level tables on PHB3 */
2019 weight = pnv_pci_ioda_pe_dma_weight(pe);
2023 pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight,
2025 segs = (weight * phb->ioda.dma32_count) / total_weight;
2030 * Allocate contiguous DMA32 segments. We begin with the expected
2031 * number of segments. With one more attempt, the number of DMA32
2032 * segments to be allocated is decreased by one until one segment
2033 * is allocated successfully.
2036 for (base = 0; base <= phb->ioda.dma32_count - segs; base++) {
2037 for (avail = 0, i = base; i < base + segs; i++) {
2038 if (phb->ioda.dma32_segmap[i] ==
2049 pe_warn(pe, "No available DMA32 segments\n");
2054 tbl = pnv_pci_table_alloc(phb->hose->node);
2055 iommu_register_group(&pe->table_group, phb->hose->global_number,
2057 pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
2059 /* Grab a 32-bit TCE table */
2060 pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n",
2061 weight, total_weight, base, segs);
2062 pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
2063 base * PNV_IODA1_DMA32_SEGSIZE,
2064 (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1);
2066 /* XXX Currently, we allocate one big contiguous table for the
2067 * TCEs. We only really need one chunk per 256M of TCE space
2068 * (ie per segment) but that's an optimization for later, it
2069 * requires some added smarts with our get/put_tce implementation
2071 * Each TCE page is 4KB in size and each TCE entry occupies 8
2074 tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3);
2075 tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
2076 get_order(tce32_segsz * segs));
2078 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
2081 addr = page_address(tce_mem);
2082 memset(addr, 0, tce32_segsz * segs);
2085 for (i = 0; i < segs; i++) {
2086 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2089 __pa(addr) + tce32_segsz * i,
2090 tce32_segsz, IOMMU_PAGE_SIZE_4K);
2092 pe_err(pe, " Failed to configure 32-bit TCE table,"
2098 /* Setup DMA32 segment mapping */
2099 for (i = base; i < base + segs; i++)
2100 phb->ioda.dma32_segmap[i] = pe->pe_number;
2102 /* Setup linux iommu table */
2103 pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs,
2104 base * PNV_IODA1_DMA32_SEGSIZE,
2105 IOMMU_PAGE_SHIFT_4K);
2107 /* OPAL variant of P7IOC SW invalidated TCEs */
2108 if (phb->ioda.tce_inval_reg)
2109 tbl->it_type |= (TCE_PCI_SWINV_CREATE |
2110 TCE_PCI_SWINV_FREE |
2111 TCE_PCI_SWINV_PAIR);
2113 tbl->it_ops = &pnv_ioda1_iommu_ops;
2114 pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
2115 pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
2116 iommu_init_table(tbl, phb->hose->node);
2118 if (pe->flags & PNV_IODA_PE_DEV) {
2120 * Setting table base here only for carrying iommu_group
2121 * further down to let iommu_add_device() do the job.
2122 * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2124 set_iommu_table_base(&pe->pdev->dev, tbl);
2125 iommu_add_device(&pe->pdev->dev);
2126 } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2127 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2131 /* XXX Failure: Try to fallback to 64-bit only ? */
2133 __free_pages(tce_mem, get_order(tce32_segsz * segs));
2135 pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
2136 iommu_free_table(tbl, "pnv");
2140 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
2141 int num, struct iommu_table *tbl)
2143 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2145 struct pnv_phb *phb = pe->phb;
2147 const unsigned long size = tbl->it_indirect_levels ?
2148 tbl->it_level_size : tbl->it_size;
2149 const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
2150 const __u64 win_size = tbl->it_size << tbl->it_page_shift;
2152 pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num,
2153 start_addr, start_addr + win_size - 1,
2154 IOMMU_PAGE_SIZE(tbl));
2157 * Map TCE table through TVT. The TVE index is the PE number
2158 * shifted by 1 bit for 32-bits DMA space.
2160 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2162 (pe->pe_number << 1) + num,
2163 tbl->it_indirect_levels + 1,
2166 IOMMU_PAGE_SIZE(tbl));
2168 pe_err(pe, "Failed to configure TCE table, err %ld\n", rc);
2172 pnv_pci_link_table_and_group(phb->hose->node, num,
2173 tbl, &pe->table_group);
2174 pnv_pci_ioda2_tce_invalidate_pe(pe);
2179 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
2181 uint16_t window_id = (pe->pe_number << 1 ) + 1;
2184 pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
2186 phys_addr_t top = memblock_end_of_DRAM();
2188 top = roundup_pow_of_two(top);
2189 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2192 pe->tce_bypass_base,
2195 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2198 pe->tce_bypass_base,
2202 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
2204 pe->tce_bypass_enabled = enable;
2207 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2208 __u32 page_shift, __u64 window_size, __u32 levels,
2209 struct iommu_table *tbl);
2211 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
2212 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2213 struct iommu_table **ptbl)
2215 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2217 int nid = pe->phb->hose->node;
2218 __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
2220 struct iommu_table *tbl;
2222 tbl = pnv_pci_table_alloc(nid);
2226 ret = pnv_pci_ioda2_table_alloc_pages(nid,
2227 bus_offset, page_shift, window_size,
2230 iommu_free_table(tbl, "pnv");
2234 tbl->it_ops = &pnv_ioda2_iommu_ops;
2235 if (pe->phb->ioda.tce_inval_reg)
2236 tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE);
2243 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
2245 struct iommu_table *tbl = NULL;
2249 * crashkernel= specifies the kdump kernel's maximum memory at
2250 * some offset and there is no guaranteed the result is a power
2251 * of 2, which will cause errors later.
2253 const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max());
2256 * In memory constrained environments, e.g. kdump kernel, the
2257 * DMA window can be larger than available memory, which will
2258 * cause errors later.
2260 const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory);
2262 rc = pnv_pci_ioda2_create_table(&pe->table_group, 0,
2263 IOMMU_PAGE_SHIFT_4K,
2265 POWERNV_IOMMU_DEFAULT_LEVELS, &tbl);
2267 pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
2272 iommu_init_table(tbl, pe->phb->hose->node);
2274 rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
2276 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n",
2278 pnv_ioda2_table_free(tbl);
2282 if (!pnv_iommu_bypass_disabled)
2283 pnv_pci_ioda2_set_bypass(pe, true);
2285 /* OPAL variant of PHB3 invalidated TCEs */
2286 if (pe->phb->ioda.tce_inval_reg)
2287 tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE);
2290 * Setting table base here only for carrying iommu_group
2291 * further down to let iommu_add_device() do the job.
2292 * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2294 if (pe->flags & PNV_IODA_PE_DEV)
2295 set_iommu_table_base(&pe->pdev->dev, tbl);
2300 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV)
2301 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
2304 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2306 struct pnv_phb *phb = pe->phb;
2309 pe_info(pe, "Removing DMA window #%d\n", num);
2311 ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
2312 (pe->pe_number << 1) + num,
2313 0/* levels */, 0/* table address */,
2314 0/* table size */, 0/* page size */);
2316 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
2318 pnv_pci_ioda2_tce_invalidate_pe(pe);
2320 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
2326 #ifdef CONFIG_IOMMU_API
2327 static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
2328 __u64 window_size, __u32 levels)
2330 unsigned long bytes = 0;
2331 const unsigned window_shift = ilog2(window_size);
2332 unsigned entries_shift = window_shift - page_shift;
2333 unsigned table_shift = entries_shift + 3;
2334 unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift);
2335 unsigned long direct_table_size;
2337 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
2338 (window_size > memory_hotplug_max()) ||
2339 !is_power_of_2(window_size))
2342 /* Calculate a direct table size from window_size and levels */
2343 entries_shift = (entries_shift + levels - 1) / levels;
2344 table_shift = entries_shift + 3;
2345 table_shift = max_t(unsigned, table_shift, PAGE_SHIFT);
2346 direct_table_size = 1UL << table_shift;
2348 for ( ; levels; --levels) {
2349 bytes += _ALIGN_UP(tce_table_size, direct_table_size);
2351 tce_table_size /= direct_table_size;
2352 tce_table_size <<= 3;
2353 tce_table_size = _ALIGN_UP(tce_table_size, direct_table_size);
2359 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
2361 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2363 /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
2364 struct iommu_table *tbl = pe->table_group.tables[0];
2366 pnv_pci_ioda2_set_bypass(pe, false);
2367 pnv_pci_ioda2_unset_window(&pe->table_group, 0);
2368 pnv_ioda2_table_free(tbl);
2371 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
2373 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2376 pnv_pci_ioda2_setup_default_config(pe);
2379 static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
2380 .get_table_size = pnv_pci_ioda2_get_table_size,
2381 .create_table = pnv_pci_ioda2_create_table,
2382 .set_window = pnv_pci_ioda2_set_window,
2383 .unset_window = pnv_pci_ioda2_unset_window,
2384 .take_ownership = pnv_ioda2_take_ownership,
2385 .release_ownership = pnv_ioda2_release_ownership,
2388 static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque)
2390 struct pci_controller *hose;
2391 struct pnv_phb *phb;
2392 struct pnv_ioda_pe **ptmppe = opaque;
2393 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
2394 struct pci_dn *pdn = pci_get_pdn(pdev);
2396 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
2399 hose = pci_bus_to_host(pdev->bus);
2400 phb = hose->private_data;
2401 if (phb->type != PNV_PHB_NPU)
2404 *ptmppe = &phb->ioda.pe_array[pdn->pe_number];
2410 * This returns PE of associated NPU.
2411 * This assumes that NPU is in the same IOMMU group with GPU and there is
2414 static struct pnv_ioda_pe *gpe_table_group_to_npe(
2415 struct iommu_table_group *table_group)
2417 struct pnv_ioda_pe *npe = NULL;
2418 int ret = iommu_group_for_each_dev(table_group->group, &npe,
2419 gpe_table_group_to_npe_cb);
2421 BUG_ON(!ret || !npe);
2426 static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group,
2427 int num, struct iommu_table *tbl)
2429 long ret = pnv_pci_ioda2_set_window(table_group, num, tbl);
2434 ret = pnv_npu_set_window(gpe_table_group_to_npe(table_group), num, tbl);
2436 pnv_pci_ioda2_unset_window(table_group, num);
2441 static long pnv_pci_ioda2_npu_unset_window(
2442 struct iommu_table_group *table_group,
2445 long ret = pnv_pci_ioda2_unset_window(table_group, num);
2450 return pnv_npu_unset_window(gpe_table_group_to_npe(table_group), num);
2453 static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group)
2456 * Detach NPU first as pnv_ioda2_take_ownership() will destroy
2457 * the iommu_table if 32bit DMA is enabled.
2459 pnv_npu_take_ownership(gpe_table_group_to_npe(table_group));
2460 pnv_ioda2_take_ownership(table_group);
2463 static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = {
2464 .get_table_size = pnv_pci_ioda2_get_table_size,
2465 .create_table = pnv_pci_ioda2_create_table,
2466 .set_window = pnv_pci_ioda2_npu_set_window,
2467 .unset_window = pnv_pci_ioda2_npu_unset_window,
2468 .take_ownership = pnv_ioda2_npu_take_ownership,
2469 .release_ownership = pnv_ioda2_release_ownership,
2472 static void pnv_pci_ioda_setup_iommu_api(void)
2474 struct pci_controller *hose, *tmp;
2475 struct pnv_phb *phb;
2476 struct pnv_ioda_pe *pe, *gpe;
2479 * Now we have all PHBs discovered, time to add NPU devices to
2480 * the corresponding IOMMU groups.
2482 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
2483 phb = hose->private_data;
2485 if (phb->type != PNV_PHB_NPU)
2488 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2489 gpe = pnv_pci_npu_setup_iommu(pe);
2491 gpe->table_group.ops = &pnv_pci_ioda2_npu_ops;
2495 #else /* !CONFIG_IOMMU_API */
2496 static void pnv_pci_ioda_setup_iommu_api(void) { };
2499 static void pnv_pci_ioda_setup_opal_tce_kill(struct pnv_phb *phb)
2501 const __be64 *swinvp;
2503 /* OPAL variant of PHB3 invalidated TCEs */
2504 swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL);
2508 phb->ioda.tce_inval_reg_phys = be64_to_cpup(swinvp);
2509 phb->ioda.tce_inval_reg = ioremap(phb->ioda.tce_inval_reg_phys, 8);
2512 static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift,
2513 unsigned levels, unsigned long limit,
2514 unsigned long *current_offset, unsigned long *total_allocated)
2516 struct page *tce_mem = NULL;
2518 unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT;
2519 unsigned long allocated = 1UL << (order + PAGE_SHIFT);
2520 unsigned entries = 1UL << (shift - 3);
2523 tce_mem = alloc_pages_node(nid, GFP_KERNEL, order);
2525 pr_err("Failed to allocate a TCE memory, order=%d\n", order);
2528 addr = page_address(tce_mem);
2529 memset(addr, 0, allocated);
2530 *total_allocated += allocated;
2534 *current_offset += allocated;
2538 for (i = 0; i < entries; ++i) {
2539 tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift,
2540 levels, limit, current_offset, total_allocated);
2544 addr[i] = cpu_to_be64(__pa(tmp) |
2545 TCE_PCI_READ | TCE_PCI_WRITE);
2547 if (*current_offset >= limit)
2554 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2555 unsigned long size, unsigned level);
2557 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2558 __u32 page_shift, __u64 window_size, __u32 levels,
2559 struct iommu_table *tbl)
2562 unsigned long offset = 0, level_shift, total_allocated = 0;
2563 const unsigned window_shift = ilog2(window_size);
2564 unsigned entries_shift = window_shift - page_shift;
2565 unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT);
2566 const unsigned long tce_table_size = 1UL << table_shift;
2568 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS))
2571 if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size))
2574 /* Adjust direct table size from window_size and levels */
2575 entries_shift = (entries_shift + levels - 1) / levels;
2576 level_shift = entries_shift + 3;
2577 level_shift = max_t(unsigned, level_shift, PAGE_SHIFT);
2579 /* Allocate TCE table */
2580 addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift,
2581 levels, tce_table_size, &offset, &total_allocated);
2583 /* addr==NULL means that the first level allocation failed */
2588 * First level was allocated but some lower level failed as
2589 * we did not allocate as much as we wanted,
2590 * release partially allocated table.
2592 if (offset < tce_table_size) {
2593 pnv_pci_ioda2_table_do_free_pages(addr,
2594 1ULL << (level_shift - 3), levels - 1);
2598 /* Setup linux iommu table */
2599 pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset,
2601 tbl->it_level_size = 1ULL << (level_shift - 3);
2602 tbl->it_indirect_levels = levels - 1;
2603 tbl->it_allocated_size = total_allocated;
2605 pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n",
2606 window_size, tce_table_size, bus_offset);
2611 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2612 unsigned long size, unsigned level)
2614 const unsigned long addr_ul = (unsigned long) addr &
2615 ~(TCE_PCI_READ | TCE_PCI_WRITE);
2619 u64 *tmp = (u64 *) addr_ul;
2621 for (i = 0; i < size; ++i) {
2622 unsigned long hpa = be64_to_cpu(tmp[i]);
2624 if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE)))
2627 pnv_pci_ioda2_table_do_free_pages(__va(hpa), size,
2632 free_pages(addr_ul, get_order(size << 3));
2635 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl)
2637 const unsigned long size = tbl->it_indirect_levels ?
2638 tbl->it_level_size : tbl->it_size;
2643 pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size,
2644 tbl->it_indirect_levels);
2647 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
2648 struct pnv_ioda_pe *pe)
2652 if (!pnv_pci_ioda_pe_dma_weight(pe))
2655 /* TVE #1 is selected by PCI address bit 59 */
2656 pe->tce_bypass_base = 1ull << 59;
2658 iommu_register_group(&pe->table_group, phb->hose->global_number,
2661 /* The PE will reserve all possible 32-bits space */
2662 pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
2663 phb->ioda.m32_pci_base);
2665 /* Setup linux iommu table */
2666 pe->table_group.tce32_start = 0;
2667 pe->table_group.tce32_size = phb->ioda.m32_pci_base;
2668 pe->table_group.max_dynamic_windows_supported =
2669 IOMMU_TABLE_GROUP_MAX_TABLES;
2670 pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
2671 pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M;
2672 #ifdef CONFIG_IOMMU_API
2673 pe->table_group.ops = &pnv_pci_ioda2_ops;
2676 rc = pnv_pci_ioda2_setup_default_config(pe);
2680 if (pe->flags & PNV_IODA_PE_DEV)
2681 iommu_add_device(&pe->pdev->dev);
2682 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2683 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2686 #ifdef CONFIG_PCI_MSI
2687 static void pnv_ioda2_msi_eoi(struct irq_data *d)
2689 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
2690 struct irq_chip *chip = irq_data_get_irq_chip(d);
2691 struct pnv_phb *phb = container_of(chip, struct pnv_phb,
2695 rc = opal_pci_msi_eoi(phb->opal_id, hw_irq);
2702 static void set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
2704 struct irq_data *idata;
2705 struct irq_chip *ichip;
2707 if (phb->type != PNV_PHB_IODA2)
2710 if (!phb->ioda.irq_chip_init) {
2712 * First time we setup an MSI IRQ, we need to setup the
2713 * corresponding IRQ chip to route correctly.
2715 idata = irq_get_irq_data(virq);
2716 ichip = irq_data_get_irq_chip(idata);
2717 phb->ioda.irq_chip_init = 1;
2718 phb->ioda.irq_chip = *ichip;
2719 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
2721 irq_set_chip(virq, &phb->ioda.irq_chip);
2724 #ifdef CONFIG_CXL_BASE
2726 struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev)
2728 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2730 return of_node_get(hose->dn);
2732 EXPORT_SYMBOL(pnv_pci_get_phb_node);
2734 int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode)
2736 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2737 struct pnv_phb *phb = hose->private_data;
2738 struct pnv_ioda_pe *pe;
2741 pe = pnv_ioda_get_pe(dev);
2745 pe_info(pe, "Switching PHB to CXL\n");
2747 rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number);
2748 if (rc == OPAL_UNSUPPORTED)
2749 dev_err(&dev->dev, "Required cxl mode not supported by firmware - update skiboot\n");
2751 dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc);
2755 EXPORT_SYMBOL(pnv_phb_to_cxl_mode);
2757 /* Find PHB for cxl dev and allocate MSI hwirqs?
2758 * Returns the absolute hardware IRQ number
2760 int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num)
2762 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2763 struct pnv_phb *phb = hose->private_data;
2764 int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num);
2767 dev_warn(&dev->dev, "Failed to find a free MSI\n");
2771 return phb->msi_base + hwirq;
2773 EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs);
2775 void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num)
2777 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2778 struct pnv_phb *phb = hose->private_data;
2780 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num);
2782 EXPORT_SYMBOL(pnv_cxl_release_hwirqs);
2784 void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs,
2785 struct pci_dev *dev)
2787 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2788 struct pnv_phb *phb = hose->private_data;
2791 for (i = 1; i < CXL_IRQ_RANGES; i++) {
2792 if (!irqs->range[i])
2794 pr_devel("cxl release irq range 0x%x: offset: 0x%lx limit: %ld\n",
2797 hwirq = irqs->offset[i] - phb->msi_base;
2798 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq,
2802 EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges);
2804 int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs,
2805 struct pci_dev *dev, int num)
2807 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2808 struct pnv_phb *phb = hose->private_data;
2811 memset(irqs, 0, sizeof(struct cxl_irq_ranges));
2813 /* 0 is reserved for the multiplexed PSL DSI interrupt */
2814 for (i = 1; i < CXL_IRQ_RANGES && num; i++) {
2817 hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try);
2825 irqs->offset[i] = phb->msi_base + hwirq;
2826 irqs->range[i] = try;
2827 pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx limit: %li\n",
2828 i, irqs->offset[i], irqs->range[i]);
2836 pnv_cxl_release_hwirq_ranges(irqs, dev);
2839 EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges);
2841 int pnv_cxl_get_irq_count(struct pci_dev *dev)
2843 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2844 struct pnv_phb *phb = hose->private_data;
2846 return phb->msi_bmp.irq_count;
2848 EXPORT_SYMBOL(pnv_cxl_get_irq_count);
2850 int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq,
2853 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2854 struct pnv_phb *phb = hose->private_data;
2855 unsigned int xive_num = hwirq - phb->msi_base;
2856 struct pnv_ioda_pe *pe;
2859 if (!(pe = pnv_ioda_get_pe(dev)))
2862 /* Assign XIVE to PE */
2863 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2865 pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x "
2866 "hwirq 0x%x XIVE 0x%x PE\n",
2867 pci_name(dev), rc, phb->msi_base, hwirq, xive_num);
2870 set_msi_irq_chip(phb, virq);
2874 EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup);
2877 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
2878 unsigned int hwirq, unsigned int virq,
2879 unsigned int is_64, struct msi_msg *msg)
2881 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
2882 unsigned int xive_num = hwirq - phb->msi_base;
2886 /* No PE assigned ? bail out ... no MSI for you ! */
2890 /* Check if we have an MVE */
2891 if (pe->mve_number < 0)
2894 /* Force 32-bit MSI on some broken devices */
2895 if (dev->no_64bit_msi)
2898 /* Assign XIVE to PE */
2899 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2901 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2902 pci_name(dev), rc, xive_num);
2909 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
2912 pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2916 msg->address_hi = be64_to_cpu(addr64) >> 32;
2917 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
2921 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
2924 pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2928 msg->address_hi = 0;
2929 msg->address_lo = be32_to_cpu(addr32);
2931 msg->data = be32_to_cpu(data);
2933 set_msi_irq_chip(phb, virq);
2935 pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
2936 " address=%x_%08x data=%x PE# %d\n",
2937 pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
2938 msg->address_hi, msg->address_lo, data, pe->pe_number);
2943 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
2946 const __be32 *prop = of_get_property(phb->hose->dn,
2947 "ibm,opal-msi-ranges", NULL);
2950 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
2955 phb->msi_base = be32_to_cpup(prop);
2956 count = be32_to_cpup(prop + 1);
2957 if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
2958 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
2959 phb->hose->global_number);
2963 phb->msi_setup = pnv_pci_ioda_msi_setup;
2964 phb->msi32_support = 1;
2965 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
2966 count, phb->msi_base);
2969 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
2970 #endif /* CONFIG_PCI_MSI */
2972 #ifdef CONFIG_PCI_IOV
2973 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
2975 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
2976 struct pnv_phb *phb = hose->private_data;
2977 const resource_size_t gate = phb->ioda.m64_segsize >> 2;
2978 struct resource *res;
2980 resource_size_t size, total_vf_bar_sz;
2984 if (!pdev->is_physfn || pdev->is_added)
2987 pdn = pci_get_pdn(pdev);
2988 pdn->vfs_expanded = 0;
2989 pdn->m64_single_mode = false;
2991 total_vfs = pci_sriov_get_totalvfs(pdev);
2992 mul = phb->ioda.total_pe_num;
2993 total_vf_bar_sz = 0;
2995 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2996 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2997 if (!res->flags || res->parent)
2999 if (!pnv_pci_is_mem_pref_64(res->flags)) {
3000 dev_warn(&pdev->dev, "Don't support SR-IOV with"
3001 " non M64 VF BAR%d: %pR. \n",
3006 total_vf_bar_sz += pci_iov_resource_size(pdev,
3007 i + PCI_IOV_RESOURCES);
3010 * If bigger than quarter of M64 segment size, just round up
3013 * Generally, one M64 BAR maps one IOV BAR. To avoid conflict
3014 * with other devices, IOV BAR size is expanded to be
3015 * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64
3016 * segment size , the expanded size would equal to half of the
3017 * whole M64 space size, which will exhaust the M64 Space and
3018 * limit the system flexibility. This is a design decision to
3019 * set the boundary to quarter of the M64 segment size.
3021 if (total_vf_bar_sz > gate) {
3022 mul = roundup_pow_of_two(total_vfs);
3023 dev_info(&pdev->dev,
3024 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n",
3025 total_vf_bar_sz, gate, mul);
3026 pdn->m64_single_mode = true;
3031 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
3032 res = &pdev->resource[i + PCI_IOV_RESOURCES];
3033 if (!res->flags || res->parent)
3036 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
3038 * On PHB3, the minimum size alignment of M64 BAR in single
3041 if (pdn->m64_single_mode && (size < SZ_32M))
3043 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res);
3044 res->end = res->start + size * mul - 1;
3045 dev_dbg(&pdev->dev, " %pR\n", res);
3046 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
3049 pdn->vfs_expanded = mul;
3054 /* To save MMIO space, IOV BAR is truncated. */
3055 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
3056 res = &pdev->resource[i + PCI_IOV_RESOURCES];
3058 res->end = res->start - 1;
3061 #endif /* CONFIG_PCI_IOV */
3063 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe,
3064 struct resource *res)
3066 struct pnv_phb *phb = pe->phb;
3067 struct pci_bus_region region;
3071 if (!res || !res->flags || res->start > res->end)
3074 if (res->flags & IORESOURCE_IO) {
3075 region.start = res->start - phb->ioda.io_pci_base;
3076 region.end = res->end - phb->ioda.io_pci_base;
3077 index = region.start / phb->ioda.io_segsize;
3079 while (index < phb->ioda.total_pe_num &&
3080 region.start <= region.end) {
3081 phb->ioda.io_segmap[index] = pe->pe_number;
3082 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3083 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
3084 if (rc != OPAL_SUCCESS) {
3085 pr_err("%s: Error %lld mapping IO segment#%d to PE#%d\n",
3086 __func__, rc, index, pe->pe_number);
3090 region.start += phb->ioda.io_segsize;
3093 } else if ((res->flags & IORESOURCE_MEM) &&
3094 !pnv_pci_is_mem_pref_64(res->flags)) {
3095 region.start = res->start -
3096 phb->hose->mem_offset[0] -
3097 phb->ioda.m32_pci_base;
3098 region.end = res->end -
3099 phb->hose->mem_offset[0] -
3100 phb->ioda.m32_pci_base;
3101 index = region.start / phb->ioda.m32_segsize;
3103 while (index < phb->ioda.total_pe_num &&
3104 region.start <= region.end) {
3105 phb->ioda.m32_segmap[index] = pe->pe_number;
3106 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3107 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
3108 if (rc != OPAL_SUCCESS) {
3109 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%d",
3110 __func__, rc, index, pe->pe_number);
3114 region.start += phb->ioda.m32_segsize;
3121 * This function is supposed to be called on basis of PE from top
3122 * to bottom style. So the the I/O or MMIO segment assigned to
3123 * parent PE could be overrided by its child PEs if necessary.
3125 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe)
3127 struct pci_dev *pdev;
3131 * NOTE: We only care PCI bus based PE for now. For PCI
3132 * device based PE, for example SRIOV sensitive VF should
3133 * be figured out later.
3135 BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
3137 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
3138 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
3139 pnv_ioda_setup_pe_res(pe, &pdev->resource[i]);
3142 * If the PE contains all subordinate PCI buses, the
3143 * windows of the child bridges should be mapped to
3146 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev))
3148 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
3149 pnv_ioda_setup_pe_res(pe,
3150 &pdev->resource[PCI_BRIDGE_RESOURCES + i]);
3154 static void pnv_pci_ioda_create_dbgfs(void)
3156 #ifdef CONFIG_DEBUG_FS
3157 struct pci_controller *hose, *tmp;
3158 struct pnv_phb *phb;
3161 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3162 phb = hose->private_data;
3164 /* Notify initialization of PHB done */
3165 phb->initialized = 1;
3167 sprintf(name, "PCI%04x", hose->global_number);
3168 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
3170 pr_warning("%s: Error on creating debugfs on PHB#%x\n",
3171 __func__, hose->global_number);
3173 #endif /* CONFIG_DEBUG_FS */
3176 static void pnv_pci_ioda_fixup(void)
3178 pnv_pci_ioda_setup_PEs();
3179 pnv_pci_ioda_setup_iommu_api();
3180 pnv_pci_ioda_create_dbgfs();
3184 eeh_addr_cache_build();
3189 * Returns the alignment for I/O or memory windows for P2P
3190 * bridges. That actually depends on how PEs are segmented.
3191 * For now, we return I/O or M32 segment size for PE sensitive
3192 * P2P bridges. Otherwise, the default values (4KiB for I/O,
3193 * 1MiB for memory) will be returned.
3195 * The current PCI bus might be put into one PE, which was
3196 * create against the parent PCI bridge. For that case, we
3197 * needn't enlarge the alignment so that we can save some
3200 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
3203 struct pci_dev *bridge;
3204 struct pci_controller *hose = pci_bus_to_host(bus);
3205 struct pnv_phb *phb = hose->private_data;
3206 int num_pci_bridges = 0;
3210 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
3212 if (num_pci_bridges >= 2)
3216 bridge = bridge->bus->self;
3219 /* We fail back to M32 if M64 isn't supported */
3220 if (phb->ioda.m64_segsize &&
3221 pnv_pci_is_mem_pref_64(type))
3222 return phb->ioda.m64_segsize;
3223 if (type & IORESOURCE_MEM)
3224 return phb->ioda.m32_segsize;
3226 return phb->ioda.io_segsize;
3230 * We are updating root port or the upstream port of the
3231 * bridge behind the root port with PHB's windows in order
3232 * to accommodate the changes on required resources during
3233 * PCI (slot) hotplug, which is connected to either root
3234 * port or the downstream ports of PCIe switch behind the
3237 static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus,
3240 struct pci_controller *hose = pci_bus_to_host(bus);
3241 struct pnv_phb *phb = hose->private_data;
3242 struct pci_dev *bridge = bus->self;
3243 struct resource *r, *w;
3244 bool msi_region = false;
3247 /* Check if we need apply fixup to the bridge's windows */
3248 if (!pci_is_root_bus(bridge->bus) &&
3249 !pci_is_root_bus(bridge->bus->self->bus))
3252 /* Fixup the resources */
3253 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
3254 r = &bridge->resource[PCI_BRIDGE_RESOURCES + i];
3255 if (!r->flags || !r->parent)
3259 if (r->flags & type & IORESOURCE_IO)
3260 w = &hose->io_resource;
3261 else if (pnv_pci_is_mem_pref_64(r->flags) &&
3262 (type & IORESOURCE_PREFETCH) &&
3263 phb->ioda.m64_segsize)
3264 w = &hose->mem_resources[1];
3265 else if (r->flags & type & IORESOURCE_MEM) {
3266 w = &hose->mem_resources[0];
3270 r->start = w->start;
3273 /* The 64KB 32-bits MSI region shouldn't be included in
3274 * the 32-bits bridge window. Otherwise, we can see strange
3275 * issues. One of them is EEH error observed on Garrison.
3277 * Exclude top 1MB region which is the minimal alignment of
3278 * 32-bits bridge window.
3287 static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type)
3289 struct pci_controller *hose = pci_bus_to_host(bus);
3290 struct pnv_phb *phb = hose->private_data;
3291 struct pci_dev *bridge = bus->self;
3292 struct pnv_ioda_pe *pe;
3293 bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE);
3295 /* Extend bridge's windows if necessary */
3296 pnv_pci_fixup_bridge_resources(bus, type);
3298 /* The PE for root bus should be realized before any one else */
3299 if (!phb->ioda.root_pe_populated) {
3300 pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false);
3302 phb->ioda.root_pe_idx = pe->pe_number;
3303 phb->ioda.root_pe_populated = true;
3307 /* Don't assign PE to PCI bus, which doesn't have subordinate devices */
3308 if (list_empty(&bus->devices))
3311 /* Reserve PEs according to used M64 resources */
3312 if (phb->reserve_m64_pe)
3313 phb->reserve_m64_pe(bus, NULL, all);
3316 * Assign PE. We might run here because of partial hotplug.
3317 * For the case, we just pick up the existing PE and should
3318 * not allocate resources again.
3320 pe = pnv_ioda_setup_bus_PE(bus, all);
3324 pnv_ioda_setup_pe_seg(pe);
3325 switch (phb->type) {
3327 pnv_pci_ioda1_setup_dma_pe(phb, pe);
3330 pnv_pci_ioda2_setup_dma_pe(phb, pe);
3333 pr_warn("%s: No DMA for PHB#%d (type %d)\n",
3334 __func__, phb->hose->global_number, phb->type);
3338 #ifdef CONFIG_PCI_IOV
3339 static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
3342 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3343 struct pnv_phb *phb = hose->private_data;
3344 struct pci_dn *pdn = pci_get_pdn(pdev);
3345 resource_size_t align;
3348 * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the
3349 * SR-IOV. While from hardware perspective, the range mapped by M64
3350 * BAR should be size aligned.
3352 * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra
3353 * powernv-specific hardware restriction is gone. But if just use the
3354 * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with
3355 * in one segment of M64 #15, which introduces the PE conflict between
3356 * PF and VF. Based on this, the minimum alignment of an IOV BAR is
3359 * This function returns the total IOV BAR size if M64 BAR is in
3360 * Shared PE mode or just VF BAR size if not.
3361 * If the M64 BAR is in Single PE mode, return the VF BAR size or
3362 * M64 segment size if IOV BAR size is less.
3364 align = pci_iov_resource_size(pdev, resno);
3365 if (!pdn->vfs_expanded)
3367 if (pdn->m64_single_mode)
3368 return max(align, (resource_size_t)phb->ioda.m64_segsize);
3370 return pdn->vfs_expanded * align;
3372 #endif /* CONFIG_PCI_IOV */
3374 /* Prevent enabling devices for which we couldn't properly
3377 static bool pnv_pci_enable_device_hook(struct pci_dev *dev)
3379 struct pci_controller *hose = pci_bus_to_host(dev->bus);
3380 struct pnv_phb *phb = hose->private_data;
3383 /* The function is probably called while the PEs have
3384 * not be created yet. For example, resource reassignment
3385 * during PCI probe period. We just skip the check if
3388 if (!phb->initialized)
3391 pdn = pci_get_pdn(dev);
3392 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3398 static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group,
3401 struct pnv_ioda_pe *pe = container_of(table_group,
3402 struct pnv_ioda_pe, table_group);
3403 struct pnv_phb *phb = pe->phb;
3407 pe_info(pe, "Removing DMA window #%d\n", num);
3408 for (idx = 0; idx < phb->ioda.dma32_count; idx++) {
3409 if (phb->ioda.dma32_segmap[idx] != pe->pe_number)
3412 rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
3413 idx, 0, 0ul, 0ul, 0ul);
3414 if (rc != OPAL_SUCCESS) {
3415 pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n",
3420 phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE;
3423 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
3424 return OPAL_SUCCESS;
3427 static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe)
3429 unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3430 struct iommu_table *tbl = pe->table_group.tables[0];
3436 rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0);
3437 if (rc != OPAL_SUCCESS)
3440 pnv_pci_ioda1_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false);
3441 if (pe->table_group.group) {
3442 iommu_group_put(pe->table_group.group);
3443 WARN_ON(pe->table_group.group);
3446 free_pages(tbl->it_base, get_order(tbl->it_size << 3));
3447 iommu_free_table(tbl, "pnv");
3450 static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe)
3452 struct iommu_table *tbl = pe->table_group.tables[0];
3453 unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3454 #ifdef CONFIG_IOMMU_API
3461 #ifdef CONFIG_IOMMU_API
3462 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
3464 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
3467 pnv_pci_ioda2_set_bypass(pe, false);
3468 if (pe->table_group.group) {
3469 iommu_group_put(pe->table_group.group);
3470 WARN_ON(pe->table_group.group);
3473 pnv_pci_ioda2_table_free_pages(tbl);
3474 iommu_free_table(tbl, "pnv");
3477 static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe,
3481 struct pnv_phb *phb = pe->phb;
3485 for (idx = 0; idx < phb->ioda.total_pe_num; idx++) {
3486 if (map[idx] != pe->pe_number)
3489 if (win == OPAL_M64_WINDOW_TYPE)
3490 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3491 phb->ioda.reserved_pe_idx, win,
3492 idx / PNV_IODA1_M64_SEGS,
3493 idx % PNV_IODA1_M64_SEGS);
3495 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3496 phb->ioda.reserved_pe_idx, win, 0, idx);
3498 if (rc != OPAL_SUCCESS)
3499 pe_warn(pe, "Error %ld unmapping (%d) segment#%d\n",
3502 map[idx] = IODA_INVALID_PE;
3506 static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe)
3508 struct pnv_phb *phb = pe->phb;
3510 if (phb->type == PNV_PHB_IODA1) {
3511 pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE,
3512 phb->ioda.io_segmap);
3513 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3514 phb->ioda.m32_segmap);
3515 pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE,
3516 phb->ioda.m64_segmap);
3517 } else if (phb->type == PNV_PHB_IODA2) {
3518 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3519 phb->ioda.m32_segmap);
3523 static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe)
3525 struct pnv_phb *phb = pe->phb;
3526 struct pnv_ioda_pe *slave, *tmp;
3528 /* Release slave PEs in compound PE */
3529 if (pe->flags & PNV_IODA_PE_MASTER) {
3530 list_for_each_entry_safe(slave, tmp, &pe->slaves, list)
3531 pnv_ioda_release_pe(slave);
3534 list_del(&pe->list);
3535 switch (phb->type) {
3537 pnv_pci_ioda1_release_pe_dma(pe);
3540 pnv_pci_ioda2_release_pe_dma(pe);
3546 pnv_ioda_release_pe_seg(pe);
3547 pnv_ioda_deconfigure_pe(pe->phb, pe);
3548 pnv_ioda_free_pe(pe);
3551 static void pnv_pci_release_device(struct pci_dev *pdev)
3553 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3554 struct pnv_phb *phb = hose->private_data;
3555 struct pci_dn *pdn = pci_get_pdn(pdev);
3556 struct pnv_ioda_pe *pe;
3558 if (pdev->is_virtfn)
3561 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3564 pe = &phb->ioda.pe_array[pdn->pe_number];
3565 WARN_ON(--pe->device_count < 0);
3566 if (pe->device_count == 0)
3567 pnv_ioda_release_pe(pe);
3570 static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
3572 struct pnv_phb *phb = hose->private_data;
3574 opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
3578 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
3579 .dma_dev_setup = pnv_pci_dma_dev_setup,
3580 .dma_bus_setup = pnv_pci_dma_bus_setup,
3581 #ifdef CONFIG_PCI_MSI
3582 .setup_msi_irqs = pnv_setup_msi_irqs,
3583 .teardown_msi_irqs = pnv_teardown_msi_irqs,
3585 .enable_device_hook = pnv_pci_enable_device_hook,
3586 .release_device = pnv_pci_release_device,
3587 .window_alignment = pnv_pci_window_alignment,
3588 .setup_bridge = pnv_pci_setup_bridge,
3589 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3590 .dma_set_mask = pnv_pci_ioda_dma_set_mask,
3591 .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask,
3592 .shutdown = pnv_pci_ioda_shutdown,
3595 static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask)
3597 dev_err_once(&npdev->dev,
3598 "%s operation unsupported for NVLink devices\n",
3603 static const struct pci_controller_ops pnv_npu_ioda_controller_ops = {
3604 .dma_dev_setup = pnv_pci_dma_dev_setup,
3605 #ifdef CONFIG_PCI_MSI
3606 .setup_msi_irqs = pnv_setup_msi_irqs,
3607 .teardown_msi_irqs = pnv_teardown_msi_irqs,
3609 .enable_device_hook = pnv_pci_enable_device_hook,
3610 .window_alignment = pnv_pci_window_alignment,
3611 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3612 .dma_set_mask = pnv_npu_dma_set_mask,
3613 .shutdown = pnv_pci_ioda_shutdown,
3616 static void __init pnv_pci_init_ioda_phb(struct device_node *np,
3617 u64 hub_id, int ioda_type)
3619 struct pci_controller *hose;
3620 struct pnv_phb *phb;
3621 unsigned long size, m64map_off, m32map_off, pemap_off;
3622 unsigned long iomap_off = 0, dma32map_off = 0;
3623 const __be64 *prop64;
3624 const __be32 *prop32;
3631 pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name);
3633 prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
3635 pr_err(" Missing \"ibm,opal-phbid\" property !\n");
3638 phb_id = be64_to_cpup(prop64);
3639 pr_debug(" PHB-ID : 0x%016llx\n", phb_id);
3641 phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0);
3643 /* Allocate PCI controller */
3644 phb->hose = hose = pcibios_alloc_controller(np);
3646 pr_err(" Can't allocate PCI controller for %s\n",
3648 memblock_free(__pa(phb), sizeof(struct pnv_phb));
3652 spin_lock_init(&phb->lock);
3653 prop32 = of_get_property(np, "bus-range", &len);
3654 if (prop32 && len == 8) {
3655 hose->first_busno = be32_to_cpu(prop32[0]);
3656 hose->last_busno = be32_to_cpu(prop32[1]);
3658 pr_warn(" Broken <bus-range> on %s\n", np->full_name);
3659 hose->first_busno = 0;
3660 hose->last_busno = 0xff;
3662 hose->private_data = phb;
3663 phb->hub_id = hub_id;
3664 phb->opal_id = phb_id;
3665 phb->type = ioda_type;
3666 mutex_init(&phb->ioda.pe_alloc_mutex);
3668 /* Detect specific models for error handling */
3669 if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
3670 phb->model = PNV_PHB_MODEL_P7IOC;
3671 else if (of_device_is_compatible(np, "ibm,power8-pciex"))
3672 phb->model = PNV_PHB_MODEL_PHB3;
3673 else if (of_device_is_compatible(np, "ibm,power8-npu-pciex"))
3674 phb->model = PNV_PHB_MODEL_NPU;
3676 phb->model = PNV_PHB_MODEL_UNKNOWN;
3678 /* Parse 32-bit and IO ranges (if any) */
3679 pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
3682 phb->regs = of_iomap(np, 0);
3683 if (phb->regs == NULL)
3684 pr_err(" Failed to map registers !\n");
3686 /* Initialize TCE kill register */
3687 pnv_pci_ioda_setup_opal_tce_kill(phb);
3689 /* Initialize more IODA stuff */
3690 phb->ioda.total_pe_num = 1;
3691 prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
3693 phb->ioda.total_pe_num = be32_to_cpup(prop32);
3694 prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
3696 phb->ioda.reserved_pe_idx = be32_to_cpup(prop32);
3698 /* Invalidate RID to PE# mapping */
3699 for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++)
3700 phb->ioda.pe_rmap[segno] = IODA_INVALID_PE;
3702 /* Parse 64-bit MMIO range */
3703 pnv_ioda_parse_m64_window(phb);
3705 phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
3706 /* FW Has already off top 64k of M32 space (MSI space) */
3707 phb->ioda.m32_size += 0x10000;
3709 phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num;
3710 phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
3711 phb->ioda.io_size = hose->pci_io_size;
3712 phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num;
3713 phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
3715 /* Calculate how many 32-bit TCE segments we have */
3716 phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3717 PNV_IODA1_DMA32_SEGSIZE;
3719 /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
3720 size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8,
3721 sizeof(unsigned long));
3723 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]);
3725 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]);
3726 if (phb->type == PNV_PHB_IODA1) {
3728 size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]);
3729 dma32map_off = size;
3730 size += phb->ioda.dma32_count *
3731 sizeof(phb->ioda.dma32_segmap[0]);
3734 size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe);
3735 aux = memblock_virt_alloc(size, 0);
3736 phb->ioda.pe_alloc = aux;
3737 phb->ioda.m64_segmap = aux + m64map_off;
3738 phb->ioda.m32_segmap = aux + m32map_off;
3739 for (segno = 0; segno < phb->ioda.total_pe_num; segno++) {
3740 phb->ioda.m64_segmap[segno] = IODA_INVALID_PE;
3741 phb->ioda.m32_segmap[segno] = IODA_INVALID_PE;
3743 if (phb->type == PNV_PHB_IODA1) {
3744 phb->ioda.io_segmap = aux + iomap_off;
3745 for (segno = 0; segno < phb->ioda.total_pe_num; segno++)
3746 phb->ioda.io_segmap[segno] = IODA_INVALID_PE;
3748 phb->ioda.dma32_segmap = aux + dma32map_off;
3749 for (segno = 0; segno < phb->ioda.dma32_count; segno++)
3750 phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE;
3752 phb->ioda.pe_array = aux + pemap_off;
3755 * Choose PE number for root bus, which shouldn't have
3756 * M64 resources consumed by its child devices. To pick
3757 * the PE number adjacent to the reserved one if possible.
3759 pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx);
3760 if (phb->ioda.reserved_pe_idx == 0) {
3761 phb->ioda.root_pe_idx = 1;
3762 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3763 } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) {
3764 phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1;
3765 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3767 phb->ioda.root_pe_idx = IODA_INVALID_PE;
3770 INIT_LIST_HEAD(&phb->ioda.pe_list);
3771 mutex_init(&phb->ioda.pe_list_mutex);
3773 /* Calculate how many 32-bit TCE segments we have */
3774 phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3775 PNV_IODA1_DMA32_SEGSIZE;
3777 #if 0 /* We should really do that ... */
3778 rc = opal_pci_set_phb_mem_window(opal->phb_id,
3781 starting_real_address,
3782 starting_pci_address,
3786 pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
3787 phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx,
3788 phb->ioda.m32_size, phb->ioda.m32_segsize);
3789 if (phb->ioda.m64_size)
3790 pr_info(" M64: 0x%lx [segment=0x%lx]\n",
3791 phb->ioda.m64_size, phb->ioda.m64_segsize);
3792 if (phb->ioda.io_size)
3793 pr_info(" IO: 0x%x [segment=0x%x]\n",
3794 phb->ioda.io_size, phb->ioda.io_segsize);
3797 phb->hose->ops = &pnv_pci_ops;
3798 phb->get_pe_state = pnv_ioda_get_pe_state;
3799 phb->freeze_pe = pnv_ioda_freeze_pe;
3800 phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
3802 /* Setup MSI support */
3803 pnv_pci_init_ioda_msis(phb);
3806 * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
3807 * to let the PCI core do resource assignment. It's supposed
3808 * that the PCI core will do correct I/O and MMIO alignment
3809 * for the P2P bridge bars so that each PCI bus (excluding
3810 * the child P2P bridges) can form individual PE.
3812 ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
3814 if (phb->type == PNV_PHB_NPU) {
3815 hose->controller_ops = pnv_npu_ioda_controller_ops;
3817 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
3818 hose->controller_ops = pnv_pci_ioda_controller_ops;
3821 #ifdef CONFIG_PCI_IOV
3822 ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources;
3823 ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
3826 pci_add_flags(PCI_REASSIGN_ALL_RSRC);
3828 /* Reset IODA tables to a clean state */
3829 rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
3831 pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc);
3833 /* If we're running in kdump kerenl, the previous kerenl never
3834 * shutdown PCI devices correctly. We already got IODA table
3835 * cleaned out. So we have to issue PHB reset to stop all PCI
3836 * transactions from previous kerenl.
3838 if (is_kdump_kernel()) {
3839 pr_info(" Issue PHB reset ...\n");
3840 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
3841 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
3844 /* Remove M64 resource if we can't configure it successfully */
3845 if (!phb->init_m64 || phb->init_m64(phb))
3846 hose->mem_resources[1].flags = 0;
3849 void __init pnv_pci_init_ioda2_phb(struct device_node *np)
3851 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
3854 void __init pnv_pci_init_npu_phb(struct device_node *np)
3856 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU);
3859 void __init pnv_pci_init_ioda_hub(struct device_node *np)
3861 struct device_node *phbn;
3862 const __be64 *prop64;
3865 pr_info("Probing IODA IO-Hub %s\n", np->full_name);
3867 prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
3869 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
3872 hub_id = be64_to_cpup(prop64);
3873 pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
3875 /* Count child PHBs */
3876 for_each_child_of_node(np, phbn) {
3877 /* Look for IODA1 PHBs */
3878 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
3879 pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);