2 * Support PCI/PCIe on PowerNV platforms
4 * Currently supports only P5IOC2
6 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
14 #include <linux/kernel.h>
15 #include <linux/pci.h>
16 #include <linux/delay.h>
17 #include <linux/string.h>
18 #include <linux/init.h>
19 #include <linux/bootmem.h>
20 #include <linux/irq.h>
23 #include <asm/sections.h>
26 #include <asm/pci-bridge.h>
27 #include <asm/machdep.h>
28 #include <asm/ppc-pci.h>
30 #include <asm/iommu.h>
32 #include <asm/abs_addr.h>
38 #define cfg_dbg(fmt...) do { } while(0)
39 //#define cfg_dbg(fmt...) printk(fmt)
42 static void pnv_pci_config_check_eeh(struct pnv_phb *phb, struct pci_bus *bus,
50 /* Get PE# if we support IODA */
51 pe_no = phb->bdfn_to_pe ? phb->bdfn_to_pe(phb, bus, bdfn & 0xff) : 0;
53 /* Read freeze status */
54 rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, &fstate, &pcierr,
57 pr_warning("PCI %d: Failed to read EEH status for PE#%d,"
58 " err %lld\n", phb->hose->global_number, pe_no, rc);
61 cfg_dbg(" -> EEH check, bdfn=%04x PE%d fstate=%x\n",
64 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
65 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
67 pr_warning("PCI %d: Failed to clear EEH freeze state"
68 " for PE#%d, err %lld\n",
69 phb->hose->global_number, pe_no, rc);
74 static int pnv_pci_read_config(struct pci_bus *bus,
76 int where, int size, u32 *val)
78 struct pci_controller *hose = pci_bus_to_host(bus);
79 struct pnv_phb *phb = hose->private_data;
80 u32 bdfn = (((uint64_t)bus->number) << 8) | devfn;
84 return PCIBIOS_DEVICE_NOT_FOUND;
89 rc = opal_pci_config_read_byte(phb->opal_id, bdfn, where, &v8);
90 *val = (rc == OPAL_SUCCESS) ? v8 : 0xff;
95 rc = opal_pci_config_read_half_word(phb->opal_id, bdfn, where,
97 *val = (rc == OPAL_SUCCESS) ? v16 : 0xffff;
102 rc = opal_pci_config_read_word(phb->opal_id, bdfn, where, &v32);
103 *val = (rc == OPAL_SUCCESS) ? v32 : 0xffffffff;
107 return PCIBIOS_FUNC_NOT_SUPPORTED;
109 cfg_dbg("pnv_pci_read_config bus: %x devfn: %x +%x/%x -> %08x\n",
110 bus->number, devfn, where, size, *val);
112 /* Check if the PHB got frozen due to an error (no response) */
113 pnv_pci_config_check_eeh(phb, bus, bdfn);
115 return PCIBIOS_SUCCESSFUL;
118 static int pnv_pci_write_config(struct pci_bus *bus,
120 int where, int size, u32 val)
122 struct pci_controller *hose = pci_bus_to_host(bus);
123 struct pnv_phb *phb = hose->private_data;
124 u32 bdfn = (((uint64_t)bus->number) << 8) | devfn;
127 return PCIBIOS_DEVICE_NOT_FOUND;
129 cfg_dbg("pnv_pci_write_config bus: %x devfn: %x +%x/%x -> %08x\n",
130 bus->number, devfn, where, size, val);
133 opal_pci_config_write_byte(phb->opal_id, bdfn, where, val);
136 opal_pci_config_write_half_word(phb->opal_id, bdfn, where, val);
139 opal_pci_config_write_word(phb->opal_id, bdfn, where, val);
142 return PCIBIOS_FUNC_NOT_SUPPORTED;
144 /* Check if the PHB got frozen due to an error (no response) */
145 pnv_pci_config_check_eeh(phb, bus, bdfn);
147 return PCIBIOS_SUCCESSFUL;
150 struct pci_ops pnv_pci_ops = {
151 .read = pnv_pci_read_config,
152 .write = pnv_pci_write_config,
155 static int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
156 unsigned long uaddr, enum dma_data_direction direction,
157 struct dma_attrs *attrs)
163 proto_tce = TCE_PCI_READ; // Read allowed
165 if (direction != DMA_TO_DEVICE)
166 proto_tce |= TCE_PCI_WRITE;
168 tcep = ((u64 *)tbl->it_base) + index;
171 /* can't move this out since we might cross LMB boundary */
172 rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
173 *tcep = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
175 uaddr += TCE_PAGE_SIZE;
181 static void pnv_tce_free(struct iommu_table *tbl, long index, long npages)
183 u64 *tcep = ((u64 *)tbl->it_base) + index;
189 void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
190 void *tce_mem, u64 tce_size,
193 tbl->it_blocksize = 16;
194 tbl->it_base = (unsigned long)tce_mem;
195 tbl->it_offset = dma_offset >> IOMMU_PAGE_SHIFT;
197 tbl->it_size = tce_size >> 3;
199 tbl->it_type = TCE_PCI;
202 static struct iommu_table * __devinit
203 pnv_pci_setup_bml_iommu(struct pci_controller *hose)
205 struct iommu_table *tbl;
209 basep = of_get_property(hose->dn, "linux,tce-base", NULL);
210 sizep = of_get_property(hose->dn, "linux,tce-size", NULL);
211 if (basep == NULL || sizep == NULL) {
212 pr_err("PCI: %s has missing tce entries !\n", hose->dn->full_name);
215 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, hose->node);
218 pnv_pci_setup_iommu_table(tbl, __va(be64_to_cpup(basep)),
219 be32_to_cpup(sizep), 0);
220 iommu_init_table(tbl, hose->node);
224 static void __devinit pnv_pci_dma_fallback_setup(struct pci_controller *hose,
225 struct pci_dev *pdev)
227 struct device_node *np = pci_bus_to_OF_node(hose->bus);
233 if (!pdn->iommu_table)
234 pdn->iommu_table = pnv_pci_setup_bml_iommu(hose);
235 if (!pdn->iommu_table)
237 set_iommu_table_base(&pdev->dev, pdn->iommu_table);
240 static void __devinit pnv_pci_dma_dev_setup(struct pci_dev *pdev)
242 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
243 struct pnv_phb *phb = hose->private_data;
245 /* If we have no phb structure, try to setup a fallback based on
246 * the device-tree (RTAS PCI for example)
248 if (phb && phb->dma_dev_setup)
249 phb->dma_dev_setup(phb, pdev);
251 pnv_pci_dma_fallback_setup(hose, pdev);
254 void __init pnv_pci_init(void)
256 struct device_node *np;
258 pci_set_flags(PCI_CAN_SKIP_ISA_ALIGN);
260 /* We do not want to just probe */
263 /* OPAL absent, try POPAL first then RTAS detection of PHBs */
264 if (!firmware_has_feature(FW_FEATURE_OPAL)) {
265 #ifdef CONFIG_PPC_POWERNV_RTAS
266 init_pci_config_tokens();
267 find_and_init_phbs();
268 #endif /* CONFIG_PPC_POWERNV_RTAS */
270 /* OPAL is here, do our normal stuff */
272 /* Look for p5ioc2 IO-Hubs */
273 for_each_compatible_node(np, NULL, "ibm,p5ioc2")
274 pnv_pci_init_p5ioc2_hub(np);
277 /* Setup the linkage between OF nodes and PHBs */
280 /* Configure IOMMU DMA hooks */
281 ppc_md.pci_dma_dev_setup = pnv_pci_dma_dev_setup;
282 ppc_md.tce_build = pnv_tce_build;
283 ppc_md.tce_free = pnv_tce_free;
284 set_pci_dma_ops(&dma_iommu_ops);