1 #ifndef __POWERNV_PCI_H
2 #define __POWERNV_PCI_H
12 /* Precise PHB model for error management */
14 PNV_PHB_MODEL_UNKNOWN,
20 #define PNV_PCI_DIAG_BUF_SIZE 8192
21 #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */
22 #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */
23 #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */
24 #define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */
25 #define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */
26 #define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */
28 /* Data associated with a PE, including IOMMU tracking etc.. */
34 /* A PE can be associated with a single device or an
35 * entire bus (& children). In the former case, pdev
36 * is populated, in the later case, pbus is.
39 struct pci_dev *parent_dev;
44 /* Effective RID (device RID for a device PE and base bus
45 * RID with devfn 0 for a bus PE)
50 unsigned int pe_number;
52 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
53 struct iommu_table_group table_group;
55 /* 64-bit TCE bypass region */
56 bool tce_bypass_enabled;
57 uint64_t tce_bypass_base;
59 /* MSIs. MVE index is identical for for 32 and 64 bit MSI
60 * and -1 if not supported. (It's actually identical to the
65 /* PEs in compound case */
66 struct pnv_ioda_pe *master;
67 struct list_head slaves;
69 /* Link in list of PE#s */
70 struct list_head list;
73 #define PNV_PHB_FLAG_EEH (1 << 0)
76 struct pci_controller *hose;
77 enum pnv_phb_type type;
78 enum pnv_phb_model model;
86 #ifdef CONFIG_DEBUG_FS
92 unsigned int msi_base;
93 unsigned int msi32_support;
94 struct msi_bitmap msi_bmp;
96 int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev,
97 unsigned int hwirq, unsigned int virq,
98 unsigned int is_64, struct msi_msg *msg);
99 void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
100 void (*fixup_phb)(struct pci_controller *hose);
101 int (*init_m64)(struct pnv_phb *phb);
102 void (*reserve_m64_pe)(struct pci_bus *bus,
103 unsigned long *pe_bitmap, bool all);
104 struct pnv_ioda_pe *(*pick_m64_pe)(struct pci_bus *bus, bool all);
105 int (*get_pe_state)(struct pnv_phb *phb, int pe_no);
106 void (*freeze_pe)(struct pnv_phb *phb, int pe_no);
107 int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt);
110 /* Global bridge info */
111 unsigned int total_pe_num;
112 unsigned int reserved_pe_idx;
114 /* 32-bit MMIO window */
115 unsigned int m32_size;
116 unsigned int m32_segsize;
117 unsigned int m32_pci_base;
119 /* 64-bit MMIO window */
120 unsigned int m64_bar_idx;
121 unsigned long m64_size;
122 unsigned long m64_segsize;
123 unsigned long m64_base;
124 unsigned long m64_bar_alloc;
127 unsigned int io_size;
128 unsigned int io_segsize;
129 unsigned int io_pci_base;
132 struct mutex pe_alloc_mutex;
133 unsigned long *pe_alloc;
134 struct pnv_ioda_pe *pe_array;
136 /* M32 & IO segment maps */
137 unsigned int *m64_segmap;
138 unsigned int *m32_segmap;
139 unsigned int *io_segmap;
141 /* DMA32 segment maps - IODA1 only */
142 unsigned int dma32_count;
143 unsigned int *dma32_segmap;
147 struct irq_chip irq_chip;
149 /* Sorted list of used PE's based
150 * on the sequence of creation
152 struct list_head pe_list;
153 struct mutex pe_list_mutex;
155 /* Reverse map of PEs, indexed by {bus, devfn} */
156 unsigned int pe_rmap[0x10000];
158 /* TCE cache invalidate registers (physical and
161 phys_addr_t tce_inval_reg_phys;
162 __be64 __iomem *tce_inval_reg;
165 /* PHB and hub status structure */
167 unsigned char blob[PNV_PCI_DIAG_BUF_SIZE];
168 struct OpalIoP7IOCPhbErrorData p7ioc;
169 struct OpalIoPhb3ErrorData phb3;
170 struct OpalIoP7IOCErrorData hub_diag;
175 extern struct pci_ops pnv_pci_ops;
176 extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
177 unsigned long uaddr, enum dma_data_direction direction,
178 struct dma_attrs *attrs);
179 extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages);
180 extern int pnv_tce_xchg(struct iommu_table *tbl, long index,
181 unsigned long *hpa, enum dma_data_direction *direction);
182 extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index);
184 void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
185 unsigned char *log_buff);
186 int pnv_pci_cfg_read(struct pci_dn *pdn,
187 int where, int size, u32 *val);
188 int pnv_pci_cfg_write(struct pci_dn *pdn,
189 int where, int size, u32 val);
190 extern struct iommu_table *pnv_pci_table_alloc(int nid);
192 extern long pnv_pci_link_table_and_group(int node, int num,
193 struct iommu_table *tbl,
194 struct iommu_table_group *table_group);
195 extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl,
196 struct iommu_table_group *table_group);
197 extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
198 void *tce_mem, u64 tce_size,
199 u64 dma_offset, unsigned page_shift);
200 extern void pnv_pci_init_ioda_hub(struct device_node *np);
201 extern void pnv_pci_init_ioda2_phb(struct device_node *np);
202 extern void pnv_pci_init_npu_phb(struct device_node *np);
203 extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl,
204 __be64 *startp, __be64 *endp, bool rm);
205 extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
206 extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);
208 extern void pnv_pci_dma_dev_setup(struct pci_dev *pdev);
209 extern void pnv_pci_dma_bus_setup(struct pci_bus *bus);
210 extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
211 extern void pnv_teardown_msi_irqs(struct pci_dev *pdev);
213 extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
214 const char *fmt, ...);
215 #define pe_err(pe, fmt, ...) \
216 pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__)
217 #define pe_warn(pe, fmt, ...) \
218 pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__)
219 #define pe_info(pe, fmt, ...) \
220 pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__)
222 /* Nvlink functions */
223 extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass);
224 extern void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm);
225 extern struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe);
226 extern long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num,
227 struct iommu_table *tbl);
228 extern long pnv_npu_unset_window(struct pnv_ioda_pe *npe, int num);
229 extern void pnv_npu_take_ownership(struct pnv_ioda_pe *npe);
230 extern void pnv_npu_release_ownership(struct pnv_ioda_pe *npe);
232 #endif /* __POWERNV_PCI_H */