2 * BPF Jit compiler for s390.
4 * Minimum build requirements:
6 * - HAVE_MARCH_Z196_FEATURES: laal, laalg
7 * - HAVE_MARCH_Z10_FEATURES: msfi, cgrj, clgrj
8 * - HAVE_MARCH_Z9_109_FEATURES: alfi, llilf, clfi, oilf, nilf
12 * Copyright IBM Corp. 2012,2015
14 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
15 * Michael Holzheu <holzheu@linux.vnet.ibm.com>
18 #define KMSG_COMPONENT "bpf_jit"
19 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
21 #include <linux/netdevice.h>
22 #include <linux/filter.h>
23 #include <linux/init.h>
24 #include <linux/bpf.h>
25 #include <asm/cacheflush.h>
29 int bpf_jit_enable __read_mostly;
32 u32 seen; /* Flags to remember seen eBPF instructions */
33 u32 seen_reg[16]; /* Array to remember which registers are used */
34 u32 *addrs; /* Array with relative instruction addresses */
35 u8 *prg_buf; /* Start of program */
36 int size; /* Size of program and literal pool */
37 int size_prg; /* Size of program */
38 int prg; /* Current position in program */
39 int lit_start; /* Start of literal pool */
40 int lit; /* Current position in literal pool */
41 int base_ip; /* Base address for literal pool */
42 int ret0_ip; /* Address of return 0 */
43 int exit_ip; /* Address of exit */
44 int tail_call_start; /* Tail call start offset */
45 int labels[1]; /* Labels for local jumps */
48 #define BPF_SIZE_MAX 0x7ffff /* Max size for program (20 bit signed displ) */
50 #define SEEN_SKB 1 /* skb access */
51 #define SEEN_MEM 2 /* use mem[] for temporary storage */
52 #define SEEN_RET0 4 /* ret0_ip points to a valid return 0 */
53 #define SEEN_LITERAL 8 /* code uses literals */
54 #define SEEN_FUNC 16 /* calls C functions */
55 #define SEEN_TAIL_CALL 32 /* code uses tail calls */
56 #define SEEN_SKB_CHANGE 64 /* code changes skb data */
57 #define SEEN_STACK (SEEN_FUNC | SEEN_MEM | SEEN_SKB)
62 #define REG_W0 (__MAX_BPF_REG+0) /* Work register 1 (even) */
63 #define REG_W1 (__MAX_BPF_REG+1) /* Work register 2 (odd) */
64 #define REG_SKB_DATA (__MAX_BPF_REG+2) /* SKB data register */
65 #define REG_L (__MAX_BPF_REG+3) /* Literal pool register */
66 #define REG_15 (__MAX_BPF_REG+4) /* Register 15 */
67 #define REG_0 REG_W0 /* Register 0 */
68 #define REG_1 REG_W1 /* Register 1 */
69 #define REG_2 BPF_REG_1 /* Register 2 */
70 #define REG_14 BPF_REG_0 /* Register 14 */
73 * Mapping of BPF registers to s390 registers
75 static const int reg2hex[] = {
78 /* Function parameters */
84 /* Call saved registers */
89 /* BPF stack pointer */
91 /* SKB data pointer */
93 /* Work registers for s390x backend */
100 static inline u32 reg(u32 dst_reg, u32 src_reg)
102 return reg2hex[dst_reg] << 4 | reg2hex[src_reg];
105 static inline u32 reg_high(u32 reg)
107 return reg2hex[reg] << 4;
110 static inline void reg_set_seen(struct bpf_jit *jit, u32 b1)
112 u32 r1 = reg2hex[b1];
114 if (!jit->seen_reg[r1] && r1 >= 6 && r1 <= 15)
115 jit->seen_reg[r1] = 1;
118 #define REG_SET_SEEN(b1) \
120 reg_set_seen(jit, b1); \
123 #define REG_SEEN(b1) jit->seen_reg[reg2hex[(b1)]]
126 * EMIT macros for code generation
132 *(u16 *) (jit->prg_buf + jit->prg) = op; \
136 #define EMIT2(op, b1, b2) \
138 _EMIT2(op | reg(b1, b2)); \
146 *(u32 *) (jit->prg_buf + jit->prg) = op; \
150 #define EMIT4(op, b1, b2) \
152 _EMIT4(op | reg(b1, b2)); \
157 #define EMIT4_RRF(op, b1, b2, b3) \
159 _EMIT4(op | reg_high(b3) << 8 | reg(b1, b2)); \
165 #define _EMIT4_DISP(op, disp) \
167 unsigned int __disp = (disp) & 0xfff; \
168 _EMIT4(op | __disp); \
171 #define EMIT4_DISP(op, b1, b2, disp) \
173 _EMIT4_DISP(op | reg_high(b1) << 16 | \
174 reg_high(b2) << 8, disp); \
179 #define EMIT4_IMM(op, b1, imm) \
181 unsigned int __imm = (imm) & 0xffff; \
182 _EMIT4(op | reg_high(b1) << 16 | __imm); \
186 #define EMIT4_PCREL(op, pcrel) \
188 long __pcrel = ((pcrel) >> 1) & 0xffff; \
189 _EMIT4(op | __pcrel); \
192 #define _EMIT6(op1, op2) \
194 if (jit->prg_buf) { \
195 *(u32 *) (jit->prg_buf + jit->prg) = op1; \
196 *(u16 *) (jit->prg_buf + jit->prg + 4) = op2; \
201 #define _EMIT6_DISP(op1, op2, disp) \
203 unsigned int __disp = (disp) & 0xfff; \
204 _EMIT6(op1 | __disp, op2); \
207 #define _EMIT6_DISP_LH(op1, op2, disp) \
209 u32 _disp = (u32) disp; \
210 unsigned int __disp_h = _disp & 0xff000; \
211 unsigned int __disp_l = _disp & 0x00fff; \
212 _EMIT6(op1 | __disp_l, op2 | __disp_h >> 4); \
215 #define EMIT6_DISP_LH(op1, op2, b1, b2, b3, disp) \
217 _EMIT6_DISP_LH(op1 | reg(b1, b2) << 16 | \
218 reg_high(b3) << 8, op2, disp); \
224 #define EMIT6_PCREL_LABEL(op1, op2, b1, b2, label, mask) \
226 int rel = (jit->labels[label] - jit->prg) >> 1; \
227 _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), \
233 #define EMIT6_PCREL_IMM_LABEL(op1, op2, b1, imm, label, mask) \
235 int rel = (jit->labels[label] - jit->prg) >> 1; \
236 _EMIT6(op1 | (reg_high(b1) | mask) << 16 | \
237 (rel & 0xffff), op2 | (imm & 0xff) << 8); \
239 BUILD_BUG_ON(((unsigned long) imm) > 0xff); \
242 #define EMIT6_PCREL(op1, op2, b1, b2, i, off, mask) \
244 /* Branch instruction needs 6 bytes */ \
245 int rel = (addrs[i + off + 1] - (addrs[i + 1] - 6)) / 2;\
246 _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), op2 | mask); \
251 #define _EMIT6_IMM(op, imm) \
253 unsigned int __imm = (imm); \
254 _EMIT6(op | (__imm >> 16), __imm & 0xffff); \
257 #define EMIT6_IMM(op, b1, imm) \
259 _EMIT6_IMM(op | reg_high(b1) << 16, imm); \
263 #define EMIT_CONST_U32(val) \
266 ret = jit->lit - jit->base_ip; \
267 jit->seen |= SEEN_LITERAL; \
269 *(u32 *) (jit->prg_buf + jit->lit) = (u32) val; \
274 #define EMIT_CONST_U64(val) \
277 ret = jit->lit - jit->base_ip; \
278 jit->seen |= SEEN_LITERAL; \
280 *(u64 *) (jit->prg_buf + jit->lit) = (u64) val; \
285 #define EMIT_ZERO(b1) \
287 /* llgfr %dst,%dst (zero extend to 64 bit) */ \
288 EMIT4(0xb9160000, b1, b1); \
293 * Fill whole space with illegal instructions
295 static void jit_fill_hole(void *area, unsigned int size)
297 memset(area, 0, size);
301 * Save registers from "rs" (register start) to "re" (register end) on stack
303 static void save_regs(struct bpf_jit *jit, u32 rs, u32 re)
305 u32 off = STK_OFF_R6 + (rs - 6) * 8;
308 /* stg %rs,off(%r15) */
309 _EMIT6(0xe300f000 | rs << 20 | off, 0x0024);
311 /* stmg %rs,%re,off(%r15) */
312 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0024, off);
316 * Restore registers from "rs" (register start) to "re" (register end) on stack
318 static void restore_regs(struct bpf_jit *jit, u32 rs, u32 re)
320 u32 off = STK_OFF_R6 + (rs - 6) * 8;
322 if (jit->seen & SEEN_STACK)
326 /* lg %rs,off(%r15) */
327 _EMIT6(0xe300f000 | rs << 20 | off, 0x0004);
329 /* lmg %rs,%re,off(%r15) */
330 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0004, off);
334 * Return first seen register (from start)
336 static int get_start(struct bpf_jit *jit, int start)
340 for (i = start; i <= 15; i++) {
341 if (jit->seen_reg[i])
348 * Return last seen register (from start) (gap >= 2)
350 static int get_end(struct bpf_jit *jit, int start)
354 for (i = start; i < 15; i++) {
355 if (!jit->seen_reg[i] && !jit->seen_reg[i + 1])
358 return jit->seen_reg[15] ? 15 : 14;
362 #define REGS_RESTORE 0
364 * Save and restore clobbered registers (6-15) on stack.
365 * We save/restore registers in chunks with gap >= 2 registers.
367 static void save_restore_regs(struct bpf_jit *jit, int op)
373 rs = get_start(jit, re);
376 re = get_end(jit, rs + 1);
378 save_regs(jit, rs, re);
380 restore_regs(jit, rs, re);
386 * For SKB access %b1 contains the SKB pointer. For "bpf_jit.S"
387 * we store the SKB header length on the stack and the SKB data
388 * pointer in REG_SKB_DATA.
390 static void emit_load_skb_data_hlen(struct bpf_jit *jit)
392 /* Header length: llgf %w1,<len>(%b1) */
393 EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1, REG_0, BPF_REG_1,
394 offsetof(struct sk_buff, len));
395 /* s %w1,<data_len>(%b1) */
396 EMIT4_DISP(0x5b000000, REG_W1, BPF_REG_1,
397 offsetof(struct sk_buff, data_len));
398 /* stg %w1,ST_OFF_HLEN(%r0,%r15) */
399 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0, REG_15, STK_OFF_HLEN);
400 /* lg %skb_data,data_off(%b1) */
401 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_SKB_DATA, REG_0,
402 BPF_REG_1, offsetof(struct sk_buff, data));
406 * Emit function prologue
408 * Save registers and create stack frame if necessary.
409 * See stack frame layout desription in "bpf_jit.h"!
411 static void bpf_jit_prologue(struct bpf_jit *jit)
413 if (jit->seen & SEEN_TAIL_CALL) {
414 /* xc STK_OFF_TCCNT(4,%r15),STK_OFF_TCCNT(%r15) */
415 _EMIT6(0xd703f000 | STK_OFF_TCCNT, 0xf000 | STK_OFF_TCCNT);
417 /* j tail_call_start: NOP if no tail calls are used */
418 EMIT4_PCREL(0xa7f40000, 6);
421 /* Tail calls have to skip above initialization */
422 jit->tail_call_start = jit->prg;
424 save_restore_regs(jit, REGS_SAVE);
425 /* Setup literal pool */
426 if (jit->seen & SEEN_LITERAL) {
428 EMIT2(0x0d00, REG_L, REG_0);
429 jit->base_ip = jit->prg;
431 /* Setup stack and backchain */
432 if (jit->seen & SEEN_STACK) {
433 if (jit->seen & SEEN_FUNC)
434 /* lgr %w1,%r15 (backchain) */
435 EMIT4(0xb9040000, REG_W1, REG_15);
436 /* la %bfp,STK_160_UNUSED(%r15) (BPF frame pointer) */
437 EMIT4_DISP(0x41000000, BPF_REG_FP, REG_15, STK_160_UNUSED);
438 /* aghi %r15,-STK_OFF */
439 EMIT4_IMM(0xa70b0000, REG_15, -STK_OFF);
440 if (jit->seen & SEEN_FUNC)
441 /* stg %w1,152(%r15) (backchain) */
442 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0,
445 if (jit->seen & SEEN_SKB)
446 emit_load_skb_data_hlen(jit);
447 if (jit->seen & SEEN_SKB_CHANGE)
448 /* stg %b1,ST_OFF_SKBP(%r0,%r15) */
449 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0, REG_15,
456 static void bpf_jit_epilogue(struct bpf_jit *jit)
459 if (jit->seen & SEEN_RET0) {
460 jit->ret0_ip = jit->prg;
462 EMIT4_IMM(0xa7090000, BPF_REG_0, 0);
464 jit->exit_ip = jit->prg;
465 /* Load exit code: lgr %r2,%b0 */
466 EMIT4(0xb9040000, REG_2, BPF_REG_0);
467 /* Restore registers */
468 save_restore_regs(jit, REGS_RESTORE);
474 * Compile one eBPF instruction into s390x code
476 * NOTE: Use noinline because for gcov (-fprofile-arcs) gcc allocates a lot of
477 * stack space for the large switch statement.
479 static noinline int bpf_jit_insn(struct bpf_jit *jit, struct bpf_prog *fp, int i)
481 struct bpf_insn *insn = &fp->insnsi[i];
482 int jmp_off, last, insn_count = 1;
483 unsigned int func_addr, mask;
484 u32 dst_reg = insn->dst_reg;
485 u32 src_reg = insn->src_reg;
486 u32 *addrs = jit->addrs;
490 switch (insn->code) {
494 case BPF_ALU | BPF_MOV | BPF_X: /* dst = (u32) src */
495 /* llgfr %dst,%src */
496 EMIT4(0xb9160000, dst_reg, src_reg);
498 case BPF_ALU64 | BPF_MOV | BPF_X: /* dst = src */
500 EMIT4(0xb9040000, dst_reg, src_reg);
502 case BPF_ALU | BPF_MOV | BPF_K: /* dst = (u32) imm */
504 EMIT6_IMM(0xc00f0000, dst_reg, imm);
506 case BPF_ALU64 | BPF_MOV | BPF_K: /* dst = imm */
508 EMIT6_IMM(0xc0010000, dst_reg, imm);
513 case BPF_LD | BPF_IMM | BPF_DW: /* dst = (u64) imm */
515 /* 16 byte instruction that uses two 'struct bpf_insn' */
518 imm64 = (u64)(u32) insn[0].imm | ((u64)(u32) insn[1].imm) << 32;
519 /* lg %dst,<d(imm)>(%l) */
520 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, REG_0, REG_L,
521 EMIT_CONST_U64(imm64));
528 case BPF_ALU | BPF_ADD | BPF_X: /* dst = (u32) dst + (u32) src */
530 EMIT2(0x1a00, dst_reg, src_reg);
533 case BPF_ALU64 | BPF_ADD | BPF_X: /* dst = dst + src */
535 EMIT4(0xb9080000, dst_reg, src_reg);
537 case BPF_ALU | BPF_ADD | BPF_K: /* dst = (u32) dst + (u32) imm */
541 EMIT6_IMM(0xc20b0000, dst_reg, imm);
544 case BPF_ALU64 | BPF_ADD | BPF_K: /* dst = dst + imm */
548 EMIT6_IMM(0xc2080000, dst_reg, imm);
553 case BPF_ALU | BPF_SUB | BPF_X: /* dst = (u32) dst - (u32) src */
555 EMIT2(0x1b00, dst_reg, src_reg);
558 case BPF_ALU64 | BPF_SUB | BPF_X: /* dst = dst - src */
560 EMIT4(0xb9090000, dst_reg, src_reg);
562 case BPF_ALU | BPF_SUB | BPF_K: /* dst = (u32) dst - (u32) imm */
566 EMIT6_IMM(0xc20b0000, dst_reg, -imm);
569 case BPF_ALU64 | BPF_SUB | BPF_K: /* dst = dst - imm */
573 EMIT6_IMM(0xc2080000, dst_reg, -imm);
578 case BPF_ALU | BPF_MUL | BPF_X: /* dst = (u32) dst * (u32) src */
580 EMIT4(0xb2520000, dst_reg, src_reg);
583 case BPF_ALU64 | BPF_MUL | BPF_X: /* dst = dst * src */
585 EMIT4(0xb90c0000, dst_reg, src_reg);
587 case BPF_ALU | BPF_MUL | BPF_K: /* dst = (u32) dst * (u32) imm */
591 EMIT6_IMM(0xc2010000, dst_reg, imm);
594 case BPF_ALU64 | BPF_MUL | BPF_K: /* dst = dst * imm */
598 EMIT6_IMM(0xc2000000, dst_reg, imm);
603 case BPF_ALU | BPF_DIV | BPF_X: /* dst = (u32) dst / (u32) src */
604 case BPF_ALU | BPF_MOD | BPF_X: /* dst = (u32) dst % (u32) src */
606 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
608 jit->seen |= SEEN_RET0;
609 /* ltr %src,%src (if src == 0 goto fail) */
610 EMIT2(0x1200, src_reg, src_reg);
612 EMIT4_PCREL(0xa7840000, jit->ret0_ip - jit->prg);
614 EMIT4_IMM(0xa7080000, REG_W0, 0);
616 EMIT2(0x1800, REG_W1, dst_reg);
618 EMIT4(0xb9970000, REG_W0, src_reg);
620 EMIT4(0xb9160000, dst_reg, rc_reg);
623 case BPF_ALU64 | BPF_DIV | BPF_X: /* dst = dst / src */
624 case BPF_ALU64 | BPF_MOD | BPF_X: /* dst = dst % src */
626 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
628 jit->seen |= SEEN_RET0;
629 /* ltgr %src,%src (if src == 0 goto fail) */
630 EMIT4(0xb9020000, src_reg, src_reg);
632 EMIT4_PCREL(0xa7840000, jit->ret0_ip - jit->prg);
634 EMIT4_IMM(0xa7090000, REG_W0, 0);
636 EMIT4(0xb9040000, REG_W1, dst_reg);
638 EMIT4(0xb9870000, REG_W0, src_reg);
640 EMIT4(0xb9040000, dst_reg, rc_reg);
643 case BPF_ALU | BPF_DIV | BPF_K: /* dst = (u32) dst / (u32) imm */
644 case BPF_ALU | BPF_MOD | BPF_K: /* dst = (u32) dst % (u32) imm */
646 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
649 if (BPF_OP(insn->code) == BPF_MOD)
651 EMIT4_IMM(0xa7090000, dst_reg, 0);
655 EMIT4_IMM(0xa7080000, REG_W0, 0);
657 EMIT2(0x1800, REG_W1, dst_reg);
658 /* dl %w0,<d(imm)>(%l) */
659 EMIT6_DISP_LH(0xe3000000, 0x0097, REG_W0, REG_0, REG_L,
660 EMIT_CONST_U32(imm));
662 EMIT4(0xb9160000, dst_reg, rc_reg);
665 case BPF_ALU64 | BPF_DIV | BPF_K: /* dst = dst / imm */
666 case BPF_ALU64 | BPF_MOD | BPF_K: /* dst = dst % imm */
668 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
671 if (BPF_OP(insn->code) == BPF_MOD)
673 EMIT4_IMM(0xa7090000, dst_reg, 0);
677 EMIT4_IMM(0xa7090000, REG_W0, 0);
679 EMIT4(0xb9040000, REG_W1, dst_reg);
680 /* dlg %w0,<d(imm)>(%l) */
681 EMIT6_DISP_LH(0xe3000000, 0x0087, REG_W0, REG_0, REG_L,
682 EMIT_CONST_U64(imm));
684 EMIT4(0xb9040000, dst_reg, rc_reg);
690 case BPF_ALU | BPF_AND | BPF_X: /* dst = (u32) dst & (u32) src */
692 EMIT2(0x1400, dst_reg, src_reg);
695 case BPF_ALU64 | BPF_AND | BPF_X: /* dst = dst & src */
697 EMIT4(0xb9800000, dst_reg, src_reg);
699 case BPF_ALU | BPF_AND | BPF_K: /* dst = (u32) dst & (u32) imm */
701 EMIT6_IMM(0xc00b0000, dst_reg, imm);
704 case BPF_ALU64 | BPF_AND | BPF_K: /* dst = dst & imm */
705 /* ng %dst,<d(imm)>(%l) */
706 EMIT6_DISP_LH(0xe3000000, 0x0080, dst_reg, REG_0, REG_L,
707 EMIT_CONST_U64(imm));
712 case BPF_ALU | BPF_OR | BPF_X: /* dst = (u32) dst | (u32) src */
714 EMIT2(0x1600, dst_reg, src_reg);
717 case BPF_ALU64 | BPF_OR | BPF_X: /* dst = dst | src */
719 EMIT4(0xb9810000, dst_reg, src_reg);
721 case BPF_ALU | BPF_OR | BPF_K: /* dst = (u32) dst | (u32) imm */
723 EMIT6_IMM(0xc00d0000, dst_reg, imm);
726 case BPF_ALU64 | BPF_OR | BPF_K: /* dst = dst | imm */
727 /* og %dst,<d(imm)>(%l) */
728 EMIT6_DISP_LH(0xe3000000, 0x0081, dst_reg, REG_0, REG_L,
729 EMIT_CONST_U64(imm));
734 case BPF_ALU | BPF_XOR | BPF_X: /* dst = (u32) dst ^ (u32) src */
736 EMIT2(0x1700, dst_reg, src_reg);
739 case BPF_ALU64 | BPF_XOR | BPF_X: /* dst = dst ^ src */
741 EMIT4(0xb9820000, dst_reg, src_reg);
743 case BPF_ALU | BPF_XOR | BPF_K: /* dst = (u32) dst ^ (u32) imm */
747 EMIT6_IMM(0xc0070000, dst_reg, imm);
750 case BPF_ALU64 | BPF_XOR | BPF_K: /* dst = dst ^ imm */
751 /* xg %dst,<d(imm)>(%l) */
752 EMIT6_DISP_LH(0xe3000000, 0x0082, dst_reg, REG_0, REG_L,
753 EMIT_CONST_U64(imm));
758 case BPF_ALU | BPF_LSH | BPF_X: /* dst = (u32) dst << (u32) src */
759 /* sll %dst,0(%src) */
760 EMIT4_DISP(0x89000000, dst_reg, src_reg, 0);
763 case BPF_ALU64 | BPF_LSH | BPF_X: /* dst = dst << src */
764 /* sllg %dst,%dst,0(%src) */
765 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, src_reg, 0);
767 case BPF_ALU | BPF_LSH | BPF_K: /* dst = (u32) dst << (u32) imm */
770 /* sll %dst,imm(%r0) */
771 EMIT4_DISP(0x89000000, dst_reg, REG_0, imm);
774 case BPF_ALU64 | BPF_LSH | BPF_K: /* dst = dst << imm */
777 /* sllg %dst,%dst,imm(%r0) */
778 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, REG_0, imm);
783 case BPF_ALU | BPF_RSH | BPF_X: /* dst = (u32) dst >> (u32) src */
784 /* srl %dst,0(%src) */
785 EMIT4_DISP(0x88000000, dst_reg, src_reg, 0);
788 case BPF_ALU64 | BPF_RSH | BPF_X: /* dst = dst >> src */
789 /* srlg %dst,%dst,0(%src) */
790 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, src_reg, 0);
792 case BPF_ALU | BPF_RSH | BPF_K: /* dst = (u32) dst >> (u32) imm */
795 /* srl %dst,imm(%r0) */
796 EMIT4_DISP(0x88000000, dst_reg, REG_0, imm);
799 case BPF_ALU64 | BPF_RSH | BPF_K: /* dst = dst >> imm */
802 /* srlg %dst,%dst,imm(%r0) */
803 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, REG_0, imm);
808 case BPF_ALU64 | BPF_ARSH | BPF_X: /* ((s64) dst) >>= src */
809 /* srag %dst,%dst,0(%src) */
810 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, src_reg, 0);
812 case BPF_ALU64 | BPF_ARSH | BPF_K: /* ((s64) dst) >>= imm */
815 /* srag %dst,%dst,imm(%r0) */
816 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, REG_0, imm);
821 case BPF_ALU | BPF_NEG: /* dst = (u32) -dst */
823 EMIT2(0x1300, dst_reg, dst_reg);
826 case BPF_ALU64 | BPF_NEG: /* dst = -dst */
828 EMIT4(0xb9130000, dst_reg, dst_reg);
833 case BPF_ALU | BPF_END | BPF_FROM_BE:
834 /* s390 is big endian, therefore only clear high order bytes */
836 case 16: /* dst = (u16) cpu_to_be16(dst) */
837 /* llghr %dst,%dst */
838 EMIT4(0xb9850000, dst_reg, dst_reg);
840 case 32: /* dst = (u32) cpu_to_be32(dst) */
841 /* llgfr %dst,%dst */
842 EMIT4(0xb9160000, dst_reg, dst_reg);
844 case 64: /* dst = (u64) cpu_to_be64(dst) */
848 case BPF_ALU | BPF_END | BPF_FROM_LE:
850 case 16: /* dst = (u16) cpu_to_le16(dst) */
852 EMIT4(0xb91f0000, dst_reg, dst_reg);
853 /* srl %dst,16(%r0) */
854 EMIT4_DISP(0x88000000, dst_reg, REG_0, 16);
855 /* llghr %dst,%dst */
856 EMIT4(0xb9850000, dst_reg, dst_reg);
858 case 32: /* dst = (u32) cpu_to_le32(dst) */
860 EMIT4(0xb91f0000, dst_reg, dst_reg);
861 /* llgfr %dst,%dst */
862 EMIT4(0xb9160000, dst_reg, dst_reg);
864 case 64: /* dst = (u64) cpu_to_le64(dst) */
865 /* lrvgr %dst,%dst */
866 EMIT4(0xb90f0000, dst_reg, dst_reg);
873 case BPF_STX | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = src_reg */
874 /* stcy %src,off(%dst) */
875 EMIT6_DISP_LH(0xe3000000, 0x0072, src_reg, dst_reg, REG_0, off);
876 jit->seen |= SEEN_MEM;
878 case BPF_STX | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = src */
879 /* sthy %src,off(%dst) */
880 EMIT6_DISP_LH(0xe3000000, 0x0070, src_reg, dst_reg, REG_0, off);
881 jit->seen |= SEEN_MEM;
883 case BPF_STX | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = src */
884 /* sty %src,off(%dst) */
885 EMIT6_DISP_LH(0xe3000000, 0x0050, src_reg, dst_reg, REG_0, off);
886 jit->seen |= SEEN_MEM;
888 case BPF_STX | BPF_MEM | BPF_DW: /* (u64 *)(dst + off) = src */
889 /* stg %src,off(%dst) */
890 EMIT6_DISP_LH(0xe3000000, 0x0024, src_reg, dst_reg, REG_0, off);
891 jit->seen |= SEEN_MEM;
893 case BPF_ST | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = imm */
895 EMIT4_IMM(0xa7080000, REG_W0, (u8) imm);
896 /* stcy %w0,off(dst) */
897 EMIT6_DISP_LH(0xe3000000, 0x0072, REG_W0, dst_reg, REG_0, off);
898 jit->seen |= SEEN_MEM;
900 case BPF_ST | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = imm */
902 EMIT4_IMM(0xa7080000, REG_W0, (u16) imm);
903 /* sthy %w0,off(dst) */
904 EMIT6_DISP_LH(0xe3000000, 0x0070, REG_W0, dst_reg, REG_0, off);
905 jit->seen |= SEEN_MEM;
907 case BPF_ST | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = imm */
909 EMIT6_IMM(0xc00f0000, REG_W0, (u32) imm);
910 /* sty %w0,off(%dst) */
911 EMIT6_DISP_LH(0xe3000000, 0x0050, REG_W0, dst_reg, REG_0, off);
912 jit->seen |= SEEN_MEM;
914 case BPF_ST | BPF_MEM | BPF_DW: /* *(u64 *)(dst + off) = imm */
916 EMIT6_IMM(0xc0010000, REG_W0, imm);
917 /* stg %w0,off(%dst) */
918 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W0, dst_reg, REG_0, off);
919 jit->seen |= SEEN_MEM;
922 * BPF_STX XADD (atomic_add)
924 case BPF_STX | BPF_XADD | BPF_W: /* *(u32 *)(dst + off) += src */
925 /* laal %w0,%src,off(%dst) */
926 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W0, src_reg,
928 jit->seen |= SEEN_MEM;
930 case BPF_STX | BPF_XADD | BPF_DW: /* *(u64 *)(dst + off) += src */
931 /* laalg %w0,%src,off(%dst) */
932 EMIT6_DISP_LH(0xeb000000, 0x00ea, REG_W0, src_reg,
934 jit->seen |= SEEN_MEM;
939 case BPF_LDX | BPF_MEM | BPF_B: /* dst = *(u8 *)(ul) (src + off) */
940 /* llgc %dst,0(off,%src) */
941 EMIT6_DISP_LH(0xe3000000, 0x0090, dst_reg, src_reg, REG_0, off);
942 jit->seen |= SEEN_MEM;
944 case BPF_LDX | BPF_MEM | BPF_H: /* dst = *(u16 *)(ul) (src + off) */
945 /* llgh %dst,0(off,%src) */
946 EMIT6_DISP_LH(0xe3000000, 0x0091, dst_reg, src_reg, REG_0, off);
947 jit->seen |= SEEN_MEM;
949 case BPF_LDX | BPF_MEM | BPF_W: /* dst = *(u32 *)(ul) (src + off) */
950 /* llgf %dst,off(%src) */
951 jit->seen |= SEEN_MEM;
952 EMIT6_DISP_LH(0xe3000000, 0x0016, dst_reg, src_reg, REG_0, off);
954 case BPF_LDX | BPF_MEM | BPF_DW: /* dst = *(u64 *)(ul) (src + off) */
955 /* lg %dst,0(off,%src) */
956 jit->seen |= SEEN_MEM;
957 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, src_reg, REG_0, off);
962 case BPF_JMP | BPF_CALL:
965 * b0 = (__bpf_call_base + imm)(b1, b2, b3, b4, b5)
967 const u64 func = (u64)__bpf_call_base + imm;
969 REG_SET_SEEN(BPF_REG_5);
970 jit->seen |= SEEN_FUNC;
971 /* lg %w1,<d(imm)>(%l) */
972 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_W1, REG_0, REG_L,
973 EMIT_CONST_U64(func));
975 EMIT2(0x0d00, REG_14, REG_W1);
976 /* lgr %b0,%r2: load return value into %b0 */
977 EMIT4(0xb9040000, BPF_REG_0, REG_2);
978 if (bpf_helper_changes_skb_data((void *)func)) {
979 jit->seen |= SEEN_SKB_CHANGE;
980 /* lg %b1,ST_OFF_SKBP(%r15) */
981 EMIT6_DISP_LH(0xe3000000, 0x0004, BPF_REG_1, REG_0,
982 REG_15, STK_OFF_SKBP);
983 emit_load_skb_data_hlen(jit);
987 case BPF_JMP | BPF_CALL | BPF_X:
991 * B2: pointer to bpf_array
992 * B3: index in bpf_array
994 jit->seen |= SEEN_TAIL_CALL;
997 * if (index >= array->map.max_entries)
1001 /* llgf %w1,map.max_entries(%b2) */
1002 EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1, REG_0, BPF_REG_2,
1003 offsetof(struct bpf_array, map.max_entries));
1004 /* clgrj %b3,%w1,0xa,label0: if %b3 >= %w1 goto out */
1005 EMIT6_PCREL_LABEL(0xec000000, 0x0065, BPF_REG_3,
1009 * if (tail_call_cnt++ > MAX_TAIL_CALL_CNT)
1013 if (jit->seen & SEEN_STACK)
1014 off = STK_OFF_TCCNT + STK_OFF;
1016 off = STK_OFF_TCCNT;
1018 EMIT4_IMM(0xa7080000, REG_W0, 1);
1019 /* laal %w1,%w0,off(%r15) */
1020 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W1, REG_W0, REG_15, off);
1021 /* clij %w1,MAX_TAIL_CALL_CNT,0x2,label0 */
1022 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007f, REG_W1,
1023 MAX_TAIL_CALL_CNT, 0, 0x2);
1026 * prog = array->ptrs[index];
1031 /* sllg %r1,%b3,3: %r1 = index * 8 */
1032 EMIT6_DISP_LH(0xeb000000, 0x000d, REG_1, BPF_REG_3, REG_0, 3);
1033 /* lg %r1,prog(%b2,%r1) */
1034 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, BPF_REG_2,
1035 REG_1, offsetof(struct bpf_array, ptrs));
1036 /* clgij %r1,0,0x8,label0 */
1037 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007d, REG_1, 0, 0, 0x8);
1040 * Restore registers before calling function
1042 save_restore_regs(jit, REGS_RESTORE);
1045 * goto *(prog->bpf_func + tail_call_start);
1048 /* lg %r1,bpf_func(%r1) */
1049 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, REG_1, REG_0,
1050 offsetof(struct bpf_prog, bpf_func));
1051 /* bc 0xf,tail_call_start(%r1) */
1052 _EMIT4(0x47f01000 + jit->tail_call_start);
1054 jit->labels[0] = jit->prg;
1056 case BPF_JMP | BPF_EXIT: /* return b0 */
1057 last = (i == fp->len - 1) ? 1 : 0;
1058 if (last && !(jit->seen & SEEN_RET0))
1061 EMIT4_PCREL(0xa7f40000, jit->exit_ip - jit->prg);
1064 * Branch relative (number of skipped instructions) to offset on
1067 * Condition code to mask mapping:
1069 * CC | Description | Mask
1070 * ------------------------------
1071 * 0 | Operands equal | 8
1072 * 1 | First operand low | 4
1073 * 2 | First operand high | 2
1076 * For s390x relative branches: ip = ip + off_bytes
1077 * For BPF relative branches: insn = insn + off_insns + 1
1079 * For example for s390x with offset 0 we jump to the branch
1080 * instruction itself (loop) and for BPF with offset 0 we
1081 * branch to the instruction behind the branch.
1083 case BPF_JMP | BPF_JA: /* if (true) */
1084 mask = 0xf000; /* j */
1086 case BPF_JMP | BPF_JSGT | BPF_K: /* ((s64) dst > (s64) imm) */
1087 mask = 0x2000; /* jh */
1089 case BPF_JMP | BPF_JSGE | BPF_K: /* ((s64) dst >= (s64) imm) */
1090 mask = 0xa000; /* jhe */
1092 case BPF_JMP | BPF_JGT | BPF_K: /* (dst_reg > imm) */
1093 mask = 0x2000; /* jh */
1095 case BPF_JMP | BPF_JGE | BPF_K: /* (dst_reg >= imm) */
1096 mask = 0xa000; /* jhe */
1098 case BPF_JMP | BPF_JNE | BPF_K: /* (dst_reg != imm) */
1099 mask = 0x7000; /* jne */
1101 case BPF_JMP | BPF_JEQ | BPF_K: /* (dst_reg == imm) */
1102 mask = 0x8000; /* je */
1104 case BPF_JMP | BPF_JSET | BPF_K: /* (dst_reg & imm) */
1105 mask = 0x7000; /* jnz */
1106 /* lgfi %w1,imm (load sign extend imm) */
1107 EMIT6_IMM(0xc0010000, REG_W1, imm);
1109 EMIT4(0xb9800000, REG_W1, dst_reg);
1112 case BPF_JMP | BPF_JSGT | BPF_X: /* ((s64) dst > (s64) src) */
1113 mask = 0x2000; /* jh */
1115 case BPF_JMP | BPF_JSGE | BPF_X: /* ((s64) dst >= (s64) src) */
1116 mask = 0xa000; /* jhe */
1118 case BPF_JMP | BPF_JGT | BPF_X: /* (dst > src) */
1119 mask = 0x2000; /* jh */
1121 case BPF_JMP | BPF_JGE | BPF_X: /* (dst >= src) */
1122 mask = 0xa000; /* jhe */
1124 case BPF_JMP | BPF_JNE | BPF_X: /* (dst != src) */
1125 mask = 0x7000; /* jne */
1127 case BPF_JMP | BPF_JEQ | BPF_X: /* (dst == src) */
1128 mask = 0x8000; /* je */
1130 case BPF_JMP | BPF_JSET | BPF_X: /* (dst & src) */
1131 mask = 0x7000; /* jnz */
1132 /* ngrk %w1,%dst,%src */
1133 EMIT4_RRF(0xb9e40000, REG_W1, dst_reg, src_reg);
1136 /* lgfi %w1,imm (load sign extend imm) */
1137 EMIT6_IMM(0xc0010000, REG_W1, imm);
1138 /* cgrj %dst,%w1,mask,off */
1139 EMIT6_PCREL(0xec000000, 0x0064, dst_reg, REG_W1, i, off, mask);
1142 /* lgfi %w1,imm (load sign extend imm) */
1143 EMIT6_IMM(0xc0010000, REG_W1, imm);
1144 /* clgrj %dst,%w1,mask,off */
1145 EMIT6_PCREL(0xec000000, 0x0065, dst_reg, REG_W1, i, off, mask);
1148 /* cgrj %dst,%src,mask,off */
1149 EMIT6_PCREL(0xec000000, 0x0064, dst_reg, src_reg, i, off, mask);
1152 /* clgrj %dst,%src,mask,off */
1153 EMIT6_PCREL(0xec000000, 0x0065, dst_reg, src_reg, i, off, mask);
1156 /* brc mask,jmp_off (branch instruction needs 4 bytes) */
1157 jmp_off = addrs[i + off + 1] - (addrs[i + 1] - 4);
1158 EMIT4_PCREL(0xa7040000 | mask << 8, jmp_off);
1163 case BPF_LD | BPF_ABS | BPF_B: /* b0 = *(u8 *) (skb->data+imm) */
1164 case BPF_LD | BPF_IND | BPF_B: /* b0 = *(u8 *) (skb->data+imm+src) */
1165 if ((BPF_MODE(insn->code) == BPF_ABS) && (imm >= 0))
1166 func_addr = __pa(sk_load_byte_pos);
1168 func_addr = __pa(sk_load_byte);
1170 case BPF_LD | BPF_ABS | BPF_H: /* b0 = *(u16 *) (skb->data+imm) */
1171 case BPF_LD | BPF_IND | BPF_H: /* b0 = *(u16 *) (skb->data+imm+src) */
1172 if ((BPF_MODE(insn->code) == BPF_ABS) && (imm >= 0))
1173 func_addr = __pa(sk_load_half_pos);
1175 func_addr = __pa(sk_load_half);
1177 case BPF_LD | BPF_ABS | BPF_W: /* b0 = *(u32 *) (skb->data+imm) */
1178 case BPF_LD | BPF_IND | BPF_W: /* b0 = *(u32 *) (skb->data+imm+src) */
1179 if ((BPF_MODE(insn->code) == BPF_ABS) && (imm >= 0))
1180 func_addr = __pa(sk_load_word_pos);
1182 func_addr = __pa(sk_load_word);
1185 jit->seen |= SEEN_SKB | SEEN_RET0 | SEEN_FUNC;
1186 REG_SET_SEEN(REG_14); /* Return address of possible func call */
1190 * BPF_REG_6 (R7) : skb pointer
1191 * REG_SKB_DATA (R12): skb data pointer
1194 * BPF_REG_2 (R3) : offset of byte(s) to fetch in skb
1195 * BPF_REG_5 (R6) : return address
1198 * BPF_REG_0 (R14): data read from skb
1200 * Scratch registers (BPF_REG_1-5)
1203 /* Call function: llilf %w1,func_addr */
1204 EMIT6_IMM(0xc00f0000, REG_W1, func_addr);
1206 /* Offset: lgfi %b2,imm */
1207 EMIT6_IMM(0xc0010000, BPF_REG_2, imm);
1208 if (BPF_MODE(insn->code) == BPF_IND)
1209 /* agfr %b2,%src (%src is s32 here) */
1210 EMIT4(0xb9180000, BPF_REG_2, src_reg);
1212 /* basr %b5,%w1 (%b5 is call saved) */
1213 EMIT2(0x0d00, BPF_REG_5, REG_W1);
1216 * Note: For fast access we jump directly after the
1217 * jnz instruction from bpf_jit.S
1220 EMIT4_PCREL(0xa7740000, jit->ret0_ip - jit->prg);
1222 default: /* too complex, give up */
1223 pr_err("Unknown opcode %02x\n", insn->code);
1230 * Compile eBPF program into s390x code
1232 static int bpf_jit_prog(struct bpf_jit *jit, struct bpf_prog *fp)
1236 jit->lit = jit->lit_start;
1239 bpf_jit_prologue(jit);
1240 for (i = 0; i < fp->len; i += insn_count) {
1241 insn_count = bpf_jit_insn(jit, fp, i);
1244 jit->addrs[i + 1] = jit->prg; /* Next instruction address */
1246 bpf_jit_epilogue(jit);
1248 jit->lit_start = jit->prg;
1249 jit->size = jit->lit;
1250 jit->size_prg = jit->prg;
1255 * Classic BPF function stub. BPF programs will be converted into
1256 * eBPF and then bpf_int_jit_compile() will be called.
1258 void bpf_jit_compile(struct bpf_prog *fp)
1263 * Compile eBPF program "fp"
1265 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *fp)
1267 struct bpf_binary_header *header;
1271 if (!bpf_jit_enable)
1274 memset(&jit, 0, sizeof(jit));
1275 jit.addrs = kcalloc(fp->len + 1, sizeof(*jit.addrs), GFP_KERNEL);
1276 if (jit.addrs == NULL)
1279 * Three initial passes:
1280 * - 1/2: Determine clobbered registers
1281 * - 3: Calculate program size and addrs arrray
1283 for (pass = 1; pass <= 3; pass++) {
1284 if (bpf_jit_prog(&jit, fp))
1288 * Final pass: Allocate and generate program
1290 if (jit.size >= BPF_SIZE_MAX)
1292 header = bpf_jit_binary_alloc(jit.size, &jit.prg_buf, 2, jit_fill_hole);
1295 if (bpf_jit_prog(&jit, fp))
1297 if (bpf_jit_enable > 1) {
1298 bpf_jit_dump(fp->len, jit.size, pass, jit.prg_buf);
1300 print_fn_code(jit.prg_buf, jit.size_prg);
1303 set_memory_ro((unsigned long)header, header->pages);
1304 fp->bpf_func = (void *) jit.prg_buf;
1315 void bpf_jit_free(struct bpf_prog *fp)
1317 unsigned long addr = (unsigned long)fp->bpf_func & PAGE_MASK;
1318 struct bpf_binary_header *header = (void *)addr;
1323 set_memory_rw(addr, header->pages);
1324 bpf_jit_binary_free(header);
1327 bpf_prog_unlock_free(fp);