arch/sh/kernel/cpu/sh4a/setup-sh7780.c

   1 /*
   2  * SH7780 Setup
   3  *
   4  *  Copyright (C) 2006  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/platform_device.h>
  11 #include <linux/init.h>
  12 #include <linux/serial.h>
  13 #include <linux/io.h>
  14 #include <linux/serial_sci.h>
  15 #include <linux/sh_timer.h>
  16
  17 static struct sh_timer_config tmu0_platform_data = {
  18         .name = "TMU0",
  19         .channel_offset = 0x04,
  20         .timer_bit = 0,
  21         .clk = "peripheral_clk",
  22         .clockevent_rating = 200,
  23 };
  24
  25 static struct resource tmu0_resources[] = {
  26         [0] = {
  27                 .name   = "TMU0",
  28                 .start  = 0xffd80008,
  29                 .end    = 0xffd80013,
  30                 .flags  = IORESOURCE_MEM,
  31         },
  32         [1] = {
  33                 .start  = 28,
  34                 .flags  = IORESOURCE_IRQ,
  35         },
  36 };
  37
  38 static struct platform_device tmu0_device = {
  39         .name           = "sh_tmu",
  40         .id             = 0,
  41         .dev = {
  42                 .platform_data  = &tmu0_platform_data,
  43         },
  44         .resource       = tmu0_resources,
  45         .num_resources  = ARRAY_SIZE(tmu0_resources),
  46 };
  47
  48 static struct sh_timer_config tmu1_platform_data = {
  49         .name = "TMU1",
  50         .channel_offset = 0x10,
  51         .timer_bit = 1,
  52         .clk = "peripheral_clk",
  53         .clocksource_rating = 200,
  54 };
  55
  56 static struct resource tmu1_resources[] = {
  57         [0] = {
  58                 .name   = "TMU1",
  59                 .start  = 0xffd80014,
  60                 .end    = 0xffd8001f,
  61                 .flags  = IORESOURCE_MEM,
  62         },
  63         [1] = {
  64                 .start  = 29,
  65                 .flags  = IORESOURCE_IRQ,
  66         },
  67 };
  68
  69 static struct platform_device tmu1_device = {
  70         .name           = "sh_tmu",
  71         .id             = 1,
  72         .dev = {
  73                 .platform_data  = &tmu1_platform_data,
  74         },
  75         .resource       = tmu1_resources,
  76         .num_resources  = ARRAY_SIZE(tmu1_resources),
  77 };
  78
  79 static struct sh_timer_config tmu2_platform_data = {
  80         .name = "TMU2",
  81         .channel_offset = 0x1c,
  82         .timer_bit = 2,
  83         .clk = "peripheral_clk",
  84 };
  85
  86 static struct resource tmu2_resources[] = {
  87         [0] = {
  88                 .name   = "TMU2",
  89                 .start  = 0xffd80020,
  90                 .end    = 0xffd8002f,
  91                 .flags  = IORESOURCE_MEM,
  92         },
  93         [1] = {
  94                 .start  = 30,
  95                 .flags  = IORESOURCE_IRQ,
  96         },
  97 };
  98
  99 static struct platform_device tmu2_device = {
 100         .name           = "sh_tmu",
 101         .id             = 2,
 102         .dev = {
 103                 .platform_data  = &tmu2_platform_data,
 104         },
 105         .resource       = tmu2_resources,
 106         .num_resources  = ARRAY_SIZE(tmu2_resources),
 107 };
 108
 109 static struct sh_timer_config tmu3_platform_data = {
 110         .name = "TMU3",
 111         .channel_offset = 0x04,
 112         .timer_bit = 0,
 113         .clk = "peripheral_clk",
 114 };
 115
 116 static struct resource tmu3_resources[] = {
 117         [0] = {
 118                 .name   = "TMU3",
 119                 .start  = 0xffdc0008,
 120                 .end    = 0xffdc0013,
 121                 .flags  = IORESOURCE_MEM,
 122         },
 123         [1] = {
 124                 .start  = 96,
 125                 .flags  = IORESOURCE_IRQ,
 126         },
 127 };
 128
 129 static struct platform_device tmu3_device = {
 130         .name           = "sh_tmu",
 131         .id             = 3,
 132         .dev = {
 133                 .platform_data  = &tmu3_platform_data,
 134         },
 135         .resource       = tmu3_resources,
 136         .num_resources  = ARRAY_SIZE(tmu3_resources),
 137 };
 138
 139 static struct sh_timer_config tmu4_platform_data = {
 140         .name = "TMU4",
 141         .channel_offset = 0x10,
 142         .timer_bit = 1,
 143         .clk = "peripheral_clk",
 144 };
 145
 146 static struct resource tmu4_resources[] = {
 147         [0] = {
 148                 .name   = "TMU4",
 149                 .start  = 0xffdc0014,
 150                 .end    = 0xffdc001f,
 151                 .flags  = IORESOURCE_MEM,
 152         },
 153         [1] = {
 154                 .start  = 97,
 155                 .flags  = IORESOURCE_IRQ,
 156         },
 157 };
 158
 159 static struct platform_device tmu4_device = {
 160         .name           = "sh_tmu",
 161         .id             = 4,
 162         .dev = {
 163                 .platform_data  = &tmu4_platform_data,
 164         },
 165         .resource       = tmu4_resources,
 166         .num_resources  = ARRAY_SIZE(tmu4_resources),
 167 };
 168
 169 static struct sh_timer_config tmu5_platform_data = {
 170         .name = "TMU5",
 171         .channel_offset = 0x1c,
 172         .timer_bit = 2,
 173         .clk = "peripheral_clk",
 174 };
 175
 176 static struct resource tmu5_resources[] = {
 177         [0] = {
 178                 .name   = "TMU5",
 179                 .start  = 0xffdc0020,
 180                 .end    = 0xffdc002b,
 181                 .flags  = IORESOURCE_MEM,
 182         },
 183         [1] = {
 184                 .start  = 98,
 185                 .flags  = IORESOURCE_IRQ,
 186         },
 187 };
 188
 189 static struct platform_device tmu5_device = {
 190         .name           = "sh_tmu",
 191         .id             = 5,
 192         .dev = {
 193                 .platform_data  = &tmu5_platform_data,
 194         },
 195         .resource       = tmu5_resources,
 196         .num_resources  = ARRAY_SIZE(tmu5_resources),
 197 };
 198
 199 static struct resource rtc_resources[] = {
 200         [0] = {
 201                 .start  = 0xffe80000,
 202                 .end    = 0xffe80000 + 0x58 - 1,
 203                 .flags  = IORESOURCE_IO,
 204         },
 205         [1] = {
 206                 /* Shared Period/Carry/Alarm IRQ */
 207                 .start  = 20,
 208                 .flags  = IORESOURCE_IRQ,
 209         },
 210 };
 211
 212 static struct platform_device rtc_device = {
 213         .name           = "sh-rtc",
 214         .id             = -1,
 215         .num_resources  = ARRAY_SIZE(rtc_resources),
 216         .resource       = rtc_resources,
 217 };
 218
 219 static struct plat_sci_port sci_platform_data[] = {
 220         {
 221                 .mapbase        = 0xffe00000,
 222                 .flags          = UPF_BOOT_AUTOCONF,
 223                 .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
 224                 .scbrr_algo_id  = SCBRR_ALGO_1,
 225                 .type           = PORT_SCIF,
 226                 .irqs           = { 40, 40, 40, 40 },
 227         }, {
 228                 .mapbase        = 0xffe10000,
 229                 .flags          = UPF_BOOT_AUTOCONF,
 230                 .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
 231                 .scbrr_algo_id  = SCBRR_ALGO_1,
 232                 .type           = PORT_SCIF,
 233                 .irqs           = { 76, 76, 76, 76 },
 234         }, {
 235                 .flags = 0,
 236         }
 237 };
 238
 239 static struct platform_device sci_device = {
 240         .name           = "sh-sci",
 241         .id             = -1,
 242         .dev            = {
 243                 .platform_data  = sci_platform_data,
 244         },
 245 };
 246
 247 static struct platform_device *sh7780_devices[] __initdata = {
 248         &tmu0_device,
 249         &tmu1_device,
 250         &tmu2_device,
 251         &tmu3_device,
 252         &tmu4_device,
 253         &tmu5_device,
 254         &rtc_device,
 255         &sci_device,
 256 };
 257
 258 static int __init sh7780_devices_setup(void)
 259 {
 260         return platform_add_devices(sh7780_devices,
 261                                     ARRAY_SIZE(sh7780_devices));
 262 }
 263 __initcall(sh7780_devices_setup);
 264
 265 static struct platform_device *sh7780_early_devices[] __initdata = {
 266         &tmu0_device,
 267         &tmu1_device,
 268         &tmu2_device,
 269         &tmu3_device,
 270         &tmu4_device,
 271         &tmu5_device,
 272 };
 273
 274 void __init plat_early_device_setup(void)
 275 {
 276         early_platform_add_devices(sh7780_early_devices,
 277                                    ARRAY_SIZE(sh7780_early_devices));
 278 }
 279
 280 enum {
 281         UNUSED = 0,
 282
 283         /* interrupt sources */
 284
 285         IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 286         IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 287         IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 288         IRL_HHLL, IRL_HHLH, IRL_HHHL,
 289
 290         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 291         RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
 292         HUDI, DMAC0, SCIF0, DMAC1, CMT, HAC,
 293         PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
 294         SCIF1, SIOF, HSPI, MMCIF, TMU3, TMU4, TMU5, SSI, FLCTL, GPIO,
 295
 296         /* interrupt groups */
 297
 298         TMU012, TMU345,
 299 };
 300
 301 static struct intc_vect vectors[] __initdata = {
 302         INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
 303         INTC_VECT(RTC, 0x4c0),
 304         INTC_VECT(WDT, 0x560),
 305         INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
 306         INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
 307         INTC_VECT(HUDI, 0x600),
 308         INTC_VECT(DMAC0, 0x640), INTC_VECT(DMAC0, 0x660),
 309         INTC_VECT(DMAC0, 0x680), INTC_VECT(DMAC0, 0x6a0),
 310         INTC_VECT(DMAC0, 0x6c0),
 311         INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
 312         INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
 313         INTC_VECT(DMAC0, 0x780), INTC_VECT(DMAC0, 0x7a0),
 314         INTC_VECT(DMAC1, 0x7c0), INTC_VECT(DMAC1, 0x7e0),
 315         INTC_VECT(CMT, 0x900), INTC_VECT(HAC, 0x980),
 316         INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
 317         INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
 318         INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
 319         INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
 320         INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
 321         INTC_VECT(SCIF1, 0xb80), INTC_VECT(SCIF1, 0xba0),
 322         INTC_VECT(SCIF1, 0xbc0), INTC_VECT(SCIF1, 0xbe0),
 323         INTC_VECT(SIOF, 0xc00), INTC_VECT(HSPI, 0xc80),
 324         INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
 325         INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
 326         INTC_VECT(DMAC1, 0xd80), INTC_VECT(DMAC1, 0xda0),
 327         INTC_VECT(DMAC1, 0xdc0), INTC_VECT(DMAC1, 0xde0),
 328         INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
 329         INTC_VECT(TMU5, 0xe40),
 330         INTC_VECT(SSI, 0xe80),
 331         INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
 332         INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
 333         INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
 334         INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
 335 };
 336
 337 static struct intc_group groups[] __initdata = {
 338         INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
 339         INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
 340 };
 341
 342 static struct intc_mask_reg mask_registers[] __initdata = {
 343         { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
 344           { 0, 0, 0, 0, 0, 0, GPIO, FLCTL,
 345             SSI, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
 346             PCIINTA, PCISERR, HAC, CMT, 0, 0, DMAC1, DMAC0,
 347             HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
 348 };
 349
 350 static struct intc_prio_reg prio_registers[] __initdata = {
 351         { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
 352                                                  TMU2, TMU2_TICPI } },
 353         { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
 354         { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
 355         { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC0, DMAC1 } },
 356         { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC,
 357                                                  PCISERR, PCIINTA, } },
 358         { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC,
 359                                                  PCIINTD, PCIC5 } },
 360         { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF, HSPI, MMCIF, SSI } },
 361         { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { FLCTL, GPIO } },
 362 };
 363
 364 static DECLARE_INTC_DESC(intc_desc, "sh7780", vectors, groups,
 365                          mask_registers, prio_registers, NULL);
 366
 367 /* Support for external interrupt pins in IRQ mode */
 368
 369 static struct intc_vect irq_vectors[] __initdata = {
 370         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
 371         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
 372         INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
 373         INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
 374 };
 375
 376 static struct intc_mask_reg irq_mask_registers[] __initdata = {
 377         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
 378           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 379 };
 380
 381 static struct intc_prio_reg irq_prio_registers[] __initdata = {
 382         { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
 383                                                IRQ4, IRQ5, IRQ6, IRQ7 } },
 384 };
 385
 386 static struct intc_sense_reg irq_sense_registers[] __initdata = {
 387         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
 388                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
 389 };
 390
 391 static struct intc_mask_reg irq_ack_registers[] __initdata = {
 392         { 0xffd00024, 0, 32, /* INTREQ */
 393           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 394 };
 395
 396 static DECLARE_INTC_DESC_ACK(intc_irq_desc, "sh7780-irq", irq_vectors,
 397                              NULL, irq_mask_registers, irq_prio_registers,
 398                              irq_sense_registers, irq_ack_registers);
 399
 400 /* External interrupt pins in IRL mode */
 401
 402 static struct intc_vect irl_vectors[] __initdata = {
 403         INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
 404         INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
 405         INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
 406         INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
 407         INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
 408         INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
 409         INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
 410         INTC_VECT(IRL_HHHL, 0x3c0),
 411 };
 412
 413 static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
 414         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 415           { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 416             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 417             IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 418             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
 419 };
 420
 421 static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
 422         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 423           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 424             IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 425             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 426             IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 427             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
 428 };
 429
 430 static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors,
 431                          NULL, irl7654_mask_registers, NULL, NULL);
 432
 433 static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
 434                          NULL, irl3210_mask_registers, NULL, NULL);
 435
 436 #define INTC_ICR0       0xffd00000
 437 #define INTC_INTMSK0    0xffd00044
 438 #define INTC_INTMSK1    0xffd00048
 439 #define INTC_INTMSK2    0xffd40080
 440 #define INTC_INTMSKCLR1 0xffd00068
 441 #define INTC_INTMSKCLR2 0xffd40084
 442
 443 void __init plat_irq_setup(void)
 444 {
 445         /* disable IRQ7-0 */
 446         ctrl_outl(0xff000000, INTC_INTMSK0);
 447
 448         /* disable IRL3-0 + IRL7-4 */
 449         ctrl_outl(0xc0000000, INTC_INTMSK1);
 450         ctrl_outl(0xfffefffe, INTC_INTMSK2);
 451
 452         /* select IRL mode for IRL3-0 + IRL7-4 */
 453         ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 454
 455         /* disable holding function, ie enable "SH-4 Mode" */
 456         ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0);
 457
 458         register_intc_controller(&intc_desc);
 459 }
 460
 461 void __init plat_irq_setup_pins(int mode)
 462 {
 463         switch (mode) {
 464         case IRQ_MODE_IRQ:
 465                 /* select IRQ mode for IRL3-0 + IRL7-4 */
 466                 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
 467                 register_intc_controller(&intc_irq_desc);
 468                 break;
 469         case IRQ_MODE_IRL7654:
 470                 /* enable IRL7-4 but don't provide any masking */
 471                 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
 472                 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
 473                 break;
 474         case IRQ_MODE_IRL3210:
 475                 /* enable IRL0-3 but don't provide any masking */
 476                 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
 477                 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
 478                 break;
 479         case IRQ_MODE_IRL7654_MASK:
 480                 /* enable IRL7-4 and mask using cpu intc controller */
 481                 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
 482                 register_intc_controller(&intc_irl7654_desc);
 483                 break;
 484         case IRQ_MODE_IRL3210_MASK:
 485                 /* enable IRL0-3 and mask using cpu intc controller */
 486                 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
 487                 register_intc_controller(&intc_irl3210_desc);
 488                 break;
 489         default:
 490                 BUG();
 491         }
 492 }