arch/sh/kernel/cpu/sh4a/setup-sh7785.c

   1 /*
   2  * SH7785 Setup
   3  *
   4  *  Copyright (C) 2007  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/platform_device.h>
  11 #include <linux/init.h>
  12 #include <linux/serial.h>
  13 #include <linux/serial_sci.h>
  14 #include <linux/io.h>
  15 #include <linux/mm.h>
  16 #include <linux/sh_timer.h>
  17 #include <asm/mmzone.h>
  18
  19 static struct sh_timer_config tmu0_platform_data = {
  20         .name = "TMU0",
  21         .channel_offset = 0x04,
  22         .timer_bit = 0,
  23         .clk = "tmu012_fck",
  24         .clockevent_rating = 200,
  25 };
  26
  27 static struct resource tmu0_resources[] = {
  28         [0] = {
  29                 .name   = "TMU0",
  30                 .start  = 0xffd80008,
  31                 .end    = 0xffd80013,
  32                 .flags  = IORESOURCE_MEM,
  33         },
  34         [1] = {
  35                 .start  = 28,
  36                 .flags  = IORESOURCE_IRQ,
  37         },
  38 };
  39
  40 static struct platform_device tmu0_device = {
  41         .name           = "sh_tmu",
  42         .id             = 0,
  43         .dev = {
  44                 .platform_data  = &tmu0_platform_data,
  45         },
  46         .resource       = tmu0_resources,
  47         .num_resources  = ARRAY_SIZE(tmu0_resources),
  48 };
  49
  50 static struct sh_timer_config tmu1_platform_data = {
  51         .name = "TMU1",
  52         .channel_offset = 0x10,
  53         .timer_bit = 1,
  54         .clk = "tmu012_fck",
  55         .clocksource_rating = 200,
  56 };
  57
  58 static struct resource tmu1_resources[] = {
  59         [0] = {
  60                 .name   = "TMU1",
  61                 .start  = 0xffd80014,
  62                 .end    = 0xffd8001f,
  63                 .flags  = IORESOURCE_MEM,
  64         },
  65         [1] = {
  66                 .start  = 29,
  67                 .flags  = IORESOURCE_IRQ,
  68         },
  69 };
  70
  71 static struct platform_device tmu1_device = {
  72         .name           = "sh_tmu",
  73         .id             = 1,
  74         .dev = {
  75                 .platform_data  = &tmu1_platform_data,
  76         },
  77         .resource       = tmu1_resources,
  78         .num_resources  = ARRAY_SIZE(tmu1_resources),
  79 };
  80
  81 static struct sh_timer_config tmu2_platform_data = {
  82         .name = "TMU2",
  83         .channel_offset = 0x1c,
  84         .timer_bit = 2,
  85         .clk = "tmu012_fck",
  86 };
  87
  88 static struct resource tmu2_resources[] = {
  89         [0] = {
  90                 .name   = "TMU2",
  91                 .start  = 0xffd80020,
  92                 .end    = 0xffd8002f,
  93                 .flags  = IORESOURCE_MEM,
  94         },
  95         [1] = {
  96                 .start  = 30,
  97                 .flags  = IORESOURCE_IRQ,
  98         },
  99 };
 100
 101 static struct platform_device tmu2_device = {
 102         .name           = "sh_tmu",
 103         .id             = 2,
 104         .dev = {
 105                 .platform_data  = &tmu2_platform_data,
 106         },
 107         .resource       = tmu2_resources,
 108         .num_resources  = ARRAY_SIZE(tmu2_resources),
 109 };
 110
 111 static struct sh_timer_config tmu3_platform_data = {
 112         .name = "TMU3",
 113         .channel_offset = 0x04,
 114         .timer_bit = 0,
 115         .clk = "tmu345_fck",
 116 };
 117
 118 static struct resource tmu3_resources[] = {
 119         [0] = {
 120                 .name   = "TMU3",
 121                 .start  = 0xffdc0008,
 122                 .end    = 0xffdc0013,
 123                 .flags  = IORESOURCE_MEM,
 124         },
 125         [1] = {
 126                 .start  = 96,
 127                 .flags  = IORESOURCE_IRQ,
 128         },
 129 };
 130
 131 static struct platform_device tmu3_device = {
 132         .name           = "sh_tmu",
 133         .id             = 3,
 134         .dev = {
 135                 .platform_data  = &tmu3_platform_data,
 136         },
 137         .resource       = tmu3_resources,
 138         .num_resources  = ARRAY_SIZE(tmu3_resources),
 139 };
 140
 141 static struct sh_timer_config tmu4_platform_data = {
 142         .name = "TMU4",
 143         .channel_offset = 0x10,
 144         .timer_bit = 1,
 145         .clk = "tmu345_fck",
 146 };
 147
 148 static struct resource tmu4_resources[] = {
 149         [0] = {
 150                 .name   = "TMU4",
 151                 .start  = 0xffdc0014,
 152                 .end    = 0xffdc001f,
 153                 .flags  = IORESOURCE_MEM,
 154         },
 155         [1] = {
 156                 .start  = 97,
 157                 .flags  = IORESOURCE_IRQ,
 158         },
 159 };
 160
 161 static struct platform_device tmu4_device = {
 162         .name           = "sh_tmu",
 163         .id             = 4,
 164         .dev = {
 165                 .platform_data  = &tmu4_platform_data,
 166         },
 167         .resource       = tmu4_resources,
 168         .num_resources  = ARRAY_SIZE(tmu4_resources),
 169 };
 170
 171 static struct sh_timer_config tmu5_platform_data = {
 172         .name = "TMU5",
 173         .channel_offset = 0x1c,
 174         .timer_bit = 2,
 175         .clk = "tmu345_fck",
 176 };
 177
 178 static struct resource tmu5_resources[] = {
 179         [0] = {
 180                 .name   = "TMU5",
 181                 .start  = 0xffdc0020,
 182                 .end    = 0xffdc002b,
 183                 .flags  = IORESOURCE_MEM,
 184         },
 185         [1] = {
 186                 .start  = 98,
 187                 .flags  = IORESOURCE_IRQ,
 188         },
 189 };
 190
 191 static struct platform_device tmu5_device = {
 192         .name           = "sh_tmu",
 193         .id             = 5,
 194         .dev = {
 195                 .platform_data  = &tmu5_platform_data,
 196         },
 197         .resource       = tmu5_resources,
 198         .num_resources  = ARRAY_SIZE(tmu5_resources),
 199 };
 200
 201 static struct plat_sci_port sci_platform_data[] = {
 202         {
 203                 .mapbase        = 0xffea0000,
 204                 .flags          = UPF_BOOT_AUTOCONF,
 205                 .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
 206                 .scbrr_algo_id  = SCBRR_ALGO_1,
 207                 .type           = PORT_SCIF,
 208                 .irqs           = { 40, 40, 40, 40 },
 209                 .clk            = "scif_fck",
 210         }, {
 211                 .mapbase        = 0xffeb0000,
 212                 .flags          = UPF_BOOT_AUTOCONF,
 213                 .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
 214                 .scbrr_algo_id  = SCBRR_ALGO_1,
 215                 .type           = PORT_SCIF,
 216                 .irqs           = { 44, 44, 44, 44 },
 217                 .clk            = "scif_fck",
 218         }, {
 219                 .mapbase        = 0xffec0000,
 220                 .flags          = UPF_BOOT_AUTOCONF,
 221                 .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
 222                 .scbrr_algo_id  = SCBRR_ALGO_1,
 223                 .type           = PORT_SCIF,
 224                 .irqs           = { 60, 60, 60, 60 },
 225                 .clk            = "scif_fck",
 226         }, {
 227                 .mapbase        = 0xffed0000,
 228                 .flags          = UPF_BOOT_AUTOCONF,
 229                 .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
 230                 .scbrr_algo_id  = SCBRR_ALGO_1,
 231                 .type           = PORT_SCIF,
 232                 .irqs           = { 61, 61, 61, 61 },
 233                 .clk            = "scif_fck",
 234         }, {
 235                 .mapbase        = 0xffee0000,
 236                 .flags          = UPF_BOOT_AUTOCONF,
 237                 .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
 238                 .scbrr_algo_id  = SCBRR_ALGO_1,
 239                 .type           = PORT_SCIF,
 240                 .irqs           = { 62, 62, 62, 62 },
 241                 .clk            = "scif_fck",
 242         }, {
 243                 .mapbase        = 0xffef0000,
 244                 .flags          = UPF_BOOT_AUTOCONF,
 245                 .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
 246                 .scbrr_algo_id  = SCBRR_ALGO_1,
 247                 .type           = PORT_SCIF,
 248                 .irqs           = { 63, 63, 63, 63 },
 249                 .clk            = "scif_fck",
 250         }, {
 251                 .flags = 0,
 252         }
 253 };
 254
 255 static struct platform_device sci_device = {
 256         .name           = "sh-sci",
 257         .id             = -1,
 258         .dev            = {
 259                 .platform_data  = sci_platform_data,
 260         },
 261 };
 262
 263 static struct platform_device *sh7785_devices[] __initdata = {
 264         &tmu0_device,
 265         &tmu1_device,
 266         &tmu2_device,
 267         &tmu3_device,
 268         &tmu4_device,
 269         &tmu5_device,
 270         &sci_device,
 271 };
 272
 273 static int __init sh7785_devices_setup(void)
 274 {
 275         return platform_add_devices(sh7785_devices,
 276                                     ARRAY_SIZE(sh7785_devices));
 277 }
 278 __initcall(sh7785_devices_setup);
 279
 280 static struct platform_device *sh7785_early_devices[] __initdata = {
 281         &tmu0_device,
 282         &tmu1_device,
 283         &tmu2_device,
 284         &tmu3_device,
 285         &tmu4_device,
 286         &tmu5_device,
 287 };
 288
 289 void __init plat_early_device_setup(void)
 290 {
 291         early_platform_add_devices(sh7785_early_devices,
 292                                    ARRAY_SIZE(sh7785_early_devices));
 293 }
 294
 295 enum {
 296         UNUSED = 0,
 297
 298         /* interrupt sources */
 299
 300         IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 301         IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 302         IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 303         IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
 304
 305         IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 306         IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 307         IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 308         IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
 309
 310         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 311         WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
 312         HUDI, DMAC0, SCIF0, SCIF1, DMAC1, HSPI,
 313         SCIF2, SCIF3, SCIF4, SCIF5,
 314         PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
 315         SIOF, MMCIF, DU, GDTA,
 316         TMU3, TMU4, TMU5,
 317         SSI0, SSI1,
 318         HAC0, HAC1,
 319         FLCTL, GPIO,
 320
 321         /* interrupt groups */
 322
 323         TMU012, TMU345
 324 };
 325
 326 static struct intc_vect vectors[] __initdata = {
 327         INTC_VECT(WDT, 0x560),
 328         INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
 329         INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
 330         INTC_VECT(HUDI, 0x600),
 331         INTC_VECT(DMAC0, 0x620), INTC_VECT(DMAC0, 0x640),
 332         INTC_VECT(DMAC0, 0x660), INTC_VECT(DMAC0, 0x680),
 333         INTC_VECT(DMAC0, 0x6a0), INTC_VECT(DMAC0, 0x6c0),
 334         INTC_VECT(DMAC0, 0x6e0),
 335         INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
 336         INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
 337         INTC_VECT(SCIF1, 0x780), INTC_VECT(SCIF1, 0x7a0),
 338         INTC_VECT(SCIF1, 0x7c0), INTC_VECT(SCIF1, 0x7e0),
 339         INTC_VECT(DMAC1, 0x880), INTC_VECT(DMAC1, 0x8a0),
 340         INTC_VECT(DMAC1, 0x8c0), INTC_VECT(DMAC1, 0x8e0),
 341         INTC_VECT(DMAC1, 0x900), INTC_VECT(DMAC1, 0x920),
 342         INTC_VECT(DMAC1, 0x940),
 343         INTC_VECT(HSPI, 0x960),
 344         INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0),
 345         INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0),
 346         INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
 347         INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
 348         INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
 349         INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
 350         INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
 351         INTC_VECT(SIOF, 0xc00),
 352         INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
 353         INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
 354         INTC_VECT(DU, 0xd80),
 355         INTC_VECT(GDTA, 0xda0), INTC_VECT(GDTA, 0xdc0),
 356         INTC_VECT(GDTA, 0xde0),
 357         INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
 358         INTC_VECT(TMU5, 0xe40),
 359         INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
 360         INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0),
 361         INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
 362         INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
 363         INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
 364         INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
 365 };
 366
 367 static struct intc_group groups[] __initdata = {
 368         INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
 369         INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
 370 };
 371
 372 static struct intc_mask_reg mask_registers[] __initdata = {
 373         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
 374           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 375
 376         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 377           { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 378             IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 379             IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 380             IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
 381             IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 382             IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 383             IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 384             IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
 385
 386         { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
 387           { 0, 0, 0, GDTA, DU, SSI0, SSI1, GPIO,
 388             FLCTL, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
 389             PCIINTA, PCISERR, HAC1, HAC0, DMAC1, DMAC0, HUDI, WDT,
 390             SCIF5, SCIF4, SCIF3, SCIF2, SCIF1, SCIF0, TMU345, TMU012 } },
 391 };
 392
 393 static struct intc_prio_reg prio_registers[] __initdata = {
 394         { 0xffd00010, 0, 32, 4, /* INTPRI */   { IRQ0, IRQ1, IRQ2, IRQ3,
 395                                                  IRQ4, IRQ5, IRQ6, IRQ7 } },
 396         { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
 397                                                  TMU2, TMU2_TICPI } },
 398         { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, } },
 399         { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1,
 400                                                  SCIF2, SCIF3 } },
 401         { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { SCIF4, SCIF5, WDT, } },
 402         { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { HUDI, DMAC0, DMAC1, } },
 403         { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { HAC0, HAC1,
 404                                                  PCISERR, PCIINTA } },
 405         { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { PCIINTB, PCIINTC,
 406                                                  PCIINTD, PCIC5 } },
 407         { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SIOF, HSPI, MMCIF, } },
 408         { 0xffd40020, 0, 32, 8, /* INT2PRI8 */ { FLCTL, GPIO, SSI0, SSI1, } },
 409         { 0xffd40024, 0, 32, 8, /* INT2PRI9 */ { DU, GDTA, } },
 410 };
 411
 412 static DECLARE_INTC_DESC(intc_desc, "sh7785", vectors, groups,
 413                          mask_registers, prio_registers, NULL);
 414
 415 /* Support for external interrupt pins in IRQ mode */
 416
 417 static struct intc_vect vectors_irq0123[] __initdata = {
 418         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
 419         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
 420 };
 421
 422 static struct intc_vect vectors_irq4567[] __initdata = {
 423         INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
 424         INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
 425 };
 426
 427 static struct intc_sense_reg sense_registers[] __initdata = {
 428         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
 429                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
 430 };
 431
 432 static struct intc_mask_reg ack_registers[] __initdata = {
 433         { 0xffd00024, 0, 32, /* INTREQ */
 434           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 435 };
 436
 437 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7785-irq0123",
 438                              vectors_irq0123, NULL, mask_registers,
 439                              prio_registers, sense_registers, ack_registers);
 440
 441 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7785-irq4567",
 442                              vectors_irq4567, NULL, mask_registers,
 443                              prio_registers, sense_registers, ack_registers);
 444
 445 /* External interrupt pins in IRL mode */
 446
 447 static struct intc_vect vectors_irl0123[] __initdata = {
 448         INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
 449         INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
 450         INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
 451         INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
 452         INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
 453         INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
 454         INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
 455         INTC_VECT(IRL0_HHHL, 0x3c0),
 456 };
 457
 458 static struct intc_vect vectors_irl4567[] __initdata = {
 459         INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
 460         INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
 461         INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
 462         INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
 463         INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
 464         INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
 465         INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
 466         INTC_VECT(IRL4_HHHL, 0xcc0),
 467 };
 468
 469 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7785-irl0123", vectors_irl0123,
 470                          NULL, mask_registers, NULL, NULL);
 471
 472 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
 473                          NULL, mask_registers, NULL, NULL);
 474
 475 #define INTC_ICR0       0xffd00000
 476 #define INTC_INTMSK0    0xffd00044
 477 #define INTC_INTMSK1    0xffd00048
 478 #define INTC_INTMSK2    0xffd40080
 479 #define INTC_INTMSKCLR1 0xffd00068
 480 #define INTC_INTMSKCLR2 0xffd40084
 481
 482 void __init plat_irq_setup(void)
 483 {
 484         /* disable IRQ3-0 + IRQ7-4 */
 485         ctrl_outl(0xff000000, INTC_INTMSK0);
 486
 487         /* disable IRL3-0 + IRL7-4 */
 488         ctrl_outl(0xc0000000, INTC_INTMSK1);
 489         ctrl_outl(0xfffefffe, INTC_INTMSK2);
 490
 491         /* select IRL mode for IRL3-0 + IRL7-4 */
 492         ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 493
 494         /* disable holding function, ie enable "SH-4 Mode" */
 495         ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0);
 496
 497         register_intc_controller(&intc_desc);
 498 }
 499
 500 void __init plat_irq_setup_pins(int mode)
 501 {
 502         switch (mode) {
 503         case IRQ_MODE_IRQ7654:
 504                 /* select IRQ mode for IRL7-4 */
 505                 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0);
 506                 register_intc_controller(&intc_desc_irq4567);
 507                 break;
 508         case IRQ_MODE_IRQ3210:
 509                 /* select IRQ mode for IRL3-0 */
 510                 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0);
 511                 register_intc_controller(&intc_desc_irq0123);
 512                 break;
 513         case IRQ_MODE_IRL7654:
 514                 /* enable IRL7-4 but don't provide any masking */
 515                 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
 516                 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
 517                 break;
 518         case IRQ_MODE_IRL3210:
 519                 /* enable IRL0-3 but don't provide any masking */
 520                 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
 521                 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
 522                 break;
 523         case IRQ_MODE_IRL7654_MASK:
 524                 /* enable IRL7-4 and mask using cpu intc controller */
 525                 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
 526                 register_intc_controller(&intc_desc_irl4567);
 527                 break;
 528         case IRQ_MODE_IRL3210_MASK:
 529                 /* enable IRL0-3 and mask using cpu intc controller */
 530                 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
 531                 register_intc_controller(&intc_desc_irl0123);
 532                 break;
 533         default:
 534                 BUG();
 535         }
 536 }
 537
 538 void __init plat_mem_setup(void)
 539 {
 540         /* Register the URAM space as Node 1 */
 541         setup_bootmem_node(1, 0xe55f0000, 0xe5610000);
 542 }