arch/x86/include/asm/svm.h

   1 #ifndef __SVM_H
   2 #define __SVM_H
   3
   4 #define SVM_EXIT_READ_CR0      0x000
   5 #define SVM_EXIT_READ_CR3      0x003
   6 #define SVM_EXIT_READ_CR4      0x004
   7 #define SVM_EXIT_READ_CR8      0x008
   8 #define SVM_EXIT_WRITE_CR0     0x010
   9 #define SVM_EXIT_WRITE_CR3     0x013
  10 #define SVM_EXIT_WRITE_CR4     0x014
  11 #define SVM_EXIT_WRITE_CR8     0x018
  12 #define SVM_EXIT_READ_DR0      0x020
  13 #define SVM_EXIT_READ_DR1      0x021
  14 #define SVM_EXIT_READ_DR2      0x022
  15 #define SVM_EXIT_READ_DR3      0x023
  16 #define SVM_EXIT_READ_DR4      0x024
  17 #define SVM_EXIT_READ_DR5      0x025
  18 #define SVM_EXIT_READ_DR6      0x026
  19 #define SVM_EXIT_READ_DR7      0x027
  20 #define SVM_EXIT_WRITE_DR0     0x030
  21 #define SVM_EXIT_WRITE_DR1     0x031
  22 #define SVM_EXIT_WRITE_DR2     0x032
  23 #define SVM_EXIT_WRITE_DR3     0x033
  24 #define SVM_EXIT_WRITE_DR4     0x034
  25 #define SVM_EXIT_WRITE_DR5     0x035
  26 #define SVM_EXIT_WRITE_DR6     0x036
  27 #define SVM_EXIT_WRITE_DR7     0x037
  28 #define SVM_EXIT_EXCP_BASE     0x040
  29 #define SVM_EXIT_INTR          0x060
  30 #define SVM_EXIT_NMI           0x061
  31 #define SVM_EXIT_SMI           0x062
  32 #define SVM_EXIT_INIT          0x063
  33 #define SVM_EXIT_VINTR         0x064
  34 #define SVM_EXIT_CR0_SEL_WRITE 0x065
  35 #define SVM_EXIT_IDTR_READ     0x066
  36 #define SVM_EXIT_GDTR_READ     0x067
  37 #define SVM_EXIT_LDTR_READ     0x068
  38 #define SVM_EXIT_TR_READ       0x069
  39 #define SVM_EXIT_IDTR_WRITE    0x06a
  40 #define SVM_EXIT_GDTR_WRITE    0x06b
  41 #define SVM_EXIT_LDTR_WRITE    0x06c
  42 #define SVM_EXIT_TR_WRITE      0x06d
  43 #define SVM_EXIT_RDTSC         0x06e
  44 #define SVM_EXIT_RDPMC         0x06f
  45 #define SVM_EXIT_PUSHF         0x070
  46 #define SVM_EXIT_POPF          0x071
  47 #define SVM_EXIT_CPUID         0x072
  48 #define SVM_EXIT_RSM           0x073
  49 #define SVM_EXIT_IRET          0x074
  50 #define SVM_EXIT_SWINT         0x075
  51 #define SVM_EXIT_INVD          0x076
  52 #define SVM_EXIT_PAUSE         0x077
  53 #define SVM_EXIT_HLT           0x078
  54 #define SVM_EXIT_INVLPG        0x079
  55 #define SVM_EXIT_INVLPGA       0x07a
  56 #define SVM_EXIT_IOIO          0x07b
  57 #define SVM_EXIT_MSR           0x07c
  58 #define SVM_EXIT_TASK_SWITCH   0x07d
  59 #define SVM_EXIT_FERR_FREEZE   0x07e
  60 #define SVM_EXIT_SHUTDOWN      0x07f
  61 #define SVM_EXIT_VMRUN         0x080
  62 #define SVM_EXIT_VMMCALL       0x081
  63 #define SVM_EXIT_VMLOAD        0x082
  64 #define SVM_EXIT_VMSAVE        0x083
  65 #define SVM_EXIT_STGI          0x084
  66 #define SVM_EXIT_CLGI          0x085
  67 #define SVM_EXIT_SKINIT        0x086
  68 #define SVM_EXIT_RDTSCP        0x087
  69 #define SVM_EXIT_ICEBP         0x088
  70 #define SVM_EXIT_WBINVD        0x089
  71 #define SVM_EXIT_MONITOR       0x08a
  72 #define SVM_EXIT_MWAIT         0x08b
  73 #define SVM_EXIT_MWAIT_COND    0x08c
  74 #define SVM_EXIT_XSETBV        0x08d
  75 #define SVM_EXIT_NPF           0x400
  76
  77 #define SVM_EXIT_ERR           -1
  78
  79 #define SVM_EXIT_REASONS \
  80         { SVM_EXIT_READ_CR0,    "read_cr0" }, \
  81         { SVM_EXIT_READ_CR3,    "read_cr3" }, \
  82         { SVM_EXIT_READ_CR4,    "read_cr4" }, \
  83         { SVM_EXIT_READ_CR8,    "read_cr8" }, \
  84         { SVM_EXIT_WRITE_CR0,   "write_cr0" }, \
  85         { SVM_EXIT_WRITE_CR3,   "write_cr3" }, \
  86         { SVM_EXIT_WRITE_CR4,   "write_cr4" }, \
  87         { SVM_EXIT_WRITE_CR8,   "write_cr8" }, \
  88         { SVM_EXIT_READ_DR0,    "read_dr0" }, \
  89         { SVM_EXIT_READ_DR1,    "read_dr1" }, \
  90         { SVM_EXIT_READ_DR2,    "read_dr2" }, \
  91         { SVM_EXIT_READ_DR3,    "read_dr3" }, \
  92         { SVM_EXIT_WRITE_DR0,   "write_dr0" }, \
  93         { SVM_EXIT_WRITE_DR1,   "write_dr1" }, \
  94         { SVM_EXIT_WRITE_DR2,   "write_dr2" }, \
  95         { SVM_EXIT_WRITE_DR3,   "write_dr3" }, \
  96         { SVM_EXIT_WRITE_DR5,   "write_dr5" }, \
  97         { SVM_EXIT_WRITE_DR7,   "write_dr7" }, \
  98         { SVM_EXIT_EXCP_BASE + DB_VECTOR,       "DB excp" }, \
  99         { SVM_EXIT_EXCP_BASE + BP_VECTOR,       "BP excp" }, \
 100         { SVM_EXIT_EXCP_BASE + UD_VECTOR,       "UD excp" }, \
 101         { SVM_EXIT_EXCP_BASE + PF_VECTOR,       "PF excp" }, \
 102         { SVM_EXIT_EXCP_BASE + NM_VECTOR,       "NM excp" }, \
 103         { SVM_EXIT_EXCP_BASE + MC_VECTOR,       "MC excp" }, \
 104         { SVM_EXIT_INTR,        "interrupt" }, \
 105         { SVM_EXIT_NMI,         "nmi" }, \
 106         { SVM_EXIT_SMI,         "smi" }, \
 107         { SVM_EXIT_INIT,        "init" }, \
 108         { SVM_EXIT_VINTR,       "vintr" }, \
 109         { SVM_EXIT_CPUID,       "cpuid" }, \
 110         { SVM_EXIT_INVD,        "invd" }, \
 111         { SVM_EXIT_HLT,         "hlt" }, \
 112         { SVM_EXIT_INVLPG,      "invlpg" }, \
 113         { SVM_EXIT_INVLPGA,     "invlpga" }, \
 114         { SVM_EXIT_IOIO,        "io" }, \
 115         { SVM_EXIT_MSR,         "msr" }, \
 116         { SVM_EXIT_TASK_SWITCH, "task_switch" }, \
 117         { SVM_EXIT_SHUTDOWN,    "shutdown" }, \
 118         { SVM_EXIT_VMRUN,       "vmrun" }, \
 119         { SVM_EXIT_VMMCALL,     "hypercall" }, \
 120         { SVM_EXIT_VMLOAD,      "vmload" }, \
 121         { SVM_EXIT_VMSAVE,      "vmsave" }, \
 122         { SVM_EXIT_STGI,        "stgi" }, \
 123         { SVM_EXIT_CLGI,        "clgi" }, \
 124         { SVM_EXIT_SKINIT,      "skinit" }, \
 125         { SVM_EXIT_WBINVD,      "wbinvd" }, \
 126         { SVM_EXIT_MONITOR,     "monitor" }, \
 127         { SVM_EXIT_MWAIT,       "mwait" }, \
 128         { SVM_EXIT_XSETBV,      "xsetbv" }, \
 129         { SVM_EXIT_NPF,         "npf" }
 130
 131 #ifdef __KERNEL__
 132
 133 enum {
 134         INTERCEPT_INTR,
 135         INTERCEPT_NMI,
 136         INTERCEPT_SMI,
 137         INTERCEPT_INIT,
 138         INTERCEPT_VINTR,
 139         INTERCEPT_SELECTIVE_CR0,
 140         INTERCEPT_STORE_IDTR,
 141         INTERCEPT_STORE_GDTR,
 142         INTERCEPT_STORE_LDTR,
 143         INTERCEPT_STORE_TR,
 144         INTERCEPT_LOAD_IDTR,
 145         INTERCEPT_LOAD_GDTR,
 146         INTERCEPT_LOAD_LDTR,
 147         INTERCEPT_LOAD_TR,
 148         INTERCEPT_RDTSC,
 149         INTERCEPT_RDPMC,
 150         INTERCEPT_PUSHF,
 151         INTERCEPT_POPF,
 152         INTERCEPT_CPUID,
 153         INTERCEPT_RSM,
 154         INTERCEPT_IRET,
 155         INTERCEPT_INTn,
 156         INTERCEPT_INVD,
 157         INTERCEPT_PAUSE,
 158         INTERCEPT_HLT,
 159         INTERCEPT_INVLPG,
 160         INTERCEPT_INVLPGA,
 161         INTERCEPT_IOIO_PROT,
 162         INTERCEPT_MSR_PROT,
 163         INTERCEPT_TASK_SWITCH,
 164         INTERCEPT_FERR_FREEZE,
 165         INTERCEPT_SHUTDOWN,
 166         INTERCEPT_VMRUN,
 167         INTERCEPT_VMMCALL,
 168         INTERCEPT_VMLOAD,
 169         INTERCEPT_VMSAVE,
 170         INTERCEPT_STGI,
 171         INTERCEPT_CLGI,
 172         INTERCEPT_SKINIT,
 173         INTERCEPT_RDTSCP,
 174         INTERCEPT_ICEBP,
 175         INTERCEPT_WBINVD,
 176         INTERCEPT_MONITOR,
 177         INTERCEPT_MWAIT,
 178         INTERCEPT_MWAIT_COND,
 179         INTERCEPT_XSETBV,
 180 };
 181
 182
 183 struct __attribute__ ((__packed__)) vmcb_control_area {
 184         u32 intercept_cr;
 185         u32 intercept_dr;
 186         u32 intercept_exceptions;
 187         u64 intercept;
 188         u8 reserved_1[42];
 189         u16 pause_filter_count;
 190         u64 iopm_base_pa;
 191         u64 msrpm_base_pa;
 192         u64 tsc_offset;
 193         u32 asid;
 194         u8 tlb_ctl;
 195         u8 reserved_2[3];
 196         u32 int_ctl;
 197         u32 int_vector;
 198         u32 int_state;
 199         u8 reserved_3[4];
 200         u32 exit_code;
 201         u32 exit_code_hi;
 202         u64 exit_info_1;
 203         u64 exit_info_2;
 204         u32 exit_int_info;
 205         u32 exit_int_info_err;
 206         u64 nested_ctl;
 207         u8 reserved_4[16];
 208         u32 event_inj;
 209         u32 event_inj_err;
 210         u64 nested_cr3;
 211         u64 lbr_ctl;
 212         u32 clean;
 213         u32 reserved_5;
 214         u64 next_rip;
 215         u8 insn_len;
 216         u8 insn_bytes[15];
 217         u8 reserved_6[800];
 218 };
 219
 220
 221 #define TLB_CONTROL_DO_NOTHING 0
 222 #define TLB_CONTROL_FLUSH_ALL_ASID 1
 223 #define TLB_CONTROL_FLUSH_ASID 3
 224 #define TLB_CONTROL_FLUSH_ASID_LOCAL 7
 225
 226 #define V_TPR_MASK 0x0f
 227
 228 #define V_IRQ_SHIFT 8
 229 #define V_IRQ_MASK (1 << V_IRQ_SHIFT)
 230
 231 #define V_INTR_PRIO_SHIFT 16
 232 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
 233
 234 #define V_IGN_TPR_SHIFT 20
 235 #define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
 236
 237 #define V_INTR_MASKING_SHIFT 24
 238 #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
 239
 240 #define SVM_INTERRUPT_SHADOW_MASK 1
 241
 242 #define SVM_IOIO_STR_SHIFT 2
 243 #define SVM_IOIO_REP_SHIFT 3
 244 #define SVM_IOIO_SIZE_SHIFT 4
 245 #define SVM_IOIO_ASIZE_SHIFT 7
 246
 247 #define SVM_IOIO_TYPE_MASK 1
 248 #define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
 249 #define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
 250 #define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
 251 #define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
 252
 253 #define SVM_VM_CR_VALID_MASK    0x001fULL
 254 #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
 255 #define SVM_VM_CR_SVM_DIS_MASK  0x0010ULL
 256
 257 struct __attribute__ ((__packed__)) vmcb_seg {
 258         u16 selector;
 259         u16 attrib;
 260         u32 limit;
 261         u64 base;
 262 };
 263
 264 struct __attribute__ ((__packed__)) vmcb_save_area {
 265         struct vmcb_seg es;
 266         struct vmcb_seg cs;
 267         struct vmcb_seg ss;
 268         struct vmcb_seg ds;
 269         struct vmcb_seg fs;
 270         struct vmcb_seg gs;
 271         struct vmcb_seg gdtr;
 272         struct vmcb_seg ldtr;
 273         struct vmcb_seg idtr;
 274         struct vmcb_seg tr;
 275         u8 reserved_1[43];
 276         u8 cpl;
 277         u8 reserved_2[4];
 278         u64 efer;
 279         u8 reserved_3[112];
 280         u64 cr4;
 281         u64 cr3;
 282         u64 cr0;
 283         u64 dr7;
 284         u64 dr6;
 285         u64 rflags;
 286         u64 rip;
 287         u8 reserved_4[88];
 288         u64 rsp;
 289         u8 reserved_5[24];
 290         u64 rax;
 291         u64 star;
 292         u64 lstar;
 293         u64 cstar;
 294         u64 sfmask;
 295         u64 kernel_gs_base;
 296         u64 sysenter_cs;
 297         u64 sysenter_esp;
 298         u64 sysenter_eip;
 299         u64 cr2;
 300         u8 reserved_6[32];
 301         u64 g_pat;
 302         u64 dbgctl;
 303         u64 br_from;
 304         u64 br_to;
 305         u64 last_excp_from;
 306         u64 last_excp_to;
 307 };
 308
 309 struct __attribute__ ((__packed__)) vmcb {
 310         struct vmcb_control_area control;
 311         struct vmcb_save_area save;
 312 };
 313
 314 #define SVM_CPUID_FEATURE_SHIFT 2
 315 #define SVM_CPUID_FUNC 0x8000000a
 316
 317 #define SVM_VM_CR_SVM_DISABLE 4
 318
 319 #define SVM_SELECTOR_S_SHIFT 4
 320 #define SVM_SELECTOR_DPL_SHIFT 5
 321 #define SVM_SELECTOR_P_SHIFT 7
 322 #define SVM_SELECTOR_AVL_SHIFT 8
 323 #define SVM_SELECTOR_L_SHIFT 9
 324 #define SVM_SELECTOR_DB_SHIFT 10
 325 #define SVM_SELECTOR_G_SHIFT 11
 326
 327 #define SVM_SELECTOR_TYPE_MASK (0xf)
 328 #define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
 329 #define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
 330 #define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
 331 #define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
 332 #define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
 333 #define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
 334 #define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
 335
 336 #define SVM_SELECTOR_WRITE_MASK (1 << 1)
 337 #define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
 338 #define SVM_SELECTOR_CODE_MASK (1 << 3)
 339
 340 #define INTERCEPT_CR0_READ      0
 341 #define INTERCEPT_CR3_READ      3
 342 #define INTERCEPT_CR4_READ      4
 343 #define INTERCEPT_CR8_READ      8
 344 #define INTERCEPT_CR0_WRITE     (16 + 0)
 345 #define INTERCEPT_CR3_WRITE     (16 + 3)
 346 #define INTERCEPT_CR4_WRITE     (16 + 4)
 347 #define INTERCEPT_CR8_WRITE     (16 + 8)
 348
 349 #define INTERCEPT_DR0_READ      0
 350 #define INTERCEPT_DR1_READ      1
 351 #define INTERCEPT_DR2_READ      2
 352 #define INTERCEPT_DR3_READ      3
 353 #define INTERCEPT_DR4_READ      4
 354 #define INTERCEPT_DR5_READ      5
 355 #define INTERCEPT_DR6_READ      6
 356 #define INTERCEPT_DR7_READ      7
 357 #define INTERCEPT_DR0_WRITE     (16 + 0)
 358 #define INTERCEPT_DR1_WRITE     (16 + 1)
 359 #define INTERCEPT_DR2_WRITE     (16 + 2)
 360 #define INTERCEPT_DR3_WRITE     (16 + 3)
 361 #define INTERCEPT_DR4_WRITE     (16 + 4)
 362 #define INTERCEPT_DR5_WRITE     (16 + 5)
 363 #define INTERCEPT_DR6_WRITE     (16 + 6)
 364 #define INTERCEPT_DR7_WRITE     (16 + 7)
 365
 366 #define SVM_EVTINJ_VEC_MASK 0xff
 367
 368 #define SVM_EVTINJ_TYPE_SHIFT 8
 369 #define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
 370
 371 #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
 372 #define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
 373 #define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
 374 #define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
 375
 376 #define SVM_EVTINJ_VALID (1 << 31)
 377 #define SVM_EVTINJ_VALID_ERR (1 << 11)
 378
 379 #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
 380 #define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK
 381
 382 #define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
 383 #define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
 384 #define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
 385 #define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
 386
 387 #define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
 388 #define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
 389
 390 #define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
 391 #define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
 392 #define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44
 393
 394 #define SVM_EXITINFO_REG_MASK 0x0F
 395
 396 #define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP)
 397
 398 #define SVM_VMLOAD ".byte 0x0f, 0x01, 0xda"
 399 #define SVM_VMRUN  ".byte 0x0f, 0x01, 0xd8"
 400 #define SVM_VMSAVE ".byte 0x0f, 0x01, 0xdb"
 401 #define SVM_CLGI   ".byte 0x0f, 0x01, 0xdd"
 402 #define SVM_STGI   ".byte 0x0f, 0x01, 0xdc"
 403 #define SVM_INVLPGA ".byte 0x0f, 0x01, 0xdf"
 404
 405 #endif
 406
 407 #endif