2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/gfp.h>
23 #include <linux/list.h>
24 #include <linux/sysdev.h>
25 #include <linux/interrupt.h>
26 #include <linux/msi.h>
27 #include <asm/pci-direct.h>
28 #include <asm/amd_iommu_types.h>
29 #include <asm/amd_iommu.h>
30 #include <asm/iommu.h>
32 #include <asm/x86_init.h>
35 * definitions for the ACPI scanning code
37 #define IVRS_HEADER_LENGTH 48
39 #define ACPI_IVHD_TYPE 0x10
40 #define ACPI_IVMD_TYPE_ALL 0x20
41 #define ACPI_IVMD_TYPE 0x21
42 #define ACPI_IVMD_TYPE_RANGE 0x22
44 #define IVHD_DEV_ALL 0x01
45 #define IVHD_DEV_SELECT 0x02
46 #define IVHD_DEV_SELECT_RANGE_START 0x03
47 #define IVHD_DEV_RANGE_END 0x04
48 #define IVHD_DEV_ALIAS 0x42
49 #define IVHD_DEV_ALIAS_RANGE 0x43
50 #define IVHD_DEV_EXT_SELECT 0x46
51 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
53 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
54 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
55 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
56 #define IVHD_FLAG_ISOC_EN_MASK 0x08
58 #define IVMD_FLAG_EXCL_RANGE 0x08
59 #define IVMD_FLAG_UNITY_MAP 0x01
61 #define ACPI_DEVFLAG_INITPASS 0x01
62 #define ACPI_DEVFLAG_EXTINT 0x02
63 #define ACPI_DEVFLAG_NMI 0x04
64 #define ACPI_DEVFLAG_SYSMGT1 0x10
65 #define ACPI_DEVFLAG_SYSMGT2 0x20
66 #define ACPI_DEVFLAG_LINT0 0x40
67 #define ACPI_DEVFLAG_LINT1 0x80
68 #define ACPI_DEVFLAG_ATSDIS 0x10000000
71 * ACPI table definitions
73 * These data structures are laid over the table to parse the important values
78 * structure describing one IOMMU in the ACPI table. Typically followed by one
79 * or more ivhd_entrys.
91 } __attribute__((packed));
94 * A device entry describing which devices a specific IOMMU translates and
95 * which requestor ids they use.
102 } __attribute__((packed));
105 * An AMD IOMMU memory definition structure. It defines things like exclusion
106 * ranges for devices and regions that should be unity mapped.
117 } __attribute__((packed));
121 static int __initdata amd_iommu_detected;
123 u16 amd_iommu_last_bdf; /* largest PCI device id we have
125 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
127 #ifdef CONFIG_IOMMU_STRESS
128 bool amd_iommu_isolate = false;
130 bool amd_iommu_isolate = true; /* if true, device isolation is
134 bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
136 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
140 * Pointer to the device table which is shared by all AMD IOMMUs
141 * it is indexed by the PCI device id or the HT unit id and contains
142 * information about the domain the device belongs to as well as the
143 * page table root pointer.
145 struct dev_table_entry *amd_iommu_dev_table;
148 * The alias table is a driver specific data structure which contains the
149 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
150 * More than one device can share the same requestor id.
152 u16 *amd_iommu_alias_table;
155 * The rlookup table is used to find the IOMMU which is responsible
156 * for a specific device. It is also indexed by the PCI device id.
158 struct amd_iommu **amd_iommu_rlookup_table;
161 * The pd table (protection domain table) is used to find the protection domain
162 * data structure a device belongs to. Indexed with the PCI device id too.
164 struct protection_domain **amd_iommu_pd_table;
167 * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap
168 * to know which ones are already in use.
170 unsigned long *amd_iommu_pd_alloc_bitmap;
172 static u32 dev_table_size; /* size of the device table */
173 static u32 alias_table_size; /* size of the alias table */
174 static u32 rlookup_table_size; /* size if the rlookup table */
176 static inline void update_last_devid(u16 devid)
178 if (devid > amd_iommu_last_bdf)
179 amd_iommu_last_bdf = devid;
182 static inline unsigned long tbl_size(int entry_size)
184 unsigned shift = PAGE_SHIFT +
185 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
190 /****************************************************************************
192 * AMD IOMMU MMIO register space handling functions
194 * These functions are used to program the IOMMU device registers in
195 * MMIO space required for that driver.
197 ****************************************************************************/
200 * This function set the exclusion range in the IOMMU. DMA accesses to the
201 * exclusion range are passed through untranslated
203 static void iommu_set_exclusion_range(struct amd_iommu *iommu)
205 u64 start = iommu->exclusion_start & PAGE_MASK;
206 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
209 if (!iommu->exclusion_start)
212 entry = start | MMIO_EXCL_ENABLE_MASK;
213 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
214 &entry, sizeof(entry));
217 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
218 &entry, sizeof(entry));
221 /* Programs the physical address of the device table into the IOMMU hardware */
222 static void __init iommu_set_device_table(struct amd_iommu *iommu)
226 BUG_ON(iommu->mmio_base == NULL);
228 entry = virt_to_phys(amd_iommu_dev_table);
229 entry |= (dev_table_size >> 12) - 1;
230 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
231 &entry, sizeof(entry));
234 /* Generic functions to enable/disable certain features of the IOMMU. */
235 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
239 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
241 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
244 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
248 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
250 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
253 /* Function to enable the hardware */
254 static void iommu_enable(struct amd_iommu *iommu)
256 printk(KERN_INFO "AMD-Vi: Enabling IOMMU at %s cap 0x%hx\n",
257 dev_name(&iommu->dev->dev), iommu->cap_ptr);
259 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
262 static void iommu_disable(struct amd_iommu *iommu)
264 /* Disable command buffer */
265 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
267 /* Disable event logging and event interrupts */
268 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
269 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
271 /* Disable IOMMU hardware itself */
272 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
276 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
277 * the system has one.
279 static u8 * __init iommu_map_mmio_space(u64 address)
283 if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu"))
286 ret = ioremap_nocache(address, MMIO_REGION_LENGTH);
290 release_mem_region(address, MMIO_REGION_LENGTH);
295 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
297 if (iommu->mmio_base)
298 iounmap(iommu->mmio_base);
299 release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH);
302 /****************************************************************************
304 * The functions below belong to the first pass of AMD IOMMU ACPI table
305 * parsing. In this pass we try to find out the highest device id this
306 * code has to handle. Upon this information the size of the shared data
307 * structures is determined later.
309 ****************************************************************************/
312 * This function calculates the length of a given IVHD entry
314 static inline int ivhd_entry_length(u8 *ivhd)
316 return 0x04 << (*ivhd >> 6);
320 * This function reads the last device id the IOMMU has to handle from the PCI
321 * capability header for this IOMMU
323 static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
327 cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
328 update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));
334 * After reading the highest device id from the IOMMU PCI capability header
335 * this function looks if there is a higher device id defined in the ACPI table
337 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
339 u8 *p = (void *)h, *end = (void *)h;
340 struct ivhd_entry *dev;
345 find_last_devid_on_pci(PCI_BUS(h->devid),
351 dev = (struct ivhd_entry *)p;
353 case IVHD_DEV_SELECT:
354 case IVHD_DEV_RANGE_END:
356 case IVHD_DEV_EXT_SELECT:
357 /* all the above subfield types refer to device ids */
358 update_last_devid(dev->devid);
363 p += ivhd_entry_length(p);
372 * Iterate over all IVHD entries in the ACPI table and find the highest device
373 * id which we need to handle. This is the first of three functions which parse
374 * the ACPI table. So we check the checksum here.
376 static int __init find_last_devid_acpi(struct acpi_table_header *table)
379 u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
380 struct ivhd_header *h;
383 * Validate checksum here so we don't need to do it when
384 * we actually parse the table
386 for (i = 0; i < table->length; ++i)
389 /* ACPI table corrupt */
392 p += IVRS_HEADER_LENGTH;
394 end += table->length;
396 h = (struct ivhd_header *)p;
399 find_last_devid_from_ivhd(h);
411 /****************************************************************************
413 * The following functions belong the the code path which parses the ACPI table
414 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
415 * data structures, initialize the device/alias/rlookup table and also
416 * basically initialize the hardware.
418 ****************************************************************************/
421 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
422 * write commands to that buffer later and the IOMMU will execute them
425 static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
427 u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
428 get_order(CMD_BUFFER_SIZE));
433 iommu->cmd_buf_size = CMD_BUFFER_SIZE;
439 * This function resets the command buffer if the IOMMU stopped fetching
442 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
444 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
446 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
447 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
449 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
453 * This function writes the command buffer address to the hardware and
456 static void iommu_enable_command_buffer(struct amd_iommu *iommu)
460 BUG_ON(iommu->cmd_buf == NULL);
462 entry = (u64)virt_to_phys(iommu->cmd_buf);
463 entry |= MMIO_CMD_SIZE_512;
465 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
466 &entry, sizeof(entry));
468 amd_iommu_reset_cmd_buffer(iommu);
471 static void __init free_command_buffer(struct amd_iommu *iommu)
473 free_pages((unsigned long)iommu->cmd_buf,
474 get_order(iommu->cmd_buf_size));
477 /* allocates the memory where the IOMMU will log its events to */
478 static u8 * __init alloc_event_buffer(struct amd_iommu *iommu)
480 iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
481 get_order(EVT_BUFFER_SIZE));
483 if (iommu->evt_buf == NULL)
486 iommu->evt_buf_size = EVT_BUFFER_SIZE;
488 return iommu->evt_buf;
491 static void iommu_enable_event_buffer(struct amd_iommu *iommu)
495 BUG_ON(iommu->evt_buf == NULL);
497 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
499 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
500 &entry, sizeof(entry));
502 /* set head and tail to zero manually */
503 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
504 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
506 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
509 static void __init free_event_buffer(struct amd_iommu *iommu)
511 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
514 /* sets a specific bit in the device table entry. */
515 static void set_dev_entry_bit(u16 devid, u8 bit)
517 int i = (bit >> 5) & 0x07;
518 int _bit = bit & 0x1f;
520 amd_iommu_dev_table[devid].data[i] |= (1 << _bit);
523 static int get_dev_entry_bit(u16 devid, u8 bit)
525 int i = (bit >> 5) & 0x07;
526 int _bit = bit & 0x1f;
528 return (amd_iommu_dev_table[devid].data[i] & (1 << _bit)) >> _bit;
532 void amd_iommu_apply_erratum_63(u16 devid)
536 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
537 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
540 set_dev_entry_bit(devid, DEV_ENTRY_IW);
543 /* Writes the specific IOMMU for a device into the rlookup table */
544 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
546 amd_iommu_rlookup_table[devid] = iommu;
550 * This function takes the device specific flags read from the ACPI
551 * table and sets up the device table entry with that information
553 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
554 u16 devid, u32 flags, u32 ext_flags)
556 if (flags & ACPI_DEVFLAG_INITPASS)
557 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
558 if (flags & ACPI_DEVFLAG_EXTINT)
559 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
560 if (flags & ACPI_DEVFLAG_NMI)
561 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
562 if (flags & ACPI_DEVFLAG_SYSMGT1)
563 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
564 if (flags & ACPI_DEVFLAG_SYSMGT2)
565 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
566 if (flags & ACPI_DEVFLAG_LINT0)
567 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
568 if (flags & ACPI_DEVFLAG_LINT1)
569 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
571 amd_iommu_apply_erratum_63(devid);
573 set_iommu_for_device(iommu, devid);
577 * Reads the device exclusion range from ACPI and initialize IOMMU with
580 static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
582 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
584 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
589 * We only can configure exclusion ranges per IOMMU, not
590 * per device. But we can enable the exclusion range per
591 * device. This is done here
593 set_dev_entry_bit(m->devid, DEV_ENTRY_EX);
594 iommu->exclusion_start = m->range_start;
595 iommu->exclusion_length = m->range_length;
600 * This function reads some important data from the IOMMU PCI space and
601 * initializes the driver data structure with it. It reads the hardware
602 * capabilities and the first/last device entries
604 static void __init init_iommu_from_pci(struct amd_iommu *iommu)
606 int cap_ptr = iommu->cap_ptr;
609 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
611 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
613 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
616 iommu->first_device = calc_devid(MMIO_GET_BUS(range),
618 iommu->last_device = calc_devid(MMIO_GET_BUS(range),
620 iommu->evt_msi_num = MMIO_MSI_NUM(misc);
624 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
625 * initializes the hardware and our data structures with it.
627 static void __init init_iommu_from_acpi(struct amd_iommu *iommu,
628 struct ivhd_header *h)
631 u8 *end = p, flags = 0;
632 u16 dev_i, devid = 0, devid_start = 0, devid_to = 0;
635 struct ivhd_entry *e;
638 * First set the recommended feature enable bits from ACPI
639 * into the IOMMU control registers
641 h->flags & IVHD_FLAG_HT_TUN_EN_MASK ?
642 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
643 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
645 h->flags & IVHD_FLAG_PASSPW_EN_MASK ?
646 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
647 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
649 h->flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
650 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
651 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
653 h->flags & IVHD_FLAG_ISOC_EN_MASK ?
654 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
655 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
658 * make IOMMU memory accesses cache coherent
660 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
663 * Done. Now parse the device entries
665 p += sizeof(struct ivhd_header);
670 e = (struct ivhd_entry *)p;
674 DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x"
675 " last device %02x:%02x.%x flags: %02x\n",
676 PCI_BUS(iommu->first_device),
677 PCI_SLOT(iommu->first_device),
678 PCI_FUNC(iommu->first_device),
679 PCI_BUS(iommu->last_device),
680 PCI_SLOT(iommu->last_device),
681 PCI_FUNC(iommu->last_device),
684 for (dev_i = iommu->first_device;
685 dev_i <= iommu->last_device; ++dev_i)
686 set_dev_entry_from_acpi(iommu, dev_i,
689 case IVHD_DEV_SELECT:
691 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
699 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
701 case IVHD_DEV_SELECT_RANGE_START:
703 DUMP_printk(" DEV_SELECT_RANGE_START\t "
704 "devid: %02x:%02x.%x flags: %02x\n",
710 devid_start = e->devid;
717 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
718 "flags: %02x devid_to: %02x:%02x.%x\n",
723 PCI_BUS(e->ext >> 8),
724 PCI_SLOT(e->ext >> 8),
725 PCI_FUNC(e->ext >> 8));
728 devid_to = e->ext >> 8;
729 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
730 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
731 amd_iommu_alias_table[devid] = devid_to;
733 case IVHD_DEV_ALIAS_RANGE:
735 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
736 "devid: %02x:%02x.%x flags: %02x "
737 "devid_to: %02x:%02x.%x\n",
742 PCI_BUS(e->ext >> 8),
743 PCI_SLOT(e->ext >> 8),
744 PCI_FUNC(e->ext >> 8));
746 devid_start = e->devid;
748 devid_to = e->ext >> 8;
752 case IVHD_DEV_EXT_SELECT:
754 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
755 "flags: %02x ext: %08x\n",
762 set_dev_entry_from_acpi(iommu, devid, e->flags,
765 case IVHD_DEV_EXT_SELECT_RANGE:
767 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
768 "%02x:%02x.%x flags: %02x ext: %08x\n",
774 devid_start = e->devid;
779 case IVHD_DEV_RANGE_END:
781 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
787 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
789 amd_iommu_alias_table[dev_i] = devid_to;
790 set_dev_entry_from_acpi(iommu,
791 devid_to, flags, ext_flags);
793 set_dev_entry_from_acpi(iommu, dev_i,
801 p += ivhd_entry_length(p);
805 /* Initializes the device->iommu mapping for the driver */
806 static int __init init_iommu_devices(struct amd_iommu *iommu)
810 for (i = iommu->first_device; i <= iommu->last_device; ++i)
811 set_iommu_for_device(iommu, i);
816 static void __init free_iommu_one(struct amd_iommu *iommu)
818 free_command_buffer(iommu);
819 free_event_buffer(iommu);
820 iommu_unmap_mmio_space(iommu);
823 static void __init free_iommu_all(void)
825 struct amd_iommu *iommu, *next;
827 for_each_iommu_safe(iommu, next) {
828 list_del(&iommu->list);
829 free_iommu_one(iommu);
835 * This function clues the initialization function for one IOMMU
836 * together and also allocates the command buffer and programs the
837 * hardware. It does NOT enable the IOMMU. This is done afterwards.
839 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
841 spin_lock_init(&iommu->lock);
842 list_add_tail(&iommu->list, &amd_iommu_list);
845 * Copy data from ACPI table entry to the iommu struct
847 iommu->dev = pci_get_bus_and_slot(PCI_BUS(h->devid), h->devid & 0xff);
851 iommu->cap_ptr = h->cap_ptr;
852 iommu->pci_seg = h->pci_seg;
853 iommu->mmio_phys = h->mmio_phys;
854 iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys);
855 if (!iommu->mmio_base)
858 iommu->cmd_buf = alloc_command_buffer(iommu);
862 iommu->evt_buf = alloc_event_buffer(iommu);
866 iommu->int_enabled = false;
868 init_iommu_from_pci(iommu);
869 init_iommu_from_acpi(iommu, h);
870 init_iommu_devices(iommu);
872 return pci_enable_device(iommu->dev);
876 * Iterates over all IOMMU entries in the ACPI table, allocates the
877 * IOMMU structure and initializes it with init_iommu_one()
879 static int __init init_iommu_all(struct acpi_table_header *table)
881 u8 *p = (u8 *)table, *end = (u8 *)table;
882 struct ivhd_header *h;
883 struct amd_iommu *iommu;
886 end += table->length;
887 p += IVRS_HEADER_LENGTH;
890 h = (struct ivhd_header *)p;
894 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
895 "seg: %d flags: %01x info %04x\n",
896 PCI_BUS(h->devid), PCI_SLOT(h->devid),
897 PCI_FUNC(h->devid), h->cap_ptr,
898 h->pci_seg, h->flags, h->info);
899 DUMP_printk(" mmio-addr: %016llx\n",
902 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
905 ret = init_iommu_one(iommu, h);
920 /****************************************************************************
922 * The following functions initialize the MSI interrupts for all IOMMUs
923 * in the system. Its a bit challenging because there could be multiple
924 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
927 ****************************************************************************/
929 static int __init iommu_setup_msi(struct amd_iommu *iommu)
933 if (pci_enable_msi(iommu->dev))
936 r = request_irq(iommu->dev->irq, amd_iommu_int_handler,
942 pci_disable_msi(iommu->dev);
946 iommu->int_enabled = true;
947 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
952 static int iommu_init_msi(struct amd_iommu *iommu)
954 if (iommu->int_enabled)
957 if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI))
958 return iommu_setup_msi(iommu);
963 /****************************************************************************
965 * The next functions belong to the third pass of parsing the ACPI
966 * table. In this last pass the memory mapping requirements are
967 * gathered (like exclusion and unity mapping reanges).
969 ****************************************************************************/
971 static void __init free_unity_maps(void)
973 struct unity_map_entry *entry, *next;
975 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
976 list_del(&entry->list);
981 /* called when we find an exclusion range definition in ACPI */
982 static int __init init_exclusion_range(struct ivmd_header *m)
988 set_device_exclusion_range(m->devid, m);
990 case ACPI_IVMD_TYPE_ALL:
991 for (i = 0; i <= amd_iommu_last_bdf; ++i)
992 set_device_exclusion_range(i, m);
994 case ACPI_IVMD_TYPE_RANGE:
995 for (i = m->devid; i <= m->aux; ++i)
996 set_device_exclusion_range(i, m);
1005 /* called for unity map ACPI definition */
1006 static int __init init_unity_map_range(struct ivmd_header *m)
1008 struct unity_map_entry *e = 0;
1011 e = kzalloc(sizeof(*e), GFP_KERNEL);
1019 case ACPI_IVMD_TYPE:
1020 s = "IVMD_TYPEi\t\t\t";
1021 e->devid_start = e->devid_end = m->devid;
1023 case ACPI_IVMD_TYPE_ALL:
1024 s = "IVMD_TYPE_ALL\t\t";
1026 e->devid_end = amd_iommu_last_bdf;
1028 case ACPI_IVMD_TYPE_RANGE:
1029 s = "IVMD_TYPE_RANGE\t\t";
1030 e->devid_start = m->devid;
1031 e->devid_end = m->aux;
1034 e->address_start = PAGE_ALIGN(m->range_start);
1035 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
1036 e->prot = m->flags >> 1;
1038 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1039 " range_start: %016llx range_end: %016llx flags: %x\n", s,
1040 PCI_BUS(e->devid_start), PCI_SLOT(e->devid_start),
1041 PCI_FUNC(e->devid_start), PCI_BUS(e->devid_end),
1042 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
1043 e->address_start, e->address_end, m->flags);
1045 list_add_tail(&e->list, &amd_iommu_unity_map);
1050 /* iterates over all memory definitions we find in the ACPI table */
1051 static int __init init_memory_definitions(struct acpi_table_header *table)
1053 u8 *p = (u8 *)table, *end = (u8 *)table;
1054 struct ivmd_header *m;
1056 end += table->length;
1057 p += IVRS_HEADER_LENGTH;
1060 m = (struct ivmd_header *)p;
1061 if (m->flags & IVMD_FLAG_EXCL_RANGE)
1062 init_exclusion_range(m);
1063 else if (m->flags & IVMD_FLAG_UNITY_MAP)
1064 init_unity_map_range(m);
1073 * Init the device table to not allow DMA access for devices and
1074 * suppress all page faults
1076 static void init_device_table(void)
1080 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1081 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
1082 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
1087 * This function finally enables all IOMMUs found in the system after
1088 * they have been initialized
1090 static void enable_iommus(void)
1092 struct amd_iommu *iommu;
1094 for_each_iommu(iommu) {
1095 iommu_disable(iommu);
1096 iommu_set_device_table(iommu);
1097 iommu_enable_command_buffer(iommu);
1098 iommu_enable_event_buffer(iommu);
1099 iommu_set_exclusion_range(iommu);
1100 iommu_init_msi(iommu);
1101 iommu_enable(iommu);
1105 static void disable_iommus(void)
1107 struct amd_iommu *iommu;
1109 for_each_iommu(iommu)
1110 iommu_disable(iommu);
1114 * Suspend/Resume support
1115 * disable suspend until real resume implemented
1118 static int amd_iommu_resume(struct sys_device *dev)
1120 /* re-load the hardware */
1124 * we have to flush after the IOMMUs are enabled because a
1125 * disabled IOMMU will never execute the commands we send
1127 amd_iommu_flush_all_devices();
1128 amd_iommu_flush_all_domains();
1133 static int amd_iommu_suspend(struct sys_device *dev, pm_message_t state)
1135 /* disable IOMMUs to go out of the way for BIOS */
1141 static struct sysdev_class amd_iommu_sysdev_class = {
1142 .name = "amd_iommu",
1143 .suspend = amd_iommu_suspend,
1144 .resume = amd_iommu_resume,
1147 static struct sys_device device_amd_iommu = {
1149 .cls = &amd_iommu_sysdev_class,
1153 * This is the core init function for AMD IOMMU hardware in the system.
1154 * This function is called from the generic x86 DMA layer initialization
1157 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
1160 * 1 pass) Find the highest PCI device id the driver has to handle.
1161 * Upon this information the size of the data structures is
1162 * determined that needs to be allocated.
1164 * 2 pass) Initialize the data structures just allocated with the
1165 * information in the ACPI table about available AMD IOMMUs
1166 * in the system. It also maps the PCI devices in the
1167 * system to specific IOMMUs
1169 * 3 pass) After the basic data structures are allocated and
1170 * initialized we update them with information about memory
1171 * remapping requirements parsed out of the ACPI table in
1174 * After that the hardware is initialized and ready to go. In the last
1175 * step we do some Linux specific things like registering the driver in
1176 * the dma_ops interface and initializing the suspend/resume support
1177 * functions. Finally it prints some information about AMD IOMMUs and
1178 * the driver state and enables the hardware.
1180 static int __init amd_iommu_init(void)
1185 * First parse ACPI tables to find the largest Bus/Dev/Func
1186 * we need to handle. Upon this information the shared data
1187 * structures for the IOMMUs in the system will be allocated
1189 if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0)
1192 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
1193 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
1194 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
1198 /* Device table - directly used by all IOMMUs */
1199 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
1200 get_order(dev_table_size));
1201 if (amd_iommu_dev_table == NULL)
1205 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1206 * IOMMU see for that device
1208 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
1209 get_order(alias_table_size));
1210 if (amd_iommu_alias_table == NULL)
1213 /* IOMMU rlookup table - find the IOMMU for a specific device */
1214 amd_iommu_rlookup_table = (void *)__get_free_pages(
1215 GFP_KERNEL | __GFP_ZERO,
1216 get_order(rlookup_table_size));
1217 if (amd_iommu_rlookup_table == NULL)
1221 * Protection Domain table - maps devices to protection domains
1222 * This table has the same size as the rlookup_table
1224 amd_iommu_pd_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
1225 get_order(rlookup_table_size));
1226 if (amd_iommu_pd_table == NULL)
1229 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
1230 GFP_KERNEL | __GFP_ZERO,
1231 get_order(MAX_DOMAIN_ID/8));
1232 if (amd_iommu_pd_alloc_bitmap == NULL)
1235 /* init the device table */
1236 init_device_table();
1239 * let all alias entries point to itself
1241 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1242 amd_iommu_alias_table[i] = i;
1245 * never allocate domain 0 because its used as the non-allocated and
1246 * error value placeholder
1248 amd_iommu_pd_alloc_bitmap[0] = 1;
1251 * now the data structures are allocated and basically initialized
1252 * start the real acpi table scan
1255 if (acpi_table_parse("IVRS", init_iommu_all) != 0)
1258 if (acpi_table_parse("IVRS", init_memory_definitions) != 0)
1261 ret = sysdev_class_register(&amd_iommu_sysdev_class);
1265 ret = sysdev_register(&device_amd_iommu);
1269 if (iommu_pass_through)
1270 ret = amd_iommu_init_passthrough();
1272 ret = amd_iommu_init_dma_ops();
1278 if (iommu_pass_through)
1281 printk(KERN_INFO "AMD-Vi: device isolation ");
1282 if (amd_iommu_isolate)
1283 printk("enabled\n");
1285 printk("disabled\n");
1287 if (amd_iommu_unmap_flush)
1288 printk(KERN_INFO "AMD-Vi: IO/TLB flush on unmap enabled\n");
1290 printk(KERN_INFO "AMD-Vi: Lazy IO/TLB flushing enabled\n");
1292 x86_platform.iommu_shutdown = disable_iommus;
1297 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
1298 get_order(MAX_DOMAIN_ID/8));
1300 free_pages((unsigned long)amd_iommu_pd_table,
1301 get_order(rlookup_table_size));
1303 free_pages((unsigned long)amd_iommu_rlookup_table,
1304 get_order(rlookup_table_size));
1306 free_pages((unsigned long)amd_iommu_alias_table,
1307 get_order(alias_table_size));
1309 free_pages((unsigned long)amd_iommu_dev_table,
1310 get_order(dev_table_size));
1319 /****************************************************************************
1321 * Early detect code. This code runs at IOMMU detection time in the DMA
1322 * layer. It just looks if there is an IVRS ACPI table to detect AMD
1325 ****************************************************************************/
1326 static int __init early_amd_iommu_detect(struct acpi_table_header *table)
1331 void __init amd_iommu_detect(void)
1333 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
1336 if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) {
1338 amd_iommu_detected = 1;
1339 x86_init.iommu.iommu_init = amd_iommu_init;
1343 /****************************************************************************
1345 * Parsing functions for the AMD IOMMU specific kernel command line
1348 ****************************************************************************/
1350 static int __init parse_amd_iommu_dump(char *str)
1352 amd_iommu_dump = true;
1357 static int __init parse_amd_iommu_options(char *str)
1359 for (; *str; ++str) {
1360 if (strncmp(str, "isolate", 7) == 0)
1361 amd_iommu_isolate = true;
1362 if (strncmp(str, "share", 5) == 0)
1363 amd_iommu_isolate = false;
1364 if (strncmp(str, "fullflush", 9) == 0)
1365 amd_iommu_unmap_flush = true;
1371 __setup("amd_iommu_dump", parse_amd_iommu_dump);
1372 __setup("amd_iommu=", parse_amd_iommu_options);