arch/x86/kernel/apic/x2apic_uv_x.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * SGI UV APIC functions (note: not an Intel compatible APIC)
   7  *
   8  * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
   9  */
  10 #include <linux/cpumask.h>
  11 #include <linux/hardirq.h>
  12 #include <linux/proc_fs.h>
  13 #include <linux/threads.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/string.h>
  17 #include <linux/ctype.h>
  18 #include <linux/sched.h>
  19 #include <linux/timer.h>
  20 #include <linux/slab.h>
  21 #include <linux/cpu.h>
  22 #include <linux/init.h>
  23 #include <linux/io.h>
  24 #include <linux/pci.h>
  25 #include <linux/kdebug.h>
  26 #include <linux/delay.h>
  27 #include <linux/crash_dump.h>
  28 #include <linux/reboot.h>
  29
  30 #include <asm/uv/uv_mmrs.h>
  31 #include <asm/uv/uv_hub.h>
  32 #include <asm/current.h>
  33 #include <asm/pgtable.h>
  34 #include <asm/uv/bios.h>
  35 #include <asm/uv/uv.h>
  36 #include <asm/apic.h>
  37 #include <asm/ipi.h>
  38 #include <asm/smp.h>
  39 #include <asm/x86_init.h>
  40 #include <asm/nmi.h>
  41
  42 DEFINE_PER_CPU(int, x2apic_extra_bits);
  43
  44 #define PR_DEVEL(fmt, args...)  pr_devel("%s: " fmt, __func__, args)
  45
  46 static enum uv_system_type uv_system_type;
  47 static u64 gru_start_paddr, gru_end_paddr;
  48 static u64 gru_dist_base, gru_first_node_paddr = -1LL, gru_last_node_paddr;
  49 static u64 gru_dist_lmask, gru_dist_umask;
  50 static union uvh_apicid uvh_apicid;
  51
  52 /* info derived from CPUID */
  53 static struct {
  54         unsigned int apicid_shift;
  55         unsigned int apicid_mask;
  56         unsigned int socketid_shift;    /* aka pnode_shift for UV1/2/3 */
  57         unsigned int pnode_mask;
  58         unsigned int gpa_shift;
  59 } uv_cpuid;
  60
  61 int uv_min_hub_revision_id;
  62 EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
  63 unsigned int uv_apicid_hibits;
  64 EXPORT_SYMBOL_GPL(uv_apicid_hibits);
  65
  66 static struct apic apic_x2apic_uv_x;
  67 static struct uv_hub_info_s uv_hub_info_node0;
  68
  69 /* Set this to use hardware error handler instead of kernel panic */
  70 static int disable_uv_undefined_panic = 1;
  71 unsigned long uv_undefined(char *str)
  72 {
  73         if (likely(!disable_uv_undefined_panic))
  74                 panic("UV: error: undefined MMR: %s\n", str);
  75         else
  76                 pr_crit("UV: error: undefined MMR: %s\n", str);
  77         return ~0ul;    /* cause a machine fault  */
  78 }
  79 EXPORT_SYMBOL(uv_undefined);
  80
  81 static unsigned long __init uv_early_read_mmr(unsigned long addr)
  82 {
  83         unsigned long val, *mmr;
  84
  85         mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
  86         val = *mmr;
  87         early_iounmap(mmr, sizeof(*mmr));
  88         return val;
  89 }
  90
  91 static inline bool is_GRU_range(u64 start, u64 end)
  92 {
  93         if (gru_dist_base) {
  94                 u64 su = start & gru_dist_umask; /* upper (incl pnode) bits */
  95                 u64 sl = start & gru_dist_lmask; /* base offset bits */
  96                 u64 eu = end & gru_dist_umask;
  97                 u64 el = end & gru_dist_lmask;
  98
  99                 /* Must reside completely within a single GRU range */
 100                 return (sl == gru_dist_base && el == gru_dist_base &&
 101                         su >= gru_first_node_paddr &&
 102                         su <= gru_last_node_paddr &&
 103                         eu == su);
 104         } else {
 105                 return start >= gru_start_paddr && end <= gru_end_paddr;
 106         }
 107 }
 108
 109 static bool uv_is_untracked_pat_range(u64 start, u64 end)
 110 {
 111         return is_ISA_range(start, end) || is_GRU_range(start, end);
 112 }
 113
 114 static int __init early_get_pnodeid(void)
 115 {
 116         union uvh_node_id_u node_id;
 117         union uvh_rh_gam_config_mmr_u  m_n_config;
 118         int pnode;
 119
 120         /* Currently, all blades have same revision number */
 121         node_id.v = uv_early_read_mmr(UVH_NODE_ID);
 122         m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR);
 123         uv_min_hub_revision_id = node_id.s.revision;
 124
 125         switch (node_id.s.part_number) {
 126         case UV2_HUB_PART_NUMBER:
 127         case UV2_HUB_PART_NUMBER_X:
 128                 uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1;
 129                 break;
 130         case UV3_HUB_PART_NUMBER:
 131         case UV3_HUB_PART_NUMBER_X:
 132                 uv_min_hub_revision_id += UV3_HUB_REVISION_BASE;
 133                 break;
 134         case UV4_HUB_PART_NUMBER:
 135                 uv_min_hub_revision_id += UV4_HUB_REVISION_BASE - 1;
 136                 break;
 137         }
 138
 139         uv_hub_info->hub_revision = uv_min_hub_revision_id;
 140         uv_cpuid.pnode_mask = (1 << m_n_config.s.n_skt) - 1;
 141         pnode = (node_id.s.node_id >> 1) & uv_cpuid.pnode_mask;
 142         uv_cpuid.gpa_shift = 46;        /* default unless changed */
 143
 144         pr_info("UV: rev:%d part#:%x nodeid:%04x n_skt:%d pnmsk:%x pn:%x\n",
 145                 node_id.s.revision, node_id.s.part_number, node_id.s.node_id,
 146                 m_n_config.s.n_skt, uv_cpuid.pnode_mask, pnode);
 147         return pnode;
 148 }
 149
 150 /* [copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()] */
 151 #define SMT_LEVEL       0       /* leaf 0xb SMT level */
 152 #define INVALID_TYPE    0       /* leaf 0xb sub-leaf types */
 153 #define SMT_TYPE        1
 154 #define CORE_TYPE       2
 155 #define LEAFB_SUBTYPE(ecx)              (((ecx) >> 8) & 0xff)
 156 #define BITS_SHIFT_NEXT_LEVEL(eax)      ((eax) & 0x1f)
 157
 158 static void set_x2apic_bits(void)
 159 {
 160         unsigned int eax, ebx, ecx, edx, sub_index;
 161         unsigned int sid_shift;
 162
 163         cpuid(0, &eax, &ebx, &ecx, &edx);
 164         if (eax < 0xb) {
 165                 pr_info("UV: CPU does not have CPUID.11\n");
 166                 return;
 167         }
 168         cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx);
 169         if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) {
 170                 pr_info("UV: CPUID.11 not implemented\n");
 171                 return;
 172         }
 173         sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
 174         sub_index = 1;
 175         do {
 176                 cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx);
 177                 if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) {
 178                         sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
 179                         break;
 180                 }
 181                 sub_index++;
 182         } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE);
 183         uv_cpuid.apicid_shift = 0;
 184         uv_cpuid.apicid_mask = (~(-1 << sid_shift));
 185         uv_cpuid.socketid_shift = sid_shift;
 186 }
 187
 188 static void __init early_get_apic_socketid_shift(void)
 189 {
 190         if (is_uv2_hub() || is_uv3_hub())
 191                 uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
 192
 193         set_x2apic_bits();
 194
 195         pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n",
 196                 uv_cpuid.apicid_shift, uv_cpuid.apicid_mask);
 197         pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n",
 198                 uv_cpuid.socketid_shift, uv_cpuid.pnode_mask);
 199 }
 200
 201 /*
 202  * Add an extra bit as dictated by bios to the destination apicid of
 203  * interrupts potentially passing through the UV HUB.  This prevents
 204  * a deadlock between interrupts and IO port operations.
 205  */
 206 static void __init uv_set_apicid_hibit(void)
 207 {
 208         union uv1h_lb_target_physical_apic_id_mask_u apicid_mask;
 209
 210         if (is_uv1_hub()) {
 211                 apicid_mask.v =
 212                         uv_early_read_mmr(UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK);
 213                 uv_apicid_hibits =
 214                         apicid_mask.s1.bit_enables & UV_APICID_HIBIT_MASK;
 215         }
 216 }
 217
 218 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
 219 {
 220         int pnodeid;
 221         int uv_apic;
 222
 223         if (strncmp(oem_id, "SGI", 3) != 0)
 224                 return 0;
 225
 226         /* Setup early hub type field in uv_hub_info for Node 0 */
 227         uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0;
 228
 229         /*
 230          * Determine UV arch type.
 231          *   SGI: UV100/1000
 232          *   SGI2: UV2000/3000
 233          *   SGI3: UV300 (truncated to 4 chars because of different varieties)
 234          *   SGI4: UV400 (truncated to 4 chars because of different varieties)
 235          */
 236         uv_hub_info->hub_revision =
 237                 !strncmp(oem_id, "SGI4", 4) ? UV4_HUB_REVISION_BASE :
 238                 !strncmp(oem_id, "SGI3", 4) ? UV3_HUB_REVISION_BASE :
 239                 !strcmp(oem_id, "SGI2") ? UV2_HUB_REVISION_BASE :
 240                 !strcmp(oem_id, "SGI") ? UV1_HUB_REVISION_BASE : 0;
 241
 242         if (uv_hub_info->hub_revision == 0)
 243                 goto badbios;
 244
 245         pnodeid = early_get_pnodeid();
 246         early_get_apic_socketid_shift();
 247         x86_platform.is_untracked_pat_range =  uv_is_untracked_pat_range;
 248         x86_platform.nmi_init = uv_nmi_init;
 249
 250         if (!strcmp(oem_table_id, "UVX")) {             /* most common */
 251                 uv_system_type = UV_X2APIC;
 252                 uv_apic = 0;
 253
 254         } else if (!strcmp(oem_table_id, "UVH")) {      /* only UV1 systems */
 255                 uv_system_type = UV_NON_UNIQUE_APIC;
 256                 __this_cpu_write(x2apic_extra_bits,
 257                         pnodeid << uvh_apicid.s.pnode_shift);
 258                 uv_set_apicid_hibit();
 259                 uv_apic = 1;
 260
 261         } else  if (!strcmp(oem_table_id, "UVL")) {     /* only used for */
 262                 uv_system_type = UV_LEGACY_APIC;        /* very small systems */
 263                 uv_apic = 0;
 264
 265         } else {
 266                 goto badbios;
 267         }
 268
 269         pr_info("UV: OEM IDs %s/%s, System/HUB Types %d/%d, uv_apic %d\n",
 270                 oem_id, oem_table_id, uv_system_type,
 271                 uv_min_hub_revision_id, uv_apic);
 272
 273         return uv_apic;
 274
 275 badbios:
 276         pr_err("UV: OEM_ID:%s OEM_TABLE_ID:%s\n", oem_id, oem_table_id);
 277         pr_err("Current BIOS not supported, update kernel and/or BIOS\n");
 278         BUG();
 279 }
 280
 281 enum uv_system_type get_uv_system_type(void)
 282 {
 283         return uv_system_type;
 284 }
 285
 286 int is_uv_system(void)
 287 {
 288         return uv_system_type != UV_NONE;
 289 }
 290 EXPORT_SYMBOL_GPL(is_uv_system);
 291
 292 void **__uv_hub_info_list;
 293 EXPORT_SYMBOL_GPL(__uv_hub_info_list);
 294
 295 DEFINE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info);
 296 EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_info);
 297
 298 short uv_possible_blades;
 299 EXPORT_SYMBOL_GPL(uv_possible_blades);
 300
 301 unsigned long sn_rtc_cycles_per_second;
 302 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
 303
 304 /* the following values are used for the per node hub info struct */
 305 static __initdata unsigned short *_node_to_pnode;
 306 static __initdata unsigned short _min_socket, _max_socket;
 307 static __initdata unsigned short _min_pnode, _max_pnode, _gr_table_len;
 308 static __initdata struct uv_gam_range_entry *uv_gre_table;
 309 static __initdata struct uv_gam_parameters *uv_gp_table;
 310 static __initdata unsigned short *_socket_to_node;
 311 static __initdata unsigned short *_socket_to_pnode;
 312 static __initdata unsigned short *_pnode_to_socket;
 313 static __initdata struct uv_gam_range_s *_gr_table;
 314 #define SOCK_EMPTY      ((unsigned short)~0)
 315
 316 extern int uv_hub_info_version(void)
 317 {
 318         return UV_HUB_INFO_VERSION;
 319 }
 320 EXPORT_SYMBOL(uv_hub_info_version);
 321
 322 /* Build GAM range lookup table */
 323 static __init void build_uv_gr_table(void)
 324 {
 325         struct uv_gam_range_entry *gre = uv_gre_table;
 326         struct uv_gam_range_s *grt;
 327         unsigned long last_limit = 0, ram_limit = 0;
 328         int bytes, i, sid, lsid = -1;
 329
 330         if (!gre)
 331                 return;
 332
 333         bytes = _gr_table_len * sizeof(struct uv_gam_range_s);
 334         grt = kzalloc(bytes, GFP_KERNEL);
 335         BUG_ON(!grt);
 336         _gr_table = grt;
 337
 338         for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
 339                 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) {
 340                         if (!ram_limit) {   /* mark hole between ram/non-ram */
 341                                 ram_limit = last_limit;
 342                                 last_limit = gre->limit;
 343                                 lsid++;
 344                                 continue;
 345                         }
 346                         last_limit = gre->limit;
 347                         pr_info("UV: extra hole in GAM RE table @%d\n",
 348                                 (int)(gre - uv_gre_table));
 349                         continue;
 350                 }
 351                 if (_max_socket < gre->sockid) {
 352                         pr_err("UV: GAM table sockid(%d) too large(>%d) @%d\n",
 353                                 gre->sockid, _max_socket,
 354                                 (int)(gre - uv_gre_table));
 355                         continue;
 356                 }
 357                 sid = gre->sockid - _min_socket;
 358                 if (lsid < sid) {               /* new range */
 359                         grt = &_gr_table[sid];
 360                         grt->base = lsid;
 361                         grt->nasid = gre->nasid;
 362                         grt->limit = last_limit = gre->limit;
 363                         lsid = sid;
 364                         continue;
 365                 }
 366                 if (lsid == sid && !ram_limit) {        /* update range */
 367                         if (grt->limit == last_limit) { /* .. if contiguous */
 368                                 grt->limit = last_limit = gre->limit;
 369                                 continue;
 370                         }
 371                 }
 372                 if (!ram_limit) {               /* non-contiguous ram range */
 373                         grt++;
 374                         grt->base = sid - 1;
 375                         grt->nasid = gre->nasid;
 376                         grt->limit = last_limit = gre->limit;
 377                         continue;
 378                 }
 379                 grt++;                          /* non-contiguous/non-ram */
 380                 grt->base = grt - _gr_table;    /* base is this entry */
 381                 grt->nasid = gre->nasid;
 382                 grt->limit = last_limit = gre->limit;
 383                 lsid++;
 384         }
 385
 386         /* shorten table if possible */
 387         grt++;
 388         i = grt - _gr_table;
 389         if (i < _gr_table_len) {
 390                 void *ret;
 391
 392                 bytes = i * sizeof(struct uv_gam_range_s);
 393                 ret = krealloc(_gr_table, bytes, GFP_KERNEL);
 394                 if (ret) {
 395                         _gr_table = ret;
 396                         _gr_table_len = i;
 397                 }
 398         }
 399
 400         /* display resultant gam range table */
 401         for (i = 0, grt = _gr_table; i < _gr_table_len; i++, grt++) {
 402                 int gb = grt->base;
 403                 unsigned long start = gb < 0 ?  0 :
 404                         (unsigned long)_gr_table[gb].limit << UV_GAM_RANGE_SHFT;
 405                 unsigned long end =
 406                         (unsigned long)grt->limit << UV_GAM_RANGE_SHFT;
 407
 408                 pr_info("UV: GAM Range %2d %04x 0x%013lx-0x%013lx (%d)\n",
 409                         i, grt->nasid, start, end, gb);
 410         }
 411 }
 412
 413 static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
 414 {
 415         unsigned long val;
 416         int pnode;
 417
 418         pnode = uv_apicid_to_pnode(phys_apicid);
 419         phys_apicid |= uv_apicid_hibits;
 420         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 421             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 422             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 423             APIC_DM_INIT;
 424         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 425
 426         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 427             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 428             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 429             APIC_DM_STARTUP;
 430         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 431
 432         return 0;
 433 }
 434
 435 static void uv_send_IPI_one(int cpu, int vector)
 436 {
 437         unsigned long apicid;
 438         int pnode;
 439
 440         apicid = per_cpu(x86_cpu_to_apicid, cpu);
 441         pnode = uv_apicid_to_pnode(apicid);
 442         uv_hub_send_ipi(pnode, apicid, vector);
 443 }
 444
 445 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
 446 {
 447         unsigned int cpu;
 448
 449         for_each_cpu(cpu, mask)
 450                 uv_send_IPI_one(cpu, vector);
 451 }
 452
 453 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
 454 {
 455         unsigned int this_cpu = smp_processor_id();
 456         unsigned int cpu;
 457
 458         for_each_cpu(cpu, mask) {
 459                 if (cpu != this_cpu)
 460                         uv_send_IPI_one(cpu, vector);
 461         }
 462 }
 463
 464 static void uv_send_IPI_allbutself(int vector)
 465 {
 466         unsigned int this_cpu = smp_processor_id();
 467         unsigned int cpu;
 468
 469         for_each_online_cpu(cpu) {
 470                 if (cpu != this_cpu)
 471                         uv_send_IPI_one(cpu, vector);
 472         }
 473 }
 474
 475 static void uv_send_IPI_all(int vector)
 476 {
 477         uv_send_IPI_mask(cpu_online_mask, vector);
 478 }
 479
 480 static int uv_apic_id_valid(int apicid)
 481 {
 482         return 1;
 483 }
 484
 485 static int uv_apic_id_registered(void)
 486 {
 487         return 1;
 488 }
 489
 490 static void uv_init_apic_ldr(void)
 491 {
 492 }
 493
 494 static int
 495 uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
 496                           const struct cpumask *andmask,
 497                           unsigned int *apicid)
 498 {
 499         int unsigned cpu;
 500
 501         /*
 502          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 503          * May as well be the first.
 504          */
 505         for_each_cpu_and(cpu, cpumask, andmask) {
 506                 if (cpumask_test_cpu(cpu, cpu_online_mask))
 507                         break;
 508         }
 509
 510         if (likely(cpu < nr_cpu_ids)) {
 511                 *apicid = per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits;
 512                 return 0;
 513         }
 514
 515         return -EINVAL;
 516 }
 517
 518 static unsigned int x2apic_get_apic_id(unsigned long x)
 519 {
 520         unsigned int id;
 521
 522         WARN_ON(preemptible() && num_online_cpus() > 1);
 523         id = x | __this_cpu_read(x2apic_extra_bits);
 524
 525         return id;
 526 }
 527
 528 static unsigned long set_apic_id(unsigned int id)
 529 {
 530         unsigned long x;
 531
 532         /* maskout x2apic_extra_bits ? */
 533         x = id;
 534         return x;
 535 }
 536
 537 static unsigned int uv_read_apic_id(void)
 538 {
 539         return x2apic_get_apic_id(apic_read(APIC_ID));
 540 }
 541
 542 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
 543 {
 544         return uv_read_apic_id() >> index_msb;
 545 }
 546
 547 static void uv_send_IPI_self(int vector)
 548 {
 549         apic_write(APIC_SELF_IPI, vector);
 550 }
 551
 552 static int uv_probe(void)
 553 {
 554         return apic == &apic_x2apic_uv_x;
 555 }
 556
 557 static struct apic __refdata apic_x2apic_uv_x = {
 558
 559         .name                           = "UV large system",
 560         .probe                          = uv_probe,
 561         .acpi_madt_oem_check            = uv_acpi_madt_oem_check,
 562         .apic_id_valid                  = uv_apic_id_valid,
 563         .apic_id_registered             = uv_apic_id_registered,
 564
 565         .irq_delivery_mode              = dest_Fixed,
 566         .irq_dest_mode                  = 0, /* physical */
 567
 568         .target_cpus                    = online_target_cpus,
 569         .disable_esr                    = 0,
 570         .dest_logical                   = APIC_DEST_LOGICAL,
 571         .check_apicid_used              = NULL,
 572
 573         .vector_allocation_domain       = default_vector_allocation_domain,
 574         .init_apic_ldr                  = uv_init_apic_ldr,
 575
 576         .ioapic_phys_id_map             = NULL,
 577         .setup_apic_routing             = NULL,
 578         .cpu_present_to_apicid          = default_cpu_present_to_apicid,
 579         .apicid_to_cpu_present          = NULL,
 580         .check_phys_apicid_present      = default_check_phys_apicid_present,
 581         .phys_pkg_id                    = uv_phys_pkg_id,
 582
 583         .get_apic_id                    = x2apic_get_apic_id,
 584         .set_apic_id                    = set_apic_id,
 585         .apic_id_mask                   = 0xFFFFFFFFu,
 586
 587         .cpu_mask_to_apicid_and         = uv_cpu_mask_to_apicid_and,
 588
 589         .send_IPI                       = uv_send_IPI_one,
 590         .send_IPI_mask                  = uv_send_IPI_mask,
 591         .send_IPI_mask_allbutself       = uv_send_IPI_mask_allbutself,
 592         .send_IPI_allbutself            = uv_send_IPI_allbutself,
 593         .send_IPI_all                   = uv_send_IPI_all,
 594         .send_IPI_self                  = uv_send_IPI_self,
 595
 596         .wakeup_secondary_cpu           = uv_wakeup_secondary,
 597         .inquire_remote_apic            = NULL,
 598
 599         .read                           = native_apic_msr_read,
 600         .write                          = native_apic_msr_write,
 601         .eoi_write                      = native_apic_msr_eoi_write,
 602         .icr_read                       = native_x2apic_icr_read,
 603         .icr_write                      = native_x2apic_icr_write,
 604         .wait_icr_idle                  = native_x2apic_wait_icr_idle,
 605         .safe_wait_icr_idle             = native_safe_x2apic_wait_icr_idle,
 606 };
 607
 608 static void set_x2apic_extra_bits(int pnode)
 609 {
 610         __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift);
 611 }
 612
 613 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH      3
 614 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 615
 616 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
 617 {
 618         union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias;
 619         union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
 620         unsigned long m_redirect;
 621         unsigned long m_overlay;
 622         int i;
 623
 624         for (i = 0; i < UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH; i++) {
 625                 switch (i) {
 626                 case 0:
 627                         m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR;
 628                         m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR;
 629                         break;
 630                 case 1:
 631                         m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR;
 632                         m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR;
 633                         break;
 634                 case 2:
 635                         m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR;
 636                         m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR;
 637                         break;
 638                 }
 639                 alias.v = uv_read_local_mmr(m_overlay);
 640                 if (alias.s.enable && alias.s.base == 0) {
 641                         *size = (1UL << alias.s.m_alias);
 642                         redirect.v = uv_read_local_mmr(m_redirect);
 643                         *base = (unsigned long)redirect.s.dest_base
 644                                                         << DEST_SHIFT;
 645                         return;
 646                 }
 647         }
 648         *base = *size = 0;
 649 }
 650
 651 enum map_type {map_wb, map_uc};
 652
 653 static __init void map_high(char *id, unsigned long base, int pshift,
 654                         int bshift, int max_pnode, enum map_type map_type)
 655 {
 656         unsigned long bytes, paddr;
 657
 658         paddr = base << pshift;
 659         bytes = (1UL << bshift) * (max_pnode + 1);
 660         if (!paddr) {
 661                 pr_info("UV: Map %s_HI base address NULL\n", id);
 662                 return;
 663         }
 664         pr_debug("UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, paddr + bytes);
 665         if (map_type == map_uc)
 666                 init_extra_mapping_uc(paddr, bytes);
 667         else
 668                 init_extra_mapping_wb(paddr, bytes);
 669 }
 670
 671 static __init void map_gru_distributed(unsigned long c)
 672 {
 673         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
 674         u64 paddr;
 675         unsigned long bytes;
 676         int nid;
 677
 678         gru.v = c;
 679         /* only base bits 42:28 relevant in dist mode */
 680         gru_dist_base = gru.v & 0x000007fff0000000UL;
 681         if (!gru_dist_base) {
 682                 pr_info("UV: Map GRU_DIST base address NULL\n");
 683                 return;
 684         }
 685         bytes = 1UL << UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
 686         gru_dist_lmask = ((1UL << uv_hub_info->m_val) - 1) & ~(bytes - 1);
 687         gru_dist_umask = ~((1UL << uv_hub_info->m_val) - 1);
 688         gru_dist_base &= gru_dist_lmask; /* Clear bits above M */
 689         for_each_online_node(nid) {
 690                 paddr = ((u64)uv_node_to_pnode(nid) << uv_hub_info->m_val) |
 691                                 gru_dist_base;
 692                 init_extra_mapping_wb(paddr, bytes);
 693                 gru_first_node_paddr = min(paddr, gru_first_node_paddr);
 694                 gru_last_node_paddr = max(paddr, gru_last_node_paddr);
 695         }
 696         /* Save upper (63:M) bits of address only for is_GRU_range */
 697         gru_first_node_paddr &= gru_dist_umask;
 698         gru_last_node_paddr &= gru_dist_umask;
 699         pr_debug("UV: Map GRU_DIST base 0x%016llx  0x%016llx - 0x%016llx\n",
 700                 gru_dist_base, gru_first_node_paddr, gru_last_node_paddr);
 701 }
 702
 703 static __init void map_gru_high(int max_pnode)
 704 {
 705         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
 706         int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
 707         unsigned long mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK;
 708         unsigned long base;
 709
 710         gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
 711         if (!gru.s.enable) {
 712                 pr_info("UV: GRU disabled\n");
 713                 return;
 714         }
 715
 716         if (is_uv3_hub() && gru.s3.mode) {
 717                 map_gru_distributed(gru.v);
 718                 return;
 719         }
 720         base = (gru.v & mask) >> shift;
 721         map_high("GRU", base, shift, shift, max_pnode, map_wb);
 722         gru_start_paddr = ((u64)base << shift);
 723         gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
 724 }
 725
 726 static __init void map_mmr_high(int max_pnode)
 727 {
 728         union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
 729         int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
 730
 731         mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
 732         if (mmr.s.enable)
 733                 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
 734         else
 735                 pr_info("UV: MMR disabled\n");
 736 }
 737
 738 /*
 739  * This commonality works because both 0 & 1 versions of the MMIOH OVERLAY
 740  * and REDIRECT MMR regs are exactly the same on UV3.
 741  */
 742 struct mmioh_config {
 743         unsigned long overlay;
 744         unsigned long redirect;
 745         char *id;
 746 };
 747
 748 static __initdata struct mmioh_config mmiohs[] = {
 749         {
 750                 UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR,
 751                 UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR,
 752                 "MMIOH0"
 753         },
 754         {
 755                 UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR,
 756                 UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR,
 757                 "MMIOH1"
 758         },
 759 };
 760
 761 /* UV3 & UV4 have identical MMIOH overlay configs */
 762 static __init void map_mmioh_high_uv3(int index, int min_pnode, int max_pnode)
 763 {
 764         union uv3h_rh_gam_mmioh_overlay_config0_mmr_u overlay;
 765         unsigned long mmr;
 766         unsigned long base;
 767         int i, n, shift, m_io, max_io;
 768         int nasid, lnasid, fi, li;
 769         char *id;
 770
 771         id = mmiohs[index].id;
 772         overlay.v = uv_read_local_mmr(mmiohs[index].overlay);
 773         pr_info("UV: %s overlay 0x%lx base:0x%x m_io:%d\n",
 774                 id, overlay.v, overlay.s3.base, overlay.s3.m_io);
 775         if (!overlay.s3.enable) {
 776                 pr_info("UV: %s disabled\n", id);
 777                 return;
 778         }
 779
 780         shift = UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT;
 781         base = (unsigned long)overlay.s3.base;
 782         m_io = overlay.s3.m_io;
 783         mmr = mmiohs[index].redirect;
 784         n = UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH;
 785         min_pnode *= 2;                         /* convert to NASID */
 786         max_pnode *= 2;
 787         max_io = lnasid = fi = li = -1;
 788
 789         for (i = 0; i < n; i++) {
 790                 union uv3h_rh_gam_mmioh_redirect_config0_mmr_u redirect;
 791
 792                 redirect.v = uv_read_local_mmr(mmr + i * 8);
 793                 nasid = redirect.s3.nasid;
 794                 if (nasid < min_pnode || max_pnode < nasid)
 795                         nasid = -1;             /* invalid NASID */
 796
 797                 if (nasid == lnasid) {
 798                         li = i;
 799                         if (i != n-1)           /* last entry check */
 800                                 continue;
 801                 }
 802
 803                 /* check if we have a cached (or last) redirect to print */
 804                 if (lnasid != -1 || (i == n-1 && nasid != -1))  {
 805                         unsigned long addr1, addr2;
 806                         int f, l;
 807
 808                         if (lnasid == -1) {
 809                                 f = l = i;
 810                                 lnasid = nasid;
 811                         } else {
 812                                 f = fi;
 813                                 l = li;
 814                         }
 815                         addr1 = (base << shift) +
 816                                 f * (unsigned long)(1 << m_io);
 817                         addr2 = (base << shift) +
 818                                 (l + 1) * (unsigned long)(1 << m_io);
 819                         pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n",
 820                                 id, fi, li, lnasid, addr1, addr2);
 821                         if (max_io < l)
 822                                 max_io = l;
 823                 }
 824                 fi = li = i;
 825                 lnasid = nasid;
 826         }
 827
 828         pr_info("UV: %s base:0x%lx shift:%d M_IO:%d MAX_IO:%d\n",
 829                 id, base, shift, m_io, max_io);
 830
 831         if (max_io >= 0)
 832                 map_high(id, base, shift, m_io, max_io, map_uc);
 833 }
 834
 835 static __init void map_mmioh_high(int min_pnode, int max_pnode)
 836 {
 837         union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
 838         unsigned long mmr, base;
 839         int shift, enable, m_io, n_io;
 840
 841         if (is_uv3_hub() || is_uv4_hub()) {
 842                 /* Map both MMIOH Regions */
 843                 map_mmioh_high_uv3(0, min_pnode, max_pnode);
 844                 map_mmioh_high_uv3(1, min_pnode, max_pnode);
 845                 return;
 846         }
 847
 848         if (is_uv1_hub()) {
 849                 mmr = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
 850                 shift = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
 851                 mmioh.v = uv_read_local_mmr(mmr);
 852                 enable = !!mmioh.s1.enable;
 853                 base = mmioh.s1.base;
 854                 m_io = mmioh.s1.m_io;
 855                 n_io = mmioh.s1.n_io;
 856         } else if (is_uv2_hub()) {
 857                 mmr = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
 858                 shift = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
 859                 mmioh.v = uv_read_local_mmr(mmr);
 860                 enable = !!mmioh.s2.enable;
 861                 base = mmioh.s2.base;
 862                 m_io = mmioh.s2.m_io;
 863                 n_io = mmioh.s2.n_io;
 864         } else
 865                 return;
 866
 867         if (enable) {
 868                 max_pnode &= (1 << n_io) - 1;
 869                 pr_info(
 870                     "UV: base:0x%lx shift:%d N_IO:%d M_IO:%d max_pnode:0x%x\n",
 871                         base, shift, m_io, n_io, max_pnode);
 872                 map_high("MMIOH", base, shift, m_io, max_pnode, map_uc);
 873         } else {
 874                 pr_info("UV: MMIOH disabled\n");
 875         }
 876 }
 877
 878 static __init void map_low_mmrs(void)
 879 {
 880         init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
 881         init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
 882 }
 883
 884 static __init void uv_rtc_init(void)
 885 {
 886         long status;
 887         u64 ticks_per_sec;
 888
 889         status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
 890                                         &ticks_per_sec);
 891         if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
 892                 printk(KERN_WARNING
 893                         "unable to determine platform RTC clock frequency, "
 894                         "guessing.\n");
 895                 /* BIOS gives wrong value for clock freq. so guess */
 896                 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
 897         } else
 898                 sn_rtc_cycles_per_second = ticks_per_sec;
 899 }
 900
 901 /*
 902  * percpu heartbeat timer
 903  */
 904 static void uv_heartbeat(unsigned long ignored)
 905 {
 906         struct timer_list *timer = &uv_scir_info->timer;
 907         unsigned char bits = uv_scir_info->state;
 908
 909         /* flip heartbeat bit */
 910         bits ^= SCIR_CPU_HEARTBEAT;
 911
 912         /* is this cpu idle? */
 913         if (idle_cpu(raw_smp_processor_id()))
 914                 bits &= ~SCIR_CPU_ACTIVITY;
 915         else
 916                 bits |= SCIR_CPU_ACTIVITY;
 917
 918         /* update system controller interface reg */
 919         uv_set_scir_bits(bits);
 920
 921         /* enable next timer period */
 922         mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL);
 923 }
 924
 925 static void uv_heartbeat_enable(int cpu)
 926 {
 927         while (!uv_cpu_scir_info(cpu)->enabled) {
 928                 struct timer_list *timer = &uv_cpu_scir_info(cpu)->timer;
 929
 930                 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
 931                 setup_timer(timer, uv_heartbeat, cpu);
 932                 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
 933                 add_timer_on(timer, cpu);
 934                 uv_cpu_scir_info(cpu)->enabled = 1;
 935
 936                 /* also ensure that boot cpu is enabled */
 937                 cpu = 0;
 938         }
 939 }
 940
 941 #ifdef CONFIG_HOTPLUG_CPU
 942 static void uv_heartbeat_disable(int cpu)
 943 {
 944         if (uv_cpu_scir_info(cpu)->enabled) {
 945                 uv_cpu_scir_info(cpu)->enabled = 0;
 946                 del_timer(&uv_cpu_scir_info(cpu)->timer);
 947         }
 948         uv_set_cpu_scir_bits(cpu, 0xff);
 949 }
 950
 951 /*
 952  * cpu hotplug notifier
 953  */
 954 static int uv_scir_cpu_notify(struct notifier_block *self, unsigned long action,
 955                               void *hcpu)
 956 {
 957         long cpu = (long)hcpu;
 958
 959         switch (action & ~CPU_TASKS_FROZEN) {
 960         case CPU_DOWN_FAILED:
 961         case CPU_ONLINE:
 962                 uv_heartbeat_enable(cpu);
 963                 break;
 964         case CPU_DOWN_PREPARE:
 965                 uv_heartbeat_disable(cpu);
 966                 break;
 967         default:
 968                 break;
 969         }
 970         return NOTIFY_OK;
 971 }
 972
 973 static __init void uv_scir_register_cpu_notifier(void)
 974 {
 975         hotcpu_notifier(uv_scir_cpu_notify, 0);
 976 }
 977
 978 #else /* !CONFIG_HOTPLUG_CPU */
 979
 980 static __init void uv_scir_register_cpu_notifier(void)
 981 {
 982 }
 983
 984 static __init int uv_init_heartbeat(void)
 985 {
 986         int cpu;
 987
 988         if (is_uv_system())
 989                 for_each_online_cpu(cpu)
 990                         uv_heartbeat_enable(cpu);
 991         return 0;
 992 }
 993
 994 late_initcall(uv_init_heartbeat);
 995
 996 #endif /* !CONFIG_HOTPLUG_CPU */
 997
 998 /* Direct Legacy VGA I/O traffic to designated IOH */
 999 int uv_set_vga_state(struct pci_dev *pdev, bool decode,
1000                       unsigned int command_bits, u32 flags)
1001 {
1002         int domain, bus, rc;
1003
1004         PR_DEVEL("devfn %x decode %d cmd %x flags %d\n",
1005                         pdev->devfn, decode, command_bits, flags);
1006
1007         if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
1008                 return 0;
1009
1010         if ((command_bits & PCI_COMMAND_IO) == 0)
1011                 return 0;
1012
1013         domain = pci_domain_nr(pdev->bus);
1014         bus = pdev->bus->number;
1015
1016         rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
1017         PR_DEVEL("vga decode %d %x:%x, rc: %d\n", decode, domain, bus, rc);
1018
1019         return rc;
1020 }
1021
1022 /*
1023  * Called on each cpu to initialize the per_cpu UV data area.
1024  * FIXME: hotplug not supported yet
1025  */
1026 void uv_cpu_init(void)
1027 {
1028         /* CPU 0 initialization will be done via uv_system_init. */
1029         if (smp_processor_id() == 0)
1030                 return;
1031
1032         uv_hub_info->nr_online_cpus++;
1033
1034         if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
1035                 set_x2apic_extra_bits(uv_hub_info->pnode);
1036 }
1037
1038 struct mn {
1039         unsigned char   m_val;
1040         unsigned char   n_val;
1041         unsigned char   m_shift;
1042         unsigned char   n_lshift;
1043 };
1044
1045 static void get_mn(struct mn *mnp)
1046 {
1047         union uvh_rh_gam_config_mmr_u m_n_config;
1048         union uv3h_gr0_gam_gr_config_u m_gr_config;
1049
1050         m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR);
1051         mnp->n_val = m_n_config.s.n_skt;
1052         if (is_uv4_hub()) {
1053                 mnp->m_val = 0;
1054                 mnp->n_lshift = 0;
1055         } else if (is_uv3_hub()) {
1056                 mnp->m_val = m_n_config.s3.m_skt;
1057                 m_gr_config.v = uv_read_local_mmr(UV3H_GR0_GAM_GR_CONFIG);
1058                 mnp->n_lshift = m_gr_config.s3.m_skt;
1059         } else if (is_uv2_hub()) {
1060                 mnp->m_val = m_n_config.s2.m_skt;
1061                 mnp->n_lshift = mnp->m_val == 40 ? 40 : 39;
1062         } else if (is_uv1_hub()) {
1063                 mnp->m_val = m_n_config.s1.m_skt;
1064                 mnp->n_lshift = mnp->m_val;
1065         }
1066         mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0;
1067 }
1068
1069 void __init uv_init_hub_info(struct uv_hub_info_s *hub_info)
1070 {
1071         struct mn mn = {0};     /* avoid unitialized warnings */
1072         union uvh_node_id_u node_id;
1073
1074         get_mn(&mn);
1075         hub_info->m_val = mn.m_val;
1076         hub_info->n_val = mn.n_val;
1077         hub_info->m_shift = mn.m_shift;
1078         hub_info->n_lshift = mn.n_lshift ? mn.n_lshift : 0;
1079
1080         hub_info->hub_revision = uv_hub_info->hub_revision;
1081         hub_info->pnode_mask = uv_cpuid.pnode_mask;
1082         hub_info->min_pnode = _min_pnode;
1083         hub_info->min_socket = _min_socket;
1084         hub_info->pnode_to_socket = _pnode_to_socket;
1085         hub_info->socket_to_node = _socket_to_node;
1086         hub_info->socket_to_pnode = _socket_to_pnode;
1087         hub_info->gr_table_len = _gr_table_len;
1088         hub_info->gr_table = _gr_table;
1089         hub_info->gpa_mask = mn.m_val ?
1090                 (1UL << (mn.m_val + mn.n_val)) - 1 :
1091                 (1UL << uv_cpuid.gpa_shift) - 1;
1092
1093         node_id.v = uv_read_local_mmr(UVH_NODE_ID);
1094         hub_info->gnode_extra =
1095                 (node_id.s.node_id & ~((1 << mn.n_val) - 1)) >> 1;
1096
1097         hub_info->gnode_upper =
1098                 ((unsigned long)hub_info->gnode_extra << mn.m_val);
1099
1100         if (uv_gp_table) {
1101                 hub_info->global_mmr_base = uv_gp_table->mmr_base;
1102                 hub_info->global_mmr_shift = uv_gp_table->mmr_shift;
1103                 hub_info->global_gru_base = uv_gp_table->gru_base;
1104                 hub_info->global_gru_shift = uv_gp_table->gru_shift;
1105                 hub_info->gpa_shift = uv_gp_table->gpa_shift;
1106                 hub_info->gpa_mask = (1UL << hub_info->gpa_shift) - 1;
1107         } else {
1108                 hub_info->global_mmr_base =
1109                         uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
1110                                         ~UV_MMR_ENABLE;
1111                 hub_info->global_mmr_shift = _UV_GLOBAL_MMR64_PNODE_SHIFT;
1112         }
1113
1114         get_lowmem_redirect(
1115                 &hub_info->lowmem_remap_base, &hub_info->lowmem_remap_top);
1116
1117         hub_info->apic_pnode_shift = uv_cpuid.socketid_shift;
1118
1119         /* show system specific info */
1120         pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n",
1121                 hub_info->n_val, hub_info->m_val,
1122                 hub_info->m_shift, hub_info->n_lshift);
1123
1124         pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n",
1125                 hub_info->gpa_mask, hub_info->gpa_shift,
1126                 hub_info->pnode_mask, hub_info->apic_pnode_shift);
1127
1128         pr_info("UV: mmr_base/shift:0x%lx/%ld gru_base/shift:0x%lx/%ld\n",
1129                 hub_info->global_mmr_base, hub_info->global_mmr_shift,
1130                 hub_info->global_gru_base, hub_info->global_gru_shift);
1131
1132         pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n",
1133                 hub_info->gnode_upper, hub_info->gnode_extra);
1134 }
1135
1136 static void __init decode_gam_params(unsigned long ptr)
1137 {
1138         uv_gp_table = (struct uv_gam_parameters *)ptr;
1139
1140         pr_info("UV: GAM Params...\n");
1141         pr_info("UV: mmr_base/shift:0x%llx/%d gru_base/shift:0x%llx/%d gpa_shift:%d\n",
1142                 uv_gp_table->mmr_base, uv_gp_table->mmr_shift,
1143                 uv_gp_table->gru_base, uv_gp_table->gru_shift,
1144                 uv_gp_table->gpa_shift);
1145 }
1146
1147 static void __init decode_gam_rng_tbl(unsigned long ptr)
1148 {
1149         struct uv_gam_range_entry *gre = (struct uv_gam_range_entry *)ptr;
1150         unsigned long lgre = 0;
1151         int index = 0;
1152         int sock_min = 999999, pnode_min = 99999;
1153         int sock_max = -1, pnode_max = -1;
1154
1155         uv_gre_table = gre;
1156         for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1157                 if (!index) {
1158                         pr_info("UV: GAM Range Table...\n");
1159                         pr_info("UV:  # %20s %14s %5s %4s %5s %3s %2s %3s\n",
1160                                 "Range", "", "Size", "Type", "NASID",
1161                                 "SID", "PN", "PXM");
1162                 }
1163                 pr_info(
1164                 "UV: %2d: 0x%014lx-0x%014lx %5luG %3d   %04x  %02x %02x %3d\n",
1165                         index++,
1166                         (unsigned long)lgre << UV_GAM_RANGE_SHFT,
1167                         (unsigned long)gre->limit << UV_GAM_RANGE_SHFT,
1168                         ((unsigned long)(gre->limit - lgre)) >>
1169                                 (30 - UV_GAM_RANGE_SHFT), /* 64M -> 1G */
1170                         gre->type, gre->nasid, gre->sockid,
1171                         gre->pnode, gre->pxm);
1172
1173                 lgre = gre->limit;
1174                 if (sock_min > gre->sockid)
1175                         sock_min = gre->sockid;
1176                 if (sock_max < gre->sockid)
1177                         sock_max = gre->sockid;
1178                 if (pnode_min > gre->pnode)
1179                         pnode_min = gre->pnode;
1180                 if (pnode_max < gre->pnode)
1181                         pnode_max = gre->pnode;
1182         }
1183         _min_socket = sock_min;
1184         _max_socket = sock_max;
1185         _min_pnode = pnode_min;
1186         _max_pnode = pnode_max;
1187         _gr_table_len = index;
1188         pr_info(
1189         "UV: GRT: %d entries, sockets(min:%x,max:%x) pnodes(min:%x,max:%x)\n",
1190                 index, _min_socket, _max_socket, _min_pnode, _max_pnode);
1191 }
1192
1193 static void __init decode_uv_systab(void)
1194 {
1195         struct uv_systab *st;
1196         int i;
1197
1198         st = uv_systab;
1199         if ((!st || st->revision < UV_SYSTAB_VERSION_UV4) && !is_uv4_hub())
1200                 return;
1201         if (st->revision != UV_SYSTAB_VERSION_UV4_LATEST) {
1202                 pr_crit(
1203                 "UV: BIOS UVsystab version(%x) mismatch, expecting(%x)\n",
1204                         st->revision, UV_SYSTAB_VERSION_UV4_LATEST);
1205                 BUG();
1206         }
1207
1208         for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) {
1209                 unsigned long ptr = st->entry[i].offset;
1210
1211                 if (!ptr)
1212                         continue;
1213
1214                 ptr = ptr + (unsigned long)st;
1215
1216                 switch (st->entry[i].type) {
1217                 case UV_SYSTAB_TYPE_GAM_PARAMS:
1218                         decode_gam_params(ptr);
1219                         break;
1220
1221                 case UV_SYSTAB_TYPE_GAM_RNG_TBL:
1222                         decode_gam_rng_tbl(ptr);
1223                         break;
1224                 }
1225         }
1226 }
1227
1228 /*
1229  * Setup physical blade translations from UVH_NODE_PRESENT_TABLE
1230  * .. NB: UVH_NODE_PRESENT_TABLE is going away,
1231  * .. being replaced by GAM Range Table
1232  */
1233 static __init void boot_init_possible_blades(struct uv_hub_info_s *hub_info)
1234 {
1235         int i, uv_pb = 0;
1236
1237         pr_info("UV: NODE_PRESENT_DEPTH = %d\n", UVH_NODE_PRESENT_TABLE_DEPTH);
1238         for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
1239                 unsigned long np;
1240
1241                 np = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
1242                 if (np)
1243                         pr_info("UV: NODE_PRESENT(%d) = 0x%016lx\n", i, np);
1244
1245                 uv_pb += hweight64(np);
1246         }
1247         if (uv_possible_blades != uv_pb)
1248                 uv_possible_blades = uv_pb;
1249 }
1250
1251 static void __init build_socket_tables(void)
1252 {
1253         struct uv_gam_range_entry *gre = uv_gre_table;
1254         int num, nump;
1255         int cpu, i, lnid;
1256         int minsock = _min_socket;
1257         int maxsock = _max_socket;
1258         int minpnode = _min_pnode;
1259         int maxpnode = _max_pnode;
1260         size_t bytes;
1261
1262         if (!gre) {
1263                 if (is_uv1_hub() || is_uv2_hub() || is_uv3_hub()) {
1264                         pr_info("UV: No UVsystab socket table, ignoring\n");
1265                         return;         /* not required */
1266                 }
1267                 pr_crit(
1268                 "UV: Error: UVsystab address translations not available!\n");
1269                 BUG();
1270         }
1271
1272         /* build socket id -> node id, pnode */
1273         num = maxsock - minsock + 1;
1274         bytes = num * sizeof(_socket_to_node[0]);
1275         _socket_to_node = kmalloc(bytes, GFP_KERNEL);
1276         _socket_to_pnode = kmalloc(bytes, GFP_KERNEL);
1277
1278         nump = maxpnode - minpnode + 1;
1279         bytes = nump * sizeof(_pnode_to_socket[0]);
1280         _pnode_to_socket = kmalloc(bytes, GFP_KERNEL);
1281         BUG_ON(!_socket_to_node || !_socket_to_pnode || !_pnode_to_socket);
1282
1283         for (i = 0; i < num; i++)
1284                 _socket_to_node[i] = _socket_to_pnode[i] = SOCK_EMPTY;
1285
1286         for (i = 0; i < nump; i++)
1287                 _pnode_to_socket[i] = SOCK_EMPTY;
1288
1289         /* fill in pnode/node/addr conversion list values */
1290         pr_info("UV: GAM Building socket/pnode/pxm conversion tables\n");
1291         for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1292                 if (gre->type == UV_GAM_RANGE_TYPE_HOLE)
1293                         continue;
1294                 i = gre->sockid - minsock;
1295                 if (_socket_to_pnode[i] != SOCK_EMPTY)
1296                         continue;       /* duplicate */
1297                 _socket_to_pnode[i] = gre->pnode;
1298                 _socket_to_node[i] = gre->pxm;
1299
1300                 i = gre->pnode - minpnode;
1301                 _pnode_to_socket[i] = gre->sockid;
1302
1303                 pr_info(
1304                 "UV: sid:%02x type:%d nasid:%04x pn:%02x pxm:%2d pn2s:%2x\n",
1305                         gre->sockid, gre->type, gre->nasid,
1306                         _socket_to_pnode[gre->sockid - minsock],
1307                         _socket_to_node[gre->sockid - minsock],
1308                         _pnode_to_socket[gre->pnode - minpnode]);
1309         }
1310
1311         /* check socket -> node values */
1312         lnid = -1;
1313         for_each_present_cpu(cpu) {
1314                 int nid = cpu_to_node(cpu);
1315                 int apicid, sockid;
1316
1317                 if (lnid == nid)
1318                         continue;
1319                 lnid = nid;
1320                 apicid = per_cpu(x86_cpu_to_apicid, cpu);
1321                 sockid = apicid >> uv_cpuid.socketid_shift;
1322                 i = sockid - minsock;
1323
1324                 if (nid != _socket_to_node[i]) {
1325                         pr_warn(
1326                         "UV: %02x: type:%d socket:%02x PXM:%02x != node:%2d\n",
1327                                 i, sockid, gre->type, _socket_to_node[i], nid);
1328                         _socket_to_node[i] = nid;
1329                 }
1330         }
1331
1332         /* Setup physical blade to pnode translation from GAM Range Table */
1333         bytes = num_possible_nodes() * sizeof(_node_to_pnode[0]);
1334         _node_to_pnode = kmalloc(bytes, GFP_KERNEL);
1335         BUG_ON(!_node_to_pnode);
1336
1337         for (lnid = 0; lnid < num_possible_nodes(); lnid++) {
1338                 unsigned short sockid;
1339
1340                 for (sockid = minsock; sockid <= maxsock; sockid++) {
1341                         if (lnid == _socket_to_node[sockid - minsock]) {
1342                                 _node_to_pnode[lnid] =
1343                                         _socket_to_pnode[sockid - minsock];
1344                                 break;
1345                         }
1346                 }
1347                 if (sockid > maxsock) {
1348                         pr_err("UV: socket for node %d not found!\n", lnid);
1349                         BUG();
1350                 }
1351         }
1352
1353         /*
1354          * If socket id == pnode or socket id == node for all nodes,
1355          *   system runs faster by removing corresponding conversion table.
1356          */
1357         pr_info("UV: Checking socket->node/pnode for identity maps\n");
1358         if (minsock == 0) {
1359                 for (i = 0; i < num; i++)
1360                         if (_socket_to_node[i] == SOCK_EMPTY ||
1361                                 i != _socket_to_node[i])
1362                                 break;
1363                 if (i >= num) {
1364                         kfree(_socket_to_node);
1365                         _socket_to_node = NULL;
1366                         pr_info("UV: 1:1 socket_to_node table removed\n");
1367                 }
1368         }
1369         if (minsock == minpnode) {
1370                 for (i = 0; i < num; i++)
1371                         if (_socket_to_pnode[i] != SOCK_EMPTY &&
1372                                 _socket_to_pnode[i] != i + minpnode)
1373                                 break;
1374                 if (i >= num) {
1375                         kfree(_socket_to_pnode);
1376                         _socket_to_pnode = NULL;
1377                         pr_info("UV: 1:1 socket_to_pnode table removed\n");
1378                 }
1379         }
1380 }
1381
1382 void __init uv_system_init(void)
1383 {
1384         struct uv_hub_info_s hub_info = {0};
1385         int bytes, cpu, nodeid;
1386         unsigned short min_pnode = 9999, max_pnode = 0;
1387         char *hub = is_uv4_hub() ? "UV400" :
1388                     is_uv3_hub() ? "UV300" :
1389                     is_uv2_hub() ? "UV2000/3000" :
1390                     is_uv1_hub() ? "UV100/1000" : NULL;
1391
1392         if (!hub) {
1393                 pr_err("UV: Unknown/unsupported UV hub\n");
1394                 return;
1395         }
1396         pr_info("UV: Found %s hub\n", hub);
1397
1398         /* We now only need to map the MMRs on UV1 */
1399         if (is_uv1_hub())
1400                 map_low_mmrs();
1401
1402         uv_bios_init();                 /* get uv_systab for decoding */
1403         decode_uv_systab();
1404         build_socket_tables();
1405         build_uv_gr_table();
1406         uv_init_hub_info(&hub_info);
1407         uv_possible_blades = num_possible_nodes();
1408         if (!_node_to_pnode)
1409                 boot_init_possible_blades(&hub_info);
1410
1411         /* uv_num_possible_blades() is really the hub count */
1412         pr_info("UV: Found %d hubs, %d nodes, %d cpus\n",
1413                         uv_num_possible_blades(),
1414                         num_possible_nodes(),
1415                         num_possible_cpus());
1416
1417         uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id,
1418                             &sn_region_size, &system_serial_number);
1419         hub_info.coherency_domain_number = sn_coherency_id;
1420         uv_rtc_init();
1421
1422         bytes = sizeof(void *) * uv_num_possible_blades();
1423         __uv_hub_info_list = kzalloc(bytes, GFP_KERNEL);
1424         BUG_ON(!__uv_hub_info_list);
1425
1426         bytes = sizeof(struct uv_hub_info_s);
1427         for_each_node(nodeid) {
1428                 struct uv_hub_info_s *new_hub;
1429
1430                 if (__uv_hub_info_list[nodeid]) {
1431                         pr_err("UV: Node %d UV HUB already initialized!?\n",
1432                                 nodeid);
1433                         BUG();
1434                 }
1435
1436                 /* Allocate new per hub info list */
1437                 new_hub = (nodeid == 0) ?
1438                         &uv_hub_info_node0 :
1439                         kzalloc_node(bytes, GFP_KERNEL, nodeid);
1440                 BUG_ON(!new_hub);
1441                 __uv_hub_info_list[nodeid] = new_hub;
1442                 new_hub = uv_hub_info_list(nodeid);
1443                 BUG_ON(!new_hub);
1444                 *new_hub = hub_info;
1445
1446                 /* Use information from GAM table if available */
1447                 if (_node_to_pnode)
1448                         new_hub->pnode = _node_to_pnode[nodeid];
1449                 else    /* Fill in during cpu loop */
1450                         new_hub->pnode = 0xffff;
1451                 new_hub->numa_blade_id = uv_node_to_blade_id(nodeid);
1452                 new_hub->memory_nid = -1;
1453                 new_hub->nr_possible_cpus = 0;
1454                 new_hub->nr_online_cpus = 0;
1455         }
1456
1457         /* Initialize per cpu info */
1458         for_each_possible_cpu(cpu) {
1459                 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
1460                 int numa_node_id;
1461                 unsigned short pnode;
1462
1463                 nodeid = cpu_to_node(cpu);
1464                 numa_node_id = numa_cpu_node(cpu);
1465                 pnode = uv_apicid_to_pnode(apicid);
1466
1467                 uv_cpu_info_per(cpu)->p_uv_hub_info = uv_hub_info_list(nodeid);
1468                 uv_cpu_info_per(cpu)->blade_cpu_id =
1469                         uv_cpu_hub_info(cpu)->nr_possible_cpus++;
1470                 if (uv_cpu_hub_info(cpu)->memory_nid == -1)
1471                         uv_cpu_hub_info(cpu)->memory_nid = cpu_to_node(cpu);
1472                 if (nodeid != numa_node_id &&   /* init memoryless node */
1473                     uv_hub_info_list(numa_node_id)->pnode == 0xffff)
1474                         uv_hub_info_list(numa_node_id)->pnode = pnode;
1475                 else if (uv_cpu_hub_info(cpu)->pnode == 0xffff)
1476                         uv_cpu_hub_info(cpu)->pnode = pnode;
1477                 uv_cpu_scir_info(cpu)->offset = uv_scir_offset(apicid);
1478         }
1479
1480         for_each_node(nodeid) {
1481                 unsigned short pnode = uv_hub_info_list(nodeid)->pnode;
1482
1483                 /* Add pnode info for pre-GAM list nodes without cpus */
1484                 if (pnode == 0xffff) {
1485                         unsigned long paddr;
1486
1487                         paddr = node_start_pfn(nodeid) << PAGE_SHIFT;
1488                         pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr));
1489                         uv_hub_info_list(nodeid)->pnode = pnode;
1490                 }
1491                 min_pnode = min(pnode, min_pnode);
1492                 max_pnode = max(pnode, max_pnode);
1493                 pr_info("UV: UVHUB node:%2d pn:%02x nrcpus:%d\n",
1494                         nodeid,
1495                         uv_hub_info_list(nodeid)->pnode,
1496                         uv_hub_info_list(nodeid)->nr_possible_cpus);
1497         }
1498
1499         pr_info("UV: min_pnode:%02x max_pnode:%02x\n", min_pnode, max_pnode);
1500         map_gru_high(max_pnode);
1501         map_mmr_high(max_pnode);
1502         map_mmioh_high(min_pnode, max_pnode);
1503
1504         uv_nmi_setup();
1505         uv_cpu_init();
1506         uv_scir_register_cpu_notifier();
1507         proc_mkdir("sgi_uv", NULL);
1508
1509         /* register Legacy VGA I/O redirection handler */
1510         pci_register_set_vga_state(uv_set_vga_state);
1511
1512         /*
1513          * For a kdump kernel the reset must be BOOT_ACPI, not BOOT_EFI, as
1514          * EFI is not enabled in the kdump kernel.
1515          */
1516         if (is_kdump_kernel())
1517                 reboot_type = BOOT_ACPI;
1518 }
1519
1520 apic_driver(apic_x2apic_uv_x);