1 #include <linux/export.h>
2 #include <linux/init.h>
3 #include <linux/bitops.h>
8 #include <linux/sched.h>
9 #include <asm/processor.h>
12 #include <asm/pci-direct.h>
15 # include <asm/mmconfig.h>
16 # include <asm/cacheflush.h>
21 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
23 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
27 WARN_ONCE((c->x86 != 0xf), "%s should only be used on K8!\n", __func__);
32 err = rdmsr_safe_regs(gprs);
34 *p = gprs[0] | ((u64)gprs[2] << 32);
39 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
41 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
44 WARN_ONCE((c->x86 != 0xf), "%s should only be used on K8!\n", __func__);
51 return wrmsr_safe_regs(gprs);
56 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause
57 * misexecution of code under Linux. Owners of such processors should
58 * contact AMD for precise details and a CPU swap.
60 * See http://www.multimania.com/poulot/k6bug.html
61 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
62 * (Publication # 21266 Issue Date: August 1998)
64 * The following test is erm.. interesting. AMD neglected to up
65 * the chip setting when fixing the bug but they also tweaked some
66 * performance at the same time..
69 extern void vide(void);
70 __asm__(".align 4\nvide: ret");
72 static void __cpuinit init_amd_k5(struct cpuinfo_x86 *c)
75 * General Systems BIOSen alias the cpu frequency registers
76 * of the Elan at 0x000df000. Unfortuantly, one of the Linux
77 * drivers subsequently pokes it, and changes the CPU speed.
78 * Workaround : Remove the unneeded alias.
80 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
81 #define CBAR_ENB (0x80000000)
82 #define CBAR_KEY (0X000000CB)
83 if (c->x86_model == 9 || c->x86_model == 10) {
84 if (inl(CBAR) & CBAR_ENB)
85 outl(0 | CBAR_KEY, CBAR);
90 static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c)
93 int mbytes = num_physpages >> (20-PAGE_SHIFT);
95 if (c->x86_model < 6) {
96 /* Based on AMD doc 20734R - June 2000 */
97 if (c->x86_model == 0) {
98 clear_cpu_cap(c, X86_FEATURE_APIC);
99 set_cpu_cap(c, X86_FEATURE_PGE);
104 if (c->x86_model == 6 && c->x86_mask == 1) {
105 const int K6_BUG_LOOP = 1000000;
107 void (*f_vide)(void);
110 printk(KERN_INFO "AMD K6 stepping B detected - ");
113 * It looks like AMD fixed the 2.6.2 bug and improved indirect
114 * calls at the same time.
125 if (d > 20*K6_BUG_LOOP)
127 "system stability may be impaired when more than 32 MB are used.\n");
129 printk(KERN_CONT "probably OK (after B9730xxxx).\n");
132 /* K6 with old style WHCR */
133 if (c->x86_model < 8 ||
134 (c->x86_model == 8 && c->x86_mask < 8)) {
135 /* We can only write allocate on the low 508Mb */
139 rdmsr(MSR_K6_WHCR, l, h);
140 if ((l&0x0000FFFF) == 0) {
142 l = (1<<0)|((mbytes/4)<<1);
143 local_irq_save(flags);
145 wrmsr(MSR_K6_WHCR, l, h);
146 local_irq_restore(flags);
147 printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
153 if ((c->x86_model == 8 && c->x86_mask > 7) ||
154 c->x86_model == 9 || c->x86_model == 13) {
155 /* The more serious chips .. */
160 rdmsr(MSR_K6_WHCR, l, h);
161 if ((l&0xFFFF0000) == 0) {
163 l = ((mbytes>>2)<<22)|(1<<16);
164 local_irq_save(flags);
166 wrmsr(MSR_K6_WHCR, l, h);
167 local_irq_restore(flags);
168 printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
175 if (c->x86_model == 10) {
176 /* AMD Geode LX is model 10 */
177 /* placeholder for any needed mods */
182 static void __cpuinit amd_k7_smp_check(struct cpuinfo_x86 *c)
184 /* calling is from identify_secondary_cpu() ? */
189 * Certain Athlons might work (for various values of 'work') in SMP
190 * but they are not certified as MP capable.
192 /* Athlon 660/661 is valid. */
193 if ((c->x86_model == 6) && ((c->x86_mask == 0) ||
197 /* Duron 670 is valid */
198 if ((c->x86_model == 7) && (c->x86_mask == 0))
202 * Athlon 662, Duron 671, and Athlon >model 7 have capability
203 * bit. It's worth noting that the A5 stepping (662) of some
204 * Athlon XP's have the MP bit set.
205 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
208 if (((c->x86_model == 6) && (c->x86_mask >= 2)) ||
209 ((c->x86_model == 7) && (c->x86_mask >= 1)) ||
214 /* If we get here, not a certified SMP capable AMD system. */
217 * Don't taint if we are running SMP kernel on a single non-MP
220 WARN_ONCE(1, "WARNING: This combination of AMD"
221 " processors is not suitable for SMP.\n");
222 if (!test_taint(TAINT_UNSAFE_SMP))
223 add_taint(TAINT_UNSAFE_SMP);
229 static void __cpuinit init_amd_k7(struct cpuinfo_x86 *c)
234 * Bit 15 of Athlon specific MSR 15, needs to be 0
235 * to enable SSE on Palomino/Morgan/Barton CPU's.
236 * If the BIOS didn't enable it already, enable it here.
238 if (c->x86_model >= 6 && c->x86_model <= 10) {
239 if (!cpu_has(c, X86_FEATURE_XMM)) {
240 printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
241 rdmsr(MSR_K7_HWCR, l, h);
243 wrmsr(MSR_K7_HWCR, l, h);
244 set_cpu_cap(c, X86_FEATURE_XMM);
249 * It's been determined by AMD that Athlons since model 8 stepping 1
250 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
251 * As per AMD technical note 27212 0.2
253 if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
254 rdmsr(MSR_K7_CLK_CTL, l, h);
255 if ((l & 0xfff00000) != 0x20000000) {
257 "CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
258 l, ((l & 0x000fffff)|0x20000000));
259 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
263 set_cpu_cap(c, X86_FEATURE_K7);
271 * To workaround broken NUMA config. Read the comment in
272 * srat_detect_node().
274 static int __cpuinit nearby_node(int apicid)
278 for (i = apicid - 1; i >= 0; i--) {
279 node = __apicid_to_node[i];
280 if (node != NUMA_NO_NODE && node_online(node))
283 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
284 node = __apicid_to_node[i];
285 if (node != NUMA_NO_NODE && node_online(node))
288 return first_node(node_online_map); /* Shouldn't happen */
293 * Fixup core topology information for
294 * (1) AMD multi-node processors
295 * Assumption: Number of cores in each internal node is the same.
296 * (2) AMD processors supporting compute units
299 static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c)
301 u32 nodes, cores_per_cu = 1;
303 int cpu = smp_processor_id();
305 /* get information required for multi-node processors */
306 if (cpu_has_topoext) {
307 u32 eax, ebx, ecx, edx;
309 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
310 nodes = ((ecx >> 8) & 7) + 1;
313 /* get compute unit information */
314 smp_num_siblings = ((ebx >> 8) & 3) + 1;
315 c->compute_unit_id = ebx & 0xff;
316 cores_per_cu += ((ebx >> 8) & 3);
317 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
320 rdmsrl(MSR_FAM10H_NODE_ID, value);
321 nodes = ((value >> 3) & 7) + 1;
326 /* fixup multi-node processor information */
331 set_cpu_cap(c, X86_FEATURE_AMD_DCM);
332 cores_per_node = c->x86_max_cores / nodes;
333 cus_per_node = cores_per_node / cores_per_cu;
335 /* store NodeID, use llc_shared_map to store sibling info */
336 per_cpu(cpu_llc_id, cpu) = node_id;
338 /* core id has to be in the [0 .. cores_per_node - 1] range */
339 c->cpu_core_id %= cores_per_node;
340 c->compute_unit_id %= cus_per_node;
346 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
347 * Assumes number of cores is a power of two.
349 static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
353 int cpu = smp_processor_id();
355 bits = c->x86_coreid_bits;
356 /* Low order bits define the core id (index of core in socket) */
357 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
358 /* Convert the initial APIC ID into the socket ID */
359 c->phys_proc_id = c->initial_apicid >> bits;
360 /* use socket ID also for last level cache */
361 per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
366 int amd_get_nb_id(int cpu)
370 id = per_cpu(cpu_llc_id, cpu);
374 EXPORT_SYMBOL_GPL(amd_get_nb_id);
376 static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c)
379 int cpu = smp_processor_id();
381 unsigned apicid = c->apicid;
383 node = numa_cpu_node(cpu);
384 if (node == NUMA_NO_NODE)
385 node = per_cpu(cpu_llc_id, cpu);
388 * On multi-fabric platform (e.g. Numascale NumaChip) a
389 * platform-specific handler needs to be called to fixup some
392 if (x86_cpuinit.fixup_cpu_id)
393 x86_cpuinit.fixup_cpu_id(c, node);
395 if (!node_online(node)) {
397 * Two possibilities here:
399 * - The CPU is missing memory and no node was created. In
400 * that case try picking one from a nearby CPU.
402 * - The APIC IDs differ from the HyperTransport node IDs
403 * which the K8 northbridge parsing fills in. Assume
404 * they are all increased by a constant offset, but in
405 * the same order as the HT nodeids. If that doesn't
406 * result in a usable node fall back to the path for the
409 * This workaround operates directly on the mapping between
410 * APIC ID and NUMA node, assuming certain relationship
411 * between APIC ID, HT node ID and NUMA topology. As going
412 * through CPU mapping may alter the outcome, directly
413 * access __apicid_to_node[].
415 int ht_nodeid = c->initial_apicid;
417 if (ht_nodeid >= 0 &&
418 __apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
419 node = __apicid_to_node[ht_nodeid];
420 /* Pick a nearby node */
421 if (!node_online(node))
422 node = nearby_node(apicid);
424 numa_set_node(cpu, node);
428 static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
433 /* Multi core CPU? */
434 if (c->extended_cpuid_level < 0x80000008)
437 ecx = cpuid_ecx(0x80000008);
439 c->x86_max_cores = (ecx & 0xff) + 1;
441 /* CPU telling us the core id bits shift? */
442 bits = (ecx >> 12) & 0xF;
444 /* Otherwise recompute */
446 while ((1 << bits) < c->x86_max_cores)
450 c->x86_coreid_bits = bits;
454 static void __cpuinit bsp_init_amd(struct cpuinfo_x86 *c)
456 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
459 (c->x86 == 0x10 && c->x86_model >= 0x2)) {
462 rdmsrl(MSR_K7_HWCR, val);
463 if (!(val & BIT(24)))
464 printk(KERN_WARNING FW_BUG "TSC doesn't count "
465 "with P0 frequency!\n");
469 if (c->x86 == 0x15) {
470 unsigned long upperbit;
473 cpuid = cpuid_edx(0x80000005);
474 assoc = cpuid >> 16 & 0xff;
475 upperbit = ((cpuid >> 24) << 10) / assoc;
477 va_align.mask = (upperbit - 1) & PAGE_MASK;
478 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64;
482 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
484 early_init_amd_mc(c);
487 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
488 * with P/T states and does not stop in deep C-states
490 if (c->x86_power & (1 << 8)) {
491 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
492 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
493 if (!check_tsc_unstable())
494 sched_clock_stable = 1;
498 set_cpu_cap(c, X86_FEATURE_SYSCALL32);
500 /* Set MTRR capability flag if appropriate */
502 if (c->x86_model == 13 || c->x86_model == 9 ||
503 (c->x86_model == 8 && c->x86_mask >= 8))
504 set_cpu_cap(c, X86_FEATURE_K6_MTRR);
506 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
507 /* check CPU config space for extended APIC ID */
508 if (cpu_has_apic && c->x86 >= 0xf) {
510 val = read_pci_config(0, 24, 0, 0x68);
511 if ((val & ((1 << 17) | (1 << 18))) == ((1 << 17) | (1 << 18)))
512 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
517 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
522 unsigned long long value;
525 * Disable TLB flush filter by setting HWCR.FFDIS on K8
526 * bit 6 of msr C001_0015
528 * Errata 63 for SH-B3 steppings
529 * Errata 122 for all steppings (F+ have it disabled by default)
532 rdmsrl(MSR_K7_HWCR, value);
534 wrmsrl(MSR_K7_HWCR, value);
541 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
542 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
544 clear_cpu_cap(c, 0*32+31);
547 /* On C+ stepping K8 rep microcode works well for copy/memset */
551 level = cpuid_eax(1);
552 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
553 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
556 * Some BIOSes incorrectly force this feature, but only K8
557 * revision D (model = 0x14) and later actually support it.
558 * (AMD Erratum #110, docId: 25759).
560 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) {
563 clear_cpu_cap(c, X86_FEATURE_LAHF_LM);
564 if (!rdmsrl_amd_safe(0xc001100d, &val)) {
565 val &= ~(1ULL << 32);
566 wrmsrl_amd_safe(0xc001100d, val);
572 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
574 /* get apicid instead of initial apic id from cpuid */
575 c->apicid = hard_smp_processor_id();
579 * FIXME: We should handle the K5 here. Set up the write
580 * range and also turn on MSR 83 bits 4 and 31 (write alloc,
591 case 6: /* An Athlon/Duron */
596 /* K6s reports MCEs but don't actually have all the MSRs */
598 clear_cpu_cap(c, X86_FEATURE_MCE);
601 /* Enable workaround for FXSAVE leak */
603 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
605 if (!c->x86_model_id[0]) {
608 /* Should distinguish Models here, but this is only
609 a fallback anyways. */
610 strcpy(c->x86_model_id, "Hammer");
615 /* re-enable TopologyExtensions if switched off by BIOS */
616 if ((c->x86 == 0x15) &&
617 (c->x86_model >= 0x10) && (c->x86_model <= 0x1f) &&
618 !cpu_has(c, X86_FEATURE_TOPOEXT)) {
621 if (!rdmsrl_safe(0xc0011005, &val)) {
623 wrmsrl_safe(0xc0011005, val);
624 rdmsrl(0xc0011005, val);
625 if (val & (1ULL << 54)) {
626 set_cpu_cap(c, X86_FEATURE_TOPOEXT);
627 printk(KERN_INFO FW_INFO "CPU: Re-enabling "
628 "disabled Topology Extensions Support\n");
634 * The way access filter has a performance penalty on some workloads.
635 * Disable it on the affected CPUs.
637 if ((c->x86 == 0x15) &&
638 (c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
641 if (!rdmsrl_safe(0xc0011021, &val) && !(val & 0x1E)) {
643 wrmsrl_safe(0xc0011021, val);
647 cpu_detect_cache_sizes(c);
649 /* Multi core CPU? */
650 if (c->extended_cpuid_level >= 0x80000008) {
659 init_amd_cacheinfo(c);
662 set_cpu_cap(c, X86_FEATURE_K8);
665 /* MFENCE stops RDTSC speculation */
666 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
670 if (c->x86 == 0x10) {
671 /* do this for boot cpu */
672 if (c == &boot_cpu_data)
673 check_enable_amd_mmconf_dmi();
675 fam10h_check_enable_mmcfg();
678 if (c == &boot_cpu_data && c->x86 >= 0xf) {
679 unsigned long long tseg;
682 * Split up direct mapping around the TSEG SMM area.
683 * Don't do it for gbpages because there seems very little
684 * benefit in doing so.
686 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
687 unsigned long pfn = tseg >> PAGE_SHIFT;
689 printk(KERN_DEBUG "tseg: %010llx\n", tseg);
690 if (pfn_range_is_mapped(pfn, pfn + 1))
691 set_memory_4k((unsigned long)__va(tseg), 1);
697 * Family 0x12 and above processors have APIC timer
698 * running in deep C states.
701 set_cpu_cap(c, X86_FEATURE_ARAT);
704 * Disable GART TLB Walk Errors on Fam10h. We do this here
705 * because this is always needed when GART is enabled, even in a
706 * kernel which has no MCE support built in.
708 if (c->x86 == 0x10) {
710 * BIOS should disable GartTlbWlk Errors themself. If
711 * it doesn't do it here as suggested by the BKDG.
713 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
718 err = rdmsrl_safe(MSR_AMD64_MCx_MASK(4), &mask);
721 wrmsrl_safe(MSR_AMD64_MCx_MASK(4), mask);
725 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
729 static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c,
732 /* AMD errata T13 (order #21922) */
735 if (c->x86_model == 3 && c->x86_mask == 0)
737 /* Tbird rev A1/A2 */
738 if (c->x86_model == 4 &&
739 (c->x86_mask == 0 || c->x86_mask == 1))
746 static void __cpuinit cpu_set_tlb_flushall_shift(struct cpuinfo_x86 *c)
748 tlb_flushall_shift = 5;
751 tlb_flushall_shift = 4;
754 static void __cpuinit cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
756 u32 ebx, eax, ecx, edx;
762 if (c->extended_cpuid_level < 0x80000006)
765 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
767 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask;
768 tlb_lli_4k[ENTRIES] = ebx & mask;
771 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB
772 * characteristics from the CPUID function 0x80000005 instead.
775 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
779 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
780 if (!((eax >> 16) & mask)) {
783 cpuid(0x80000005, &a, &b, &c, &d);
784 tlb_lld_2m[ENTRIES] = (a >> 16) & 0xff;
786 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask;
789 /* a 4M entry uses two 2M entries */
790 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1;
792 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
795 if (c->x86 == 0x15 && c->x86_model <= 0x1f) {
796 tlb_lli_2m[ENTRIES] = 1024;
798 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
799 tlb_lli_2m[ENTRIES] = eax & 0xff;
802 tlb_lli_2m[ENTRIES] = eax & mask;
804 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
806 cpu_set_tlb_flushall_shift(c);
809 static const struct cpu_dev __cpuinitconst amd_cpu_dev = {
811 .c_ident = { "AuthenticAMD" },
814 { .vendor = X86_VENDOR_AMD, .family = 4, .model_names =
825 .c_size_cache = amd_size_cache,
827 .c_early_init = early_init_amd,
828 .c_detect_tlb = cpu_detect_tlb_amd,
829 .c_bsp_init = bsp_init_amd,
831 .c_x86_vendor = X86_VENDOR_AMD,
834 cpu_dev_register(amd_cpu_dev);
837 * AMD errata checking
839 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
840 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
841 * have an OSVW id assigned, which it takes as first argument. Both take a
842 * variable number of family-specific model-stepping ranges created by
843 * AMD_MODEL_RANGE(). Each erratum also has to be declared as extern const
844 * int[] in arch/x86/include/asm/processor.h.
848 * const int amd_erratum_319[] =
849 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
850 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
851 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
854 const int amd_erratum_400[] =
855 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
856 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
857 EXPORT_SYMBOL_GPL(amd_erratum_400);
859 const int amd_erratum_383[] =
860 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
861 EXPORT_SYMBOL_GPL(amd_erratum_383);
863 bool cpu_has_amd_erratum(const int *erratum)
865 struct cpuinfo_x86 *cpu = __this_cpu_ptr(&cpu_info);
866 int osvw_id = *erratum++;
871 * If called early enough that current_cpu_data hasn't been initialized
872 * yet, fall back to boot_cpu_data.
875 cpu = &boot_cpu_data;
877 if (cpu->x86_vendor != X86_VENDOR_AMD)
880 if (osvw_id >= 0 && osvw_id < 65536 &&
881 cpu_has(cpu, X86_FEATURE_OSVW)) {
884 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
885 if (osvw_id < osvw_len) {
888 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
890 return osvw_bits & (1ULL << (osvw_id & 0x3f));
894 /* OSVW unavailable or ID unknown, match family-model-stepping range */
895 ms = (cpu->x86_model << 4) | cpu->x86_mask;
896 while ((range = *erratum++))
897 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
898 (ms >= AMD_MODEL_RANGE_START(range)) &&
899 (ms <= AMD_MODEL_RANGE_END(range)))
905 EXPORT_SYMBOL_GPL(cpu_has_amd_erratum);