2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13 #include <linux/thread_info.h>
14 #include <linux/capability.h>
15 #include <linux/miscdevice.h>
16 #include <linux/ratelimit.h>
17 #include <linux/kallsyms.h>
18 #include <linux/rcupdate.h>
19 #include <linux/kobject.h>
20 #include <linux/uaccess.h>
21 #include <linux/kdebug.h>
22 #include <linux/kernel.h>
23 #include <linux/percpu.h>
24 #include <linux/string.h>
25 #include <linux/device.h>
26 #include <linux/syscore_ops.h>
27 #include <linux/delay.h>
28 #include <linux/ctype.h>
29 #include <linux/sched.h>
30 #include <linux/sysfs.h>
31 #include <linux/types.h>
32 #include <linux/slab.h>
33 #include <linux/init.h>
34 #include <linux/kmod.h>
35 #include <linux/poll.h>
36 #include <linux/nmi.h>
37 #include <linux/cpu.h>
38 #include <linux/smp.h>
41 #include <linux/debugfs.h>
42 #include <linux/irq_work.h>
43 #include <linux/export.h>
45 #include <asm/processor.h>
49 #include "mce-internal.h"
51 static DEFINE_MUTEX(mce_chrdev_read_mutex);
53 #define rcu_dereference_check_mce(p) \
54 rcu_dereference_index_check((p), \
55 rcu_read_lock_sched_held() || \
56 lockdep_is_held(&mce_chrdev_read_mutex))
58 #define CREATE_TRACE_POINTS
59 #include <trace/events/mce.h>
61 #define SPINUNIT 100 /* 100ns */
63 DEFINE_PER_CPU(unsigned, mce_exception_count);
65 struct mce_bank *mce_banks __read_mostly;
67 struct mca_config mca_cfg __read_mostly = {
71 * 0: always panic on uncorrected errors, log corrected errors
72 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
73 * 2: SIGBUS or log uncorrected errors (if possible), log corr. errors
74 * 3: never panic or SIGBUS, log all errors (for testing only)
80 /* User mode helper program triggered by machine check event */
81 static unsigned long mce_need_notify;
82 static char mce_helper[128];
83 static char *mce_helper_argv[2] = { mce_helper, NULL };
85 static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait);
87 static DEFINE_PER_CPU(struct mce, mces_seen);
88 static int cpu_missing;
90 /* CMCI storm detection filter */
91 static DEFINE_PER_CPU(unsigned long, mce_polled_error);
94 * MCA banks polled by the period polling timer for corrected events.
95 * With Intel CMCI, this only has MCA banks which do not support CMCI (if any).
97 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
98 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
102 * MCA banks controlled through firmware first for corrected errors.
103 * This is a global list of banks for which we won't enable CMCI and we
104 * won't poll. Firmware controls these banks and is responsible for
105 * reporting corrected errors through GHES. Uncorrected/recoverable
106 * errors are still notified through a machine check.
108 mce_banks_t mce_banks_ce_disabled;
110 static DEFINE_PER_CPU(struct work_struct, mce_work);
112 static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs);
115 * CPU/chipset specific EDAC code can register a notifier call here to print
116 * MCE errors in a human-readable form.
118 ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain);
120 /* Do initial initialization of a struct mce */
121 void mce_setup(struct mce *m)
123 memset(m, 0, sizeof(struct mce));
124 m->cpu = m->extcpu = smp_processor_id();
126 /* We hope get_seconds stays lockless */
127 m->time = get_seconds();
128 m->cpuvendor = boot_cpu_data.x86_vendor;
129 m->cpuid = cpuid_eax(1);
130 m->socketid = cpu_data(m->extcpu).phys_proc_id;
131 m->apicid = cpu_data(m->extcpu).initial_apicid;
132 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
135 DEFINE_PER_CPU(struct mce, injectm);
136 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
139 * Lockless MCE logging infrastructure.
140 * This avoids deadlocks on printk locks without having to break locks. Also
141 * separate MCEs from kernel messages to avoid bogus bug reports.
144 static struct mce_log mcelog = {
145 .signature = MCE_LOG_SIGNATURE,
147 .recordlen = sizeof(struct mce),
150 void mce_log(struct mce *mce)
152 unsigned next, entry;
154 /* Emit the trace record: */
155 trace_mce_record(mce);
157 atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, mce);
162 entry = rcu_dereference_check_mce(mcelog.next);
166 * When the buffer fills up discard new entries.
167 * Assume that the earlier errors are the more
170 if (entry >= MCE_LOG_LEN) {
171 set_bit(MCE_OVERFLOW,
172 (unsigned long *)&mcelog.flags);
175 /* Old left over entry. Skip: */
176 if (mcelog.entry[entry].finished) {
184 if (cmpxchg(&mcelog.next, entry, next) == entry)
187 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
189 mcelog.entry[entry].finished = 1;
193 set_bit(0, &mce_need_notify);
196 static void drain_mcelog_buffer(void)
198 unsigned int next, i, prev = 0;
200 next = ACCESS_ONCE(mcelog.next);
205 /* drain what was logged during boot */
206 for (i = prev; i < next; i++) {
207 unsigned long start = jiffies;
208 unsigned retries = 1;
210 m = &mcelog.entry[i];
212 while (!m->finished) {
213 if (time_after_eq(jiffies, start + 2*retries))
218 if (!m->finished && retries >= 4) {
219 pr_err("skipping error being logged currently!\n");
224 atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
227 memset(mcelog.entry + prev, 0, (next - prev) * sizeof(*m));
229 next = cmpxchg(&mcelog.next, prev, 0);
230 } while (next != prev);
234 void mce_register_decode_chain(struct notifier_block *nb)
236 atomic_notifier_chain_register(&x86_mce_decoder_chain, nb);
237 drain_mcelog_buffer();
239 EXPORT_SYMBOL_GPL(mce_register_decode_chain);
241 void mce_unregister_decode_chain(struct notifier_block *nb)
243 atomic_notifier_chain_unregister(&x86_mce_decoder_chain, nb);
245 EXPORT_SYMBOL_GPL(mce_unregister_decode_chain);
247 static void print_mce(struct mce *m)
251 pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n",
252 m->extcpu, m->mcgstatus, m->bank, m->status);
255 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
256 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
259 if (m->cs == __KERNEL_CS)
260 print_symbol("{%s}", m->ip);
264 pr_emerg(HW_ERR "TSC %llx ", m->tsc);
266 pr_cont("ADDR %llx ", m->addr);
268 pr_cont("MISC %llx ", m->misc);
272 * Note this output is parsed by external tools and old fields
273 * should not be changed.
275 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
276 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
277 cpu_data(m->extcpu).microcode);
280 * Print out human-readable details about the MCE error,
281 * (if the CPU has an implementation for that)
283 ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
284 if (ret == NOTIFY_STOP)
287 pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");
290 #define PANIC_TIMEOUT 5 /* 5 seconds */
292 static atomic_t mce_panicked;
294 static int fake_panic;
295 static atomic_t mce_fake_panicked;
297 /* Panic in progress. Enable interrupts and wait for final IPI */
298 static void wait_for_panic(void)
300 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
304 while (timeout-- > 0)
306 if (panic_timeout == 0)
307 panic_timeout = mca_cfg.panic_timeout;
308 panic("Panicing machine check CPU died");
311 static void mce_panic(char *msg, struct mce *final, char *exp)
317 * Make sure only one CPU runs in machine check panic
319 if (atomic_inc_return(&mce_panicked) > 1)
326 /* Don't log too much for fake panic */
327 if (atomic_inc_return(&mce_fake_panicked) > 1)
330 /* First print corrected ones that are still unlogged */
331 for (i = 0; i < MCE_LOG_LEN; i++) {
332 struct mce *m = &mcelog.entry[i];
333 if (!(m->status & MCI_STATUS_VAL))
335 if (!(m->status & MCI_STATUS_UC)) {
338 apei_err = apei_write_mce(m);
341 /* Now print uncorrected but with the final one last */
342 for (i = 0; i < MCE_LOG_LEN; i++) {
343 struct mce *m = &mcelog.entry[i];
344 if (!(m->status & MCI_STATUS_VAL))
346 if (!(m->status & MCI_STATUS_UC))
348 if (!final || memcmp(m, final, sizeof(struct mce))) {
351 apei_err = apei_write_mce(m);
357 apei_err = apei_write_mce(final);
360 pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n");
362 pr_emerg(HW_ERR "Machine check: %s\n", exp);
364 if (panic_timeout == 0)
365 panic_timeout = mca_cfg.panic_timeout;
368 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
371 /* Support code for software error injection */
373 static int msr_to_offset(u32 msr)
375 unsigned bank = __this_cpu_read(injectm.bank);
377 if (msr == mca_cfg.rip_msr)
378 return offsetof(struct mce, ip);
379 if (msr == MSR_IA32_MCx_STATUS(bank))
380 return offsetof(struct mce, status);
381 if (msr == MSR_IA32_MCx_ADDR(bank))
382 return offsetof(struct mce, addr);
383 if (msr == MSR_IA32_MCx_MISC(bank))
384 return offsetof(struct mce, misc);
385 if (msr == MSR_IA32_MCG_STATUS)
386 return offsetof(struct mce, mcgstatus);
390 /* MSR access wrappers used for error injection */
391 static u64 mce_rdmsrl(u32 msr)
395 if (__this_cpu_read(injectm.finished)) {
396 int offset = msr_to_offset(msr);
400 return *(u64 *)((char *)this_cpu_ptr(&injectm) + offset);
403 if (rdmsrl_safe(msr, &v)) {
404 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr);
406 * Return zero in case the access faulted. This should
407 * not happen normally but can happen if the CPU does
408 * something weird, or if the code is buggy.
416 static void mce_wrmsrl(u32 msr, u64 v)
418 if (__this_cpu_read(injectm.finished)) {
419 int offset = msr_to_offset(msr);
422 *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v;
429 * Collect all global (w.r.t. this processor) status about this machine
430 * check into our "mce" struct so that we can use it later to assess
431 * the severity of the problem as we read per-bank specific details.
433 static inline void mce_gather_info(struct mce *m, struct pt_regs *regs)
437 m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
440 * Get the address of the instruction at the time of
441 * the machine check error.
443 if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) {
448 * When in VM86 mode make the cs look like ring 3
449 * always. This is a lie, but it's better than passing
450 * the additional vm86 bit around everywhere.
452 if (v8086_mode(regs))
455 /* Use accurate RIP reporting if available. */
457 m->ip = mce_rdmsrl(mca_cfg.rip_msr);
462 * Simple lockless ring to communicate PFNs from the exception handler with the
463 * process context work function. This is vastly simplified because there's
464 * only a single reader and a single writer.
466 #define MCE_RING_SIZE 16 /* we use one entry less */
469 unsigned short start;
471 unsigned long ring[MCE_RING_SIZE];
473 static DEFINE_PER_CPU(struct mce_ring, mce_ring);
475 /* Runs with CPU affinity in workqueue */
476 static int mce_ring_empty(void)
478 struct mce_ring *r = this_cpu_ptr(&mce_ring);
480 return r->start == r->end;
483 static int mce_ring_get(unsigned long *pfn)
490 r = this_cpu_ptr(&mce_ring);
491 if (r->start == r->end)
493 *pfn = r->ring[r->start];
494 r->start = (r->start + 1) % MCE_RING_SIZE;
501 /* Always runs in MCE context with preempt off */
502 static int mce_ring_add(unsigned long pfn)
504 struct mce_ring *r = this_cpu_ptr(&mce_ring);
507 next = (r->end + 1) % MCE_RING_SIZE;
508 if (next == r->start)
510 r->ring[r->end] = pfn;
516 int mce_available(struct cpuinfo_x86 *c)
518 if (mca_cfg.disabled)
520 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
523 static void mce_schedule_work(void)
525 if (!mce_ring_empty())
526 schedule_work(this_cpu_ptr(&mce_work));
529 DEFINE_PER_CPU(struct irq_work, mce_irq_work);
531 static void mce_irq_work_cb(struct irq_work *entry)
537 static void mce_report_event(struct pt_regs *regs)
539 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
542 * Triggering the work queue here is just an insurance
543 * policy in case the syscall exit notify handler
544 * doesn't run soon enough or ends up running on the
545 * wrong CPU (can happen when audit sleeps)
551 irq_work_queue(this_cpu_ptr(&mce_irq_work));
555 * Read ADDR and MISC registers.
557 static void mce_read_aux(struct mce *m, int i)
559 if (m->status & MCI_STATUS_MISCV)
560 m->misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
561 if (m->status & MCI_STATUS_ADDRV) {
562 m->addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
565 * Mask the reported address by the reported granularity.
567 if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) {
568 u8 shift = MCI_MISC_ADDR_LSB(m->misc);
575 static bool memory_error(struct mce *m)
577 struct cpuinfo_x86 *c = &boot_cpu_data;
579 if (c->x86_vendor == X86_VENDOR_AMD) {
584 } else if (c->x86_vendor == X86_VENDOR_INTEL) {
586 * Intel SDM Volume 3B - 15.9.2 Compound Error Codes
588 * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for
589 * indicating a memory error. Bit 8 is used for indicating a
590 * cache hierarchy error. The combination of bit 2 and bit 3
591 * is used for indicating a `generic' cache hierarchy error
592 * But we can't just blindly check the above bits, because if
593 * bit 11 is set, then it is a bus/interconnect error - and
594 * either way the above bits just gives more detail on what
595 * bus/interconnect error happened. Note that bit 12 can be
596 * ignored, as it's the "filter" bit.
598 return (m->status & 0xef80) == BIT(7) ||
599 (m->status & 0xef00) == BIT(8) ||
600 (m->status & 0xeffc) == 0xc;
606 DEFINE_PER_CPU(unsigned, mce_poll_count);
609 * Poll for corrected events or events that happened before reset.
610 * Those are just logged through /dev/mcelog.
612 * This is executed in standard interrupt context.
614 * Note: spec recommends to panic for fatal unsignalled
615 * errors here. However this would be quite problematic --
616 * we would need to reimplement the Monarch handling and
617 * it would mess up the exclusion between exception handler
618 * and poll hander -- * so we skip this for now.
619 * These cases should not happen anyways, or only when the CPU
620 * is already totally * confused. In this case it's likely it will
621 * not fully execute the machine check handler either.
623 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
629 this_cpu_inc(mce_poll_count);
631 mce_gather_info(&m, NULL);
633 for (i = 0; i < mca_cfg.banks; i++) {
634 if (!mce_banks[i].ctl || !test_bit(i, *b))
643 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
644 if (!(m.status & MCI_STATUS_VAL))
647 this_cpu_write(mce_polled_error, 1);
649 * Uncorrected or signalled events are handled by the exception
650 * handler when it is enabled, so don't process those here.
652 * TBD do the same check for MCI_STATUS_EN here?
654 if (!(flags & MCP_UC) &&
655 (m.status & (mca_cfg.ser ? MCI_STATUS_S : MCI_STATUS_UC)))
660 if (!(flags & MCP_TIMESTAMP))
663 severity = mce_severity(&m, mca_cfg.tolerant, NULL, false);
666 * In the cases where we don't have a valid address after all,
667 * do not add it into the ring buffer.
669 if (severity == MCE_DEFERRED_SEVERITY && memory_error(&m)) {
670 if (m.status & MCI_STATUS_ADDRV) {
671 mce_ring_add(m.addr >> PAGE_SHIFT);
677 * Don't get the IP here because it's unlikely to
678 * have anything to do with the actual error location.
680 if (!(flags & MCP_DONTLOG) && !mca_cfg.dont_log_ce)
684 * Clear state for this bank.
686 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
690 * Don't clear MCG_STATUS here because it's only defined for
696 EXPORT_SYMBOL_GPL(machine_check_poll);
699 * Do a quick check if any of the events requires a panic.
700 * This decides if we keep the events around or clear them.
702 static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp,
703 struct pt_regs *regs)
707 for (i = 0; i < mca_cfg.banks; i++) {
708 m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
709 if (m->status & MCI_STATUS_VAL) {
710 __set_bit(i, validp);
711 if (quirk_no_way_out)
712 quirk_no_way_out(i, m, regs);
714 if (mce_severity(m, mca_cfg.tolerant, msg, true) >=
722 * Variable to establish order between CPUs while scanning.
723 * Each CPU spins initially until executing is equal its number.
725 static atomic_t mce_executing;
728 * Defines order of CPUs on entry. First CPU becomes Monarch.
730 static atomic_t mce_callin;
733 * Check if a timeout waiting for other CPUs happened.
735 static int mce_timed_out(u64 *t)
738 * The others already did panic for some reason.
739 * Bail out like in a timeout.
740 * rmb() to tell the compiler that system_state
741 * might have been modified by someone else.
744 if (atomic_read(&mce_panicked))
746 if (!mca_cfg.monarch_timeout)
748 if ((s64)*t < SPINUNIT) {
749 if (mca_cfg.tolerant <= 1)
750 mce_panic("Timeout synchronizing machine check over CPUs",
757 touch_nmi_watchdog();
762 * The Monarch's reign. The Monarch is the CPU who entered
763 * the machine check handler first. It waits for the others to
764 * raise the exception too and then grades them. When any
765 * error is fatal panic. Only then let the others continue.
767 * The other CPUs entering the MCE handler will be controlled by the
768 * Monarch. They are called Subjects.
770 * This way we prevent any potential data corruption in a unrecoverable case
771 * and also makes sure always all CPU's errors are examined.
773 * Also this detects the case of a machine check event coming from outer
774 * space (not detected by any CPUs) In this case some external agent wants
775 * us to shut down, so panic too.
777 * The other CPUs might still decide to panic if the handler happens
778 * in a unrecoverable place, but in this case the system is in a semi-stable
779 * state and won't corrupt anything by itself. It's ok to let the others
780 * continue for a bit first.
782 * All the spin loops have timeouts; when a timeout happens a CPU
783 * typically elects itself to be Monarch.
785 static void mce_reign(void)
788 struct mce *m = NULL;
789 int global_worst = 0;
794 * This CPU is the Monarch and the other CPUs have run
795 * through their handlers.
796 * Grade the severity of the errors of all the CPUs.
798 for_each_possible_cpu(cpu) {
799 int severity = mce_severity(&per_cpu(mces_seen, cpu),
802 if (severity > global_worst) {
804 global_worst = severity;
805 m = &per_cpu(mces_seen, cpu);
810 * Cannot recover? Panic here then.
811 * This dumps all the mces in the log buffer and stops the
814 if (m && global_worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3)
815 mce_panic("Fatal Machine check", m, msg);
818 * For UC somewhere we let the CPU who detects it handle it.
819 * Also must let continue the others, otherwise the handling
820 * CPU could deadlock on a lock.
824 * No machine check event found. Must be some external
825 * source or one CPU is hung. Panic.
827 if (global_worst <= MCE_KEEP_SEVERITY && mca_cfg.tolerant < 3)
828 mce_panic("Machine check from unknown source", NULL, NULL);
831 * Now clear all the mces_seen so that they don't reappear on
834 for_each_possible_cpu(cpu)
835 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
838 static atomic_t global_nwo;
841 * Start of Monarch synchronization. This waits until all CPUs have
842 * entered the exception handler and then determines if any of them
843 * saw a fatal event that requires panic. Then it executes them
844 * in the entry order.
845 * TBD double check parallel CPU hotunplug
847 static int mce_start(int *no_way_out)
850 int cpus = num_online_cpus();
851 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
856 atomic_add(*no_way_out, &global_nwo);
858 * global_nwo should be updated before mce_callin
861 order = atomic_inc_return(&mce_callin);
866 while (atomic_read(&mce_callin) != cpus) {
867 if (mce_timed_out(&timeout)) {
868 atomic_set(&global_nwo, 0);
875 * mce_callin should be read before global_nwo
881 * Monarch: Starts executing now, the others wait.
883 atomic_set(&mce_executing, 1);
886 * Subject: Now start the scanning loop one by one in
887 * the original callin order.
888 * This way when there are any shared banks it will be
889 * only seen by one CPU before cleared, avoiding duplicates.
891 while (atomic_read(&mce_executing) < order) {
892 if (mce_timed_out(&timeout)) {
893 atomic_set(&global_nwo, 0);
901 * Cache the global no_way_out state.
903 *no_way_out = atomic_read(&global_nwo);
909 * Synchronize between CPUs after main scanning loop.
910 * This invokes the bulk of the Monarch processing.
912 static int mce_end(int order)
915 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
923 * Allow others to run.
925 atomic_inc(&mce_executing);
928 /* CHECKME: Can this race with a parallel hotplug? */
929 int cpus = num_online_cpus();
932 * Monarch: Wait for everyone to go through their scanning
935 while (atomic_read(&mce_executing) <= cpus) {
936 if (mce_timed_out(&timeout))
946 * Subject: Wait for Monarch to finish.
948 while (atomic_read(&mce_executing) != 0) {
949 if (mce_timed_out(&timeout))
955 * Don't reset anything. That's done by the Monarch.
961 * Reset all global state.
964 atomic_set(&global_nwo, 0);
965 atomic_set(&mce_callin, 0);
969 * Let others run again.
971 atomic_set(&mce_executing, 0);
976 * Check if the address reported by the CPU is in a format we can parse.
977 * It would be possible to add code for most other cases, but all would
978 * be somewhat complicated (e.g. segment offset would require an instruction
979 * parser). So only support physical addresses up to page granuality for now.
981 static int mce_usable_address(struct mce *m)
983 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
985 if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
987 if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
992 static void mce_clear_state(unsigned long *toclear)
996 for (i = 0; i < mca_cfg.banks; i++) {
997 if (test_bit(i, toclear))
998 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
1003 * Need to save faulting physical address associated with a process
1004 * in the machine check handler some place where we can grab it back
1005 * later in mce_notify_process()
1007 #define MCE_INFO_MAX 16
1011 struct task_struct *t;
1014 } mce_info[MCE_INFO_MAX];
1016 static void mce_save_info(__u64 addr, int c)
1018 struct mce_info *mi;
1020 for (mi = mce_info; mi < &mce_info[MCE_INFO_MAX]; mi++) {
1021 if (atomic_cmpxchg(&mi->inuse, 0, 1) == 0) {
1024 mi->restartable = c;
1029 mce_panic("Too many concurrent recoverable errors", NULL, NULL);
1032 static struct mce_info *mce_find_info(void)
1034 struct mce_info *mi;
1036 for (mi = mce_info; mi < &mce_info[MCE_INFO_MAX]; mi++)
1037 if (atomic_read(&mi->inuse) && mi->t == current)
1042 static void mce_clear_info(struct mce_info *mi)
1044 atomic_set(&mi->inuse, 0);
1048 * The actual machine check handler. This only handles real
1049 * exceptions when something got corrupted coming in through int 18.
1051 * This is executed in NMI context not subject to normal locking rules. This
1052 * implies that most kernel services cannot be safely used. Don't even
1053 * think about putting a printk in there!
1055 * On Intel systems this is entered on all CPUs in parallel through
1056 * MCE broadcast. However some CPUs might be broken beyond repair,
1057 * so be always careful when synchronizing with others.
1059 void do_machine_check(struct pt_regs *regs, long error_code)
1061 struct mca_config *cfg = &mca_cfg;
1062 struct mce m, *final;
1067 * Establish sequential order between the CPUs entering the machine
1072 * If no_way_out gets set, there is no safe way to recover from this
1073 * MCE. If mca_cfg.tolerant is cranked up, we'll try anyway.
1077 * If kill_it gets set, there might be a way to recover from this
1081 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
1082 DECLARE_BITMAP(valid_banks, MAX_NR_BANKS);
1083 char *msg = "Unknown";
1085 this_cpu_inc(mce_exception_count);
1090 mce_gather_info(&m, regs);
1092 final = this_cpu_ptr(&mces_seen);
1095 memset(valid_banks, 0, sizeof(valid_banks));
1096 no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs);
1101 * When no restart IP might need to kill or panic.
1102 * Assume the worst for now, but if we find the
1103 * severity is MCE_AR_SEVERITY we have other options.
1105 if (!(m.mcgstatus & MCG_STATUS_RIPV))
1109 * Go through all the banks in exclusion of the other CPUs.
1110 * This way we don't report duplicated events on shared banks
1111 * because the first one to see it will clear it.
1113 order = mce_start(&no_way_out);
1114 for (i = 0; i < cfg->banks; i++) {
1115 __clear_bit(i, toclear);
1116 if (!test_bit(i, valid_banks))
1118 if (!mce_banks[i].ctl)
1125 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
1126 if ((m.status & MCI_STATUS_VAL) == 0)
1130 * Non uncorrected or non signaled errors are handled by
1131 * machine_check_poll. Leave them alone, unless this panics.
1133 if (!(m.status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
1138 * Set taint even when machine check was not enabled.
1140 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
1142 severity = mce_severity(&m, cfg->tolerant, NULL, true);
1145 * When machine check was for corrected/deferred handler don't
1146 * touch, unless we're panicing.
1148 if ((severity == MCE_KEEP_SEVERITY ||
1149 severity == MCE_UCNA_SEVERITY) && !no_way_out)
1151 __set_bit(i, toclear);
1152 if (severity == MCE_NO_SEVERITY) {
1154 * Machine check event was not enabled. Clear, but
1160 mce_read_aux(&m, i);
1163 * Action optional error. Queue address for later processing.
1164 * When the ring overflows we just ignore the AO error.
1165 * RED-PEN add some logging mechanism when
1166 * usable_address or mce_add_ring fails.
1167 * RED-PEN don't ignore overflow for mca_cfg.tolerant == 0
1169 if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
1170 mce_ring_add(m.addr >> PAGE_SHIFT);
1174 if (severity > worst) {
1180 /* mce_clear_state will clear *final, save locally for use later */
1184 mce_clear_state(toclear);
1187 * Do most of the synchronization with other CPUs.
1188 * When there's any problem use only local no_way_out state.
1190 if (mce_end(order) < 0)
1191 no_way_out = worst >= MCE_PANIC_SEVERITY;
1194 * At insane "tolerant" levels we take no action. Otherwise
1195 * we only die if we have no other choice. For less serious
1196 * issues we try to recover, or limit damage to the current
1199 if (cfg->tolerant < 3) {
1201 mce_panic("Fatal machine check on current CPU", &m, msg);
1202 if (worst == MCE_AR_SEVERITY) {
1203 /* schedule action before return to userland */
1204 mce_save_info(m.addr, m.mcgstatus & MCG_STATUS_RIPV);
1205 set_thread_flag(TIF_MCE_NOTIFY);
1206 } else if (kill_it) {
1207 force_sig(SIGBUS, current);
1212 mce_report_event(regs);
1213 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1217 EXPORT_SYMBOL_GPL(do_machine_check);
1219 #ifndef CONFIG_MEMORY_FAILURE
1220 int memory_failure(unsigned long pfn, int vector, int flags)
1222 /* mce_severity() should not hand us an ACTION_REQUIRED error */
1223 BUG_ON(flags & MF_ACTION_REQUIRED);
1224 pr_err("Uncorrected memory error in page 0x%lx ignored\n"
1225 "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n",
1233 * Called in process context that interrupted by MCE and marked with
1234 * TIF_MCE_NOTIFY, just before returning to erroneous userland.
1235 * This code is allowed to sleep.
1236 * Attempt possible recovery such as calling the high level VM handler to
1237 * process any corrupted pages, and kill/signal current process if required.
1238 * Action required errors are handled here.
1240 void mce_notify_process(void)
1243 struct mce_info *mi = mce_find_info();
1244 int flags = MF_ACTION_REQUIRED;
1247 mce_panic("Lost physical address for unconsumed uncorrectable error", NULL, NULL);
1248 pfn = mi->paddr >> PAGE_SHIFT;
1250 clear_thread_flag(TIF_MCE_NOTIFY);
1252 pr_err("Uncorrected hardware memory error in user-access at %llx",
1255 * We must call memory_failure() here even if the current process is
1256 * doomed. We still need to mark the page as poisoned and alert any
1257 * other users of the page.
1259 if (!mi->restartable)
1260 flags |= MF_MUST_KILL;
1261 if (memory_failure(pfn, MCE_VECTOR, flags) < 0) {
1262 pr_err("Memory error not recovered");
1263 force_sig(SIGBUS, current);
1269 * Action optional processing happens here (picking up
1270 * from the list of faulting pages that do_machine_check()
1271 * placed into the "ring").
1273 static void mce_process_work(struct work_struct *dummy)
1277 while (mce_ring_get(&pfn))
1278 memory_failure(pfn, MCE_VECTOR, 0);
1281 #ifdef CONFIG_X86_MCE_INTEL
1283 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1284 * @cpu: The CPU on which the event occurred.
1285 * @status: Event status information
1287 * This function should be called by the thermal interrupt after the
1288 * event has been processed and the decision was made to log the event
1291 * The status parameter will be saved to the 'status' field of 'struct mce'
1292 * and historically has been the register value of the
1293 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1295 void mce_log_therm_throt_event(__u64 status)
1300 m.bank = MCE_THERMAL_BANK;
1304 #endif /* CONFIG_X86_MCE_INTEL */
1307 * Periodic polling timer for "silent" machine check errors. If the
1308 * poller finds an MCE, poll 2x faster. When the poller finds no more
1309 * errors, poll 2x slower (up to check_interval seconds).
1311 static unsigned long check_interval = 5 * 60; /* 5 minutes */
1313 static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */
1314 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1316 static unsigned long mce_adjust_timer_default(unsigned long interval)
1321 static unsigned long (*mce_adjust_timer)(unsigned long interval) =
1322 mce_adjust_timer_default;
1324 static int cmc_error_seen(void)
1326 unsigned long *v = this_cpu_ptr(&mce_polled_error);
1328 return test_and_clear_bit(0, v);
1331 static void mce_timer_fn(unsigned long data)
1333 struct timer_list *t = this_cpu_ptr(&mce_timer);
1337 WARN_ON(smp_processor_id() != data);
1339 if (mce_available(this_cpu_ptr(&cpu_info))) {
1340 machine_check_poll(MCP_TIMESTAMP,
1341 this_cpu_ptr(&mce_poll_banks));
1342 mce_intel_cmci_poll();
1346 * Alert userspace if needed. If we logged an MCE, reduce the
1347 * polling interval, otherwise increase the polling interval.
1349 iv = __this_cpu_read(mce_next_interval);
1350 notify = mce_notify_irq();
1351 notify |= cmc_error_seen();
1353 iv = max(iv / 2, (unsigned long) HZ/100);
1355 iv = min(iv * 2, round_jiffies_relative(check_interval * HZ));
1356 iv = mce_adjust_timer(iv);
1358 __this_cpu_write(mce_next_interval, iv);
1359 /* Might have become 0 after CMCI storm subsided */
1361 t->expires = jiffies + iv;
1362 add_timer_on(t, smp_processor_id());
1367 * Ensure that the timer is firing in @interval from now.
1369 void mce_timer_kick(unsigned long interval)
1371 struct timer_list *t = this_cpu_ptr(&mce_timer);
1372 unsigned long when = jiffies + interval;
1373 unsigned long iv = __this_cpu_read(mce_next_interval);
1375 if (timer_pending(t)) {
1376 if (time_before(when, t->expires))
1377 mod_timer_pinned(t, when);
1379 t->expires = round_jiffies(when);
1380 add_timer_on(t, smp_processor_id());
1383 __this_cpu_write(mce_next_interval, interval);
1386 /* Must not be called in IRQ context where del_timer_sync() can deadlock */
1387 static void mce_timer_delete_all(void)
1391 for_each_online_cpu(cpu)
1392 del_timer_sync(&per_cpu(mce_timer, cpu));
1395 static void mce_do_trigger(struct work_struct *work)
1397 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
1400 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
1403 * Notify the user(s) about new machine check events.
1404 * Can be called from interrupt context, but not from machine check/NMI
1407 int mce_notify_irq(void)
1409 /* Not more than two messages every minute */
1410 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1412 if (test_and_clear_bit(0, &mce_need_notify)) {
1413 /* wake processes polling /dev/mcelog */
1414 wake_up_interruptible(&mce_chrdev_wait);
1417 schedule_work(&mce_trigger_work);
1419 if (__ratelimit(&ratelimit))
1420 pr_info(HW_ERR "Machine check events logged\n");
1426 EXPORT_SYMBOL_GPL(mce_notify_irq);
1428 static int __mcheck_cpu_mce_banks_init(void)
1431 u8 num_banks = mca_cfg.banks;
1433 mce_banks = kzalloc(num_banks * sizeof(struct mce_bank), GFP_KERNEL);
1437 for (i = 0; i < num_banks; i++) {
1438 struct mce_bank *b = &mce_banks[i];
1447 * Initialize Machine Checks for a CPU.
1449 static int __mcheck_cpu_cap_init(void)
1454 rdmsrl(MSR_IA32_MCG_CAP, cap);
1456 b = cap & MCG_BANKCNT_MASK;
1458 pr_info("CPU supports %d MCE banks\n", b);
1460 if (b > MAX_NR_BANKS) {
1461 pr_warn("Using only %u machine check banks out of %u\n",
1466 /* Don't support asymmetric configurations today */
1467 WARN_ON(mca_cfg.banks != 0 && b != mca_cfg.banks);
1471 int err = __mcheck_cpu_mce_banks_init();
1477 /* Use accurate RIP reporting if available. */
1478 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1479 mca_cfg.rip_msr = MSR_IA32_MCG_EIP;
1481 if (cap & MCG_SER_P)
1487 static void __mcheck_cpu_init_generic(void)
1489 enum mcp_flags m_fl = 0;
1490 mce_banks_t all_banks;
1494 if (!mca_cfg.bootlog)
1498 * Log the machine checks left over from the previous reset.
1500 bitmap_fill(all_banks, MAX_NR_BANKS);
1501 machine_check_poll(MCP_UC | m_fl, &all_banks);
1503 set_in_cr4(X86_CR4_MCE);
1505 rdmsrl(MSR_IA32_MCG_CAP, cap);
1506 if (cap & MCG_CTL_P)
1507 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1509 for (i = 0; i < mca_cfg.banks; i++) {
1510 struct mce_bank *b = &mce_banks[i];
1514 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1515 wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
1520 * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and
1521 * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM
1522 * Vol 3B Table 15-20). But this confuses both the code that determines
1523 * whether the machine check occurred in kernel or user mode, and also
1524 * the severity assessment code. Pretend that EIPV was set, and take the
1525 * ip/cs values from the pt_regs that mce_gather_info() ignored earlier.
1527 static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs)
1531 if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0)
1533 if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC|
1534 MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV|
1535 MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR|
1537 (MCI_STATUS_UC|MCI_STATUS_EN|
1538 MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S|
1539 MCI_STATUS_AR|MCACOD_INSTR))
1542 m->mcgstatus |= MCG_STATUS_EIPV;
1547 /* Add per CPU specific workarounds here */
1548 static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1550 struct mca_config *cfg = &mca_cfg;
1552 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1553 pr_info("unknown CPU type - not enabling MCE support\n");
1557 /* This should be disabled by the BIOS, but isn't always */
1558 if (c->x86_vendor == X86_VENDOR_AMD) {
1559 if (c->x86 == 15 && cfg->banks > 4) {
1561 * disable GART TBL walk error reporting, which
1562 * trips off incorrectly with the IOMMU & 3ware
1565 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1567 if (c->x86 <= 17 && cfg->bootlog < 0) {
1569 * Lots of broken BIOS around that don't clear them
1570 * by default and leave crap in there. Don't log:
1575 * Various K7s with broken bank 0 around. Always disable
1578 if (c->x86 == 6 && cfg->banks > 0)
1579 mce_banks[0].ctl = 0;
1582 * Turn off MC4_MISC thresholding banks on those models since
1583 * they're not supported there.
1585 if (c->x86 == 0x15 &&
1586 (c->x86_model >= 0x10 && c->x86_model <= 0x1f)) {
1591 0x00000413, /* MC4_MISC0 */
1592 0xc0000408, /* MC4_MISC1 */
1595 rdmsrl(MSR_K7_HWCR, hwcr);
1597 /* McStatusWrEn has to be set */
1598 need_toggle = !(hwcr & BIT(18));
1601 wrmsrl(MSR_K7_HWCR, hwcr | BIT(18));
1603 for (i = 0; i < ARRAY_SIZE(msrs); i++) {
1604 rdmsrl(msrs[i], val);
1607 if (val & BIT_64(62)) {
1609 wrmsrl(msrs[i], val);
1613 /* restore old settings */
1615 wrmsrl(MSR_K7_HWCR, hwcr);
1619 if (c->x86_vendor == X86_VENDOR_INTEL) {
1621 * SDM documents that on family 6 bank 0 should not be written
1622 * because it aliases to another special BIOS controlled
1624 * But it's not aliased anymore on model 0x1a+
1625 * Don't ignore bank 0 completely because there could be a
1626 * valid event later, merely don't write CTL0.
1629 if (c->x86 == 6 && c->x86_model < 0x1A && cfg->banks > 0)
1630 mce_banks[0].init = 0;
1633 * All newer Intel systems support MCE broadcasting. Enable
1634 * synchronization with a one second timeout.
1636 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1637 cfg->monarch_timeout < 0)
1638 cfg->monarch_timeout = USEC_PER_SEC;
1641 * There are also broken BIOSes on some Pentium M and
1644 if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0)
1647 if (c->x86 == 6 && c->x86_model == 45)
1648 quirk_no_way_out = quirk_sandybridge_ifu;
1650 if (cfg->monarch_timeout < 0)
1651 cfg->monarch_timeout = 0;
1652 if (cfg->bootlog != 0)
1653 cfg->panic_timeout = 30;
1658 static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1663 switch (c->x86_vendor) {
1664 case X86_VENDOR_INTEL:
1665 intel_p5_mcheck_init(c);
1668 case X86_VENDOR_CENTAUR:
1669 winchip_mcheck_init(c);
1677 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1679 switch (c->x86_vendor) {
1680 case X86_VENDOR_INTEL:
1681 mce_intel_feature_init(c);
1682 mce_adjust_timer = mce_intel_adjust_timer;
1684 case X86_VENDOR_AMD:
1685 mce_amd_feature_init(c);
1692 static void mce_start_timer(unsigned int cpu, struct timer_list *t)
1694 unsigned long iv = check_interval * HZ;
1696 if (mca_cfg.ignore_ce || !iv)
1699 per_cpu(mce_next_interval, cpu) = iv;
1701 t->expires = round_jiffies(jiffies + iv);
1702 add_timer_on(t, cpu);
1705 static void __mcheck_cpu_init_timer(void)
1707 struct timer_list *t = this_cpu_ptr(&mce_timer);
1708 unsigned int cpu = smp_processor_id();
1710 setup_timer(t, mce_timer_fn, cpu);
1711 mce_start_timer(cpu, t);
1714 /* Handle unconfigured int18 (should never happen) */
1715 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1717 pr_err("CPU#%d: Unexpected int18 (Machine Check)\n",
1718 smp_processor_id());
1721 /* Call the installed machine check handler for this CPU setup. */
1722 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1723 unexpected_machine_check;
1726 * Called for each booted CPU to set up machine checks.
1727 * Must be called with preempt off:
1729 void mcheck_cpu_init(struct cpuinfo_x86 *c)
1731 if (mca_cfg.disabled)
1734 if (__mcheck_cpu_ancient_init(c))
1737 if (!mce_available(c))
1740 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
1741 mca_cfg.disabled = true;
1745 machine_check_vector = do_machine_check;
1747 __mcheck_cpu_init_generic();
1748 __mcheck_cpu_init_vendor(c);
1749 __mcheck_cpu_init_timer();
1750 INIT_WORK(this_cpu_ptr(&mce_work), mce_process_work);
1751 init_irq_work(this_cpu_ptr(&mce_irq_work), &mce_irq_work_cb);
1755 * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log.
1758 static DEFINE_SPINLOCK(mce_chrdev_state_lock);
1759 static int mce_chrdev_open_count; /* #times opened */
1760 static int mce_chrdev_open_exclu; /* already open exclusive? */
1762 static int mce_chrdev_open(struct inode *inode, struct file *file)
1764 spin_lock(&mce_chrdev_state_lock);
1766 if (mce_chrdev_open_exclu ||
1767 (mce_chrdev_open_count && (file->f_flags & O_EXCL))) {
1768 spin_unlock(&mce_chrdev_state_lock);
1773 if (file->f_flags & O_EXCL)
1774 mce_chrdev_open_exclu = 1;
1775 mce_chrdev_open_count++;
1777 spin_unlock(&mce_chrdev_state_lock);
1779 return nonseekable_open(inode, file);
1782 static int mce_chrdev_release(struct inode *inode, struct file *file)
1784 spin_lock(&mce_chrdev_state_lock);
1786 mce_chrdev_open_count--;
1787 mce_chrdev_open_exclu = 0;
1789 spin_unlock(&mce_chrdev_state_lock);
1794 static void collect_tscs(void *data)
1796 unsigned long *cpu_tsc = (unsigned long *)data;
1798 rdtscll(cpu_tsc[smp_processor_id()]);
1801 static int mce_apei_read_done;
1803 /* Collect MCE record of previous boot in persistent storage via APEI ERST. */
1804 static int __mce_read_apei(char __user **ubuf, size_t usize)
1810 if (usize < sizeof(struct mce))
1813 rc = apei_read_mce(&m, &record_id);
1814 /* Error or no more MCE record */
1816 mce_apei_read_done = 1;
1818 * When ERST is disabled, mce_chrdev_read() should return
1819 * "no record" instead of "no device."
1826 if (copy_to_user(*ubuf, &m, sizeof(struct mce)))
1829 * In fact, we should have cleared the record after that has
1830 * been flushed to the disk or sent to network in
1831 * /sbin/mcelog, but we have no interface to support that now,
1832 * so just clear it to avoid duplication.
1834 rc = apei_clear_mce(record_id);
1836 mce_apei_read_done = 1;
1839 *ubuf += sizeof(struct mce);
1844 static ssize_t mce_chrdev_read(struct file *filp, char __user *ubuf,
1845 size_t usize, loff_t *off)
1847 char __user *buf = ubuf;
1848 unsigned long *cpu_tsc;
1849 unsigned prev, next;
1852 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
1856 mutex_lock(&mce_chrdev_read_mutex);
1858 if (!mce_apei_read_done) {
1859 err = __mce_read_apei(&buf, usize);
1860 if (err || buf != ubuf)
1864 next = rcu_dereference_check_mce(mcelog.next);
1866 /* Only supports full reads right now */
1868 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce))
1874 for (i = prev; i < next; i++) {
1875 unsigned long start = jiffies;
1876 struct mce *m = &mcelog.entry[i];
1878 while (!m->finished) {
1879 if (time_after_eq(jiffies, start + 2)) {
1880 memset(m, 0, sizeof(*m));
1886 err |= copy_to_user(buf, m, sizeof(*m));
1892 memset(mcelog.entry + prev, 0,
1893 (next - prev) * sizeof(struct mce));
1895 next = cmpxchg(&mcelog.next, prev, 0);
1896 } while (next != prev);
1898 synchronize_sched();
1901 * Collect entries that were still getting written before the
1904 on_each_cpu(collect_tscs, cpu_tsc, 1);
1906 for (i = next; i < MCE_LOG_LEN; i++) {
1907 struct mce *m = &mcelog.entry[i];
1909 if (m->finished && m->tsc < cpu_tsc[m->cpu]) {
1910 err |= copy_to_user(buf, m, sizeof(*m));
1913 memset(m, 0, sizeof(*m));
1921 mutex_unlock(&mce_chrdev_read_mutex);
1924 return err ? err : buf - ubuf;
1927 static unsigned int mce_chrdev_poll(struct file *file, poll_table *wait)
1929 poll_wait(file, &mce_chrdev_wait, wait);
1930 if (rcu_access_index(mcelog.next))
1931 return POLLIN | POLLRDNORM;
1932 if (!mce_apei_read_done && apei_check_mce())
1933 return POLLIN | POLLRDNORM;
1937 static long mce_chrdev_ioctl(struct file *f, unsigned int cmd,
1940 int __user *p = (int __user *)arg;
1942 if (!capable(CAP_SYS_ADMIN))
1946 case MCE_GET_RECORD_LEN:
1947 return put_user(sizeof(struct mce), p);
1948 case MCE_GET_LOG_LEN:
1949 return put_user(MCE_LOG_LEN, p);
1950 case MCE_GETCLEAR_FLAGS: {
1954 flags = mcelog.flags;
1955 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
1957 return put_user(flags, p);
1964 static ssize_t (*mce_write)(struct file *filp, const char __user *ubuf,
1965 size_t usize, loff_t *off);
1967 void register_mce_write_callback(ssize_t (*fn)(struct file *filp,
1968 const char __user *ubuf,
1969 size_t usize, loff_t *off))
1973 EXPORT_SYMBOL_GPL(register_mce_write_callback);
1975 ssize_t mce_chrdev_write(struct file *filp, const char __user *ubuf,
1976 size_t usize, loff_t *off)
1979 return mce_write(filp, ubuf, usize, off);
1984 static const struct file_operations mce_chrdev_ops = {
1985 .open = mce_chrdev_open,
1986 .release = mce_chrdev_release,
1987 .read = mce_chrdev_read,
1988 .write = mce_chrdev_write,
1989 .poll = mce_chrdev_poll,
1990 .unlocked_ioctl = mce_chrdev_ioctl,
1991 .llseek = no_llseek,
1994 static struct miscdevice mce_chrdev_device = {
2000 static void __mce_disable_bank(void *arg)
2002 int bank = *((int *)arg);
2003 __clear_bit(bank, this_cpu_ptr(mce_poll_banks));
2004 cmci_disable_bank(bank);
2007 void mce_disable_bank(int bank)
2009 if (bank >= mca_cfg.banks) {
2011 "Ignoring request to disable invalid MCA bank %d.\n",
2015 set_bit(bank, mce_banks_ce_disabled);
2016 on_each_cpu(__mce_disable_bank, &bank, 1);
2020 * mce=off Disables machine check
2021 * mce=no_cmci Disables CMCI
2022 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
2023 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
2024 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
2025 * monarchtimeout is how long to wait for other CPUs on machine
2026 * check, or 0 to not wait
2027 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
2028 * mce=nobootlog Don't log MCEs from before booting.
2029 * mce=bios_cmci_threshold Don't program the CMCI threshold
2031 static int __init mcheck_enable(char *str)
2033 struct mca_config *cfg = &mca_cfg;
2041 if (!strcmp(str, "off"))
2042 cfg->disabled = true;
2043 else if (!strcmp(str, "no_cmci"))
2044 cfg->cmci_disabled = true;
2045 else if (!strcmp(str, "dont_log_ce"))
2046 cfg->dont_log_ce = true;
2047 else if (!strcmp(str, "ignore_ce"))
2048 cfg->ignore_ce = true;
2049 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
2050 cfg->bootlog = (str[0] == 'b');
2051 else if (!strcmp(str, "bios_cmci_threshold"))
2052 cfg->bios_cmci_threshold = true;
2053 else if (isdigit(str[0])) {
2054 get_option(&str, &(cfg->tolerant));
2057 get_option(&str, &(cfg->monarch_timeout));
2060 pr_info("mce argument %s ignored. Please use /sys\n", str);
2065 __setup("mce", mcheck_enable);
2067 int __init mcheck_init(void)
2069 mcheck_intel_therm_init();
2075 * mce_syscore: PM support
2079 * Disable machine checks on suspend and shutdown. We can't really handle
2082 static int mce_disable_error_reporting(void)
2086 for (i = 0; i < mca_cfg.banks; i++) {
2087 struct mce_bank *b = &mce_banks[i];
2090 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
2095 static int mce_syscore_suspend(void)
2097 return mce_disable_error_reporting();
2100 static void mce_syscore_shutdown(void)
2102 mce_disable_error_reporting();
2106 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
2107 * Only one CPU is active at this time, the others get re-added later using
2110 static void mce_syscore_resume(void)
2112 __mcheck_cpu_init_generic();
2113 __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info));
2116 static struct syscore_ops mce_syscore_ops = {
2117 .suspend = mce_syscore_suspend,
2118 .shutdown = mce_syscore_shutdown,
2119 .resume = mce_syscore_resume,
2123 * mce_device: Sysfs support
2126 static void mce_cpu_restart(void *data)
2128 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2130 __mcheck_cpu_init_generic();
2131 __mcheck_cpu_init_timer();
2134 /* Reinit MCEs after user configuration changes */
2135 static void mce_restart(void)
2137 mce_timer_delete_all();
2138 on_each_cpu(mce_cpu_restart, NULL, 1);
2141 /* Toggle features for corrected errors */
2142 static void mce_disable_cmci(void *data)
2144 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2149 static void mce_enable_ce(void *all)
2151 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2156 __mcheck_cpu_init_timer();
2159 static struct bus_type mce_subsys = {
2160 .name = "machinecheck",
2161 .dev_name = "machinecheck",
2164 DEFINE_PER_CPU(struct device *, mce_device);
2166 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
2168 static inline struct mce_bank *attr_to_bank(struct device_attribute *attr)
2170 return container_of(attr, struct mce_bank, attr);
2173 static ssize_t show_bank(struct device *s, struct device_attribute *attr,
2176 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
2179 static ssize_t set_bank(struct device *s, struct device_attribute *attr,
2180 const char *buf, size_t size)
2184 if (kstrtou64(buf, 0, &new) < 0)
2187 attr_to_bank(attr)->ctl = new;
2194 show_trigger(struct device *s, struct device_attribute *attr, char *buf)
2196 strcpy(buf, mce_helper);
2198 return strlen(mce_helper) + 1;
2201 static ssize_t set_trigger(struct device *s, struct device_attribute *attr,
2202 const char *buf, size_t siz)
2206 strncpy(mce_helper, buf, sizeof(mce_helper));
2207 mce_helper[sizeof(mce_helper)-1] = 0;
2208 p = strchr(mce_helper, '\n');
2213 return strlen(mce_helper) + !!p;
2216 static ssize_t set_ignore_ce(struct device *s,
2217 struct device_attribute *attr,
2218 const char *buf, size_t size)
2222 if (kstrtou64(buf, 0, &new) < 0)
2225 if (mca_cfg.ignore_ce ^ !!new) {
2227 /* disable ce features */
2228 mce_timer_delete_all();
2229 on_each_cpu(mce_disable_cmci, NULL, 1);
2230 mca_cfg.ignore_ce = true;
2232 /* enable ce features */
2233 mca_cfg.ignore_ce = false;
2234 on_each_cpu(mce_enable_ce, (void *)1, 1);
2240 static ssize_t set_cmci_disabled(struct device *s,
2241 struct device_attribute *attr,
2242 const char *buf, size_t size)
2246 if (kstrtou64(buf, 0, &new) < 0)
2249 if (mca_cfg.cmci_disabled ^ !!new) {
2252 on_each_cpu(mce_disable_cmci, NULL, 1);
2253 mca_cfg.cmci_disabled = true;
2256 mca_cfg.cmci_disabled = false;
2257 on_each_cpu(mce_enable_ce, NULL, 1);
2263 static ssize_t store_int_with_restart(struct device *s,
2264 struct device_attribute *attr,
2265 const char *buf, size_t size)
2267 ssize_t ret = device_store_int(s, attr, buf, size);
2272 static DEVICE_ATTR(trigger, 0644, show_trigger, set_trigger);
2273 static DEVICE_INT_ATTR(tolerant, 0644, mca_cfg.tolerant);
2274 static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout);
2275 static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce);
2277 static struct dev_ext_attribute dev_attr_check_interval = {
2278 __ATTR(check_interval, 0644, device_show_int, store_int_with_restart),
2282 static struct dev_ext_attribute dev_attr_ignore_ce = {
2283 __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce),
2287 static struct dev_ext_attribute dev_attr_cmci_disabled = {
2288 __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled),
2289 &mca_cfg.cmci_disabled
2292 static struct device_attribute *mce_device_attrs[] = {
2293 &dev_attr_tolerant.attr,
2294 &dev_attr_check_interval.attr,
2296 &dev_attr_monarch_timeout.attr,
2297 &dev_attr_dont_log_ce.attr,
2298 &dev_attr_ignore_ce.attr,
2299 &dev_attr_cmci_disabled.attr,
2303 static cpumask_var_t mce_device_initialized;
2305 static void mce_device_release(struct device *dev)
2310 /* Per cpu device init. All of the cpus still share the same ctrl bank: */
2311 static int mce_device_create(unsigned int cpu)
2317 if (!mce_available(&boot_cpu_data))
2320 dev = kzalloc(sizeof *dev, GFP_KERNEL);
2324 dev->bus = &mce_subsys;
2325 dev->release = &mce_device_release;
2327 err = device_register(dev);
2333 for (i = 0; mce_device_attrs[i]; i++) {
2334 err = device_create_file(dev, mce_device_attrs[i]);
2338 for (j = 0; j < mca_cfg.banks; j++) {
2339 err = device_create_file(dev, &mce_banks[j].attr);
2343 cpumask_set_cpu(cpu, mce_device_initialized);
2344 per_cpu(mce_device, cpu) = dev;
2349 device_remove_file(dev, &mce_banks[j].attr);
2352 device_remove_file(dev, mce_device_attrs[i]);
2354 device_unregister(dev);
2359 static void mce_device_remove(unsigned int cpu)
2361 struct device *dev = per_cpu(mce_device, cpu);
2364 if (!cpumask_test_cpu(cpu, mce_device_initialized))
2367 for (i = 0; mce_device_attrs[i]; i++)
2368 device_remove_file(dev, mce_device_attrs[i]);
2370 for (i = 0; i < mca_cfg.banks; i++)
2371 device_remove_file(dev, &mce_banks[i].attr);
2373 device_unregister(dev);
2374 cpumask_clear_cpu(cpu, mce_device_initialized);
2375 per_cpu(mce_device, cpu) = NULL;
2378 /* Make sure there are no machine checks on offlined CPUs. */
2379 static void mce_disable_cpu(void *h)
2381 unsigned long action = *(unsigned long *)h;
2384 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2387 if (!(action & CPU_TASKS_FROZEN))
2389 for (i = 0; i < mca_cfg.banks; i++) {
2390 struct mce_bank *b = &mce_banks[i];
2393 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
2397 static void mce_reenable_cpu(void *h)
2399 unsigned long action = *(unsigned long *)h;
2402 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2405 if (!(action & CPU_TASKS_FROZEN))
2407 for (i = 0; i < mca_cfg.banks; i++) {
2408 struct mce_bank *b = &mce_banks[i];
2411 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
2415 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
2417 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
2419 unsigned int cpu = (unsigned long)hcpu;
2420 struct timer_list *t = &per_cpu(mce_timer, cpu);
2422 switch (action & ~CPU_TASKS_FROZEN) {
2424 mce_device_create(cpu);
2425 if (threshold_cpu_callback)
2426 threshold_cpu_callback(action, cpu);
2429 if (threshold_cpu_callback)
2430 threshold_cpu_callback(action, cpu);
2431 mce_device_remove(cpu);
2432 mce_intel_hcpu_update(cpu);
2434 /* intentionally ignoring frozen here */
2435 if (!(action & CPU_TASKS_FROZEN))
2438 case CPU_DOWN_PREPARE:
2439 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
2442 case CPU_DOWN_FAILED:
2443 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
2444 mce_start_timer(cpu, t);
2451 static struct notifier_block mce_cpu_notifier = {
2452 .notifier_call = mce_cpu_callback,
2455 static __init void mce_init_banks(void)
2459 for (i = 0; i < mca_cfg.banks; i++) {
2460 struct mce_bank *b = &mce_banks[i];
2461 struct device_attribute *a = &b->attr;
2463 sysfs_attr_init(&a->attr);
2464 a->attr.name = b->attrname;
2465 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2467 a->attr.mode = 0644;
2468 a->show = show_bank;
2469 a->store = set_bank;
2473 static __init int mcheck_init_device(void)
2478 if (!mce_available(&boot_cpu_data)) {
2483 if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) {
2490 err = subsys_system_register(&mce_subsys, NULL);
2494 cpu_notifier_register_begin();
2495 for_each_online_cpu(i) {
2496 err = mce_device_create(i);
2499 * Register notifier anyway (and do not unreg it) so
2500 * that we don't leave undeleted timers, see notifier
2503 __register_hotcpu_notifier(&mce_cpu_notifier);
2504 cpu_notifier_register_done();
2505 goto err_device_create;
2509 __register_hotcpu_notifier(&mce_cpu_notifier);
2510 cpu_notifier_register_done();
2512 register_syscore_ops(&mce_syscore_ops);
2514 /* register character device /dev/mcelog */
2515 err = misc_register(&mce_chrdev_device);
2522 unregister_syscore_ops(&mce_syscore_ops);
2526 * We didn't keep track of which devices were created above, but
2527 * even if we had, the set of online cpus might have changed.
2528 * Play safe and remove for every possible cpu, since
2529 * mce_device_remove() will do the right thing.
2531 for_each_possible_cpu(i)
2532 mce_device_remove(i);
2535 free_cpumask_var(mce_device_initialized);
2538 pr_err("Unable to init device /dev/mcelog (rc: %d)\n", err);
2542 device_initcall_sync(mcheck_init_device);
2545 * Old style boot options parsing. Only for compatibility.
2547 static int __init mcheck_disable(char *str)
2549 mca_cfg.disabled = true;
2552 __setup("nomce", mcheck_disable);
2554 #ifdef CONFIG_DEBUG_FS
2555 struct dentry *mce_get_debugfs_dir(void)
2557 static struct dentry *dmce;
2560 dmce = debugfs_create_dir("mce", NULL);
2565 static void mce_reset(void)
2568 atomic_set(&mce_fake_panicked, 0);
2569 atomic_set(&mce_executing, 0);
2570 atomic_set(&mce_callin, 0);
2571 atomic_set(&global_nwo, 0);
2574 static int fake_panic_get(void *data, u64 *val)
2580 static int fake_panic_set(void *data, u64 val)
2587 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2588 fake_panic_set, "%llu\n");
2590 static int __init mcheck_debugfs_init(void)
2592 struct dentry *dmce, *ffake_panic;
2594 dmce = mce_get_debugfs_dir();
2597 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2604 late_initcall(mcheck_debugfs_init);