arch/x86/kernel/cpu/perf_event.c

   1 /*
   2  * Performance events x86 architecture code
   3  *
   4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   6  *  Copyright (C) 2009 Jaswinder Singh Rajput
   7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
   9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
  11  *
  12  *  For licencing details see kernel-base/COPYING
  13  */
  14
  15 #include <linux/perf_event.h>
  16 #include <linux/capability.h>
  17 #include <linux/notifier.h>
  18 #include <linux/hardirq.h>
  19 #include <linux/kprobes.h>
  20 #include <linux/module.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/sched.h>
  23 #include <linux/uaccess.h>
  24 #include <linux/slab.h>
  25 #include <linux/cpu.h>
  26 #include <linux/bitops.h>
  27 #include <linux/device.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/stacktrace.h>
  31 #include <asm/nmi.h>
  32 #include <asm/smp.h>
  33 #include <asm/alternative.h>
  34 #include <asm/mmu_context.h>
  35 #include <asm/tlbflush.h>
  36 #include <asm/timer.h>
  37 #include <asm/desc.h>
  38 #include <asm/ldt.h>
  39
  40 #include "perf_event.h"
  41
  42 struct x86_pmu x86_pmu __read_mostly;
  43
  44 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
  45         .enabled = 1,
  46 };
  47
  48 struct static_key rdpmc_always_available = STATIC_KEY_INIT_FALSE;
  49
  50 u64 __read_mostly hw_cache_event_ids
  51                                 [PERF_COUNT_HW_CACHE_MAX]
  52                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  53                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
  54 u64 __read_mostly hw_cache_extra_regs
  55                                 [PERF_COUNT_HW_CACHE_MAX]
  56                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  57                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
  58
  59 /*
  60  * Propagate event elapsed time into the generic event.
  61  * Can only be executed on the CPU where the event is active.
  62  * Returns the delta events processed.
  63  */
  64 u64 x86_perf_event_update(struct perf_event *event)
  65 {
  66         struct hw_perf_event *hwc = &event->hw;
  67         int shift = 64 - x86_pmu.cntval_bits;
  68         u64 prev_raw_count, new_raw_count;
  69         int idx = hwc->idx;
  70         s64 delta;
  71
  72         if (idx == INTEL_PMC_IDX_FIXED_BTS)
  73                 return 0;
  74
  75         /*
  76          * Careful: an NMI might modify the previous event value.
  77          *
  78          * Our tactic to handle this is to first atomically read and
  79          * exchange a new raw count - then add that new-prev delta
  80          * count to the generic event atomically:
  81          */
  82 again:
  83         prev_raw_count = local64_read(&hwc->prev_count);
  84         rdpmcl(hwc->event_base_rdpmc, new_raw_count);
  85
  86         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
  87                                         new_raw_count) != prev_raw_count)
  88                 goto again;
  89
  90         /*
  91          * Now we have the new raw value and have updated the prev
  92          * timestamp already. We can now calculate the elapsed delta
  93          * (event-)time and add that to the generic event.
  94          *
  95          * Careful, not all hw sign-extends above the physical width
  96          * of the count.
  97          */
  98         delta = (new_raw_count << shift) - (prev_raw_count << shift);
  99         delta >>= shift;
 100
 101         local64_add(delta, &event->count);
 102         local64_sub(delta, &hwc->period_left);
 103
 104         return new_raw_count;
 105 }
 106
 107 /*
 108  * Find and validate any extra registers to set up.
 109  */
 110 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
 111 {
 112         struct hw_perf_event_extra *reg;
 113         struct extra_reg *er;
 114
 115         reg = &event->hw.extra_reg;
 116
 117         if (!x86_pmu.extra_regs)
 118                 return 0;
 119
 120         for (er = x86_pmu.extra_regs; er->msr; er++) {
 121                 if (er->event != (config & er->config_mask))
 122                         continue;
 123                 if (event->attr.config1 & ~er->valid_mask)
 124                         return -EINVAL;
 125                 /* Check if the extra msrs can be safely accessed*/
 126                 if (!er->extra_msr_access)
 127                         return -ENXIO;
 128
 129                 reg->idx = er->idx;
 130                 reg->config = event->attr.config1;
 131                 reg->reg = er->msr;
 132                 break;
 133         }
 134         return 0;
 135 }
 136
 137 static atomic_t active_events;
 138 static atomic_t pmc_refcount;
 139 static DEFINE_MUTEX(pmc_reserve_mutex);
 140
 141 #ifdef CONFIG_X86_LOCAL_APIC
 142
 143 static bool reserve_pmc_hardware(void)
 144 {
 145         int i;
 146
 147         for (i = 0; i < x86_pmu.num_counters; i++) {
 148                 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
 149                         goto perfctr_fail;
 150         }
 151
 152         for (i = 0; i < x86_pmu.num_counters; i++) {
 153                 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
 154                         goto eventsel_fail;
 155         }
 156
 157         return true;
 158
 159 eventsel_fail:
 160         for (i--; i >= 0; i--)
 161                 release_evntsel_nmi(x86_pmu_config_addr(i));
 162
 163         i = x86_pmu.num_counters;
 164
 165 perfctr_fail:
 166         for (i--; i >= 0; i--)
 167                 release_perfctr_nmi(x86_pmu_event_addr(i));
 168
 169         return false;
 170 }
 171
 172 static void release_pmc_hardware(void)
 173 {
 174         int i;
 175
 176         for (i = 0; i < x86_pmu.num_counters; i++) {
 177                 release_perfctr_nmi(x86_pmu_event_addr(i));
 178                 release_evntsel_nmi(x86_pmu_config_addr(i));
 179         }
 180 }
 181
 182 #else
 183
 184 static bool reserve_pmc_hardware(void) { return true; }
 185 static void release_pmc_hardware(void) {}
 186
 187 #endif
 188
 189 static bool check_hw_exists(void)
 190 {
 191         u64 val, val_fail, val_new= ~0;
 192         int i, reg, reg_fail, ret = 0;
 193         int bios_fail = 0;
 194         int reg_safe = -1;
 195
 196         /*
 197          * Check to see if the BIOS enabled any of the counters, if so
 198          * complain and bail.
 199          */
 200         for (i = 0; i < x86_pmu.num_counters; i++) {
 201                 reg = x86_pmu_config_addr(i);
 202                 ret = rdmsrl_safe(reg, &val);
 203                 if (ret)
 204                         goto msr_fail;
 205                 if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
 206                         bios_fail = 1;
 207                         val_fail = val;
 208                         reg_fail = reg;
 209                 } else {
 210                         reg_safe = i;
 211                 }
 212         }
 213
 214         if (x86_pmu.num_counters_fixed) {
 215                 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 216                 ret = rdmsrl_safe(reg, &val);
 217                 if (ret)
 218                         goto msr_fail;
 219                 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
 220                         if (val & (0x03 << i*4)) {
 221                                 bios_fail = 1;
 222                                 val_fail = val;
 223                                 reg_fail = reg;
 224                         }
 225                 }
 226         }
 227
 228         /*
 229          * If all the counters are enabled, the below test will always
 230          * fail.  The tools will also become useless in this scenario.
 231          * Just fail and disable the hardware counters.
 232          */
 233
 234         if (reg_safe == -1) {
 235                 reg = reg_safe;
 236                 goto msr_fail;
 237         }
 238
 239         /*
 240          * Read the current value, change it and read it back to see if it
 241          * matches, this is needed to detect certain hardware emulators
 242          * (qemu/kvm) that don't trap on the MSR access and always return 0s.
 243          */
 244         reg = x86_pmu_event_addr(reg_safe);
 245         if (rdmsrl_safe(reg, &val))
 246                 goto msr_fail;
 247         val ^= 0xffffUL;
 248         ret = wrmsrl_safe(reg, val);
 249         ret |= rdmsrl_safe(reg, &val_new);
 250         if (ret || val != val_new)
 251                 goto msr_fail;
 252
 253         /*
 254          * We still allow the PMU driver to operate:
 255          */
 256         if (bios_fail) {
 257                 printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n");
 258                 printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg_fail, val_fail);
 259         }
 260
 261         return true;
 262
 263 msr_fail:
 264         printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n");
 265         printk("%sFailed to access perfctr msr (MSR %x is %Lx)\n",
 266                 boot_cpu_has(X86_FEATURE_HYPERVISOR) ? KERN_INFO : KERN_ERR,
 267                 reg, val_new);
 268
 269         return false;
 270 }
 271
 272 static void hw_perf_event_destroy(struct perf_event *event)
 273 {
 274         x86_release_hardware();
 275         atomic_dec(&active_events);
 276 }
 277
 278 void hw_perf_lbr_event_destroy(struct perf_event *event)
 279 {
 280         hw_perf_event_destroy(event);
 281
 282         /* undo the lbr/bts event accounting */
 283         x86_del_exclusive(x86_lbr_exclusive_lbr);
 284 }
 285
 286 static inline int x86_pmu_initialized(void)
 287 {
 288         return x86_pmu.handle_irq != NULL;
 289 }
 290
 291 static inline int
 292 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
 293 {
 294         struct perf_event_attr *attr = &event->attr;
 295         unsigned int cache_type, cache_op, cache_result;
 296         u64 config, val;
 297
 298         config = attr->config;
 299
 300         cache_type = (config >>  0) & 0xff;
 301         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 302                 return -EINVAL;
 303
 304         cache_op = (config >>  8) & 0xff;
 305         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 306                 return -EINVAL;
 307
 308         cache_result = (config >> 16) & 0xff;
 309         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 310                 return -EINVAL;
 311
 312         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
 313
 314         if (val == 0)
 315                 return -ENOENT;
 316
 317         if (val == -1)
 318                 return -EINVAL;
 319
 320         hwc->config |= val;
 321         attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
 322         return x86_pmu_extra_regs(val, event);
 323 }
 324
 325 int x86_reserve_hardware(void)
 326 {
 327         int err = 0;
 328
 329         if (!atomic_inc_not_zero(&pmc_refcount)) {
 330                 mutex_lock(&pmc_reserve_mutex);
 331                 if (atomic_read(&pmc_refcount) == 0) {
 332                         if (!reserve_pmc_hardware())
 333                                 err = -EBUSY;
 334                         else
 335                                 reserve_ds_buffers();
 336                 }
 337                 if (!err)
 338                         atomic_inc(&pmc_refcount);
 339                 mutex_unlock(&pmc_reserve_mutex);
 340         }
 341
 342         return err;
 343 }
 344
 345 void x86_release_hardware(void)
 346 {
 347         if (atomic_dec_and_mutex_lock(&pmc_refcount, &pmc_reserve_mutex)) {
 348                 release_pmc_hardware();
 349                 release_ds_buffers();
 350                 mutex_unlock(&pmc_reserve_mutex);
 351         }
 352 }
 353
 354 /*
 355  * Check if we can create event of a certain type (that no conflicting events
 356  * are present).
 357  */
 358 int x86_add_exclusive(unsigned int what)
 359 {
 360         int i;
 361
 362         if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {
 363                 mutex_lock(&pmc_reserve_mutex);
 364                 for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) {
 365                         if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i]))
 366                                 goto fail_unlock;
 367                 }
 368                 atomic_inc(&x86_pmu.lbr_exclusive[what]);
 369                 mutex_unlock(&pmc_reserve_mutex);
 370         }
 371
 372         atomic_inc(&active_events);
 373         return 0;
 374
 375 fail_unlock:
 376         mutex_unlock(&pmc_reserve_mutex);
 377         return -EBUSY;
 378 }
 379
 380 void x86_del_exclusive(unsigned int what)
 381 {
 382         atomic_dec(&x86_pmu.lbr_exclusive[what]);
 383         atomic_dec(&active_events);
 384 }
 385
 386 int x86_setup_perfctr(struct perf_event *event)
 387 {
 388         struct perf_event_attr *attr = &event->attr;
 389         struct hw_perf_event *hwc = &event->hw;
 390         u64 config;
 391
 392         if (!is_sampling_event(event)) {
 393                 hwc->sample_period = x86_pmu.max_period;
 394                 hwc->last_period = hwc->sample_period;
 395                 local64_set(&hwc->period_left, hwc->sample_period);
 396         }
 397
 398         if (attr->type == PERF_TYPE_RAW)
 399                 return x86_pmu_extra_regs(event->attr.config, event);
 400
 401         if (attr->type == PERF_TYPE_HW_CACHE)
 402                 return set_ext_hw_attr(hwc, event);
 403
 404         if (attr->config >= x86_pmu.max_events)
 405                 return -EINVAL;
 406
 407         /*
 408          * The generic map:
 409          */
 410         config = x86_pmu.event_map(attr->config);
 411
 412         if (config == 0)
 413                 return -ENOENT;
 414
 415         if (config == -1LL)
 416                 return -EINVAL;
 417
 418         /*
 419          * Branch tracing:
 420          */
 421         if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&
 422             !attr->freq && hwc->sample_period == 1) {
 423                 /* BTS is not supported by this architecture. */
 424                 if (!x86_pmu.bts_active)
 425                         return -EOPNOTSUPP;
 426
 427                 /* BTS is currently only allowed for user-mode. */
 428                 if (!attr->exclude_kernel)
 429                         return -EOPNOTSUPP;
 430
 431                 /* disallow bts if conflicting events are present */
 432                 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
 433                         return -EBUSY;
 434
 435                 event->destroy = hw_perf_lbr_event_destroy;
 436         }
 437
 438         hwc->config |= config;
 439
 440         return 0;
 441 }
 442
 443 /*
 444  * check that branch_sample_type is compatible with
 445  * settings needed for precise_ip > 1 which implies
 446  * using the LBR to capture ALL taken branches at the
 447  * priv levels of the measurement
 448  */
 449 static inline int precise_br_compat(struct perf_event *event)
 450 {
 451         u64 m = event->attr.branch_sample_type;
 452         u64 b = 0;
 453
 454         /* must capture all branches */
 455         if (!(m & PERF_SAMPLE_BRANCH_ANY))
 456                 return 0;
 457
 458         m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;
 459
 460         if (!event->attr.exclude_user)
 461                 b |= PERF_SAMPLE_BRANCH_USER;
 462
 463         if (!event->attr.exclude_kernel)
 464                 b |= PERF_SAMPLE_BRANCH_KERNEL;
 465
 466         /*
 467          * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
 468          */
 469
 470         return m == b;
 471 }
 472
 473 int x86_pmu_hw_config(struct perf_event *event)
 474 {
 475         if (event->attr.precise_ip) {
 476                 int precise = 0;
 477
 478                 /* Support for constant skid */
 479                 if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
 480                         precise++;
 481
 482                         /* Support for IP fixup */
 483                         if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2)
 484                                 precise++;
 485
 486                         if (x86_pmu.pebs_prec_dist)
 487                                 precise++;
 488                 }
 489
 490                 if (event->attr.precise_ip > precise)
 491                         return -EOPNOTSUPP;
 492         }
 493         /*
 494          * check that PEBS LBR correction does not conflict with
 495          * whatever the user is asking with attr->branch_sample_type
 496          */
 497         if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) {
 498                 u64 *br_type = &event->attr.branch_sample_type;
 499
 500                 if (has_branch_stack(event)) {
 501                         if (!precise_br_compat(event))
 502                                 return -EOPNOTSUPP;
 503
 504                         /* branch_sample_type is compatible */
 505
 506                 } else {
 507                         /*
 508                          * user did not specify  branch_sample_type
 509                          *
 510                          * For PEBS fixups, we capture all
 511                          * the branches at the priv level of the
 512                          * event.
 513                          */
 514                         *br_type = PERF_SAMPLE_BRANCH_ANY;
 515
 516                         if (!event->attr.exclude_user)
 517                                 *br_type |= PERF_SAMPLE_BRANCH_USER;
 518
 519                         if (!event->attr.exclude_kernel)
 520                                 *br_type |= PERF_SAMPLE_BRANCH_KERNEL;
 521                 }
 522         }
 523
 524         if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK)
 525                 event->attach_state |= PERF_ATTACH_TASK_DATA;
 526
 527         /*
 528          * Generate PMC IRQs:
 529          * (keep 'enabled' bit clear for now)
 530          */
 531         event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
 532
 533         /*
 534          * Count user and OS events unless requested not to
 535          */
 536         if (!event->attr.exclude_user)
 537                 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
 538         if (!event->attr.exclude_kernel)
 539                 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
 540
 541         if (event->attr.type == PERF_TYPE_RAW)
 542                 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
 543
 544         if (event->attr.sample_period && x86_pmu.limit_period) {
 545                 if (x86_pmu.limit_period(event, event->attr.sample_period) >
 546                                 event->attr.sample_period)
 547                         return -EINVAL;
 548         }
 549
 550         return x86_setup_perfctr(event);
 551 }
 552
 553 /*
 554  * Setup the hardware configuration for a given attr_type
 555  */
 556 static int __x86_pmu_event_init(struct perf_event *event)
 557 {
 558         int err;
 559
 560         if (!x86_pmu_initialized())
 561                 return -ENODEV;
 562
 563         err = x86_reserve_hardware();
 564         if (err)
 565                 return err;
 566
 567         atomic_inc(&active_events);
 568         event->destroy = hw_perf_event_destroy;
 569
 570         event->hw.idx = -1;
 571         event->hw.last_cpu = -1;
 572         event->hw.last_tag = ~0ULL;
 573
 574         /* mark unused */
 575         event->hw.extra_reg.idx = EXTRA_REG_NONE;
 576         event->hw.branch_reg.idx = EXTRA_REG_NONE;
 577
 578         return x86_pmu.hw_config(event);
 579 }
 580
 581 void x86_pmu_disable_all(void)
 582 {
 583         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 584         int idx;
 585
 586         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 587                 u64 val;
 588
 589                 if (!test_bit(idx, cpuc->active_mask))
 590                         continue;
 591                 rdmsrl(x86_pmu_config_addr(idx), val);
 592                 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
 593                         continue;
 594                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
 595                 wrmsrl(x86_pmu_config_addr(idx), val);
 596         }
 597 }
 598
 599 static void x86_pmu_disable(struct pmu *pmu)
 600 {
 601         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 602
 603         if (!x86_pmu_initialized())
 604                 return;
 605
 606         if (!cpuc->enabled)
 607                 return;
 608
 609         cpuc->n_added = 0;
 610         cpuc->enabled = 0;
 611         barrier();
 612
 613         x86_pmu.disable_all();
 614 }
 615
 616 void x86_pmu_enable_all(int added)
 617 {
 618         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 619         int idx;
 620
 621         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 622                 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
 623
 624                 if (!test_bit(idx, cpuc->active_mask))
 625                         continue;
 626
 627                 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
 628         }
 629 }
 630
 631 static struct pmu pmu;
 632
 633 static inline int is_x86_event(struct perf_event *event)
 634 {
 635         return event->pmu == &pmu;
 636 }
 637
 638 /*
 639  * Event scheduler state:
 640  *
 641  * Assign events iterating over all events and counters, beginning
 642  * with events with least weights first. Keep the current iterator
 643  * state in struct sched_state.
 644  */
 645 struct sched_state {
 646         int     weight;
 647         int     event;          /* event index */
 648         int     counter;        /* counter index */
 649         int     unassigned;     /* number of events to be assigned left */
 650         int     nr_gp;          /* number of GP counters used */
 651         unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 652 };
 653
 654 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
 655 #define SCHED_STATES_MAX        2
 656
 657 struct perf_sched {
 658         int                     max_weight;
 659         int                     max_events;
 660         int                     max_gp;
 661         int                     saved_states;
 662         struct event_constraint **constraints;
 663         struct sched_state      state;
 664         struct sched_state      saved[SCHED_STATES_MAX];
 665 };
 666
 667 /*
 668  * Initialize interator that runs through all events and counters.
 669  */
 670 static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints,
 671                             int num, int wmin, int wmax, int gpmax)
 672 {
 673         int idx;
 674
 675         memset(sched, 0, sizeof(*sched));
 676         sched->max_events       = num;
 677         sched->max_weight       = wmax;
 678         sched->max_gp           = gpmax;
 679         sched->constraints      = constraints;
 680
 681         for (idx = 0; idx < num; idx++) {
 682                 if (constraints[idx]->weight == wmin)
 683                         break;
 684         }
 685
 686         sched->state.event      = idx;          /* start with min weight */
 687         sched->state.weight     = wmin;
 688         sched->state.unassigned = num;
 689 }
 690
 691 static void perf_sched_save_state(struct perf_sched *sched)
 692 {
 693         if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
 694                 return;
 695
 696         sched->saved[sched->saved_states] = sched->state;
 697         sched->saved_states++;
 698 }
 699
 700 static bool perf_sched_restore_state(struct perf_sched *sched)
 701 {
 702         if (!sched->saved_states)
 703                 return false;
 704
 705         sched->saved_states--;
 706         sched->state = sched->saved[sched->saved_states];
 707
 708         /* continue with next counter: */
 709         clear_bit(sched->state.counter++, sched->state.used);
 710
 711         return true;
 712 }
 713
 714 /*
 715  * Select a counter for the current event to schedule. Return true on
 716  * success.
 717  */
 718 static bool __perf_sched_find_counter(struct perf_sched *sched)
 719 {
 720         struct event_constraint *c;
 721         int idx;
 722
 723         if (!sched->state.unassigned)
 724                 return false;
 725
 726         if (sched->state.event >= sched->max_events)
 727                 return false;
 728
 729         c = sched->constraints[sched->state.event];
 730         /* Prefer fixed purpose counters */
 731         if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
 732                 idx = INTEL_PMC_IDX_FIXED;
 733                 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
 734                         if (!__test_and_set_bit(idx, sched->state.used))
 735                                 goto done;
 736                 }
 737         }
 738
 739         /* Grab the first unused counter starting with idx */
 740         idx = sched->state.counter;
 741         for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
 742                 if (!__test_and_set_bit(idx, sched->state.used)) {
 743                         if (sched->state.nr_gp++ >= sched->max_gp)
 744                                 return false;
 745
 746                         goto done;
 747                 }
 748         }
 749
 750         return false;
 751
 752 done:
 753         sched->state.counter = idx;
 754
 755         if (c->overlap)
 756                 perf_sched_save_state(sched);
 757
 758         return true;
 759 }
 760
 761 static bool perf_sched_find_counter(struct perf_sched *sched)
 762 {
 763         while (!__perf_sched_find_counter(sched)) {
 764                 if (!perf_sched_restore_state(sched))
 765                         return false;
 766         }
 767
 768         return true;
 769 }
 770
 771 /*
 772  * Go through all unassigned events and find the next one to schedule.
 773  * Take events with the least weight first. Return true on success.
 774  */
 775 static bool perf_sched_next_event(struct perf_sched *sched)
 776 {
 777         struct event_constraint *c;
 778
 779         if (!sched->state.unassigned || !--sched->state.unassigned)
 780                 return false;
 781
 782         do {
 783                 /* next event */
 784                 sched->state.event++;
 785                 if (sched->state.event >= sched->max_events) {
 786                         /* next weight */
 787                         sched->state.event = 0;
 788                         sched->state.weight++;
 789                         if (sched->state.weight > sched->max_weight)
 790                                 return false;
 791                 }
 792                 c = sched->constraints[sched->state.event];
 793         } while (c->weight != sched->state.weight);
 794
 795         sched->state.counter = 0;       /* start with first counter */
 796
 797         return true;
 798 }
 799
 800 /*
 801  * Assign a counter for each event.
 802  */
 803 int perf_assign_events(struct event_constraint **constraints, int n,
 804                         int wmin, int wmax, int gpmax, int *assign)
 805 {
 806         struct perf_sched sched;
 807
 808         perf_sched_init(&sched, constraints, n, wmin, wmax, gpmax);
 809
 810         do {
 811                 if (!perf_sched_find_counter(&sched))
 812                         break;  /* failed */
 813                 if (assign)
 814                         assign[sched.state.event] = sched.state.counter;
 815         } while (perf_sched_next_event(&sched));
 816
 817         return sched.state.unassigned;
 818 }
 819 EXPORT_SYMBOL_GPL(perf_assign_events);
 820
 821 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 822 {
 823         struct event_constraint *c;
 824         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 825         struct perf_event *e;
 826         int i, wmin, wmax, unsched = 0;
 827         struct hw_perf_event *hwc;
 828
 829         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 830
 831         if (x86_pmu.start_scheduling)
 832                 x86_pmu.start_scheduling(cpuc);
 833
 834         for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
 835                 cpuc->event_constraint[i] = NULL;
 836                 c = x86_pmu.get_event_constraints(cpuc, i, cpuc->event_list[i]);
 837                 cpuc->event_constraint[i] = c;
 838
 839                 wmin = min(wmin, c->weight);
 840                 wmax = max(wmax, c->weight);
 841         }
 842
 843         /*
 844          * fastpath, try to reuse previous register
 845          */
 846         for (i = 0; i < n; i++) {
 847                 hwc = &cpuc->event_list[i]->hw;
 848                 c = cpuc->event_constraint[i];
 849
 850                 /* never assigned */
 851                 if (hwc->idx == -1)
 852                         break;
 853
 854                 /* constraint still honored */
 855                 if (!test_bit(hwc->idx, c->idxmsk))
 856                         break;
 857
 858                 /* not already used */
 859                 if (test_bit(hwc->idx, used_mask))
 860                         break;
 861
 862                 __set_bit(hwc->idx, used_mask);
 863                 if (assign)
 864                         assign[i] = hwc->idx;
 865         }
 866
 867         /* slow path */
 868         if (i != n) {
 869                 int gpmax = x86_pmu.num_counters;
 870
 871                 /*
 872                  * Do not allow scheduling of more than half the available
 873                  * generic counters.
 874                  *
 875                  * This helps avoid counter starvation of sibling thread by
 876                  * ensuring at most half the counters cannot be in exclusive
 877                  * mode. There is no designated counters for the limits. Any
 878                  * N/2 counters can be used. This helps with events with
 879                  * specific counter constraints.
 880                  */
 881                 if (is_ht_workaround_enabled() && !cpuc->is_fake &&
 882                     READ_ONCE(cpuc->excl_cntrs->exclusive_present))
 883                         gpmax /= 2;
 884
 885                 unsched = perf_assign_events(cpuc->event_constraint, n, wmin,
 886                                              wmax, gpmax, assign);
 887         }
 888
 889         /*
 890          * In case of success (unsched = 0), mark events as committed,
 891          * so we do not put_constraint() in case new events are added
 892          * and fail to be scheduled
 893          *
 894          * We invoke the lower level commit callback to lock the resource
 895          *
 896          * We do not need to do all of this in case we are called to
 897          * validate an event group (assign == NULL)
 898          */
 899         if (!unsched && assign) {
 900                 for (i = 0; i < n; i++) {
 901                         e = cpuc->event_list[i];
 902                         e->hw.flags |= PERF_X86_EVENT_COMMITTED;
 903                         if (x86_pmu.commit_scheduling)
 904                                 x86_pmu.commit_scheduling(cpuc, i, assign[i]);
 905                 }
 906         } else {
 907                 for (i = 0; i < n; i++) {
 908                         e = cpuc->event_list[i];
 909                         /*
 910                          * do not put_constraint() on comitted events,
 911                          * because they are good to go
 912                          */
 913                         if ((e->hw.flags & PERF_X86_EVENT_COMMITTED))
 914                                 continue;
 915
 916                         /*
 917                          * release events that failed scheduling
 918                          */
 919                         if (x86_pmu.put_event_constraints)
 920                                 x86_pmu.put_event_constraints(cpuc, e);
 921                 }
 922         }
 923
 924         if (x86_pmu.stop_scheduling)
 925                 x86_pmu.stop_scheduling(cpuc);
 926
 927         return unsched ? -EINVAL : 0;
 928 }
 929
 930 /*
 931  * dogrp: true if must collect siblings events (group)
 932  * returns total number of events and error code
 933  */
 934 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
 935 {
 936         struct perf_event *event;
 937         int n, max_count;
 938
 939         max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
 940
 941         /* current number of events already accepted */
 942         n = cpuc->n_events;
 943
 944         if (is_x86_event(leader)) {
 945                 if (n >= max_count)
 946                         return -EINVAL;
 947                 cpuc->event_list[n] = leader;
 948                 n++;
 949         }
 950         if (!dogrp)
 951                 return n;
 952
 953         list_for_each_entry(event, &leader->sibling_list, group_entry) {
 954                 if (!is_x86_event(event) ||
 955                     event->state <= PERF_EVENT_STATE_OFF)
 956                         continue;
 957
 958                 if (n >= max_count)
 959                         return -EINVAL;
 960
 961                 cpuc->event_list[n] = event;
 962                 n++;
 963         }
 964         return n;
 965 }
 966
 967 static inline void x86_assign_hw_event(struct perf_event *event,
 968                                 struct cpu_hw_events *cpuc, int i)
 969 {
 970         struct hw_perf_event *hwc = &event->hw;
 971
 972         hwc->idx = cpuc->assign[i];
 973         hwc->last_cpu = smp_processor_id();
 974         hwc->last_tag = ++cpuc->tags[i];
 975
 976         if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) {
 977                 hwc->config_base = 0;
 978                 hwc->event_base = 0;
 979         } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) {
 980                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 981                 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED);
 982                 hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30;
 983         } else {
 984                 hwc->config_base = x86_pmu_config_addr(hwc->idx);
 985                 hwc->event_base  = x86_pmu_event_addr(hwc->idx);
 986                 hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
 987         }
 988 }
 989
 990 static inline int match_prev_assignment(struct hw_perf_event *hwc,
 991                                         struct cpu_hw_events *cpuc,
 992                                         int i)
 993 {
 994         return hwc->idx == cpuc->assign[i] &&
 995                 hwc->last_cpu == smp_processor_id() &&
 996                 hwc->last_tag == cpuc->tags[i];
 997 }
 998
 999 static void x86_pmu_start(struct perf_event *event, int flags);
1000
1001 static void x86_pmu_enable(struct pmu *pmu)
1002 {
1003         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1004         struct perf_event *event;
1005         struct hw_perf_event *hwc;
1006         int i, added = cpuc->n_added;
1007
1008         if (!x86_pmu_initialized())
1009                 return;
1010
1011         if (cpuc->enabled)
1012                 return;
1013
1014         if (cpuc->n_added) {
1015                 int n_running = cpuc->n_events - cpuc->n_added;
1016                 /*
1017                  * apply assignment obtained either from
1018                  * hw_perf_group_sched_in() or x86_pmu_enable()
1019                  *
1020                  * step1: save events moving to new counters
1021                  */
1022                 for (i = 0; i < n_running; i++) {
1023                         event = cpuc->event_list[i];
1024                         hwc = &event->hw;
1025
1026                         /*
1027                          * we can avoid reprogramming counter if:
1028                          * - assigned same counter as last time
1029                          * - running on same CPU as last time
1030                          * - no other event has used the counter since
1031                          */
1032                         if (hwc->idx == -1 ||
1033                             match_prev_assignment(hwc, cpuc, i))
1034                                 continue;
1035
1036                         /*
1037                          * Ensure we don't accidentally enable a stopped
1038                          * counter simply because we rescheduled.
1039                          */
1040                         if (hwc->state & PERF_HES_STOPPED)
1041                                 hwc->state |= PERF_HES_ARCH;
1042
1043                         x86_pmu_stop(event, PERF_EF_UPDATE);
1044                 }
1045
1046                 /*
1047                  * step2: reprogram moved events into new counters
1048                  */
1049                 for (i = 0; i < cpuc->n_events; i++) {
1050                         event = cpuc->event_list[i];
1051                         hwc = &event->hw;
1052
1053                         if (!match_prev_assignment(hwc, cpuc, i))
1054                                 x86_assign_hw_event(event, cpuc, i);
1055                         else if (i < n_running)
1056                                 continue;
1057
1058                         if (hwc->state & PERF_HES_ARCH)
1059                                 continue;
1060
1061                         x86_pmu_start(event, PERF_EF_RELOAD);
1062                 }
1063                 cpuc->n_added = 0;
1064                 perf_events_lapic_init();
1065         }
1066
1067         cpuc->enabled = 1;
1068         barrier();
1069
1070         x86_pmu.enable_all(added);
1071 }
1072
1073 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
1074
1075 /*
1076  * Set the next IRQ period, based on the hwc->period_left value.
1077  * To be called with the event disabled in hw:
1078  */
1079 int x86_perf_event_set_period(struct perf_event *event)
1080 {
1081         struct hw_perf_event *hwc = &event->hw;
1082         s64 left = local64_read(&hwc->period_left);
1083         s64 period = hwc->sample_period;
1084         int ret = 0, idx = hwc->idx;
1085
1086         if (idx == INTEL_PMC_IDX_FIXED_BTS)
1087                 return 0;
1088
1089         /*
1090          * If we are way outside a reasonable range then just skip forward:
1091          */
1092         if (unlikely(left <= -period)) {
1093                 left = period;
1094                 local64_set(&hwc->period_left, left);
1095                 hwc->last_period = period;
1096                 ret = 1;
1097         }
1098
1099         if (unlikely(left <= 0)) {
1100                 left += period;
1101                 local64_set(&hwc->period_left, left);
1102                 hwc->last_period = period;
1103                 ret = 1;
1104         }
1105         /*
1106          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1107          */
1108         if (unlikely(left < 2))
1109                 left = 2;
1110
1111         if (left > x86_pmu.max_period)
1112                 left = x86_pmu.max_period;
1113
1114         if (x86_pmu.limit_period)
1115                 left = x86_pmu.limit_period(event, left);
1116
1117         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
1118
1119         if (!(hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) ||
1120             local64_read(&hwc->prev_count) != (u64)-left) {
1121                 /*
1122                  * The hw event starts counting from this event offset,
1123                  * mark it to be able to extra future deltas:
1124                  */
1125                 local64_set(&hwc->prev_count, (u64)-left);
1126
1127                 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
1128         }
1129
1130         /*
1131          * Due to erratum on certan cpu we need
1132          * a second write to be sure the register
1133          * is updated properly
1134          */
1135         if (x86_pmu.perfctr_second_write) {
1136                 wrmsrl(hwc->event_base,
1137                         (u64)(-left) & x86_pmu.cntval_mask);
1138         }
1139
1140         perf_event_update_userpage(event);
1141
1142         return ret;
1143 }
1144
1145 void x86_pmu_enable_event(struct perf_event *event)
1146 {
1147         if (__this_cpu_read(cpu_hw_events.enabled))
1148                 __x86_pmu_enable_event(&event->hw,
1149                                        ARCH_PERFMON_EVENTSEL_ENABLE);
1150 }
1151
1152 /*
1153  * Add a single event to the PMU.
1154  *
1155  * The event is added to the group of enabled events
1156  * but only if it can be scehduled with existing events.
1157  */
1158 static int x86_pmu_add(struct perf_event *event, int flags)
1159 {
1160         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1161         struct hw_perf_event *hwc;
1162         int assign[X86_PMC_IDX_MAX];
1163         int n, n0, ret;
1164
1165         hwc = &event->hw;
1166
1167         n0 = cpuc->n_events;
1168         ret = n = collect_events(cpuc, event, false);
1169         if (ret < 0)
1170                 goto out;
1171
1172         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1173         if (!(flags & PERF_EF_START))
1174                 hwc->state |= PERF_HES_ARCH;
1175
1176         /*
1177          * If group events scheduling transaction was started,
1178          * skip the schedulability test here, it will be performed
1179          * at commit time (->commit_txn) as a whole.
1180          */
1181         if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1182                 goto done_collect;
1183
1184         ret = x86_pmu.schedule_events(cpuc, n, assign);
1185         if (ret)
1186                 goto out;
1187         /*
1188          * copy new assignment, now we know it is possible
1189          * will be used by hw_perf_enable()
1190          */
1191         memcpy(cpuc->assign, assign, n*sizeof(int));
1192
1193 done_collect:
1194         /*
1195          * Commit the collect_events() state. See x86_pmu_del() and
1196          * x86_pmu_*_txn().
1197          */
1198         cpuc->n_events = n;
1199         cpuc->n_added += n - n0;
1200         cpuc->n_txn += n - n0;
1201
1202         ret = 0;
1203 out:
1204         return ret;
1205 }
1206
1207 static void x86_pmu_start(struct perf_event *event, int flags)
1208 {
1209         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1210         int idx = event->hw.idx;
1211
1212         if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1213                 return;
1214
1215         if (WARN_ON_ONCE(idx == -1))
1216                 return;
1217
1218         if (flags & PERF_EF_RELOAD) {
1219                 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1220                 x86_perf_event_set_period(event);
1221         }
1222
1223         event->hw.state = 0;
1224
1225         cpuc->events[idx] = event;
1226         __set_bit(idx, cpuc->active_mask);
1227         __set_bit(idx, cpuc->running);
1228         x86_pmu.enable(event);
1229         perf_event_update_userpage(event);
1230 }
1231
1232 void perf_event_print_debug(void)
1233 {
1234         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1235         u64 pebs, debugctl;
1236         struct cpu_hw_events *cpuc;
1237         unsigned long flags;
1238         int cpu, idx;
1239
1240         if (!x86_pmu.num_counters)
1241                 return;
1242
1243         local_irq_save(flags);
1244
1245         cpu = smp_processor_id();
1246         cpuc = &per_cpu(cpu_hw_events, cpu);
1247
1248         if (x86_pmu.version >= 2) {
1249                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1250                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1251                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1252                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1253
1254                 pr_info("\n");
1255                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1256                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1257                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1258                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1259                 if (x86_pmu.pebs_constraints) {
1260                         rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1261                         pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
1262                 }
1263                 if (x86_pmu.lbr_nr) {
1264                         rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
1265                         pr_info("CPU#%d: debugctl:   %016llx\n", cpu, debugctl);
1266                 }
1267         }
1268         pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1269
1270         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1271                 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1272                 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1273
1274                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1275
1276                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1277                         cpu, idx, pmc_ctrl);
1278                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1279                         cpu, idx, pmc_count);
1280                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1281                         cpu, idx, prev_left);
1282         }
1283         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1284                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1285
1286                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1287                         cpu, idx, pmc_count);
1288         }
1289         local_irq_restore(flags);
1290 }
1291
1292 void x86_pmu_stop(struct perf_event *event, int flags)
1293 {
1294         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1295         struct hw_perf_event *hwc = &event->hw;
1296
1297         if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
1298                 x86_pmu.disable(event);
1299                 cpuc->events[hwc->idx] = NULL;
1300                 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1301                 hwc->state |= PERF_HES_STOPPED;
1302         }
1303
1304         if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1305                 /*
1306                  * Drain the remaining delta count out of a event
1307                  * that we are disabling:
1308                  */
1309                 x86_perf_event_update(event);
1310                 hwc->state |= PERF_HES_UPTODATE;
1311         }
1312 }
1313
1314 static void x86_pmu_del(struct perf_event *event, int flags)
1315 {
1316         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1317         int i;
1318
1319         /*
1320          * event is descheduled
1321          */
1322         event->hw.flags &= ~PERF_X86_EVENT_COMMITTED;
1323
1324         /*
1325          * If we're called during a txn, we don't need to do anything.
1326          * The events never got scheduled and ->cancel_txn will truncate
1327          * the event_list.
1328          *
1329          * XXX assumes any ->del() called during a TXN will only be on
1330          * an event added during that same TXN.
1331          */
1332         if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1333                 return;
1334
1335         /*
1336          * Not a TXN, therefore cleanup properly.
1337          */
1338         x86_pmu_stop(event, PERF_EF_UPDATE);
1339
1340         for (i = 0; i < cpuc->n_events; i++) {
1341                 if (event == cpuc->event_list[i])
1342                         break;
1343         }
1344
1345         if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */
1346                 return;
1347
1348         /* If we have a newly added event; make sure to decrease n_added. */
1349         if (i >= cpuc->n_events - cpuc->n_added)
1350                 --cpuc->n_added;
1351
1352         if (x86_pmu.put_event_constraints)
1353                 x86_pmu.put_event_constraints(cpuc, event);
1354
1355         /* Delete the array entry. */
1356         while (++i < cpuc->n_events) {
1357                 cpuc->event_list[i-1] = cpuc->event_list[i];
1358                 cpuc->event_constraint[i-1] = cpuc->event_constraint[i];
1359         }
1360         --cpuc->n_events;
1361
1362         perf_event_update_userpage(event);
1363 }
1364
1365 int x86_pmu_handle_irq(struct pt_regs *regs)
1366 {
1367         struct perf_sample_data data;
1368         struct cpu_hw_events *cpuc;
1369         struct perf_event *event;
1370         int idx, handled = 0;
1371         u64 val;
1372
1373         cpuc = this_cpu_ptr(&cpu_hw_events);
1374
1375         /*
1376          * Some chipsets need to unmask the LVTPC in a particular spot
1377          * inside the nmi handler.  As a result, the unmasking was pushed
1378          * into all the nmi handlers.
1379          *
1380          * This generic handler doesn't seem to have any issues where the
1381          * unmasking occurs so it was left at the top.
1382          */
1383         apic_write(APIC_LVTPC, APIC_DM_NMI);
1384
1385         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1386                 if (!test_bit(idx, cpuc->active_mask)) {
1387                         /*
1388                          * Though we deactivated the counter some cpus
1389                          * might still deliver spurious interrupts still
1390                          * in flight. Catch them:
1391                          */
1392                         if (__test_and_clear_bit(idx, cpuc->running))
1393                                 handled++;
1394                         continue;
1395                 }
1396
1397                 event = cpuc->events[idx];
1398
1399                 val = x86_perf_event_update(event);
1400                 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1401                         continue;
1402
1403                 /*
1404                  * event overflow
1405                  */
1406                 handled++;
1407                 perf_sample_data_init(&data, 0, event->hw.last_period);
1408
1409                 if (!x86_perf_event_set_period(event))
1410                         continue;
1411
1412                 if (perf_event_overflow(event, &data, regs))
1413                         x86_pmu_stop(event, 0);
1414         }
1415
1416         if (handled)
1417                 inc_irq_stat(apic_perf_irqs);
1418
1419         return handled;
1420 }
1421
1422 void perf_events_lapic_init(void)
1423 {
1424         if (!x86_pmu.apic || !x86_pmu_initialized())
1425                 return;
1426
1427         /*
1428          * Always use NMI for PMU
1429          */
1430         apic_write(APIC_LVTPC, APIC_DM_NMI);
1431 }
1432
1433 static int
1434 perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1435 {
1436         u64 start_clock;
1437         u64 finish_clock;
1438         int ret;
1439
1440         /*
1441          * All PMUs/events that share this PMI handler should make sure to
1442          * increment active_events for their events.
1443          */
1444         if (!atomic_read(&active_events))
1445                 return NMI_DONE;
1446
1447         start_clock = sched_clock();
1448         ret = x86_pmu.handle_irq(regs);
1449         finish_clock = sched_clock();
1450
1451         perf_sample_event_took(finish_clock - start_clock);
1452
1453         return ret;
1454 }
1455 NOKPROBE_SYMBOL(perf_event_nmi_handler);
1456
1457 struct event_constraint emptyconstraint;
1458 struct event_constraint unconstrained;
1459
1460 static int
1461 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1462 {
1463         unsigned int cpu = (long)hcpu;
1464         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1465         int i, ret = NOTIFY_OK;
1466
1467         switch (action & ~CPU_TASKS_FROZEN) {
1468         case CPU_UP_PREPARE:
1469                 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++)
1470                         cpuc->kfree_on_online[i] = NULL;
1471                 if (x86_pmu.cpu_prepare)
1472                         ret = x86_pmu.cpu_prepare(cpu);
1473                 break;
1474
1475         case CPU_STARTING:
1476                 if (x86_pmu.cpu_starting)
1477                         x86_pmu.cpu_starting(cpu);
1478                 break;
1479
1480         case CPU_ONLINE:
1481                 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) {
1482                         kfree(cpuc->kfree_on_online[i]);
1483                         cpuc->kfree_on_online[i] = NULL;
1484                 }
1485                 break;
1486
1487         case CPU_DYING:
1488                 if (x86_pmu.cpu_dying)
1489                         x86_pmu.cpu_dying(cpu);
1490                 break;
1491
1492         case CPU_UP_CANCELED:
1493         case CPU_DEAD:
1494                 if (x86_pmu.cpu_dead)
1495                         x86_pmu.cpu_dead(cpu);
1496                 break;
1497
1498         default:
1499                 break;
1500         }
1501
1502         return ret;
1503 }
1504
1505 static void __init pmu_check_apic(void)
1506 {
1507         if (cpu_has_apic)
1508                 return;
1509
1510         x86_pmu.apic = 0;
1511         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1512         pr_info("no hardware sampling interrupt available.\n");
1513
1514         /*
1515          * If we have a PMU initialized but no APIC
1516          * interrupts, we cannot sample hardware
1517          * events (user-space has to fall back and
1518          * sample via a hrtimer based software event):
1519          */
1520         pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
1521
1522 }
1523
1524 static struct attribute_group x86_pmu_format_group = {
1525         .name = "format",
1526         .attrs = NULL,
1527 };
1528
1529 /*
1530  * Remove all undefined events (x86_pmu.event_map(id) == 0)
1531  * out of events_attr attributes.
1532  */
1533 static void __init filter_events(struct attribute **attrs)
1534 {
1535         struct device_attribute *d;
1536         struct perf_pmu_events_attr *pmu_attr;
1537         int offset = 0;
1538         int i, j;
1539
1540         for (i = 0; attrs[i]; i++) {
1541                 d = (struct device_attribute *)attrs[i];
1542                 pmu_attr = container_of(d, struct perf_pmu_events_attr, attr);
1543                 /* str trumps id */
1544                 if (pmu_attr->event_str)
1545                         continue;
1546                 if (x86_pmu.event_map(i + offset))
1547                         continue;
1548
1549                 for (j = i; attrs[j]; j++)
1550                         attrs[j] = attrs[j + 1];
1551
1552                 /* Check the shifted attr. */
1553                 i--;
1554
1555                 /*
1556                  * event_map() is index based, the attrs array is organized
1557                  * by increasing event index. If we shift the events, then
1558                  * we need to compensate for the event_map(), otherwise
1559                  * we are looking up the wrong event in the map
1560                  */
1561                 offset++;
1562         }
1563 }
1564
1565 /* Merge two pointer arrays */
1566 __init struct attribute **merge_attr(struct attribute **a, struct attribute **b)
1567 {
1568         struct attribute **new;
1569         int j, i;
1570
1571         for (j = 0; a[j]; j++)
1572                 ;
1573         for (i = 0; b[i]; i++)
1574                 j++;
1575         j++;
1576
1577         new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL);
1578         if (!new)
1579                 return NULL;
1580
1581         j = 0;
1582         for (i = 0; a[i]; i++)
1583                 new[j++] = a[i];
1584         for (i = 0; b[i]; i++)
1585                 new[j++] = b[i];
1586         new[j] = NULL;
1587
1588         return new;
1589 }
1590
1591 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
1592                           char *page)
1593 {
1594         struct perf_pmu_events_attr *pmu_attr = \
1595                 container_of(attr, struct perf_pmu_events_attr, attr);
1596         u64 config = x86_pmu.event_map(pmu_attr->id);
1597
1598         /* string trumps id */
1599         if (pmu_attr->event_str)
1600                 return sprintf(page, "%s", pmu_attr->event_str);
1601
1602         return x86_pmu.events_sysfs_show(page, config);
1603 }
1604
1605 EVENT_ATTR(cpu-cycles,                  CPU_CYCLES              );
1606 EVENT_ATTR(instructions,                INSTRUCTIONS            );
1607 EVENT_ATTR(cache-references,            CACHE_REFERENCES        );
1608 EVENT_ATTR(cache-misses,                CACHE_MISSES            );
1609 EVENT_ATTR(branch-instructions,         BRANCH_INSTRUCTIONS     );
1610 EVENT_ATTR(branch-misses,               BRANCH_MISSES           );
1611 EVENT_ATTR(bus-cycles,                  BUS_CYCLES              );
1612 EVENT_ATTR(stalled-cycles-frontend,     STALLED_CYCLES_FRONTEND );
1613 EVENT_ATTR(stalled-cycles-backend,      STALLED_CYCLES_BACKEND  );
1614 EVENT_ATTR(ref-cycles,                  REF_CPU_CYCLES          );
1615
1616 static struct attribute *empty_attrs;
1617
1618 static struct attribute *events_attr[] = {
1619         EVENT_PTR(CPU_CYCLES),
1620         EVENT_PTR(INSTRUCTIONS),
1621         EVENT_PTR(CACHE_REFERENCES),
1622         EVENT_PTR(CACHE_MISSES),
1623         EVENT_PTR(BRANCH_INSTRUCTIONS),
1624         EVENT_PTR(BRANCH_MISSES),
1625         EVENT_PTR(BUS_CYCLES),
1626         EVENT_PTR(STALLED_CYCLES_FRONTEND),
1627         EVENT_PTR(STALLED_CYCLES_BACKEND),
1628         EVENT_PTR(REF_CPU_CYCLES),
1629         NULL,
1630 };
1631
1632 static struct attribute_group x86_pmu_events_group = {
1633         .name = "events",
1634         .attrs = events_attr,
1635 };
1636
1637 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
1638 {
1639         u64 umask  = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
1640         u64 cmask  = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
1641         bool edge  = (config & ARCH_PERFMON_EVENTSEL_EDGE);
1642         bool pc    = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
1643         bool any   = (config & ARCH_PERFMON_EVENTSEL_ANY);
1644         bool inv   = (config & ARCH_PERFMON_EVENTSEL_INV);
1645         ssize_t ret;
1646
1647         /*
1648         * We have whole page size to spend and just little data
1649         * to write, so we can safely use sprintf.
1650         */
1651         ret = sprintf(page, "event=0x%02llx", event);
1652
1653         if (umask)
1654                 ret += sprintf(page + ret, ",umask=0x%02llx", umask);
1655
1656         if (edge)
1657                 ret += sprintf(page + ret, ",edge");
1658
1659         if (pc)
1660                 ret += sprintf(page + ret, ",pc");
1661
1662         if (any)
1663                 ret += sprintf(page + ret, ",any");
1664
1665         if (inv)
1666                 ret += sprintf(page + ret, ",inv");
1667
1668         if (cmask)
1669                 ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);
1670
1671         ret += sprintf(page + ret, "\n");
1672
1673         return ret;
1674 }
1675
1676 static int __init init_hw_perf_events(void)
1677 {
1678         struct x86_pmu_quirk *quirk;
1679         int err;
1680
1681         pr_info("Performance Events: ");
1682
1683         switch (boot_cpu_data.x86_vendor) {
1684         case X86_VENDOR_INTEL:
1685                 err = intel_pmu_init();
1686                 break;
1687         case X86_VENDOR_AMD:
1688                 err = amd_pmu_init();
1689                 break;
1690         default:
1691                 err = -ENOTSUPP;
1692         }
1693         if (err != 0) {
1694                 pr_cont("no PMU driver, software events only.\n");
1695                 return 0;
1696         }
1697
1698         pmu_check_apic();
1699
1700         /* sanity check that the hardware exists or is emulated */
1701         if (!check_hw_exists())
1702                 return 0;
1703
1704         pr_cont("%s PMU driver.\n", x86_pmu.name);
1705
1706         x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
1707
1708         for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
1709                 quirk->func();
1710
1711         if (!x86_pmu.intel_ctrl)
1712                 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1713
1714         perf_events_lapic_init();
1715         register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
1716
1717         unconstrained = (struct event_constraint)
1718                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1719                                    0, x86_pmu.num_counters, 0, 0);
1720
1721         x86_pmu_format_group.attrs = x86_pmu.format_attrs;
1722
1723         if (x86_pmu.event_attrs)
1724                 x86_pmu_events_group.attrs = x86_pmu.event_attrs;
1725
1726         if (!x86_pmu.events_sysfs_show)
1727                 x86_pmu_events_group.attrs = &empty_attrs;
1728         else
1729                 filter_events(x86_pmu_events_group.attrs);
1730
1731         if (x86_pmu.cpu_events) {
1732                 struct attribute **tmp;
1733
1734                 tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events);
1735                 if (!WARN_ON(!tmp))
1736                         x86_pmu_events_group.attrs = tmp;
1737         }
1738
1739         pr_info("... version:                %d\n",     x86_pmu.version);
1740         pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
1741         pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
1742         pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
1743         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1744         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1745         pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1746
1747         perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1748         perf_cpu_notifier(x86_pmu_notifier);
1749
1750         return 0;
1751 }
1752 early_initcall(init_hw_perf_events);
1753
1754 static inline void x86_pmu_read(struct perf_event *event)
1755 {
1756         x86_perf_event_update(event);
1757 }
1758
1759 /*
1760  * Start group events scheduling transaction
1761  * Set the flag to make pmu::enable() not perform the
1762  * schedulability test, it will be performed at commit time
1763  *
1764  * We only support PERF_PMU_TXN_ADD transactions. Save the
1765  * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
1766  * transactions.
1767  */
1768 static void x86_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
1769 {
1770         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1771
1772         WARN_ON_ONCE(cpuc->txn_flags);          /* txn already in flight */
1773
1774         cpuc->txn_flags = txn_flags;
1775         if (txn_flags & ~PERF_PMU_TXN_ADD)
1776                 return;
1777
1778         perf_pmu_disable(pmu);
1779         __this_cpu_write(cpu_hw_events.n_txn, 0);
1780 }
1781
1782 /*
1783  * Stop group events scheduling transaction
1784  * Clear the flag and pmu::enable() will perform the
1785  * schedulability test.
1786  */
1787 static void x86_pmu_cancel_txn(struct pmu *pmu)
1788 {
1789         unsigned int txn_flags;
1790         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1791
1792         WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
1793
1794         txn_flags = cpuc->txn_flags;
1795         cpuc->txn_flags = 0;
1796         if (txn_flags & ~PERF_PMU_TXN_ADD)
1797                 return;
1798
1799         /*
1800          * Truncate collected array by the number of events added in this
1801          * transaction. See x86_pmu_add() and x86_pmu_*_txn().
1802          */
1803         __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
1804         __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
1805         perf_pmu_enable(pmu);
1806 }
1807
1808 /*
1809  * Commit group events scheduling transaction
1810  * Perform the group schedulability test as a whole
1811  * Return 0 if success
1812  *
1813  * Does not cancel the transaction on failure; expects the caller to do this.
1814  */
1815 static int x86_pmu_commit_txn(struct pmu *pmu)
1816 {
1817         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1818         int assign[X86_PMC_IDX_MAX];
1819         int n, ret;
1820
1821         WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
1822
1823         if (cpuc->txn_flags & ~PERF_PMU_TXN_ADD) {
1824                 cpuc->txn_flags = 0;
1825                 return 0;
1826         }
1827
1828         n = cpuc->n_events;
1829
1830         if (!x86_pmu_initialized())
1831                 return -EAGAIN;
1832
1833         ret = x86_pmu.schedule_events(cpuc, n, assign);
1834         if (ret)
1835                 return ret;
1836
1837         /*
1838          * copy new assignment, now we know it is possible
1839          * will be used by hw_perf_enable()
1840          */
1841         memcpy(cpuc->assign, assign, n*sizeof(int));
1842
1843         cpuc->txn_flags = 0;
1844         perf_pmu_enable(pmu);
1845         return 0;
1846 }
1847 /*
1848  * a fake_cpuc is used to validate event groups. Due to
1849  * the extra reg logic, we need to also allocate a fake
1850  * per_core and per_cpu structure. Otherwise, group events
1851  * using extra reg may conflict without the kernel being
1852  * able to catch this when the last event gets added to
1853  * the group.
1854  */
1855 static void free_fake_cpuc(struct cpu_hw_events *cpuc)
1856 {
1857         kfree(cpuc->shared_regs);
1858         kfree(cpuc);
1859 }
1860
1861 static struct cpu_hw_events *allocate_fake_cpuc(void)
1862 {
1863         struct cpu_hw_events *cpuc;
1864         int cpu = raw_smp_processor_id();
1865
1866         cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
1867         if (!cpuc)
1868                 return ERR_PTR(-ENOMEM);
1869
1870         /* only needed, if we have extra_regs */
1871         if (x86_pmu.extra_regs) {
1872                 cpuc->shared_regs = allocate_shared_regs(cpu);
1873                 if (!cpuc->shared_regs)
1874                         goto error;
1875         }
1876         cpuc->is_fake = 1;
1877         return cpuc;
1878 error:
1879         free_fake_cpuc(cpuc);
1880         return ERR_PTR(-ENOMEM);
1881 }
1882
1883 /*
1884  * validate that we can schedule this event
1885  */
1886 static int validate_event(struct perf_event *event)
1887 {
1888         struct cpu_hw_events *fake_cpuc;
1889         struct event_constraint *c;
1890         int ret = 0;
1891
1892         fake_cpuc = allocate_fake_cpuc();
1893         if (IS_ERR(fake_cpuc))
1894                 return PTR_ERR(fake_cpuc);
1895
1896         c = x86_pmu.get_event_constraints(fake_cpuc, -1, event);
1897
1898         if (!c || !c->weight)
1899                 ret = -EINVAL;
1900
1901         if (x86_pmu.put_event_constraints)
1902                 x86_pmu.put_event_constraints(fake_cpuc, event);
1903
1904         free_fake_cpuc(fake_cpuc);
1905
1906         return ret;
1907 }
1908
1909 /*
1910  * validate a single event group
1911  *
1912  * validation include:
1913  *      - check events are compatible which each other
1914  *      - events do not compete for the same counter
1915  *      - number of events <= number of counters
1916  *
1917  * validation ensures the group can be loaded onto the
1918  * PMU if it was the only group available.
1919  */
1920 static int validate_group(struct perf_event *event)
1921 {
1922         struct perf_event *leader = event->group_leader;
1923         struct cpu_hw_events *fake_cpuc;
1924         int ret = -EINVAL, n;
1925
1926         fake_cpuc = allocate_fake_cpuc();
1927         if (IS_ERR(fake_cpuc))
1928                 return PTR_ERR(fake_cpuc);
1929         /*
1930          * the event is not yet connected with its
1931          * siblings therefore we must first collect
1932          * existing siblings, then add the new event
1933          * before we can simulate the scheduling
1934          */
1935         n = collect_events(fake_cpuc, leader, true);
1936         if (n < 0)
1937                 goto out;
1938
1939         fake_cpuc->n_events = n;
1940         n = collect_events(fake_cpuc, event, false);
1941         if (n < 0)
1942                 goto out;
1943
1944         fake_cpuc->n_events = n;
1945
1946         ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1947
1948 out:
1949         free_fake_cpuc(fake_cpuc);
1950         return ret;
1951 }
1952
1953 static int x86_pmu_event_init(struct perf_event *event)
1954 {
1955         struct pmu *tmp;
1956         int err;
1957
1958         switch (event->attr.type) {
1959         case PERF_TYPE_RAW:
1960         case PERF_TYPE_HARDWARE:
1961         case PERF_TYPE_HW_CACHE:
1962                 break;
1963
1964         default:
1965                 return -ENOENT;
1966         }
1967
1968         err = __x86_pmu_event_init(event);
1969         if (!err) {
1970                 /*
1971                  * we temporarily connect event to its pmu
1972                  * such that validate_group() can classify
1973                  * it as an x86 event using is_x86_event()
1974                  */
1975                 tmp = event->pmu;
1976                 event->pmu = &pmu;
1977
1978                 if (event->group_leader != event)
1979                         err = validate_group(event);
1980                 else
1981                         err = validate_event(event);
1982
1983                 event->pmu = tmp;
1984         }
1985         if (err) {
1986                 if (event->destroy)
1987                         event->destroy(event);
1988         }
1989
1990         if (ACCESS_ONCE(x86_pmu.attr_rdpmc))
1991                 event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED;
1992
1993         return err;
1994 }
1995
1996 static void refresh_pce(void *ignored)
1997 {
1998         if (current->mm)
1999                 load_mm_cr4(current->mm);
2000 }
2001
2002 static void x86_pmu_event_mapped(struct perf_event *event)
2003 {
2004         if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2005                 return;
2006
2007         if (atomic_inc_return(&current->mm->context.perf_rdpmc_allowed) == 1)
2008                 on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1);
2009 }
2010
2011 static void x86_pmu_event_unmapped(struct perf_event *event)
2012 {
2013         if (!current->mm)
2014                 return;
2015
2016         if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2017                 return;
2018
2019         if (atomic_dec_and_test(&current->mm->context.perf_rdpmc_allowed))
2020                 on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1);
2021 }
2022
2023 static int x86_pmu_event_idx(struct perf_event *event)
2024 {
2025         int idx = event->hw.idx;
2026
2027         if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2028                 return 0;
2029
2030         if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) {
2031                 idx -= INTEL_PMC_IDX_FIXED;
2032                 idx |= 1 << 30;
2033         }
2034
2035         return idx + 1;
2036 }
2037
2038 static ssize_t get_attr_rdpmc(struct device *cdev,
2039                               struct device_attribute *attr,
2040                               char *buf)
2041 {
2042         return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
2043 }
2044
2045 static ssize_t set_attr_rdpmc(struct device *cdev,
2046                               struct device_attribute *attr,
2047                               const char *buf, size_t count)
2048 {
2049         unsigned long val;
2050         ssize_t ret;
2051
2052         ret = kstrtoul(buf, 0, &val);
2053         if (ret)
2054                 return ret;
2055
2056         if (val > 2)
2057                 return -EINVAL;
2058
2059         if (x86_pmu.attr_rdpmc_broken)
2060                 return -ENOTSUPP;
2061
2062         if ((val == 2) != (x86_pmu.attr_rdpmc == 2)) {
2063                 /*
2064                  * Changing into or out of always available, aka
2065                  * perf-event-bypassing mode.  This path is extremely slow,
2066                  * but only root can trigger it, so it's okay.
2067                  */
2068                 if (val == 2)
2069                         static_key_slow_inc(&rdpmc_always_available);
2070                 else
2071                         static_key_slow_dec(&rdpmc_always_available);
2072                 on_each_cpu(refresh_pce, NULL, 1);
2073         }
2074
2075         x86_pmu.attr_rdpmc = val;
2076
2077         return count;
2078 }
2079
2080 static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);
2081
2082 static struct attribute *x86_pmu_attrs[] = {
2083         &dev_attr_rdpmc.attr,
2084         NULL,
2085 };
2086
2087 static struct attribute_group x86_pmu_attr_group = {
2088         .attrs = x86_pmu_attrs,
2089 };
2090
2091 static const struct attribute_group *x86_pmu_attr_groups[] = {
2092         &x86_pmu_attr_group,
2093         &x86_pmu_format_group,
2094         &x86_pmu_events_group,
2095         NULL,
2096 };
2097
2098 static void x86_pmu_sched_task(struct perf_event_context *ctx, bool sched_in)
2099 {
2100         if (x86_pmu.sched_task)
2101                 x86_pmu.sched_task(ctx, sched_in);
2102 }
2103
2104 void perf_check_microcode(void)
2105 {
2106         if (x86_pmu.check_microcode)
2107                 x86_pmu.check_microcode();
2108 }
2109 EXPORT_SYMBOL_GPL(perf_check_microcode);
2110
2111 static struct pmu pmu = {
2112         .pmu_enable             = x86_pmu_enable,
2113         .pmu_disable            = x86_pmu_disable,
2114
2115         .attr_groups            = x86_pmu_attr_groups,
2116
2117         .event_init             = x86_pmu_event_init,
2118
2119         .event_mapped           = x86_pmu_event_mapped,
2120         .event_unmapped         = x86_pmu_event_unmapped,
2121
2122         .add                    = x86_pmu_add,
2123         .del                    = x86_pmu_del,
2124         .start                  = x86_pmu_start,
2125         .stop                   = x86_pmu_stop,
2126         .read                   = x86_pmu_read,
2127
2128         .start_txn              = x86_pmu_start_txn,
2129         .cancel_txn             = x86_pmu_cancel_txn,
2130         .commit_txn             = x86_pmu_commit_txn,
2131
2132         .event_idx              = x86_pmu_event_idx,
2133         .sched_task             = x86_pmu_sched_task,
2134         .task_ctx_size          = sizeof(struct x86_perf_task_context),
2135 };
2136
2137 void arch_perf_update_userpage(struct perf_event *event,
2138                                struct perf_event_mmap_page *userpg, u64 now)
2139 {
2140         struct cyc2ns_data *data;
2141
2142         userpg->cap_user_time = 0;
2143         userpg->cap_user_time_zero = 0;
2144         userpg->cap_user_rdpmc =
2145                 !!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED);
2146         userpg->pmc_width = x86_pmu.cntval_bits;
2147
2148         if (!sched_clock_stable())
2149                 return;
2150
2151         data = cyc2ns_read_begin();
2152
2153         /*
2154          * Internal timekeeping for enabled/running/stopped times
2155          * is always in the local_clock domain.
2156          */
2157         userpg->cap_user_time = 1;
2158         userpg->time_mult = data->cyc2ns_mul;
2159         userpg->time_shift = data->cyc2ns_shift;
2160         userpg->time_offset = data->cyc2ns_offset - now;
2161
2162         /*
2163          * cap_user_time_zero doesn't make sense when we're using a different
2164          * time base for the records.
2165          */
2166         if (event->clock == &local_clock) {
2167                 userpg->cap_user_time_zero = 1;
2168                 userpg->time_zero = data->cyc2ns_offset;
2169         }
2170
2171         cyc2ns_read_end(data);
2172 }
2173
2174 /*
2175  * callchain support
2176  */
2177
2178 static int backtrace_stack(void *data, char *name)
2179 {
2180         return 0;
2181 }
2182
2183 static void backtrace_address(void *data, unsigned long addr, int reliable)
2184 {
2185         struct perf_callchain_entry *entry = data;
2186
2187         perf_callchain_store(entry, addr);
2188 }
2189
2190 static const struct stacktrace_ops backtrace_ops = {
2191         .stack                  = backtrace_stack,
2192         .address                = backtrace_address,
2193         .walk_stack             = print_context_stack_bp,
2194 };
2195
2196 void
2197 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
2198 {
2199         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2200                 /* TODO: We don't support guest os callchain now */
2201                 return;
2202         }
2203
2204         perf_callchain_store(entry, regs->ip);
2205
2206         dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry);
2207 }
2208
2209 static inline int
2210 valid_user_frame(const void __user *fp, unsigned long size)
2211 {
2212         return (__range_not_ok(fp, size, TASK_SIZE) == 0);
2213 }
2214
2215 static unsigned long get_segment_base(unsigned int segment)
2216 {
2217         struct desc_struct *desc;
2218         int idx = segment >> 3;
2219
2220         if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2221 #ifdef CONFIG_MODIFY_LDT_SYSCALL
2222                 struct ldt_struct *ldt;
2223
2224                 if (idx > LDT_ENTRIES)
2225                         return 0;
2226
2227                 /* IRQs are off, so this synchronizes with smp_store_release */
2228                 ldt = lockless_dereference(current->active_mm->context.ldt);
2229                 if (!ldt || idx > ldt->size)
2230                         return 0;
2231
2232                 desc = &ldt->entries[idx];
2233 #else
2234                 return 0;
2235 #endif
2236         } else {
2237                 if (idx > GDT_ENTRIES)
2238                         return 0;
2239
2240                 desc = raw_cpu_ptr(gdt_page.gdt) + idx;
2241         }
2242
2243         return get_desc_base(desc);
2244 }
2245
2246 #ifdef CONFIG_IA32_EMULATION
2247
2248 #include <asm/compat.h>
2249
2250 static inline int
2251 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
2252 {
2253         /* 32-bit process in 64-bit kernel. */
2254         unsigned long ss_base, cs_base;
2255         struct stack_frame_ia32 frame;
2256         const void __user *fp;
2257
2258         if (!test_thread_flag(TIF_IA32))
2259                 return 0;
2260
2261         cs_base = get_segment_base(regs->cs);
2262         ss_base = get_segment_base(regs->ss);
2263
2264         fp = compat_ptr(ss_base + regs->bp);
2265         pagefault_disable();
2266         while (entry->nr < PERF_MAX_STACK_DEPTH) {
2267                 unsigned long bytes;
2268                 frame.next_frame     = 0;
2269                 frame.return_address = 0;
2270
2271                 if (!access_ok(VERIFY_READ, fp, 8))
2272                         break;
2273
2274                 bytes = __copy_from_user_nmi(&frame.next_frame, fp, 4);
2275                 if (bytes != 0)
2276                         break;
2277                 bytes = __copy_from_user_nmi(&frame.return_address, fp+4, 4);
2278                 if (bytes != 0)
2279                         break;
2280
2281                 if (!valid_user_frame(fp, sizeof(frame)))
2282                         break;
2283
2284                 perf_callchain_store(entry, cs_base + frame.return_address);
2285                 fp = compat_ptr(ss_base + frame.next_frame);
2286         }
2287         pagefault_enable();
2288         return 1;
2289 }
2290 #else
2291 static inline int
2292 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
2293 {
2294     return 0;
2295 }
2296 #endif
2297
2298 void
2299 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
2300 {
2301         struct stack_frame frame;
2302         const void __user *fp;
2303
2304         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2305                 /* TODO: We don't support guest os callchain now */
2306                 return;
2307         }
2308
2309         /*
2310          * We don't know what to do with VM86 stacks.. ignore them for now.
2311          */
2312         if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
2313                 return;
2314
2315         fp = (void __user *)regs->bp;
2316
2317         perf_callchain_store(entry, regs->ip);
2318
2319         if (!current->mm)
2320                 return;
2321
2322         if (perf_callchain_user32(regs, entry))
2323                 return;
2324
2325         pagefault_disable();
2326         while (entry->nr < PERF_MAX_STACK_DEPTH) {
2327                 unsigned long bytes;
2328                 frame.next_frame             = NULL;
2329                 frame.return_address = 0;
2330
2331                 if (!access_ok(VERIFY_READ, fp, 16))
2332                         break;
2333
2334                 bytes = __copy_from_user_nmi(&frame.next_frame, fp, 8);
2335                 if (bytes != 0)
2336                         break;
2337                 bytes = __copy_from_user_nmi(&frame.return_address, fp+8, 8);
2338                 if (bytes != 0)
2339                         break;
2340
2341                 if (!valid_user_frame(fp, sizeof(frame)))
2342                         break;
2343
2344                 perf_callchain_store(entry, frame.return_address);
2345                 fp = (void __user *)frame.next_frame;
2346         }
2347         pagefault_enable();
2348 }
2349
2350 /*
2351  * Deal with code segment offsets for the various execution modes:
2352  *
2353  *   VM86 - the good olde 16 bit days, where the linear address is
2354  *          20 bits and we use regs->ip + 0x10 * regs->cs.
2355  *
2356  *   IA32 - Where we need to look at GDT/LDT segment descriptor tables
2357  *          to figure out what the 32bit base address is.
2358  *
2359  *    X32 - has TIF_X32 set, but is running in x86_64
2360  *
2361  * X86_64 - CS,DS,SS,ES are all zero based.
2362  */
2363 static unsigned long code_segment_base(struct pt_regs *regs)
2364 {
2365         /*
2366          * For IA32 we look at the GDT/LDT segment base to convert the
2367          * effective IP to a linear address.
2368          */
2369
2370 #ifdef CONFIG_X86_32
2371         /*
2372          * If we are in VM86 mode, add the segment offset to convert to a
2373          * linear address.
2374          */
2375         if (regs->flags & X86_VM_MASK)
2376                 return 0x10 * regs->cs;
2377
2378         if (user_mode(regs) && regs->cs != __USER_CS)
2379                 return get_segment_base(regs->cs);
2380 #else
2381         if (user_mode(regs) && !user_64bit_mode(regs) &&
2382             regs->cs != __USER32_CS)
2383                 return get_segment_base(regs->cs);
2384 #endif
2385         return 0;
2386 }
2387
2388 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2389 {
2390         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
2391                 return perf_guest_cbs->get_guest_ip();
2392
2393         return regs->ip + code_segment_base(regs);
2394 }
2395
2396 unsigned long perf_misc_flags(struct pt_regs *regs)
2397 {
2398         int misc = 0;
2399
2400         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2401                 if (perf_guest_cbs->is_user_mode())
2402                         misc |= PERF_RECORD_MISC_GUEST_USER;
2403                 else
2404                         misc |= PERF_RECORD_MISC_GUEST_KERNEL;
2405         } else {
2406                 if (user_mode(regs))
2407                         misc |= PERF_RECORD_MISC_USER;
2408                 else
2409                         misc |= PERF_RECORD_MISC_KERNEL;
2410         }
2411
2412         if (regs->flags & PERF_EFLAGS_EXACT)
2413                 misc |= PERF_RECORD_MISC_EXACT_IP;
2414
2415         return misc;
2416 }
2417
2418 void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
2419 {
2420         cap->version            = x86_pmu.version;
2421         cap->num_counters_gp    = x86_pmu.num_counters;
2422         cap->num_counters_fixed = x86_pmu.num_counters_fixed;
2423         cap->bit_width_gp       = x86_pmu.cntval_bits;
2424         cap->bit_width_fixed    = x86_pmu.cntval_bits;
2425         cap->events_mask        = (unsigned int)x86_pmu.events_maskl;
2426         cap->events_mask_len    = x86_pmu.events_mask_len;
2427 }
2428 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);