2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #include <linux/init.h>
43 #include <linux/smp.h>
44 #include <linux/module.h>
45 #include <linux/sched.h>
46 #include <linux/percpu.h>
47 #include <linux/bootmem.h>
48 #include <linux/err.h>
49 #include <linux/nmi.h>
50 #include <linux/tboot.h>
51 #include <linux/stackprotector.h>
52 #include <linux/gfp.h>
59 #include <asm/trampoline.h>
62 #include <asm/pgtable.h>
63 #include <asm/tlbflush.h>
65 #include <asm/mwait.h>
67 #include <asm/io_apic.h>
68 #include <asm/setup.h>
69 #include <asm/uv/uv.h>
70 #include <linux/mc146818rtc.h>
72 #include <asm/smpboot_hooks.h>
73 #include <asm/i8259.h>
75 /* State of each CPU */
76 DEFINE_PER_CPU(int, cpu_state) = { 0 };
78 /* Store all idle threads, this can be reused instead of creating
79 * a new thread. Also avoids complicated thread destroy functionality
82 #ifdef CONFIG_HOTPLUG_CPU
84 * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is
85 * removed after init for !CONFIG_HOTPLUG_CPU.
87 static DEFINE_PER_CPU(struct task_struct *, idle_thread_array);
88 #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x))
89 #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p))
92 * We need this for trampoline_base protection from concurrent accesses when
93 * off- and onlining cores wildly.
95 static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex);
97 void cpu_hotplug_driver_lock(void)
99 mutex_lock(&x86_cpu_hotplug_driver_mutex);
102 void cpu_hotplug_driver_unlock(void)
104 mutex_unlock(&x86_cpu_hotplug_driver_mutex);
107 ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; }
108 ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; }
110 static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ;
111 #define get_idle_for_cpu(x) (idle_thread_array[(x)])
112 #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p))
115 /* Number of siblings per CPU package */
116 int smp_num_siblings = 1;
117 EXPORT_SYMBOL(smp_num_siblings);
119 /* Last level cache ID of each logical CPU */
120 DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID;
122 /* representing HT siblings of each logical CPU */
123 DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map);
124 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
126 /* representing HT and core siblings of each logical CPU */
127 DEFINE_PER_CPU(cpumask_var_t, cpu_core_map);
128 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
130 DEFINE_PER_CPU(cpumask_var_t, cpu_llc_shared_map);
132 /* Per CPU bogomips and other parameters */
133 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
134 EXPORT_PER_CPU_SYMBOL(cpu_info);
136 atomic_t init_deasserted;
139 * Report back to the Boot Processor.
142 static void __cpuinit smp_callin(void)
145 unsigned long timeout;
148 * If waken up by an INIT in an 82489DX configuration
149 * we may get here before an INIT-deassert IPI reaches
150 * our local APIC. We have to wait for the IPI or we'll
151 * lock up on an APIC access.
153 if (apic->wait_for_init_deassert)
154 apic->wait_for_init_deassert(&init_deasserted);
157 * (This works even if the APIC is not enabled.)
159 phys_id = read_apic_id();
160 cpuid = smp_processor_id();
161 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) {
162 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__,
165 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
168 * STARTUP IPIs are fragile beasts as they might sometimes
169 * trigger some glue motherboard logic. Complete APIC bus
170 * silence for 1 second, this overestimates the time the
171 * boot CPU is spending to send the up to 2 STARTUP IPIs
172 * by a factor of two. This should be enough.
176 * Waiting 2s total for startup (udelay is not yet working)
178 timeout = jiffies + 2*HZ;
179 while (time_before(jiffies, timeout)) {
181 * Has the boot CPU finished it's STARTUP sequence?
183 if (cpumask_test_cpu(cpuid, cpu_callout_mask))
188 if (!time_before(jiffies, timeout)) {
189 panic("%s: CPU%d started up but did not get a callout!\n",
194 * the boot CPU has finished the init stage and is spinning
195 * on callin_map until we finish. We are free to set up this
196 * CPU, first the APIC. (this is probably redundant on most
200 pr_debug("CALLIN, before setup_local_APIC().\n");
201 if (apic->smp_callin_clear_local_apic)
202 apic->smp_callin_clear_local_apic();
204 end_local_APIC_setup();
207 * Need to setup vector mappings before we enable interrupts.
209 setup_vector_irq(smp_processor_id());
212 * Save our processor parameters. Note: this information
213 * is needed for clock calibration.
215 smp_store_cpu_info(cpuid);
219 * Update loops_per_jiffy in cpu_data. Previous call to
220 * smp_store_cpu_info() stored a value that is close but not as
221 * accurate as the value just calculated.
224 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
225 pr_debug("Stack at about %p\n", &cpuid);
228 * This must be done before setting cpu_online_mask
229 * or calling notify_cpu_starting.
231 set_cpu_sibling_map(raw_smp_processor_id());
234 notify_cpu_starting(cpuid);
237 * Allow the master to continue.
239 cpumask_set_cpu(cpuid, cpu_callin_mask);
243 * Activate a secondary processor.
245 notrace static void __cpuinit start_secondary(void *unused)
248 * Don't put *anything* before cpu_init(), SMP booting is too
249 * fragile that we want to limit the things done here to the
250 * most necessary things.
257 /* switch away from the initial page table */
258 load_cr3(swapper_pg_dir);
262 /* otherwise gcc will move up smp_processor_id before the cpu_init */
265 * Check TSC synchronization with the BP:
267 check_tsc_sync_target();
270 * We need to hold call_lock, so there is no inconsistency
271 * between the time smp_call_function() determines number of
272 * IPI recipients, and the time when the determination is made
273 * for which cpus receive the IPI. Holding this
274 * lock helps us to not include this cpu in a currently in progress
275 * smp_call_function().
277 * We need to hold vector_lock so there the set of online cpus
278 * does not change while we are assigning vectors to cpus. Holding
279 * this lock ensures we don't half assign or remove an irq from a cpu.
283 set_cpu_online(smp_processor_id(), true);
284 unlock_vector_lock();
286 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
287 x86_platform.nmi_init();
289 /* enable local interrupts */
292 /* to prevent fake stack check failure in clock setup */
293 boot_init_stack_canary();
295 x86_cpuinit.setup_percpu_clockev();
302 * The bootstrap kernel entry code has set these up. Save them for
306 void __cpuinit smp_store_cpu_info(int id)
308 struct cpuinfo_x86 *c = &cpu_data(id);
313 identify_secondary_cpu(c);
316 static void __cpuinit link_thread_siblings(int cpu1, int cpu2)
318 cpumask_set_cpu(cpu1, cpu_sibling_mask(cpu2));
319 cpumask_set_cpu(cpu2, cpu_sibling_mask(cpu1));
320 cpumask_set_cpu(cpu1, cpu_core_mask(cpu2));
321 cpumask_set_cpu(cpu2, cpu_core_mask(cpu1));
322 cpumask_set_cpu(cpu1, cpu_llc_shared_mask(cpu2));
323 cpumask_set_cpu(cpu2, cpu_llc_shared_mask(cpu1));
327 void __cpuinit set_cpu_sibling_map(int cpu)
330 struct cpuinfo_x86 *c = &cpu_data(cpu);
332 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
334 if (smp_num_siblings > 1) {
335 for_each_cpu(i, cpu_sibling_setup_mask) {
336 struct cpuinfo_x86 *o = &cpu_data(i);
338 if (cpu_has(c, X86_FEATURE_TOPOEXT)) {
339 if (c->phys_proc_id == o->phys_proc_id &&
340 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i) &&
341 c->compute_unit_id == o->compute_unit_id)
342 link_thread_siblings(cpu, i);
343 } else if (c->phys_proc_id == o->phys_proc_id &&
344 c->cpu_core_id == o->cpu_core_id) {
345 link_thread_siblings(cpu, i);
349 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
352 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
354 if (__this_cpu_read(cpu_info.x86_max_cores) == 1) {
355 cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu));
360 for_each_cpu(i, cpu_sibling_setup_mask) {
361 if (per_cpu(cpu_llc_id, cpu) != BAD_APICID &&
362 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) {
363 cpumask_set_cpu(i, cpu_llc_shared_mask(cpu));
364 cpumask_set_cpu(cpu, cpu_llc_shared_mask(i));
366 if (c->phys_proc_id == cpu_data(i).phys_proc_id) {
367 cpumask_set_cpu(i, cpu_core_mask(cpu));
368 cpumask_set_cpu(cpu, cpu_core_mask(i));
370 * Does this new cpu bringup a new core?
372 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) {
374 * for each core in package, increment
375 * the booted_cores for this new cpu
377 if (cpumask_first(cpu_sibling_mask(i)) == i)
380 * increment the core count for all
381 * the other cpus in this package
384 cpu_data(i).booted_cores++;
385 } else if (i != cpu && !c->booted_cores)
386 c->booted_cores = cpu_data(i).booted_cores;
391 /* maps the cpu to the sched domain representing multi-core */
392 const struct cpumask *cpu_coregroup_mask(int cpu)
394 struct cpuinfo_x86 *c = &cpu_data(cpu);
396 * For perf, we return last level cache shared map.
397 * And for power savings, we return cpu_core_map
399 if ((sched_mc_power_savings || sched_smt_power_savings) &&
400 !(cpu_has(c, X86_FEATURE_AMD_DCM)))
401 return cpu_core_mask(cpu);
403 return cpu_llc_shared_mask(cpu);
406 static void impress_friends(void)
409 unsigned long bogosum = 0;
411 * Allow the user to impress friends.
413 pr_debug("Before bogomips.\n");
414 for_each_possible_cpu(cpu)
415 if (cpumask_test_cpu(cpu, cpu_callout_mask))
416 bogosum += cpu_data(cpu).loops_per_jiffy;
418 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
421 (bogosum/(5000/HZ))%100);
423 pr_debug("Before bogocount - setting activated=1.\n");
426 void __inquire_remote_apic(int apicid)
428 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
429 const char * const names[] = { "ID", "VERSION", "SPIV" };
433 printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid);
435 for (i = 0; i < ARRAY_SIZE(regs); i++) {
436 printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]);
441 status = safe_apic_wait_icr_idle();
444 "a previous APIC delivery may have failed\n");
446 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
451 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
452 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
455 case APIC_ICR_RR_VALID:
456 status = apic_read(APIC_RRR);
457 printk(KERN_CONT "%08x\n", status);
460 printk(KERN_CONT "failed\n");
466 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
467 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
468 * won't ... remember to clear down the APIC, etc later.
471 wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip)
473 unsigned long send_status, accept_status = 0;
477 /* Boot on the stack */
478 /* Kick the second */
479 apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid);
481 pr_debug("Waiting for send to finish...\n");
482 send_status = safe_apic_wait_icr_idle();
485 * Give the other CPU some time to accept the IPI.
488 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
489 maxlvt = lapic_get_maxlvt();
490 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
491 apic_write(APIC_ESR, 0);
492 accept_status = (apic_read(APIC_ESR) & 0xEF);
494 pr_debug("NMI sent.\n");
497 printk(KERN_ERR "APIC never delivered???\n");
499 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
501 return (send_status | accept_status);
505 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
507 unsigned long send_status, accept_status = 0;
508 int maxlvt, num_starts, j;
510 maxlvt = lapic_get_maxlvt();
513 * Be paranoid about clearing APIC errors.
515 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
516 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
517 apic_write(APIC_ESR, 0);
521 pr_debug("Asserting INIT.\n");
524 * Turn INIT on target chip
529 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
532 pr_debug("Waiting for send to finish...\n");
533 send_status = safe_apic_wait_icr_idle();
537 pr_debug("Deasserting INIT.\n");
541 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
543 pr_debug("Waiting for send to finish...\n");
544 send_status = safe_apic_wait_icr_idle();
547 atomic_set(&init_deasserted, 1);
550 * Should we send STARTUP IPIs ?
552 * Determine this based on the APIC version.
553 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
555 if (APIC_INTEGRATED(apic_version[phys_apicid]))
561 * Paravirt / VMI wants a startup IPI hook here to set up the
562 * target processor state.
564 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
568 * Run STARTUP IPI loop.
570 pr_debug("#startup loops: %d.\n", num_starts);
572 for (j = 1; j <= num_starts; j++) {
573 pr_debug("Sending STARTUP #%d.\n", j);
574 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
575 apic_write(APIC_ESR, 0);
577 pr_debug("After apic_write.\n");
584 /* Boot on the stack */
585 /* Kick the second */
586 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
590 * Give the other CPU some time to accept the IPI.
594 pr_debug("Startup point 1.\n");
596 pr_debug("Waiting for send to finish...\n");
597 send_status = safe_apic_wait_icr_idle();
600 * Give the other CPU some time to accept the IPI.
603 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
604 apic_write(APIC_ESR, 0);
605 accept_status = (apic_read(APIC_ESR) & 0xEF);
606 if (send_status || accept_status)
609 pr_debug("After Startup.\n");
612 printk(KERN_ERR "APIC never delivered???\n");
614 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
616 return (send_status | accept_status);
620 struct work_struct work;
621 struct task_struct *idle;
622 struct completion done;
626 static void __cpuinit do_fork_idle(struct work_struct *work)
628 struct create_idle *c_idle =
629 container_of(work, struct create_idle, work);
631 c_idle->idle = fork_idle(c_idle->cpu);
632 complete(&c_idle->done);
635 /* reduce the number of lines printed when booting a large cpu count system */
636 static void __cpuinit announce_cpu(int cpu, int apicid)
638 static int current_node = -1;
639 int node = early_cpu_to_node(cpu);
641 if (system_state == SYSTEM_BOOTING) {
642 if (node != current_node) {
643 if (current_node > (-1))
646 pr_info("Booting Node %3d, Processors ", node);
648 pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : "");
651 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
656 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
657 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
658 * Returns zero if CPU booted OK, else error code from
659 * ->wakeup_secondary_cpu.
661 static int __cpuinit do_boot_cpu(int apicid, int cpu)
663 unsigned long boot_error = 0;
664 unsigned long start_ip;
666 struct create_idle c_idle = {
668 .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done),
671 INIT_WORK_ONSTACK(&c_idle.work, do_fork_idle);
673 alternatives_smp_switch(1);
675 c_idle.idle = get_idle_for_cpu(cpu);
678 * We can't use kernel_thread since we must avoid to
679 * reschedule the child.
682 c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *)
683 (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1);
684 init_idle(c_idle.idle, cpu);
688 schedule_work(&c_idle.work);
689 wait_for_completion(&c_idle.done);
691 if (IS_ERR(c_idle.idle)) {
692 printk("failed fork for CPU %d\n", cpu);
693 destroy_work_on_stack(&c_idle.work);
694 return PTR_ERR(c_idle.idle);
697 set_idle_for_cpu(cpu, c_idle.idle);
699 per_cpu(current_task, cpu) = c_idle.idle;
701 /* Stack for startup_32 can be just as for start_secondary onwards */
704 clear_tsk_thread_flag(c_idle.idle, TIF_FORK);
705 initial_gs = per_cpu_offset(cpu);
706 per_cpu(kernel_stack, cpu) =
707 (unsigned long)task_stack_page(c_idle.idle) -
708 KERNEL_STACK_OFFSET + THREAD_SIZE;
710 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
711 initial_code = (unsigned long)start_secondary;
712 stack_start = c_idle.idle->thread.sp;
714 /* start_ip had better be page-aligned! */
715 start_ip = trampoline_address();
717 /* So we see what's up */
718 announce_cpu(cpu, apicid);
721 * This grunge runs the startup process for
722 * the targeted processor.
725 printk(KERN_DEBUG "smpboot cpu %d: start_ip = %lx\n", cpu, start_ip);
727 atomic_set(&init_deasserted, 0);
729 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
731 pr_debug("Setting warm reset code and vector.\n");
733 smpboot_setup_warm_reset_vector(start_ip);
735 * Be paranoid about clearing APIC errors.
737 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
738 apic_write(APIC_ESR, 0);
744 * Kick the secondary CPU. Use the method in the APIC driver
745 * if it's defined - or use an INIT boot APIC message otherwise:
747 if (apic->wakeup_secondary_cpu)
748 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
750 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
754 * allow APs to start initializing.
756 pr_debug("Before Callout %d.\n", cpu);
757 cpumask_set_cpu(cpu, cpu_callout_mask);
758 pr_debug("After Callout %d.\n", cpu);
761 * Wait 5s total for a response
763 for (timeout = 0; timeout < 50000; timeout++) {
764 if (cpumask_test_cpu(cpu, cpu_callin_mask))
765 break; /* It has booted */
768 * Allow other tasks to run while we wait for the
769 * AP to come online. This also gives a chance
770 * for the MTRR work(triggered by the AP coming online)
771 * to be completed in the stop machine context.
776 if (cpumask_test_cpu(cpu, cpu_callin_mask))
777 pr_debug("CPU%d: has booted.\n", cpu);
780 if (*(volatile u32 *)TRAMPOLINE_SYM(trampoline_status)
782 /* trampoline started but...? */
783 pr_err("CPU%d: Stuck ??\n", cpu);
785 /* trampoline code not run */
786 pr_err("CPU%d: Not responding.\n", cpu);
787 if (apic->inquire_remote_apic)
788 apic->inquire_remote_apic(apicid);
793 /* Try to put things back the way they were before ... */
794 numa_remove_cpu(cpu); /* was set by numa_add_cpu */
796 /* was set by do_boot_cpu() */
797 cpumask_clear_cpu(cpu, cpu_callout_mask);
799 /* was set by cpu_init() */
800 cpumask_clear_cpu(cpu, cpu_initialized_mask);
802 set_cpu_present(cpu, false);
803 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID;
806 /* mark "stuck" area as not stuck */
807 *(volatile u32 *)TRAMPOLINE_SYM(trampoline_status) = 0;
809 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
811 * Cleanup possible dangling ends...
813 smpboot_restore_warm_reset_vector();
816 destroy_work_on_stack(&c_idle.work);
820 int __cpuinit native_cpu_up(unsigned int cpu)
822 int apicid = apic->cpu_present_to_apicid(cpu);
826 WARN_ON(irqs_disabled());
828 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
830 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid ||
831 !physid_isset(apicid, phys_cpu_present_map) ||
832 (!x2apic_mode && apicid >= 255)) {
833 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu);
838 * Already booted CPU?
840 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
841 pr_debug("do_boot_cpu %d Already started\n", cpu);
846 * Save current MTRR state in case it was changed since early boot
847 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
851 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
853 err = do_boot_cpu(apicid, cpu);
855 pr_debug("do_boot_cpu failed %d\n", err);
860 * Check TSC synchronization with the AP (keep irqs disabled
863 local_irq_save(flags);
864 check_tsc_sync_source(cpu);
865 local_irq_restore(flags);
867 while (!cpu_online(cpu)) {
869 touch_nmi_watchdog();
876 * arch_disable_smp_support() - disables SMP support for x86 at runtime
878 void arch_disable_smp_support(void)
880 disable_ioapic_support();
884 * Fall back to non SMP mode after errors.
886 * RED-PEN audit/test this more. I bet there is more state messed up here.
888 static __init void disable_smp(void)
890 init_cpu_present(cpumask_of(0));
891 init_cpu_possible(cpumask_of(0));
892 smpboot_clear_io_apic_irqs();
894 if (smp_found_config)
895 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
897 physid_set_mask_of_physid(0, &phys_cpu_present_map);
898 cpumask_set_cpu(0, cpu_sibling_mask(0));
899 cpumask_set_cpu(0, cpu_core_mask(0));
903 * Various sanity checks.
905 static int __init smp_sanity_check(unsigned max_cpus)
909 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
910 if (def_to_bigsmp && nr_cpu_ids > 8) {
915 "More than 8 CPUs detected - skipping them.\n"
916 "Use CONFIG_X86_BIGSMP.\n");
919 for_each_present_cpu(cpu) {
921 set_cpu_present(cpu, false);
926 for_each_possible_cpu(cpu) {
928 set_cpu_possible(cpu, false);
936 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
938 "weird, boot CPU (#%d) not listed by the BIOS.\n",
939 hard_smp_processor_id());
941 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
945 * If we couldn't find an SMP configuration at boot time,
946 * get out of here now!
948 if (!smp_found_config && !acpi_lapic) {
950 printk(KERN_NOTICE "SMP motherboard not detected.\n");
952 if (APIC_init_uniprocessor())
953 printk(KERN_NOTICE "Local APIC not detected."
954 " Using dummy APIC emulation.\n");
959 * Should not be necessary because the MP table should list the boot
960 * CPU too, but we do it for the sake of robustness anyway.
962 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
964 "weird, boot CPU (#%d) not listed by the BIOS.\n",
965 boot_cpu_physical_apicid);
966 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
971 * If we couldn't find a local APIC, then get out of here now!
973 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
976 pr_err("BIOS bug, local APIC #%d not detected!...\n",
977 boot_cpu_physical_apicid);
978 pr_err("... forcing use of dummy APIC emulation."
979 "(tell your hw vendor)\n");
981 smpboot_clear_io_apic();
982 disable_ioapic_support();
989 * If SMP should be disabled, then really disable it!
992 printk(KERN_INFO "SMP mode deactivated.\n");
993 smpboot_clear_io_apic();
997 bsp_end_local_APIC_setup();
1004 static void __init smp_cpu_index_default(void)
1007 struct cpuinfo_x86 *c;
1009 for_each_possible_cpu(i) {
1011 /* mark all to hotplug */
1012 c->cpu_index = nr_cpu_ids;
1017 * Prepare for SMP bootup. The MP table or ACPI has been read
1018 * earlier. Just do some sanity checking here and enable APIC mode.
1020 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1025 smp_cpu_index_default();
1028 * Setup boot CPU information
1030 smp_store_cpu_info(0); /* Final full version of the data */
1031 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1034 current_thread_info()->cpu = 0; /* needed? */
1035 for_each_possible_cpu(i) {
1036 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1037 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1038 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1040 set_cpu_sibling_map(0);
1043 if (smp_sanity_check(max_cpus) < 0) {
1044 printk(KERN_INFO "SMP disabled\n");
1049 default_setup_apic_routing();
1052 if (read_apic_id() != boot_cpu_physical_apicid) {
1053 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1054 read_apic_id(), boot_cpu_physical_apicid);
1055 /* Or can we switch back to PIC here? */
1062 * Switch from PIC to APIC mode.
1067 * Enable IO APIC before setting up error vector
1069 if (!skip_ioapic_setup && nr_ioapics)
1072 bsp_end_local_APIC_setup();
1074 if (apic->setup_portio_remap)
1075 apic->setup_portio_remap();
1077 smpboot_setup_io_apic();
1079 * Set up local APIC timer on boot CPU.
1082 printk(KERN_INFO "CPU%d: ", 0);
1083 print_cpu_info(&cpu_data(0));
1084 x86_init.timers.setup_percpu_clockev();
1089 set_mtrr_aps_delayed_init();
1094 void arch_disable_nonboot_cpus_begin(void)
1097 * Avoid the smp alternatives switch during the disable_nonboot_cpus().
1098 * In the suspend path, we will be back in the SMP mode shortly anyways.
1100 skip_smp_alternatives = true;
1103 void arch_disable_nonboot_cpus_end(void)
1105 skip_smp_alternatives = false;
1108 void arch_enable_nonboot_cpus_begin(void)
1110 set_mtrr_aps_delayed_init();
1113 void arch_enable_nonboot_cpus_end(void)
1119 * Early setup to make printk work.
1121 void __init native_smp_prepare_boot_cpu(void)
1123 int me = smp_processor_id();
1124 switch_to_new_gdt(me);
1125 /* already set me in cpu_online_mask in boot_cpu_init() */
1126 cpumask_set_cpu(me, cpu_callout_mask);
1127 per_cpu(cpu_state, me) = CPU_ONLINE;
1130 void __init native_smp_cpus_done(unsigned int max_cpus)
1132 pr_debug("Boot done.\n");
1136 #ifdef CONFIG_X86_IO_APIC
1137 setup_ioapic_dest();
1142 static int __initdata setup_possible_cpus = -1;
1143 static int __init _setup_possible_cpus(char *str)
1145 get_option(&str, &setup_possible_cpus);
1148 early_param("possible_cpus", _setup_possible_cpus);
1152 * cpu_possible_mask should be static, it cannot change as cpu's
1153 * are onlined, or offlined. The reason is per-cpu data-structures
1154 * are allocated by some modules at init time, and dont expect to
1155 * do this dynamically on cpu arrival/departure.
1156 * cpu_present_mask on the other hand can change dynamically.
1157 * In case when cpu_hotplug is not compiled, then we resort to current
1158 * behaviour, which is cpu_possible == cpu_present.
1161 * Three ways to find out the number of additional hotplug CPUs:
1162 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1163 * - The user can overwrite it with possible_cpus=NUM
1164 * - Otherwise don't reserve additional CPUs.
1165 * We do this because additional CPUs waste a lot of memory.
1168 __init void prefill_possible_map(void)
1172 /* no processor from mptable or madt */
1173 if (!num_processors)
1176 i = setup_max_cpus ?: 1;
1177 if (setup_possible_cpus == -1) {
1178 possible = num_processors;
1179 #ifdef CONFIG_HOTPLUG_CPU
1181 possible += disabled_cpus;
1187 possible = setup_possible_cpus;
1189 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1191 /* nr_cpu_ids could be reduced via nr_cpus= */
1192 if (possible > nr_cpu_ids) {
1194 "%d Processors exceeds NR_CPUS limit of %d\n",
1195 possible, nr_cpu_ids);
1196 possible = nr_cpu_ids;
1199 #ifdef CONFIG_HOTPLUG_CPU
1200 if (!setup_max_cpus)
1204 "%d Processors exceeds max_cpus limit of %u\n",
1205 possible, setup_max_cpus);
1209 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n",
1210 possible, max_t(int, possible - num_processors, 0));
1212 for (i = 0; i < possible; i++)
1213 set_cpu_possible(i, true);
1214 for (; i < NR_CPUS; i++)
1215 set_cpu_possible(i, false);
1217 nr_cpu_ids = possible;
1220 #ifdef CONFIG_HOTPLUG_CPU
1222 static void remove_siblinginfo(int cpu)
1225 struct cpuinfo_x86 *c = &cpu_data(cpu);
1227 for_each_cpu(sibling, cpu_core_mask(cpu)) {
1228 cpumask_clear_cpu(cpu, cpu_core_mask(sibling));
1230 * last thread sibling in this cpu core going down
1232 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1)
1233 cpu_data(sibling).booted_cores--;
1236 for_each_cpu(sibling, cpu_sibling_mask(cpu))
1237 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling));
1238 cpumask_clear(cpu_sibling_mask(cpu));
1239 cpumask_clear(cpu_core_mask(cpu));
1240 c->phys_proc_id = 0;
1242 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1245 static void __ref remove_cpu_from_maps(int cpu)
1247 set_cpu_online(cpu, false);
1248 cpumask_clear_cpu(cpu, cpu_callout_mask);
1249 cpumask_clear_cpu(cpu, cpu_callin_mask);
1250 /* was set by cpu_init() */
1251 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1252 numa_remove_cpu(cpu);
1255 void cpu_disable_common(void)
1257 int cpu = smp_processor_id();
1259 remove_siblinginfo(cpu);
1261 /* It's now safe to remove this processor from the online map */
1263 remove_cpu_from_maps(cpu);
1264 unlock_vector_lock();
1268 int native_cpu_disable(void)
1270 int cpu = smp_processor_id();
1273 * Perhaps use cpufreq to drop frequency, but that could go
1274 * into generic code.
1276 * We won't take down the boot processor on i386 due to some
1277 * interrupts only being able to be serviced by the BSP.
1278 * Especially so if we're not using an IOAPIC -zwane
1285 cpu_disable_common();
1289 void native_cpu_die(unsigned int cpu)
1291 /* We don't do anything here: idle task is faking death itself. */
1294 for (i = 0; i < 10; i++) {
1295 /* They ack this in play_dead by setting CPU_DEAD */
1296 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1297 if (system_state == SYSTEM_RUNNING)
1298 pr_info("CPU %u is now offline\n", cpu);
1300 if (1 == num_online_cpus())
1301 alternatives_smp_switch(0);
1306 pr_err("CPU %u didn't die...\n", cpu);
1309 void play_dead_common(void)
1312 reset_lazy_tlbstate();
1313 amd_e400_remove_cpu(raw_smp_processor_id());
1317 __this_cpu_write(cpu_state, CPU_DEAD);
1320 * With physical CPU hotplug, we should halt the cpu
1322 local_irq_disable();
1326 * We need to flush the caches before going to sleep, lest we have
1327 * dirty data in our caches when we come back up.
1329 static inline void mwait_play_dead(void)
1331 unsigned int eax, ebx, ecx, edx;
1332 unsigned int highest_cstate = 0;
1333 unsigned int highest_subcstate = 0;
1336 struct cpuinfo_x86 *c = __this_cpu_ptr(&cpu_info);
1338 if (!(this_cpu_has(X86_FEATURE_MWAIT) && mwait_usable(c)))
1340 if (!this_cpu_has(X86_FEATURE_CLFLSH))
1342 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1345 eax = CPUID_MWAIT_LEAF;
1347 native_cpuid(&eax, &ebx, &ecx, &edx);
1350 * eax will be 0 if EDX enumeration is not valid.
1351 * Initialized below to cstate, sub_cstate value when EDX is valid.
1353 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1356 edx >>= MWAIT_SUBSTATE_SIZE;
1357 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1358 if (edx & MWAIT_SUBSTATE_MASK) {
1360 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1363 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1364 (highest_subcstate - 1);
1368 * This should be a memory location in a cache line which is
1369 * unlikely to be touched by other processors. The actual
1370 * content is immaterial as it is not actually modified in any way.
1372 mwait_ptr = ¤t_thread_info()->flags;
1378 * The CLFLUSH is a workaround for erratum AAI65 for
1379 * the Xeon 7400 series. It's not clear it is actually
1380 * needed, but it should be harmless in either case.
1381 * The WBINVD is insufficient due to the spurious-wakeup
1382 * case where we return around the loop.
1385 __monitor(mwait_ptr, 0, 0);
1391 static inline void hlt_play_dead(void)
1393 if (__this_cpu_read(cpu_info.x86) >= 4)
1401 void native_play_dead(void)
1404 tboot_shutdown(TB_SHUTDOWN_WFS);
1406 mwait_play_dead(); /* Only returns on failure */
1410 #else /* ... !CONFIG_HOTPLUG_CPU */
1411 int native_cpu_disable(void)
1416 void native_cpu_die(unsigned int cpu)
1418 /* We said "no" in __cpu_disable */
1422 void native_play_dead(void)