arch/x86/kvm/lapic.c

   1
   2 /*
   3  * Local APIC virtualization
   4  *
   5  * Copyright (C) 2006 Qumranet, Inc.
   6  * Copyright (C) 2007 Novell
   7  * Copyright (C) 2007 Intel
   8  * Copyright 2009 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Dor Laor <dor.laor@qumranet.com>
  12  *   Gregory Haskins <ghaskins@novell.com>
  13  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
  14  *
  15  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  16  *
  17  * This work is licensed under the terms of the GNU GPL, version 2.  See
  18  * the COPYING file in the top-level directory.
  19  */
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/kvm.h>
  23 #include <linux/mm.h>
  24 #include <linux/highmem.h>
  25 #include <linux/smp.h>
  26 #include <linux/hrtimer.h>
  27 #include <linux/io.h>
  28 #include <linux/module.h>
  29 #include <linux/math64.h>
  30 #include <linux/slab.h>
  31 #include <asm/processor.h>
  32 #include <asm/msr.h>
  33 #include <asm/page.h>
  34 #include <asm/current.h>
  35 #include <asm/apicdef.h>
  36 #include <asm/delay.h>
  37 #include <linux/atomic.h>
  38 #include <linux/jump_label.h>
  39 #include "kvm_cache_regs.h"
  40 #include "irq.h"
  41 #include "trace.h"
  42 #include "x86.h"
  43 #include "cpuid.h"
  44 #include "hyperv.h"
  45
  46 #ifndef CONFIG_X86_64
  47 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
  48 #else
  49 #define mod_64(x, y) ((x) % (y))
  50 #endif
  51
  52 #define PRId64 "d"
  53 #define PRIx64 "llx"
  54 #define PRIu64 "u"
  55 #define PRIo64 "o"
  56
  57 #define APIC_BUS_CYCLE_NS 1
  58
  59 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
  60 #define apic_debug(fmt, arg...)
  61
  62 #define APIC_LVT_NUM                    6
  63 /* 14 is the version for Xeon and Pentium 8.4.8*/
  64 #define APIC_VERSION                    (0x14UL | ((APIC_LVT_NUM - 1) << 16))
  65 #define LAPIC_MMIO_LENGTH               (1 << 12)
  66 /* followed define is not in apicdef.h */
  67 #define APIC_SHORT_MASK                 0xc0000
  68 #define APIC_DEST_NOSHORT               0x0
  69 #define APIC_DEST_MASK                  0x800
  70 #define MAX_APIC_VECTOR                 256
  71 #define APIC_VECTORS_PER_REG            32
  72
  73 #define APIC_BROADCAST                  0xFF
  74 #define X2APIC_BROADCAST                0xFFFFFFFFul
  75
  76 #define VEC_POS(v) ((v) & (32 - 1))
  77 #define REG_POS(v) (((v) >> 5) << 4)
  78
  79 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
  80 {
  81         *((u32 *) (apic->regs + reg_off)) = val;
  82 }
  83
  84 static inline int apic_test_vector(int vec, void *bitmap)
  85 {
  86         return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  87 }
  88
  89 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
  90 {
  91         struct kvm_lapic *apic = vcpu->arch.apic;
  92
  93         return apic_test_vector(vector, apic->regs + APIC_ISR) ||
  94                 apic_test_vector(vector, apic->regs + APIC_IRR);
  95 }
  96
  97 static inline void apic_set_vector(int vec, void *bitmap)
  98 {
  99         set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 100 }
 101
 102 static inline void apic_clear_vector(int vec, void *bitmap)
 103 {
 104         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 105 }
 106
 107 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
 108 {
 109         return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 110 }
 111
 112 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
 113 {
 114         return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 115 }
 116
 117 struct static_key_deferred apic_hw_disabled __read_mostly;
 118 struct static_key_deferred apic_sw_disabled __read_mostly;
 119
 120 static inline int apic_enabled(struct kvm_lapic *apic)
 121 {
 122         return kvm_apic_sw_enabled(apic) &&     kvm_apic_hw_enabled(apic);
 123 }
 124
 125 #define LVT_MASK        \
 126         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
 127
 128 #define LINT_MASK       \
 129         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
 130          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 131
 132 /* The logical map is definitely wrong if we have multiple
 133  * modes at the same time.  (Physical map is always right.)
 134  */
 135 static inline bool kvm_apic_logical_map_valid(struct kvm_apic_map *map)
 136 {
 137         return !(map->mode & (map->mode - 1));
 138 }
 139
 140 static inline void
 141 apic_logical_id(struct kvm_apic_map *map, u32 dest_id, u16 *cid, u16 *lid)
 142 {
 143         unsigned lid_bits;
 144
 145         BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_CLUSTER !=  4);
 146         BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_FLAT    !=  8);
 147         BUILD_BUG_ON(KVM_APIC_MODE_X2APIC        != 16);
 148         lid_bits = map->mode;
 149
 150         *cid = dest_id >> lid_bits;
 151         *lid = dest_id & ((1 << lid_bits) - 1);
 152 }
 153
 154 static void recalculate_apic_map(struct kvm *kvm)
 155 {
 156         struct kvm_apic_map *new, *old = NULL;
 157         struct kvm_vcpu *vcpu;
 158         int i;
 159
 160         new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);
 161
 162         mutex_lock(&kvm->arch.apic_map_lock);
 163
 164         if (!new)
 165                 goto out;
 166
 167         kvm_for_each_vcpu(i, vcpu, kvm) {
 168                 struct kvm_lapic *apic = vcpu->arch.apic;
 169                 u16 cid, lid;
 170                 u32 ldr, aid;
 171
 172                 if (!kvm_apic_present(vcpu))
 173                         continue;
 174
 175                 aid = kvm_apic_id(apic);
 176                 ldr = kvm_apic_get_reg(apic, APIC_LDR);
 177
 178                 if (aid < ARRAY_SIZE(new->phys_map))
 179                         new->phys_map[aid] = apic;
 180
 181                 if (apic_x2apic_mode(apic)) {
 182                         new->mode |= KVM_APIC_MODE_X2APIC;
 183                 } else if (ldr) {
 184                         ldr = GET_APIC_LOGICAL_ID(ldr);
 185                         if (kvm_apic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
 186                                 new->mode |= KVM_APIC_MODE_XAPIC_FLAT;
 187                         else
 188                                 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER;
 189                 }
 190
 191                 if (!kvm_apic_logical_map_valid(new))
 192                         continue;
 193
 194                 apic_logical_id(new, ldr, &cid, &lid);
 195
 196                 if (lid && cid < ARRAY_SIZE(new->logical_map))
 197                         new->logical_map[cid][ffs(lid) - 1] = apic;
 198         }
 199 out:
 200         old = rcu_dereference_protected(kvm->arch.apic_map,
 201                         lockdep_is_held(&kvm->arch.apic_map_lock));
 202         rcu_assign_pointer(kvm->arch.apic_map, new);
 203         mutex_unlock(&kvm->arch.apic_map_lock);
 204
 205         if (old)
 206                 kfree_rcu(old, rcu);
 207
 208         kvm_make_scan_ioapic_request(kvm);
 209 }
 210
 211 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
 212 {
 213         bool enabled = val & APIC_SPIV_APIC_ENABLED;
 214
 215         apic_set_reg(apic, APIC_SPIV, val);
 216
 217         if (enabled != apic->sw_enabled) {
 218                 apic->sw_enabled = enabled;
 219                 if (enabled) {
 220                         static_key_slow_dec_deferred(&apic_sw_disabled);
 221                         recalculate_apic_map(apic->vcpu->kvm);
 222                 } else
 223                         static_key_slow_inc(&apic_sw_disabled.key);
 224         }
 225 }
 226
 227 static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
 228 {
 229         apic_set_reg(apic, APIC_ID, id << 24);
 230         recalculate_apic_map(apic->vcpu->kvm);
 231 }
 232
 233 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
 234 {
 235         apic_set_reg(apic, APIC_LDR, id);
 236         recalculate_apic_map(apic->vcpu->kvm);
 237 }
 238
 239 static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u8 id)
 240 {
 241         u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
 242
 243         apic_set_reg(apic, APIC_ID, id << 24);
 244         apic_set_reg(apic, APIC_LDR, ldr);
 245         recalculate_apic_map(apic->vcpu->kvm);
 246 }
 247
 248 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 249 {
 250         return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 251 }
 252
 253 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
 254 {
 255         return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
 256 }
 257
 258 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
 259 {
 260         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
 261 }
 262
 263 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 264 {
 265         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
 266 }
 267
 268 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
 269 {
 270         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
 271 }
 272
 273 static inline int apic_lvt_nmi_mode(u32 lvt_val)
 274 {
 275         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
 276 }
 277
 278 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
 279 {
 280         struct kvm_lapic *apic = vcpu->arch.apic;
 281         struct kvm_cpuid_entry2 *feat;
 282         u32 v = APIC_VERSION;
 283
 284         if (!kvm_vcpu_has_lapic(vcpu))
 285                 return;
 286
 287         feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
 288         if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
 289                 v |= APIC_LVR_DIRECTED_EOI;
 290         apic_set_reg(apic, APIC_LVR, v);
 291 }
 292
 293 static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
 294         LVT_MASK ,      /* part LVTT mask, timer mode mask added at runtime */
 295         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
 296         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
 297         LINT_MASK, LINT_MASK,   /* LVT0-1 */
 298         LVT_MASK                /* LVTERR */
 299 };
 300
 301 static int find_highest_vector(void *bitmap)
 302 {
 303         int vec;
 304         u32 *reg;
 305
 306         for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
 307              vec >= 0; vec -= APIC_VECTORS_PER_REG) {
 308                 reg = bitmap + REG_POS(vec);
 309                 if (*reg)
 310                         return fls(*reg) - 1 + vec;
 311         }
 312
 313         return -1;
 314 }
 315
 316 static u8 count_vectors(void *bitmap)
 317 {
 318         int vec;
 319         u32 *reg;
 320         u8 count = 0;
 321
 322         for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
 323                 reg = bitmap + REG_POS(vec);
 324                 count += hweight32(*reg);
 325         }
 326
 327         return count;
 328 }
 329
 330 void __kvm_apic_update_irr(u32 *pir, void *regs)
 331 {
 332         u32 i, pir_val;
 333
 334         for (i = 0; i <= 7; i++) {
 335                 pir_val = xchg(&pir[i], 0);
 336                 if (pir_val)
 337                         *((u32 *)(regs + APIC_IRR + i * 0x10)) |= pir_val;
 338         }
 339 }
 340 EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
 341
 342 void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
 343 {
 344         struct kvm_lapic *apic = vcpu->arch.apic;
 345
 346         __kvm_apic_update_irr(pir, apic->regs);
 347
 348         kvm_make_request(KVM_REQ_EVENT, vcpu);
 349 }
 350 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
 351
 352 static inline void apic_set_irr(int vec, struct kvm_lapic *apic)
 353 {
 354         apic_set_vector(vec, apic->regs + APIC_IRR);
 355         /*
 356          * irr_pending must be true if any interrupt is pending; set it after
 357          * APIC_IRR to avoid race with apic_clear_irr
 358          */
 359         apic->irr_pending = true;
 360 }
 361
 362 static inline int apic_search_irr(struct kvm_lapic *apic)
 363 {
 364         return find_highest_vector(apic->regs + APIC_IRR);
 365 }
 366
 367 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 368 {
 369         int result;
 370
 371         /*
 372          * Note that irr_pending is just a hint. It will be always
 373          * true with virtual interrupt delivery enabled.
 374          */
 375         if (!apic->irr_pending)
 376                 return -1;
 377
 378         if (apic->vcpu->arch.apicv_active)
 379                 kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
 380         result = apic_search_irr(apic);
 381         ASSERT(result == -1 || result >= 16);
 382
 383         return result;
 384 }
 385
 386 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 387 {
 388         struct kvm_vcpu *vcpu;
 389
 390         vcpu = apic->vcpu;
 391
 392         if (unlikely(vcpu->arch.apicv_active)) {
 393                 /* try to update RVI */
 394                 apic_clear_vector(vec, apic->regs + APIC_IRR);
 395                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 396         } else {
 397                 apic->irr_pending = false;
 398                 apic_clear_vector(vec, apic->regs + APIC_IRR);
 399                 if (apic_search_irr(apic) != -1)
 400                         apic->irr_pending = true;
 401         }
 402 }
 403
 404 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
 405 {
 406         struct kvm_vcpu *vcpu;
 407
 408         if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
 409                 return;
 410
 411         vcpu = apic->vcpu;
 412
 413         /*
 414          * With APIC virtualization enabled, all caching is disabled
 415          * because the processor can modify ISR under the hood.  Instead
 416          * just set SVI.
 417          */
 418         if (unlikely(vcpu->arch.apicv_active))
 419                 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, vec);
 420         else {
 421                 ++apic->isr_count;
 422                 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
 423                 /*
 424                  * ISR (in service register) bit is set when injecting an interrupt.
 425                  * The highest vector is injected. Thus the latest bit set matches
 426                  * the highest bit in ISR.
 427                  */
 428                 apic->highest_isr_cache = vec;
 429         }
 430 }
 431
 432 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 433 {
 434         int result;
 435
 436         /*
 437          * Note that isr_count is always 1, and highest_isr_cache
 438          * is always -1, with APIC virtualization enabled.
 439          */
 440         if (!apic->isr_count)
 441                 return -1;
 442         if (likely(apic->highest_isr_cache != -1))
 443                 return apic->highest_isr_cache;
 444
 445         result = find_highest_vector(apic->regs + APIC_ISR);
 446         ASSERT(result == -1 || result >= 16);
 447
 448         return result;
 449 }
 450
 451 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
 452 {
 453         struct kvm_vcpu *vcpu;
 454         if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
 455                 return;
 456
 457         vcpu = apic->vcpu;
 458
 459         /*
 460          * We do get here for APIC virtualization enabled if the guest
 461          * uses the Hyper-V APIC enlightenment.  In this case we may need
 462          * to trigger a new interrupt delivery by writing the SVI field;
 463          * on the other hand isr_count and highest_isr_cache are unused
 464          * and must be left alone.
 465          */
 466         if (unlikely(vcpu->arch.apicv_active))
 467                 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
 468                                                apic_find_highest_isr(apic));
 469         else {
 470                 --apic->isr_count;
 471                 BUG_ON(apic->isr_count < 0);
 472                 apic->highest_isr_cache = -1;
 473         }
 474 }
 475
 476 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 477 {
 478         /* This may race with setting of irr in __apic_accept_irq() and
 479          * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
 480          * will cause vmexit immediately and the value will be recalculated
 481          * on the next vmentry.
 482          */
 483         return apic_find_highest_irr(vcpu->arch.apic);
 484 }
 485
 486 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 487                              int vector, int level, int trig_mode,
 488                              unsigned long *dest_map);
 489
 490 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
 491                 unsigned long *dest_map)
 492 {
 493         struct kvm_lapic *apic = vcpu->arch.apic;
 494
 495         return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
 496                         irq->level, irq->trig_mode, dest_map);
 497 }
 498
 499 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
 500 {
 501
 502         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
 503                                       sizeof(val));
 504 }
 505
 506 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
 507 {
 508
 509         return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
 510                                       sizeof(*val));
 511 }
 512
 513 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
 514 {
 515         return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
 516 }
 517
 518 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
 519 {
 520         u8 val;
 521         if (pv_eoi_get_user(vcpu, &val) < 0)
 522                 apic_debug("Can't read EOI MSR value: 0x%llx\n",
 523                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 524         return val & 0x1;
 525 }
 526
 527 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
 528 {
 529         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
 530                 apic_debug("Can't set EOI MSR value: 0x%llx\n",
 531                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 532                 return;
 533         }
 534         __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 535 }
 536
 537 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
 538 {
 539         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
 540                 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
 541                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 542                 return;
 543         }
 544         __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 545 }
 546
 547 static void apic_update_ppr(struct kvm_lapic *apic)
 548 {
 549         u32 tpr, isrv, ppr, old_ppr;
 550         int isr;
 551
 552         old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
 553         tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
 554         isr = apic_find_highest_isr(apic);
 555         isrv = (isr != -1) ? isr : 0;
 556
 557         if ((tpr & 0xf0) >= (isrv & 0xf0))
 558                 ppr = tpr & 0xff;
 559         else
 560                 ppr = isrv & 0xf0;
 561
 562         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
 563                    apic, ppr, isr, isrv);
 564
 565         if (old_ppr != ppr) {
 566                 apic_set_reg(apic, APIC_PROCPRI, ppr);
 567                 if (ppr < old_ppr)
 568                         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 569         }
 570 }
 571
 572 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
 573 {
 574         apic_set_reg(apic, APIC_TASKPRI, tpr);
 575         apic_update_ppr(apic);
 576 }
 577
 578 static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
 579 {
 580         if (apic_x2apic_mode(apic))
 581                 return mda == X2APIC_BROADCAST;
 582
 583         return GET_APIC_DEST_FIELD(mda) == APIC_BROADCAST;
 584 }
 585
 586 static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
 587 {
 588         if (kvm_apic_broadcast(apic, mda))
 589                 return true;
 590
 591         if (apic_x2apic_mode(apic))
 592                 return mda == kvm_apic_id(apic);
 593
 594         return mda == SET_APIC_DEST_FIELD(kvm_apic_id(apic));
 595 }
 596
 597 static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
 598 {
 599         u32 logical_id;
 600
 601         if (kvm_apic_broadcast(apic, mda))
 602                 return true;
 603
 604         logical_id = kvm_apic_get_reg(apic, APIC_LDR);
 605
 606         if (apic_x2apic_mode(apic))
 607                 return ((logical_id >> 16) == (mda >> 16))
 608                        && (logical_id & mda & 0xffff) != 0;
 609
 610         logical_id = GET_APIC_LOGICAL_ID(logical_id);
 611         mda = GET_APIC_DEST_FIELD(mda);
 612
 613         switch (kvm_apic_get_reg(apic, APIC_DFR)) {
 614         case APIC_DFR_FLAT:
 615                 return (logical_id & mda) != 0;
 616         case APIC_DFR_CLUSTER:
 617                 return ((logical_id >> 4) == (mda >> 4))
 618                        && (logical_id & mda & 0xf) != 0;
 619         default:
 620                 apic_debug("Bad DFR vcpu %d: %08x\n",
 621                            apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
 622                 return false;
 623         }
 624 }
 625
 626 /* KVM APIC implementation has two quirks
 627  *  - dest always begins at 0 while xAPIC MDA has offset 24,
 628  *  - IOxAPIC messages have to be delivered (directly) to x2APIC.
 629  */
 630 static u32 kvm_apic_mda(unsigned int dest_id, struct kvm_lapic *source,
 631                                               struct kvm_lapic *target)
 632 {
 633         bool ipi = source != NULL;
 634         bool x2apic_mda = apic_x2apic_mode(ipi ? source : target);
 635
 636         if (!ipi && dest_id == APIC_BROADCAST && x2apic_mda)
 637                 return X2APIC_BROADCAST;
 638
 639         return x2apic_mda ? dest_id : SET_APIC_DEST_FIELD(dest_id);
 640 }
 641
 642 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 643                            int short_hand, unsigned int dest, int dest_mode)
 644 {
 645         struct kvm_lapic *target = vcpu->arch.apic;
 646         u32 mda = kvm_apic_mda(dest, source, target);
 647
 648         apic_debug("target %p, source %p, dest 0x%x, "
 649                    "dest_mode 0x%x, short_hand 0x%x\n",
 650                    target, source, dest, dest_mode, short_hand);
 651
 652         ASSERT(target);
 653         switch (short_hand) {
 654         case APIC_DEST_NOSHORT:
 655                 if (dest_mode == APIC_DEST_PHYSICAL)
 656                         return kvm_apic_match_physical_addr(target, mda);
 657                 else
 658                         return kvm_apic_match_logical_addr(target, mda);
 659         case APIC_DEST_SELF:
 660                 return target == source;
 661         case APIC_DEST_ALLINC:
 662                 return true;
 663         case APIC_DEST_ALLBUT:
 664                 return target != source;
 665         default:
 666                 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
 667                            short_hand);
 668                 return false;
 669         }
 670 }
 671
 672 int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
 673                        const unsigned long *bitmap, u32 bitmap_size)
 674 {
 675         u32 mod;
 676         int i, idx = -1;
 677
 678         mod = vector % dest_vcpus;
 679
 680         for (i = 0; i <= mod; i++) {
 681                 idx = find_next_bit(bitmap, bitmap_size, idx + 1);
 682                 BUG_ON(idx == bitmap_size);
 683         }
 684
 685         return idx;
 686 }
 687
 688 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
 689                 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map)
 690 {
 691         struct kvm_apic_map *map;
 692         unsigned long bitmap = 1;
 693         struct kvm_lapic **dst;
 694         int i;
 695         bool ret, x2apic_ipi;
 696
 697         *r = -1;
 698
 699         if (irq->shorthand == APIC_DEST_SELF) {
 700                 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
 701                 return true;
 702         }
 703
 704         if (irq->shorthand)
 705                 return false;
 706
 707         x2apic_ipi = src && apic_x2apic_mode(src);
 708         if (irq->dest_id == (x2apic_ipi ? X2APIC_BROADCAST : APIC_BROADCAST))
 709                 return false;
 710
 711         ret = true;
 712         rcu_read_lock();
 713         map = rcu_dereference(kvm->arch.apic_map);
 714
 715         if (!map) {
 716                 ret = false;
 717                 goto out;
 718         }
 719
 720         if (irq->dest_mode == APIC_DEST_PHYSICAL) {
 721                 if (irq->dest_id >= ARRAY_SIZE(map->phys_map))
 722                         goto out;
 723
 724                 dst = &map->phys_map[irq->dest_id];
 725         } else {
 726                 u16 cid;
 727
 728                 if (!kvm_apic_logical_map_valid(map)) {
 729                         ret = false;
 730                         goto out;
 731                 }
 732
 733                 apic_logical_id(map, irq->dest_id, &cid, (u16 *)&bitmap);
 734
 735                 if (cid >= ARRAY_SIZE(map->logical_map))
 736                         goto out;
 737
 738                 dst = map->logical_map[cid];
 739
 740                 if (!kvm_lowest_prio_delivery(irq))
 741                         goto set_irq;
 742
 743                 if (!kvm_vector_hashing_enabled()) {
 744                         int l = -1;
 745                         for_each_set_bit(i, &bitmap, 16) {
 746                                 if (!dst[i])
 747                                         continue;
 748                                 if (l < 0)
 749                                         l = i;
 750                                 else if (kvm_apic_compare_prio(dst[i]->vcpu,
 751                                                         dst[l]->vcpu) < 0)
 752                                         l = i;
 753                         }
 754                         bitmap = (l >= 0) ? 1 << l : 0;
 755                 } else {
 756                         int idx;
 757                         unsigned int dest_vcpus;
 758
 759                         dest_vcpus = hweight16(bitmap);
 760                         if (dest_vcpus == 0)
 761                                 goto out;
 762
 763                         idx = kvm_vector_to_index(irq->vector,
 764                                 dest_vcpus, &bitmap, 16);
 765
 766                         /*
 767                          * We may find a hardware disabled LAPIC here, if that
 768                          * is the case, print out a error message once for each
 769                          * guest and return.
 770                          */
 771                         if (!dst[idx] && !kvm->arch.disabled_lapic_found) {
 772                                 kvm->arch.disabled_lapic_found = true;
 773                                 printk(KERN_INFO
 774                                         "Disabled LAPIC found during irq injection\n");
 775                                 goto out;
 776                         }
 777
 778                         bitmap = (idx >= 0) ? 1 << idx : 0;
 779                 }
 780         }
 781
 782 set_irq:
 783         for_each_set_bit(i, &bitmap, 16) {
 784                 if (!dst[i])
 785                         continue;
 786                 if (*r < 0)
 787                         *r = 0;
 788                 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
 789         }
 790 out:
 791         rcu_read_unlock();
 792         return ret;
 793 }
 794
 795 /*
 796  * This routine tries to handler interrupts in posted mode, here is how
 797  * it deals with different cases:
 798  * - For single-destination interrupts, handle it in posted mode
 799  * - Else if vector hashing is enabled and it is a lowest-priority
 800  *   interrupt, handle it in posted mode and use the following mechanism
 801  *   to find the destinaiton vCPU.
 802  *      1. For lowest-priority interrupts, store all the possible
 803  *         destination vCPUs in an array.
 804  *      2. Use "guest vector % max number of destination vCPUs" to find
 805  *         the right destination vCPU in the array for the lowest-priority
 806  *         interrupt.
 807  * - Otherwise, use remapped mode to inject the interrupt.
 808  */
 809 bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
 810                         struct kvm_vcpu **dest_vcpu)
 811 {
 812         struct kvm_apic_map *map;
 813         bool ret = false;
 814         struct kvm_lapic *dst = NULL;
 815
 816         if (irq->shorthand)
 817                 return false;
 818
 819         rcu_read_lock();
 820         map = rcu_dereference(kvm->arch.apic_map);
 821
 822         if (!map)
 823                 goto out;
 824
 825         if (irq->dest_mode == APIC_DEST_PHYSICAL) {
 826                 if (irq->dest_id == 0xFF)
 827                         goto out;
 828
 829                 if (irq->dest_id >= ARRAY_SIZE(map->phys_map))
 830                         goto out;
 831
 832                 dst = map->phys_map[irq->dest_id];
 833                 if (dst && kvm_apic_present(dst->vcpu))
 834                         *dest_vcpu = dst->vcpu;
 835                 else
 836                         goto out;
 837         } else {
 838                 u16 cid;
 839                 unsigned long bitmap = 1;
 840                 int i, r = 0;
 841
 842                 if (!kvm_apic_logical_map_valid(map))
 843                         goto out;
 844
 845                 apic_logical_id(map, irq->dest_id, &cid, (u16 *)&bitmap);
 846
 847                 if (cid >= ARRAY_SIZE(map->logical_map))
 848                         goto out;
 849
 850                 if (kvm_vector_hashing_enabled() &&
 851                                 kvm_lowest_prio_delivery(irq)) {
 852                         int idx;
 853                         unsigned int dest_vcpus;
 854
 855                         dest_vcpus = hweight16(bitmap);
 856                         if (dest_vcpus == 0)
 857                                 goto out;
 858
 859                         idx = kvm_vector_to_index(irq->vector, dest_vcpus,
 860                                                   &bitmap, 16);
 861
 862                         /*
 863                          * We may find a hardware disabled LAPIC here, if that
 864                          * is the case, print out a error message once for each
 865                          * guest and return
 866                          */
 867                         dst = map->logical_map[cid][idx];
 868                         if (!dst && !kvm->arch.disabled_lapic_found) {
 869                                 kvm->arch.disabled_lapic_found = true;
 870                                 printk(KERN_INFO
 871                                         "Disabled LAPIC found during irq injection\n");
 872                                 goto out;
 873                         }
 874
 875                         *dest_vcpu = dst->vcpu;
 876                 } else {
 877                         for_each_set_bit(i, &bitmap, 16) {
 878                                 dst = map->logical_map[cid][i];
 879                                 if (++r == 2)
 880                                         goto out;
 881                         }
 882
 883                         if (dst && kvm_apic_present(dst->vcpu))
 884                                 *dest_vcpu = dst->vcpu;
 885                         else
 886                                 goto out;
 887                 }
 888         }
 889
 890         ret = true;
 891 out:
 892         rcu_read_unlock();
 893         return ret;
 894 }
 895
 896 /*
 897  * Add a pending IRQ into lapic.
 898  * Return 1 if successfully added and 0 if discarded.
 899  */
 900 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 901                              int vector, int level, int trig_mode,
 902                              unsigned long *dest_map)
 903 {
 904         int result = 0;
 905         struct kvm_vcpu *vcpu = apic->vcpu;
 906
 907         trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
 908                                   trig_mode, vector);
 909         switch (delivery_mode) {
 910         case APIC_DM_LOWEST:
 911                 vcpu->arch.apic_arb_prio++;
 912         case APIC_DM_FIXED:
 913                 if (unlikely(trig_mode && !level))
 914                         break;
 915
 916                 /* FIXME add logic for vcpu on reset */
 917                 if (unlikely(!apic_enabled(apic)))
 918                         break;
 919
 920                 result = 1;
 921
 922                 if (dest_map)
 923                         __set_bit(vcpu->vcpu_id, dest_map);
 924
 925                 if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) {
 926                         if (trig_mode)
 927                                 apic_set_vector(vector, apic->regs + APIC_TMR);
 928                         else
 929                                 apic_clear_vector(vector, apic->regs + APIC_TMR);
 930                 }
 931
 932                 if (vcpu->arch.apicv_active)
 933                         kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
 934                 else {
 935                         apic_set_irr(vector, apic);
 936
 937                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 938                         kvm_vcpu_kick(vcpu);
 939                 }
 940                 break;
 941
 942         case APIC_DM_REMRD:
 943                 result = 1;
 944                 vcpu->arch.pv.pv_unhalted = 1;
 945                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 946                 kvm_vcpu_kick(vcpu);
 947                 break;
 948
 949         case APIC_DM_SMI:
 950                 result = 1;
 951                 kvm_make_request(KVM_REQ_SMI, vcpu);
 952                 kvm_vcpu_kick(vcpu);
 953                 break;
 954
 955         case APIC_DM_NMI:
 956                 result = 1;
 957                 kvm_inject_nmi(vcpu);
 958                 kvm_vcpu_kick(vcpu);
 959                 break;
 960
 961         case APIC_DM_INIT:
 962                 if (!trig_mode || level) {
 963                         result = 1;
 964                         /* assumes that there are only KVM_APIC_INIT/SIPI */
 965                         apic->pending_events = (1UL << KVM_APIC_INIT);
 966                         /* make sure pending_events is visible before sending
 967                          * the request */
 968                         smp_wmb();
 969                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 970                         kvm_vcpu_kick(vcpu);
 971                 } else {
 972                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
 973                                    vcpu->vcpu_id);
 974                 }
 975                 break;
 976
 977         case APIC_DM_STARTUP:
 978                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
 979                            vcpu->vcpu_id, vector);
 980                 result = 1;
 981                 apic->sipi_vector = vector;
 982                 /* make sure sipi_vector is visible for the receiver */
 983                 smp_wmb();
 984                 set_bit(KVM_APIC_SIPI, &apic->pending_events);
 985                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 986                 kvm_vcpu_kick(vcpu);
 987                 break;
 988
 989         case APIC_DM_EXTINT:
 990                 /*
 991                  * Should only be called by kvm_apic_local_deliver() with LVT0,
 992                  * before NMI watchdog was enabled. Already handled by
 993                  * kvm_apic_accept_pic_intr().
 994                  */
 995                 break;
 996
 997         default:
 998                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
 999                        delivery_mode);
1000                 break;
1001         }
1002         return result;
1003 }
1004
1005 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
1006 {
1007         return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
1008 }
1009
1010 static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector)
1011 {
1012         return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors);
1013 }
1014
1015 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
1016 {
1017         int trigger_mode;
1018
1019         /* Eoi the ioapic only if the ioapic doesn't own the vector. */
1020         if (!kvm_ioapic_handles_vector(apic, vector))
1021                 return;
1022
1023         /* Request a KVM exit to inform the userspace IOAPIC. */
1024         if (irqchip_split(apic->vcpu->kvm)) {
1025                 apic->vcpu->arch.pending_ioapic_eoi = vector;
1026                 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu);
1027                 return;
1028         }
1029
1030         if (apic_test_vector(vector, apic->regs + APIC_TMR))
1031                 trigger_mode = IOAPIC_LEVEL_TRIG;
1032         else
1033                 trigger_mode = IOAPIC_EDGE_TRIG;
1034
1035         kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
1036 }
1037
1038 static int apic_set_eoi(struct kvm_lapic *apic)
1039 {
1040         int vector = apic_find_highest_isr(apic);
1041
1042         trace_kvm_eoi(apic, vector);
1043
1044         /*
1045          * Not every write EOI will has corresponding ISR,
1046          * one example is when Kernel check timer on setup_IO_APIC
1047          */
1048         if (vector == -1)
1049                 return vector;
1050
1051         apic_clear_isr(vector, apic);
1052         apic_update_ppr(apic);
1053
1054         if (test_bit(vector, vcpu_to_synic(apic->vcpu)->vec_bitmap))
1055                 kvm_hv_synic_send_eoi(apic->vcpu, vector);
1056
1057         kvm_ioapic_send_eoi(apic, vector);
1058         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1059         return vector;
1060 }
1061
1062 /*
1063  * this interface assumes a trap-like exit, which has already finished
1064  * desired side effect including vISR and vPPR update.
1065  */
1066 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
1067 {
1068         struct kvm_lapic *apic = vcpu->arch.apic;
1069
1070         trace_kvm_eoi(apic, vector);
1071
1072         kvm_ioapic_send_eoi(apic, vector);
1073         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1074 }
1075 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
1076
1077 static void apic_send_ipi(struct kvm_lapic *apic)
1078 {
1079         u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
1080         u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
1081         struct kvm_lapic_irq irq;
1082
1083         irq.vector = icr_low & APIC_VECTOR_MASK;
1084         irq.delivery_mode = icr_low & APIC_MODE_MASK;
1085         irq.dest_mode = icr_low & APIC_DEST_MASK;
1086         irq.level = (icr_low & APIC_INT_ASSERT) != 0;
1087         irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
1088         irq.shorthand = icr_low & APIC_SHORT_MASK;
1089         irq.msi_redir_hint = false;
1090         if (apic_x2apic_mode(apic))
1091                 irq.dest_id = icr_high;
1092         else
1093                 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
1094
1095         trace_kvm_apic_ipi(icr_low, irq.dest_id);
1096
1097         apic_debug("icr_high 0x%x, icr_low 0x%x, "
1098                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
1099                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, "
1100                    "msi_redir_hint 0x%x\n",
1101                    icr_high, icr_low, irq.shorthand, irq.dest_id,
1102                    irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
1103                    irq.vector, irq.msi_redir_hint);
1104
1105         kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
1106 }
1107
1108 static u32 apic_get_tmcct(struct kvm_lapic *apic)
1109 {
1110         ktime_t remaining;
1111         s64 ns;
1112         u32 tmcct;
1113
1114         ASSERT(apic != NULL);
1115
1116         /* if initial count is 0, current count should also be 0 */
1117         if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 ||
1118                 apic->lapic_timer.period == 0)
1119                 return 0;
1120
1121         remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
1122         if (ktime_to_ns(remaining) < 0)
1123                 remaining = ktime_set(0, 0);
1124
1125         ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
1126         tmcct = div64_u64(ns,
1127                          (APIC_BUS_CYCLE_NS * apic->divide_count));
1128
1129         return tmcct;
1130 }
1131
1132 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
1133 {
1134         struct kvm_vcpu *vcpu = apic->vcpu;
1135         struct kvm_run *run = vcpu->run;
1136
1137         kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
1138         run->tpr_access.rip = kvm_rip_read(vcpu);
1139         run->tpr_access.is_write = write;
1140 }
1141
1142 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
1143 {
1144         if (apic->vcpu->arch.tpr_access_reporting)
1145                 __report_tpr_access(apic, write);
1146 }
1147
1148 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
1149 {
1150         u32 val = 0;
1151
1152         if (offset >= LAPIC_MMIO_LENGTH)
1153                 return 0;
1154
1155         switch (offset) {
1156         case APIC_ID:
1157                 if (apic_x2apic_mode(apic))
1158                         val = kvm_apic_id(apic);
1159                 else
1160                         val = kvm_apic_id(apic) << 24;
1161                 break;
1162         case APIC_ARBPRI:
1163                 apic_debug("Access APIC ARBPRI register which is for P6\n");
1164                 break;
1165
1166         case APIC_TMCCT:        /* Timer CCR */
1167                 if (apic_lvtt_tscdeadline(apic))
1168                         return 0;
1169
1170                 val = apic_get_tmcct(apic);
1171                 break;
1172         case APIC_PROCPRI:
1173                 apic_update_ppr(apic);
1174                 val = kvm_apic_get_reg(apic, offset);
1175                 break;
1176         case APIC_TASKPRI:
1177                 report_tpr_access(apic, false);
1178                 /* fall thru */
1179         default:
1180                 val = kvm_apic_get_reg(apic, offset);
1181                 break;
1182         }
1183
1184         return val;
1185 }
1186
1187 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1188 {
1189         return container_of(dev, struct kvm_lapic, dev);
1190 }
1191
1192 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1193                 void *data)
1194 {
1195         unsigned char alignment = offset & 0xf;
1196         u32 result;
1197         /* this bitmask has a bit cleared for each reserved register */
1198         static const u64 rmask = 0x43ff01ffffffe70cULL;
1199
1200         if ((alignment + len) > 4) {
1201                 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1202                            offset, len);
1203                 return 1;
1204         }
1205
1206         if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
1207                 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1208                            offset);
1209                 return 1;
1210         }
1211
1212         result = __apic_read(apic, offset & ~0xf);
1213
1214         trace_kvm_apic_read(offset, result);
1215
1216         switch (len) {
1217         case 1:
1218         case 2:
1219         case 4:
1220                 memcpy(data, (char *)&result + alignment, len);
1221                 break;
1222         default:
1223                 printk(KERN_ERR "Local APIC read with len = %x, "
1224                        "should be 1,2, or 4 instead\n", len);
1225                 break;
1226         }
1227         return 0;
1228 }
1229
1230 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1231 {
1232         return kvm_apic_hw_enabled(apic) &&
1233             addr >= apic->base_address &&
1234             addr < apic->base_address + LAPIC_MMIO_LENGTH;
1235 }
1236
1237 static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1238                            gpa_t address, int len, void *data)
1239 {
1240         struct kvm_lapic *apic = to_lapic(this);
1241         u32 offset = address - apic->base_address;
1242
1243         if (!apic_mmio_in_range(apic, address))
1244                 return -EOPNOTSUPP;
1245
1246         apic_reg_read(apic, offset, len, data);
1247
1248         return 0;
1249 }
1250
1251 static void update_divide_count(struct kvm_lapic *apic)
1252 {
1253         u32 tmp1, tmp2, tdcr;
1254
1255         tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
1256         tmp1 = tdcr & 0xf;
1257         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1258         apic->divide_count = 0x1 << (tmp2 & 0x7);
1259
1260         apic_debug("timer divide count is 0x%x\n",
1261                                    apic->divide_count);
1262 }
1263
1264 static void apic_update_lvtt(struct kvm_lapic *apic)
1265 {
1266         u32 timer_mode = kvm_apic_get_reg(apic, APIC_LVTT) &
1267                         apic->lapic_timer.timer_mode_mask;
1268
1269         if (apic->lapic_timer.timer_mode != timer_mode) {
1270                 apic->lapic_timer.timer_mode = timer_mode;
1271                 hrtimer_cancel(&apic->lapic_timer.timer);
1272         }
1273 }
1274
1275 static void apic_timer_expired(struct kvm_lapic *apic)
1276 {
1277         struct kvm_vcpu *vcpu = apic->vcpu;
1278         wait_queue_head_t *q = &vcpu->wq;
1279         struct kvm_timer *ktimer = &apic->lapic_timer;
1280
1281         if (atomic_read(&apic->lapic_timer.pending))
1282                 return;
1283
1284         atomic_inc(&apic->lapic_timer.pending);
1285         kvm_set_pending_timer(vcpu);
1286
1287         if (waitqueue_active(q))
1288                 wake_up_interruptible(q);
1289
1290         if (apic_lvtt_tscdeadline(apic))
1291                 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1292 }
1293
1294 /*
1295  * On APICv, this test will cause a busy wait
1296  * during a higher-priority task.
1297  */
1298
1299 static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1300 {
1301         struct kvm_lapic *apic = vcpu->arch.apic;
1302         u32 reg = kvm_apic_get_reg(apic, APIC_LVTT);
1303
1304         if (kvm_apic_hw_enabled(apic)) {
1305                 int vec = reg & APIC_VECTOR_MASK;
1306                 void *bitmap = apic->regs + APIC_ISR;
1307
1308                 if (vcpu->arch.apicv_active)
1309                         bitmap = apic->regs + APIC_IRR;
1310
1311                 if (apic_test_vector(vec, bitmap))
1312                         return true;
1313         }
1314         return false;
1315 }
1316
1317 void wait_lapic_expire(struct kvm_vcpu *vcpu)
1318 {
1319         struct kvm_lapic *apic = vcpu->arch.apic;
1320         u64 guest_tsc, tsc_deadline;
1321
1322         if (!kvm_vcpu_has_lapic(vcpu))
1323                 return;
1324
1325         if (apic->lapic_timer.expired_tscdeadline == 0)
1326                 return;
1327
1328         if (!lapic_timer_int_injected(vcpu))
1329                 return;
1330
1331         tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1332         apic->lapic_timer.expired_tscdeadline = 0;
1333         guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1334         trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline);
1335
1336         /* __delay is delay_tsc whenever the hardware has TSC, thus always.  */
1337         if (guest_tsc < tsc_deadline)
1338                 __delay(tsc_deadline - guest_tsc);
1339 }
1340
1341 static void start_apic_timer(struct kvm_lapic *apic)
1342 {
1343         ktime_t now;
1344
1345         atomic_set(&apic->lapic_timer.pending, 0);
1346
1347         if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
1348                 /* lapic timer in oneshot or periodic mode */
1349                 now = apic->lapic_timer.timer.base->get_time();
1350                 apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
1351                             * APIC_BUS_CYCLE_NS * apic->divide_count;
1352
1353                 if (!apic->lapic_timer.period)
1354                         return;
1355                 /*
1356                  * Do not allow the guest to program periodic timers with small
1357                  * interval, since the hrtimers are not throttled by the host
1358                  * scheduler.
1359                  */
1360                 if (apic_lvtt_period(apic)) {
1361                         s64 min_period = min_timer_period_us * 1000LL;
1362
1363                         if (apic->lapic_timer.period < min_period) {
1364                                 pr_info_ratelimited(
1365                                     "kvm: vcpu %i: requested %lld ns "
1366                                     "lapic timer period limited to %lld ns\n",
1367                                     apic->vcpu->vcpu_id,
1368                                     apic->lapic_timer.period, min_period);
1369                                 apic->lapic_timer.period = min_period;
1370                         }
1371                 }
1372
1373                 hrtimer_start(&apic->lapic_timer.timer,
1374                               ktime_add_ns(now, apic->lapic_timer.period),
1375                               HRTIMER_MODE_ABS);
1376
1377                 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1378                            PRIx64 ", "
1379                            "timer initial count 0x%x, period %lldns, "
1380                            "expire @ 0x%016" PRIx64 ".\n", __func__,
1381                            APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1382                            kvm_apic_get_reg(apic, APIC_TMICT),
1383                            apic->lapic_timer.period,
1384                            ktime_to_ns(ktime_add_ns(now,
1385                                         apic->lapic_timer.period)));
1386         } else if (apic_lvtt_tscdeadline(apic)) {
1387                 /* lapic timer in tsc deadline mode */
1388                 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1389                 u64 ns = 0;
1390                 ktime_t expire;
1391                 struct kvm_vcpu *vcpu = apic->vcpu;
1392                 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1393                 unsigned long flags;
1394
1395                 if (unlikely(!tscdeadline || !this_tsc_khz))
1396                         return;
1397
1398                 local_irq_save(flags);
1399
1400                 now = apic->lapic_timer.timer.base->get_time();
1401                 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1402                 if (likely(tscdeadline > guest_tsc)) {
1403                         ns = (tscdeadline - guest_tsc) * 1000000ULL;
1404                         do_div(ns, this_tsc_khz);
1405                         expire = ktime_add_ns(now, ns);
1406                         expire = ktime_sub_ns(expire, lapic_timer_advance_ns);
1407                         hrtimer_start(&apic->lapic_timer.timer,
1408                                       expire, HRTIMER_MODE_ABS);
1409                 } else
1410                         apic_timer_expired(apic);
1411
1412                 local_irq_restore(flags);
1413         }
1414 }
1415
1416 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1417 {
1418         bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val);
1419
1420         if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) {
1421                 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode;
1422                 if (lvt0_in_nmi_mode) {
1423                         apic_debug("Receive NMI setting on APIC_LVT0 "
1424                                    "for cpu %d\n", apic->vcpu->vcpu_id);
1425                         atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1426                 } else
1427                         atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1428         }
1429 }
1430
1431 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1432 {
1433         int ret = 0;
1434
1435         trace_kvm_apic_write(reg, val);
1436
1437         switch (reg) {
1438         case APIC_ID:           /* Local APIC ID */
1439                 if (!apic_x2apic_mode(apic))
1440                         kvm_apic_set_id(apic, val >> 24);
1441                 else
1442                         ret = 1;
1443                 break;
1444
1445         case APIC_TASKPRI:
1446                 report_tpr_access(apic, true);
1447                 apic_set_tpr(apic, val & 0xff);
1448                 break;
1449
1450         case APIC_EOI:
1451                 apic_set_eoi(apic);
1452                 break;
1453
1454         case APIC_LDR:
1455                 if (!apic_x2apic_mode(apic))
1456                         kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1457                 else
1458                         ret = 1;
1459                 break;
1460
1461         case APIC_DFR:
1462                 if (!apic_x2apic_mode(apic)) {
1463                         apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1464                         recalculate_apic_map(apic->vcpu->kvm);
1465                 } else
1466                         ret = 1;
1467                 break;
1468
1469         case APIC_SPIV: {
1470                 u32 mask = 0x3ff;
1471                 if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1472                         mask |= APIC_SPIV_DIRECTED_EOI;
1473                 apic_set_spiv(apic, val & mask);
1474                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1475                         int i;
1476                         u32 lvt_val;
1477
1478                         for (i = 0; i < APIC_LVT_NUM; i++) {
1479                                 lvt_val = kvm_apic_get_reg(apic,
1480                                                        APIC_LVTT + 0x10 * i);
1481                                 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
1482                                              lvt_val | APIC_LVT_MASKED);
1483                         }
1484                         apic_update_lvtt(apic);
1485                         atomic_set(&apic->lapic_timer.pending, 0);
1486
1487                 }
1488                 break;
1489         }
1490         case APIC_ICR:
1491                 /* No delay here, so we always clear the pending bit */
1492                 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1493                 apic_send_ipi(apic);
1494                 break;
1495
1496         case APIC_ICR2:
1497                 if (!apic_x2apic_mode(apic))
1498                         val &= 0xff000000;
1499                 apic_set_reg(apic, APIC_ICR2, val);
1500                 break;
1501
1502         case APIC_LVT0:
1503                 apic_manage_nmi_watchdog(apic, val);
1504         case APIC_LVTTHMR:
1505         case APIC_LVTPC:
1506         case APIC_LVT1:
1507         case APIC_LVTERR:
1508                 /* TODO: Check vector */
1509                 if (!kvm_apic_sw_enabled(apic))
1510                         val |= APIC_LVT_MASKED;
1511
1512                 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1513                 apic_set_reg(apic, reg, val);
1514
1515                 break;
1516
1517         case APIC_LVTT:
1518                 if (!kvm_apic_sw_enabled(apic))
1519                         val |= APIC_LVT_MASKED;
1520                 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1521                 apic_set_reg(apic, APIC_LVTT, val);
1522                 apic_update_lvtt(apic);
1523                 break;
1524
1525         case APIC_TMICT:
1526                 if (apic_lvtt_tscdeadline(apic))
1527                         break;
1528
1529                 hrtimer_cancel(&apic->lapic_timer.timer);
1530                 apic_set_reg(apic, APIC_TMICT, val);
1531                 start_apic_timer(apic);
1532                 break;
1533
1534         case APIC_TDCR:
1535                 if (val & 4)
1536                         apic_debug("KVM_WRITE:TDCR %x\n", val);
1537                 apic_set_reg(apic, APIC_TDCR, val);
1538                 update_divide_count(apic);
1539                 break;
1540
1541         case APIC_ESR:
1542                 if (apic_x2apic_mode(apic) && val != 0) {
1543                         apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1544                         ret = 1;
1545                 }
1546                 break;
1547
1548         case APIC_SELF_IPI:
1549                 if (apic_x2apic_mode(apic)) {
1550                         apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1551                 } else
1552                         ret = 1;
1553                 break;
1554         default:
1555                 ret = 1;
1556                 break;
1557         }
1558         if (ret)
1559                 apic_debug("Local APIC Write to read-only register %x\n", reg);
1560         return ret;
1561 }
1562
1563 static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1564                             gpa_t address, int len, const void *data)
1565 {
1566         struct kvm_lapic *apic = to_lapic(this);
1567         unsigned int offset = address - apic->base_address;
1568         u32 val;
1569
1570         if (!apic_mmio_in_range(apic, address))
1571                 return -EOPNOTSUPP;
1572
1573         /*
1574          * APIC register must be aligned on 128-bits boundary.
1575          * 32/64/128 bits registers must be accessed thru 32 bits.
1576          * Refer SDM 8.4.1
1577          */
1578         if (len != 4 || (offset & 0xf)) {
1579                 /* Don't shout loud, $infamous_os would cause only noise. */
1580                 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1581                 return 0;
1582         }
1583
1584         val = *(u32*)data;
1585
1586         /* too common printing */
1587         if (offset != APIC_EOI)
1588                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1589                            "0x%x\n", __func__, offset, len, val);
1590
1591         apic_reg_write(apic, offset & 0xff0, val);
1592
1593         return 0;
1594 }
1595
1596 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1597 {
1598         apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1599 }
1600 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1601
1602 /* emulate APIC access in a trap manner */
1603 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1604 {
1605         u32 val = 0;
1606
1607         /* hw has done the conditional check and inst decode */
1608         offset &= 0xff0;
1609
1610         apic_reg_read(vcpu->arch.apic, offset, 4, &val);
1611
1612         /* TODO: optimize to just emulate side effect w/o one more write */
1613         apic_reg_write(vcpu->arch.apic, offset, val);
1614 }
1615 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1616
1617 void kvm_free_lapic(struct kvm_vcpu *vcpu)
1618 {
1619         struct kvm_lapic *apic = vcpu->arch.apic;
1620
1621         if (!vcpu->arch.apic)
1622                 return;
1623
1624         hrtimer_cancel(&apic->lapic_timer.timer);
1625
1626         if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1627                 static_key_slow_dec_deferred(&apic_hw_disabled);
1628
1629         if (!apic->sw_enabled)
1630                 static_key_slow_dec_deferred(&apic_sw_disabled);
1631
1632         if (apic->regs)
1633                 free_page((unsigned long)apic->regs);
1634
1635         kfree(apic);
1636 }
1637
1638 /*
1639  *----------------------------------------------------------------------
1640  * LAPIC interface
1641  *----------------------------------------------------------------------
1642  */
1643
1644 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1645 {
1646         struct kvm_lapic *apic = vcpu->arch.apic;
1647
1648         if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1649                         apic_lvtt_period(apic))
1650                 return 0;
1651
1652         return apic->lapic_timer.tscdeadline;
1653 }
1654
1655 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1656 {
1657         struct kvm_lapic *apic = vcpu->arch.apic;
1658
1659         if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1660                         apic_lvtt_period(apic))
1661                 return;
1662
1663         hrtimer_cancel(&apic->lapic_timer.timer);
1664         apic->lapic_timer.tscdeadline = data;
1665         start_apic_timer(apic);
1666 }
1667
1668 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1669 {
1670         struct kvm_lapic *apic = vcpu->arch.apic;
1671
1672         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1673                      | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
1674 }
1675
1676 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1677 {
1678         u64 tpr;
1679
1680         tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
1681
1682         return (tpr & 0xf0) >> 4;
1683 }
1684
1685 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1686 {
1687         u64 old_value = vcpu->arch.apic_base;
1688         struct kvm_lapic *apic = vcpu->arch.apic;
1689
1690         if (!apic) {
1691                 value |= MSR_IA32_APICBASE_BSP;
1692                 vcpu->arch.apic_base = value;
1693                 return;
1694         }
1695
1696         vcpu->arch.apic_base = value;
1697
1698         /* update jump label if enable bit changes */
1699         if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
1700                 if (value & MSR_IA32_APICBASE_ENABLE)
1701                         static_key_slow_dec_deferred(&apic_hw_disabled);
1702                 else
1703                         static_key_slow_inc(&apic_hw_disabled.key);
1704                 recalculate_apic_map(vcpu->kvm);
1705         }
1706
1707         if ((old_value ^ value) & X2APIC_ENABLE) {
1708                 if (value & X2APIC_ENABLE) {
1709                         kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id);
1710                         kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1711                 } else
1712                         kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
1713         }
1714
1715         apic->base_address = apic->vcpu->arch.apic_base &
1716                              MSR_IA32_APICBASE_BASE;
1717
1718         if ((value & MSR_IA32_APICBASE_ENABLE) &&
1719              apic->base_address != APIC_DEFAULT_PHYS_BASE)
1720                 pr_warn_once("APIC base relocation is unsupported by KVM");
1721
1722         /* with FSB delivery interrupt, we can restart APIC functionality */
1723         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1724                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1725
1726 }
1727
1728 void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
1729 {
1730         struct kvm_lapic *apic;
1731         int i;
1732
1733         apic_debug("%s\n", __func__);
1734
1735         ASSERT(vcpu);
1736         apic = vcpu->arch.apic;
1737         ASSERT(apic != NULL);
1738
1739         /* Stop the timer in case it's a reset to an active apic */
1740         hrtimer_cancel(&apic->lapic_timer.timer);
1741
1742         if (!init_event)
1743                 kvm_apic_set_id(apic, vcpu->vcpu_id);
1744         kvm_apic_set_version(apic->vcpu);
1745
1746         for (i = 0; i < APIC_LVT_NUM; i++)
1747                 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1748         apic_update_lvtt(apic);
1749         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED))
1750                 apic_set_reg(apic, APIC_LVT0,
1751                              SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1752         apic_manage_nmi_watchdog(apic, kvm_apic_get_reg(apic, APIC_LVT0));
1753
1754         apic_set_reg(apic, APIC_DFR, 0xffffffffU);
1755         apic_set_spiv(apic, 0xff);
1756         apic_set_reg(apic, APIC_TASKPRI, 0);
1757         if (!apic_x2apic_mode(apic))
1758                 kvm_apic_set_ldr(apic, 0);
1759         apic_set_reg(apic, APIC_ESR, 0);
1760         apic_set_reg(apic, APIC_ICR, 0);
1761         apic_set_reg(apic, APIC_ICR2, 0);
1762         apic_set_reg(apic, APIC_TDCR, 0);
1763         apic_set_reg(apic, APIC_TMICT, 0);
1764         for (i = 0; i < 8; i++) {
1765                 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1766                 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1767                 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1768         }
1769         apic->irr_pending = vcpu->arch.apicv_active;
1770         apic->isr_count = vcpu->arch.apicv_active ? 1 : 0;
1771         apic->highest_isr_cache = -1;
1772         update_divide_count(apic);
1773         atomic_set(&apic->lapic_timer.pending, 0);
1774         if (kvm_vcpu_is_bsp(vcpu))
1775                 kvm_lapic_set_base(vcpu,
1776                                 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
1777         vcpu->arch.pv_eoi.msr_val = 0;
1778         apic_update_ppr(apic);
1779
1780         vcpu->arch.apic_arb_prio = 0;
1781         vcpu->arch.apic_attention = 0;
1782
1783         apic_debug("%s: vcpu=%p, id=%d, base_msr="
1784                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1785                    vcpu, kvm_apic_id(apic),
1786                    vcpu->arch.apic_base, apic->base_address);
1787 }
1788
1789 /*
1790  *----------------------------------------------------------------------
1791  * timer interface
1792  *----------------------------------------------------------------------
1793  */
1794
1795 static bool lapic_is_periodic(struct kvm_lapic *apic)
1796 {
1797         return apic_lvtt_period(apic);
1798 }
1799
1800 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1801 {
1802         struct kvm_lapic *apic = vcpu->arch.apic;
1803
1804         if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
1805                         apic_lvt_enabled(apic, APIC_LVTT))
1806                 return atomic_read(&apic->lapic_timer.pending);
1807
1808         return 0;
1809 }
1810
1811 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1812 {
1813         u32 reg = kvm_apic_get_reg(apic, lvt_type);
1814         int vector, mode, trig_mode;
1815
1816         if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1817                 vector = reg & APIC_VECTOR_MASK;
1818                 mode = reg & APIC_MODE_MASK;
1819                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1820                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1821                                         NULL);
1822         }
1823         return 0;
1824 }
1825
1826 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1827 {
1828         struct kvm_lapic *apic = vcpu->arch.apic;
1829
1830         if (apic)
1831                 kvm_apic_local_deliver(apic, APIC_LVT0);
1832 }
1833
1834 static const struct kvm_io_device_ops apic_mmio_ops = {
1835         .read     = apic_mmio_read,
1836         .write    = apic_mmio_write,
1837 };
1838
1839 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1840 {
1841         struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
1842         struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
1843
1844         apic_timer_expired(apic);
1845
1846         if (lapic_is_periodic(apic)) {
1847                 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1848                 return HRTIMER_RESTART;
1849         } else
1850                 return HRTIMER_NORESTART;
1851 }
1852
1853 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1854 {
1855         struct kvm_lapic *apic;
1856
1857         ASSERT(vcpu != NULL);
1858         apic_debug("apic_init %d\n", vcpu->vcpu_id);
1859
1860         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1861         if (!apic)
1862                 goto nomem;
1863
1864         vcpu->arch.apic = apic;
1865
1866         apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1867         if (!apic->regs) {
1868                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1869                        vcpu->vcpu_id);
1870                 goto nomem_free_apic;
1871         }
1872         apic->vcpu = vcpu;
1873
1874         hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1875                      HRTIMER_MODE_ABS);
1876         apic->lapic_timer.timer.function = apic_timer_fn;
1877
1878         /*
1879          * APIC is created enabled. This will prevent kvm_lapic_set_base from
1880          * thinking that APIC satet has changed.
1881          */
1882         vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
1883         kvm_lapic_set_base(vcpu,
1884                         APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
1885
1886         static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
1887         kvm_lapic_reset(vcpu, false);
1888         kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1889
1890         return 0;
1891 nomem_free_apic:
1892         kfree(apic);
1893 nomem:
1894         return -ENOMEM;
1895 }
1896
1897 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1898 {
1899         struct kvm_lapic *apic = vcpu->arch.apic;
1900         int highest_irr;
1901
1902         if (!apic_enabled(apic))
1903                 return -1;
1904
1905         apic_update_ppr(apic);
1906         highest_irr = apic_find_highest_irr(apic);
1907         if ((highest_irr == -1) ||
1908             ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
1909                 return -1;
1910         return highest_irr;
1911 }
1912
1913 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1914 {
1915         u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1916         int r = 0;
1917
1918         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
1919                 r = 1;
1920         if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1921             GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1922                 r = 1;
1923         return r;
1924 }
1925
1926 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1927 {
1928         struct kvm_lapic *apic = vcpu->arch.apic;
1929
1930         if (!kvm_vcpu_has_lapic(vcpu))
1931                 return;
1932
1933         if (atomic_read(&apic->lapic_timer.pending) > 0) {
1934                 kvm_apic_local_deliver(apic, APIC_LVTT);
1935                 if (apic_lvtt_tscdeadline(apic))
1936                         apic->lapic_timer.tscdeadline = 0;
1937                 atomic_set(&apic->lapic_timer.pending, 0);
1938         }
1939 }
1940
1941 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1942 {
1943         int vector = kvm_apic_has_interrupt(vcpu);
1944         struct kvm_lapic *apic = vcpu->arch.apic;
1945
1946         if (vector == -1)
1947                 return -1;
1948
1949         /*
1950          * We get here even with APIC virtualization enabled, if doing
1951          * nested virtualization and L1 runs with the "acknowledge interrupt
1952          * on exit" mode.  Then we cannot inject the interrupt via RVI,
1953          * because the process would deliver it through the IDT.
1954          */
1955
1956         apic_set_isr(vector, apic);
1957         apic_update_ppr(apic);
1958         apic_clear_irr(vector, apic);
1959
1960         if (test_bit(vector, vcpu_to_synic(vcpu)->auto_eoi_bitmap)) {
1961                 apic_clear_isr(vector, apic);
1962                 apic_update_ppr(apic);
1963         }
1964
1965         return vector;
1966 }
1967
1968 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
1969                 struct kvm_lapic_state *s)
1970 {
1971         struct kvm_lapic *apic = vcpu->arch.apic;
1972
1973         kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
1974         /* set SPIV separately to get count of SW disabled APICs right */
1975         apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
1976         memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1977         /* call kvm_apic_set_id() to put apic into apic_map */
1978         kvm_apic_set_id(apic, kvm_apic_id(apic));
1979         kvm_apic_set_version(vcpu);
1980
1981         apic_update_ppr(apic);
1982         hrtimer_cancel(&apic->lapic_timer.timer);
1983         apic_update_lvtt(apic);
1984         apic_manage_nmi_watchdog(apic, kvm_apic_get_reg(apic, APIC_LVT0));
1985         update_divide_count(apic);
1986         start_apic_timer(apic);
1987         apic->irr_pending = true;
1988         apic->isr_count = vcpu->arch.apicv_active ?
1989                                 1 : count_vectors(apic->regs + APIC_ISR);
1990         apic->highest_isr_cache = -1;
1991         if (vcpu->arch.apicv_active) {
1992                 kvm_x86_ops->hwapic_irr_update(vcpu,
1993                                 apic_find_highest_irr(apic));
1994                 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
1995                                 apic_find_highest_isr(apic));
1996         }
1997         kvm_make_request(KVM_REQ_EVENT, vcpu);
1998         if (ioapic_in_kernel(vcpu->kvm))
1999                 kvm_rtc_eoi_tracking_restore_one(vcpu);
2000
2001         vcpu->arch.apic_arb_prio = 0;
2002 }
2003
2004 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
2005 {
2006         struct hrtimer *timer;
2007
2008         if (!kvm_vcpu_has_lapic(vcpu))
2009                 return;
2010
2011         timer = &vcpu->arch.apic->lapic_timer.timer;
2012         if (hrtimer_cancel(timer))
2013                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
2014 }
2015
2016 /*
2017  * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
2018  *
2019  * Detect whether guest triggered PV EOI since the
2020  * last entry. If yes, set EOI on guests's behalf.
2021  * Clear PV EOI in guest memory in any case.
2022  */
2023 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
2024                                         struct kvm_lapic *apic)
2025 {
2026         bool pending;
2027         int vector;
2028         /*
2029          * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
2030          * and KVM_PV_EOI_ENABLED in guest memory as follows:
2031          *
2032          * KVM_APIC_PV_EOI_PENDING is unset:
2033          *      -> host disabled PV EOI.
2034          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
2035          *      -> host enabled PV EOI, guest did not execute EOI yet.
2036          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
2037          *      -> host enabled PV EOI, guest executed EOI.
2038          */
2039         BUG_ON(!pv_eoi_enabled(vcpu));
2040         pending = pv_eoi_get_pending(vcpu);
2041         /*
2042          * Clear pending bit in any case: it will be set again on vmentry.
2043          * While this might not be ideal from performance point of view,
2044          * this makes sure pv eoi is only enabled when we know it's safe.
2045          */
2046         pv_eoi_clr_pending(vcpu);
2047         if (pending)
2048                 return;
2049         vector = apic_set_eoi(apic);
2050         trace_kvm_pv_eoi(apic, vector);
2051 }
2052
2053 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
2054 {
2055         u32 data;
2056
2057         if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
2058                 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
2059
2060         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2061                 return;
2062
2063         if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2064                                   sizeof(u32)))
2065                 return;
2066
2067         apic_set_tpr(vcpu->arch.apic, data & 0xff);
2068 }
2069
2070 /*
2071  * apic_sync_pv_eoi_to_guest - called before vmentry
2072  *
2073  * Detect whether it's safe to enable PV EOI and
2074  * if yes do so.
2075  */
2076 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
2077                                         struct kvm_lapic *apic)
2078 {
2079         if (!pv_eoi_enabled(vcpu) ||
2080             /* IRR set or many bits in ISR: could be nested. */
2081             apic->irr_pending ||
2082             /* Cache not set: could be safe but we don't bother. */
2083             apic->highest_isr_cache == -1 ||
2084             /* Need EOI to update ioapic. */
2085             kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) {
2086                 /*
2087                  * PV EOI was disabled by apic_sync_pv_eoi_from_guest
2088                  * so we need not do anything here.
2089                  */
2090                 return;
2091         }
2092
2093         pv_eoi_set_pending(apic->vcpu);
2094 }
2095
2096 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
2097 {
2098         u32 data, tpr;
2099         int max_irr, max_isr;
2100         struct kvm_lapic *apic = vcpu->arch.apic;
2101
2102         apic_sync_pv_eoi_to_guest(vcpu, apic);
2103
2104         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2105                 return;
2106
2107         tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
2108         max_irr = apic_find_highest_irr(apic);
2109         if (max_irr < 0)
2110                 max_irr = 0;
2111         max_isr = apic_find_highest_isr(apic);
2112         if (max_isr < 0)
2113                 max_isr = 0;
2114         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
2115
2116         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2117                                 sizeof(u32));
2118 }
2119
2120 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
2121 {
2122         if (vapic_addr) {
2123                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2124                                         &vcpu->arch.apic->vapic_cache,
2125                                         vapic_addr, sizeof(u32)))
2126                         return -EINVAL;
2127                 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2128         } else {
2129                 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2130         }
2131
2132         vcpu->arch.apic->vapic_addr = vapic_addr;
2133         return 0;
2134 }
2135
2136 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2137 {
2138         struct kvm_lapic *apic = vcpu->arch.apic;
2139         u32 reg = (msr - APIC_BASE_MSR) << 4;
2140
2141         if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2142                 return 1;
2143
2144         if (reg == APIC_ICR2)
2145                 return 1;
2146
2147         /* if this is ICR write vector before command */
2148         if (reg == APIC_ICR)
2149                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2150         return apic_reg_write(apic, reg, (u32)data);
2151 }
2152
2153 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
2154 {
2155         struct kvm_lapic *apic = vcpu->arch.apic;
2156         u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
2157
2158         if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2159                 return 1;
2160
2161         if (reg == APIC_DFR || reg == APIC_ICR2) {
2162                 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
2163                            reg);
2164                 return 1;
2165         }
2166
2167         if (apic_reg_read(apic, reg, 4, &low))
2168                 return 1;
2169         if (reg == APIC_ICR)
2170                 apic_reg_read(apic, APIC_ICR2, 4, &high);
2171
2172         *data = (((u64)high) << 32) | low;
2173
2174         return 0;
2175 }
2176
2177 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
2178 {
2179         struct kvm_lapic *apic = vcpu->arch.apic;
2180
2181         if (!kvm_vcpu_has_lapic(vcpu))
2182                 return 1;
2183
2184         /* if this is ICR write vector before command */
2185         if (reg == APIC_ICR)
2186                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2187         return apic_reg_write(apic, reg, (u32)data);
2188 }
2189
2190 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2191 {
2192         struct kvm_lapic *apic = vcpu->arch.apic;
2193         u32 low, high = 0;
2194
2195         if (!kvm_vcpu_has_lapic(vcpu))
2196                 return 1;
2197
2198         if (apic_reg_read(apic, reg, 4, &low))
2199                 return 1;
2200         if (reg == APIC_ICR)
2201                 apic_reg_read(apic, APIC_ICR2, 4, &high);
2202
2203         *data = (((u64)high) << 32) | low;
2204
2205         return 0;
2206 }
2207
2208 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
2209 {
2210         u64 addr = data & ~KVM_MSR_ENABLED;
2211         if (!IS_ALIGNED(addr, 4))
2212                 return 1;
2213
2214         vcpu->arch.pv_eoi.msr_val = data;
2215         if (!pv_eoi_enabled(vcpu))
2216                 return 0;
2217         return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
2218                                          addr, sizeof(u8));
2219 }
2220
2221 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2222 {
2223         struct kvm_lapic *apic = vcpu->arch.apic;
2224         u8 sipi_vector;
2225         unsigned long pe;
2226
2227         if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events)
2228                 return;
2229
2230         /*
2231          * INITs are latched while in SMM.  Because an SMM CPU cannot
2232          * be in KVM_MP_STATE_INIT_RECEIVED state, just eat SIPIs
2233          * and delay processing of INIT until the next RSM.
2234          */
2235         if (is_smm(vcpu)) {
2236                 WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED);
2237                 if (test_bit(KVM_APIC_SIPI, &apic->pending_events))
2238                         clear_bit(KVM_APIC_SIPI, &apic->pending_events);
2239                 return;
2240         }
2241
2242         pe = xchg(&apic->pending_events, 0);
2243         if (test_bit(KVM_APIC_INIT, &pe)) {
2244                 kvm_lapic_reset(vcpu, true);
2245                 kvm_vcpu_reset(vcpu, true);
2246                 if (kvm_vcpu_is_bsp(apic->vcpu))
2247                         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2248                 else
2249                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2250         }
2251         if (test_bit(KVM_APIC_SIPI, &pe) &&
2252             vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2253                 /* evaluate pending_events before reading the vector */
2254                 smp_rmb();
2255                 sipi_vector = apic->sipi_vector;
2256                 apic_debug("vcpu %d received sipi with vector # %x\n",
2257                          vcpu->vcpu_id, sipi_vector);
2258                 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2259                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2260         }
2261 }
2262
2263 void kvm_lapic_init(void)
2264 {
2265         /* do not patch jump label more than once per second */
2266         jump_label_rate_limit(&apic_hw_disabled, HZ);
2267         jump_label_rate_limit(&apic_sw_disabled, HZ);
2268 }