arch/x86/kvm/lapic.c

   1
   2 /*
   3  * Local APIC virtualization
   4  *
   5  * Copyright (C) 2006 Qumranet, Inc.
   6  * Copyright (C) 2007 Novell
   7  * Copyright (C) 2007 Intel
   8  * Copyright 2009 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Dor Laor <dor.laor@qumranet.com>
  12  *   Gregory Haskins <ghaskins@novell.com>
  13  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
  14  *
  15  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  16  *
  17  * This work is licensed under the terms of the GNU GPL, version 2.  See
  18  * the COPYING file in the top-level directory.
  19  */
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/kvm.h>
  23 #include <linux/mm.h>
  24 #include <linux/highmem.h>
  25 #include <linux/smp.h>
  26 #include <linux/hrtimer.h>
  27 #include <linux/io.h>
  28 #include <linux/module.h>
  29 #include <linux/math64.h>
  30 #include <linux/slab.h>
  31 #include <asm/processor.h>
  32 #include <asm/msr.h>
  33 #include <asm/page.h>
  34 #include <asm/current.h>
  35 #include <asm/apicdef.h>
  36 #include <asm/delay.h>
  37 #include <linux/atomic.h>
  38 #include <linux/jump_label.h>
  39 #include "kvm_cache_regs.h"
  40 #include "irq.h"
  41 #include "trace.h"
  42 #include "x86.h"
  43 #include "cpuid.h"
  44
  45 #ifndef CONFIG_X86_64
  46 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
  47 #else
  48 #define mod_64(x, y) ((x) % (y))
  49 #endif
  50
  51 #define PRId64 "d"
  52 #define PRIx64 "llx"
  53 #define PRIu64 "u"
  54 #define PRIo64 "o"
  55
  56 #define APIC_BUS_CYCLE_NS 1
  57
  58 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
  59 #define apic_debug(fmt, arg...)
  60
  61 #define APIC_LVT_NUM                    6
  62 /* 14 is the version for Xeon and Pentium 8.4.8*/
  63 #define APIC_VERSION                    (0x14UL | ((APIC_LVT_NUM - 1) << 16))
  64 #define LAPIC_MMIO_LENGTH               (1 << 12)
  65 /* followed define is not in apicdef.h */
  66 #define APIC_SHORT_MASK                 0xc0000
  67 #define APIC_DEST_NOSHORT               0x0
  68 #define APIC_DEST_MASK                  0x800
  69 #define MAX_APIC_VECTOR                 256
  70 #define APIC_VECTORS_PER_REG            32
  71
  72 #define APIC_BROADCAST                  0xFF
  73 #define X2APIC_BROADCAST                0xFFFFFFFFul
  74
  75 #define VEC_POS(v) ((v) & (32 - 1))
  76 #define REG_POS(v) (((v) >> 5) << 4)
  77
  78 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
  79 {
  80         *((u32 *) (apic->regs + reg_off)) = val;
  81 }
  82
  83 static inline int apic_test_vector(int vec, void *bitmap)
  84 {
  85         return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  86 }
  87
  88 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
  89 {
  90         struct kvm_lapic *apic = vcpu->arch.apic;
  91
  92         return apic_test_vector(vector, apic->regs + APIC_ISR) ||
  93                 apic_test_vector(vector, apic->regs + APIC_IRR);
  94 }
  95
  96 static inline void apic_set_vector(int vec, void *bitmap)
  97 {
  98         set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  99 }
 100
 101 static inline void apic_clear_vector(int vec, void *bitmap)
 102 {
 103         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 104 }
 105
 106 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
 107 {
 108         return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 109 }
 110
 111 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
 112 {
 113         return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 114 }
 115
 116 struct static_key_deferred apic_hw_disabled __read_mostly;
 117 struct static_key_deferred apic_sw_disabled __read_mostly;
 118
 119 static inline int apic_enabled(struct kvm_lapic *apic)
 120 {
 121         return kvm_apic_sw_enabled(apic) &&     kvm_apic_hw_enabled(apic);
 122 }
 123
 124 #define LVT_MASK        \
 125         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
 126
 127 #define LINT_MASK       \
 128         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
 129          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 130
 131 static inline int kvm_apic_id(struct kvm_lapic *apic)
 132 {
 133         return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
 134 }
 135
 136 static void recalculate_apic_map(struct kvm *kvm)
 137 {
 138         struct kvm_apic_map *new, *old = NULL;
 139         struct kvm_vcpu *vcpu;
 140         int i;
 141
 142         new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);
 143
 144         mutex_lock(&kvm->arch.apic_map_lock);
 145
 146         if (!new)
 147                 goto out;
 148
 149         new->ldr_bits = 8;
 150         /* flat mode is default */
 151         new->cid_shift = 8;
 152         new->cid_mask = 0;
 153         new->lid_mask = 0xff;
 154
 155         kvm_for_each_vcpu(i, vcpu, kvm) {
 156                 struct kvm_lapic *apic = vcpu->arch.apic;
 157
 158                 if (!kvm_apic_present(vcpu))
 159                         continue;
 160
 161                 if (apic_x2apic_mode(apic)) {
 162                         new->ldr_bits = 32;
 163                         new->cid_shift = 16;
 164                         new->cid_mask = new->lid_mask = 0xffff;
 165                 } else if (kvm_apic_get_reg(apic, APIC_LDR)) {
 166                         if (kvm_apic_get_reg(apic, APIC_DFR) ==
 167                                                         APIC_DFR_CLUSTER) {
 168                                 new->cid_shift = 4;
 169                                 new->cid_mask = 0xf;
 170                                 new->lid_mask = 0xf;
 171                         } else {
 172                                 new->cid_shift = 8;
 173                                 new->cid_mask = 0;
 174                                 new->lid_mask = 0xff;
 175                         }
 176                 }
 177
 178                 /*
 179                  * All APICs have to be configured in the same mode by an OS.
 180                  * We take advatage of this while building logical id loockup
 181                  * table. After reset APICs are in software disabled mode, so if
 182                  * we find apic with different setting we assume this is the mode
 183                  * OS wants all apics to be in; build lookup table accordingly.
 184                  */
 185                 if (kvm_apic_sw_enabled(apic))
 186                         break;
 187         }
 188
 189         kvm_for_each_vcpu(i, vcpu, kvm) {
 190                 struct kvm_lapic *apic = vcpu->arch.apic;
 191                 u16 cid, lid;
 192                 u32 ldr, aid;
 193
 194                 if (!kvm_apic_present(vcpu))
 195                         continue;
 196
 197                 aid = kvm_apic_id(apic);
 198                 ldr = kvm_apic_get_reg(apic, APIC_LDR);
 199                 cid = apic_cluster_id(new, ldr);
 200                 lid = apic_logical_id(new, ldr);
 201
 202                 if (aid < ARRAY_SIZE(new->phys_map))
 203                         new->phys_map[aid] = apic;
 204                 if (lid && cid < ARRAY_SIZE(new->logical_map))
 205                         new->logical_map[cid][ffs(lid) - 1] = apic;
 206         }
 207 out:
 208         old = rcu_dereference_protected(kvm->arch.apic_map,
 209                         lockdep_is_held(&kvm->arch.apic_map_lock));
 210         rcu_assign_pointer(kvm->arch.apic_map, new);
 211         mutex_unlock(&kvm->arch.apic_map_lock);
 212
 213         if (old)
 214                 kfree_rcu(old, rcu);
 215
 216         kvm_vcpu_request_scan_ioapic(kvm);
 217 }
 218
 219 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
 220 {
 221         bool enabled = val & APIC_SPIV_APIC_ENABLED;
 222
 223         apic_set_reg(apic, APIC_SPIV, val);
 224
 225         if (enabled != apic->sw_enabled) {
 226                 apic->sw_enabled = enabled;
 227                 if (enabled) {
 228                         static_key_slow_dec_deferred(&apic_sw_disabled);
 229                         recalculate_apic_map(apic->vcpu->kvm);
 230                 } else
 231                         static_key_slow_inc(&apic_sw_disabled.key);
 232         }
 233 }
 234
 235 static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
 236 {
 237         apic_set_reg(apic, APIC_ID, id << 24);
 238         recalculate_apic_map(apic->vcpu->kvm);
 239 }
 240
 241 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
 242 {
 243         apic_set_reg(apic, APIC_LDR, id);
 244         recalculate_apic_map(apic->vcpu->kvm);
 245 }
 246
 247 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 248 {
 249         return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 250 }
 251
 252 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
 253 {
 254         return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
 255 }
 256
 257 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
 258 {
 259         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
 260 }
 261
 262 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 263 {
 264         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
 265 }
 266
 267 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
 268 {
 269         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
 270 }
 271
 272 static inline int apic_lvt_nmi_mode(u32 lvt_val)
 273 {
 274         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
 275 }
 276
 277 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
 278 {
 279         struct kvm_lapic *apic = vcpu->arch.apic;
 280         struct kvm_cpuid_entry2 *feat;
 281         u32 v = APIC_VERSION;
 282
 283         if (!kvm_vcpu_has_lapic(vcpu))
 284                 return;
 285
 286         feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
 287         if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
 288                 v |= APIC_LVR_DIRECTED_EOI;
 289         apic_set_reg(apic, APIC_LVR, v);
 290 }
 291
 292 static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
 293         LVT_MASK ,      /* part LVTT mask, timer mode mask added at runtime */
 294         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
 295         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
 296         LINT_MASK, LINT_MASK,   /* LVT0-1 */
 297         LVT_MASK                /* LVTERR */
 298 };
 299
 300 static int find_highest_vector(void *bitmap)
 301 {
 302         int vec;
 303         u32 *reg;
 304
 305         for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
 306              vec >= 0; vec -= APIC_VECTORS_PER_REG) {
 307                 reg = bitmap + REG_POS(vec);
 308                 if (*reg)
 309                         return fls(*reg) - 1 + vec;
 310         }
 311
 312         return -1;
 313 }
 314
 315 static u8 count_vectors(void *bitmap)
 316 {
 317         int vec;
 318         u32 *reg;
 319         u8 count = 0;
 320
 321         for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
 322                 reg = bitmap + REG_POS(vec);
 323                 count += hweight32(*reg);
 324         }
 325
 326         return count;
 327 }
 328
 329 void __kvm_apic_update_irr(u32 *pir, void *regs)
 330 {
 331         u32 i, pir_val;
 332
 333         for (i = 0; i <= 7; i++) {
 334                 pir_val = xchg(&pir[i], 0);
 335                 if (pir_val)
 336                         *((u32 *)(regs + APIC_IRR + i * 0x10)) |= pir_val;
 337         }
 338 }
 339 EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
 340
 341 void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
 342 {
 343         struct kvm_lapic *apic = vcpu->arch.apic;
 344
 345         __kvm_apic_update_irr(pir, apic->regs);
 346 }
 347 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
 348
 349 static inline void apic_set_irr(int vec, struct kvm_lapic *apic)
 350 {
 351         apic_set_vector(vec, apic->regs + APIC_IRR);
 352         /*
 353          * irr_pending must be true if any interrupt is pending; set it after
 354          * APIC_IRR to avoid race with apic_clear_irr
 355          */
 356         apic->irr_pending = true;
 357 }
 358
 359 static inline int apic_search_irr(struct kvm_lapic *apic)
 360 {
 361         return find_highest_vector(apic->regs + APIC_IRR);
 362 }
 363
 364 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 365 {
 366         int result;
 367
 368         /*
 369          * Note that irr_pending is just a hint. It will be always
 370          * true with virtual interrupt delivery enabled.
 371          */
 372         if (!apic->irr_pending)
 373                 return -1;
 374
 375         kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
 376         result = apic_search_irr(apic);
 377         ASSERT(result == -1 || result >= 16);
 378
 379         return result;
 380 }
 381
 382 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 383 {
 384         struct kvm_vcpu *vcpu;
 385
 386         vcpu = apic->vcpu;
 387
 388         if (unlikely(kvm_apic_vid_enabled(vcpu->kvm))) {
 389                 /* try to update RVI */
 390                 apic_clear_vector(vec, apic->regs + APIC_IRR);
 391                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 392         } else {
 393                 apic->irr_pending = false;
 394                 apic_clear_vector(vec, apic->regs + APIC_IRR);
 395                 if (apic_search_irr(apic) != -1)
 396                         apic->irr_pending = true;
 397         }
 398 }
 399
 400 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
 401 {
 402         struct kvm_vcpu *vcpu;
 403
 404         if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
 405                 return;
 406
 407         vcpu = apic->vcpu;
 408
 409         /*
 410          * With APIC virtualization enabled, all caching is disabled
 411          * because the processor can modify ISR under the hood.  Instead
 412          * just set SVI.
 413          */
 414         if (unlikely(kvm_x86_ops->hwapic_isr_update))
 415                 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, vec);
 416         else {
 417                 ++apic->isr_count;
 418                 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
 419                 /*
 420                  * ISR (in service register) bit is set when injecting an interrupt.
 421                  * The highest vector is injected. Thus the latest bit set matches
 422                  * the highest bit in ISR.
 423                  */
 424                 apic->highest_isr_cache = vec;
 425         }
 426 }
 427
 428 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 429 {
 430         int result;
 431
 432         /*
 433          * Note that isr_count is always 1, and highest_isr_cache
 434          * is always -1, with APIC virtualization enabled.
 435          */
 436         if (!apic->isr_count)
 437                 return -1;
 438         if (likely(apic->highest_isr_cache != -1))
 439                 return apic->highest_isr_cache;
 440
 441         result = find_highest_vector(apic->regs + APIC_ISR);
 442         ASSERT(result == -1 || result >= 16);
 443
 444         return result;
 445 }
 446
 447 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
 448 {
 449         struct kvm_vcpu *vcpu;
 450         if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
 451                 return;
 452
 453         vcpu = apic->vcpu;
 454
 455         /*
 456          * We do get here for APIC virtualization enabled if the guest
 457          * uses the Hyper-V APIC enlightenment.  In this case we may need
 458          * to trigger a new interrupt delivery by writing the SVI field;
 459          * on the other hand isr_count and highest_isr_cache are unused
 460          * and must be left alone.
 461          */
 462         if (unlikely(kvm_x86_ops->hwapic_isr_update))
 463                 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
 464                                                apic_find_highest_isr(apic));
 465         else {
 466                 --apic->isr_count;
 467                 BUG_ON(apic->isr_count < 0);
 468                 apic->highest_isr_cache = -1;
 469         }
 470 }
 471
 472 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 473 {
 474         int highest_irr;
 475
 476         /* This may race with setting of irr in __apic_accept_irq() and
 477          * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
 478          * will cause vmexit immediately and the value will be recalculated
 479          * on the next vmentry.
 480          */
 481         if (!kvm_vcpu_has_lapic(vcpu))
 482                 return 0;
 483         highest_irr = apic_find_highest_irr(vcpu->arch.apic);
 484
 485         return highest_irr;
 486 }
 487
 488 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 489                              int vector, int level, int trig_mode,
 490                              unsigned long *dest_map);
 491
 492 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
 493                 unsigned long *dest_map)
 494 {
 495         struct kvm_lapic *apic = vcpu->arch.apic;
 496
 497         return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
 498                         irq->level, irq->trig_mode, dest_map);
 499 }
 500
 501 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
 502 {
 503
 504         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
 505                                       sizeof(val));
 506 }
 507
 508 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
 509 {
 510
 511         return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
 512                                       sizeof(*val));
 513 }
 514
 515 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
 516 {
 517         return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
 518 }
 519
 520 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
 521 {
 522         u8 val;
 523         if (pv_eoi_get_user(vcpu, &val) < 0)
 524                 apic_debug("Can't read EOI MSR value: 0x%llx\n",
 525                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 526         return val & 0x1;
 527 }
 528
 529 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
 530 {
 531         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
 532                 apic_debug("Can't set EOI MSR value: 0x%llx\n",
 533                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 534                 return;
 535         }
 536         __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 537 }
 538
 539 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
 540 {
 541         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
 542                 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
 543                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 544                 return;
 545         }
 546         __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 547 }
 548
 549 void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr)
 550 {
 551         struct kvm_lapic *apic = vcpu->arch.apic;
 552         int i;
 553
 554         for (i = 0; i < 8; i++)
 555                 apic_set_reg(apic, APIC_TMR + 0x10 * i, tmr[i]);
 556 }
 557
 558 static void apic_update_ppr(struct kvm_lapic *apic)
 559 {
 560         u32 tpr, isrv, ppr, old_ppr;
 561         int isr;
 562
 563         old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
 564         tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
 565         isr = apic_find_highest_isr(apic);
 566         isrv = (isr != -1) ? isr : 0;
 567
 568         if ((tpr & 0xf0) >= (isrv & 0xf0))
 569                 ppr = tpr & 0xff;
 570         else
 571                 ppr = isrv & 0xf0;
 572
 573         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
 574                    apic, ppr, isr, isrv);
 575
 576         if (old_ppr != ppr) {
 577                 apic_set_reg(apic, APIC_PROCPRI, ppr);
 578                 if (ppr < old_ppr)
 579                         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 580         }
 581 }
 582
 583 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
 584 {
 585         apic_set_reg(apic, APIC_TASKPRI, tpr);
 586         apic_update_ppr(apic);
 587 }
 588
 589 static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
 590 {
 591         if (apic_x2apic_mode(apic))
 592                 return mda == X2APIC_BROADCAST;
 593
 594         return GET_APIC_DEST_FIELD(mda) == APIC_BROADCAST;
 595 }
 596
 597 static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
 598 {
 599         if (kvm_apic_broadcast(apic, mda))
 600                 return true;
 601
 602         if (apic_x2apic_mode(apic))
 603                 return mda == kvm_apic_id(apic);
 604
 605         return mda == SET_APIC_DEST_FIELD(kvm_apic_id(apic));
 606 }
 607
 608 static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
 609 {
 610         u32 logical_id;
 611
 612         if (kvm_apic_broadcast(apic, mda))
 613                 return true;
 614
 615         logical_id = kvm_apic_get_reg(apic, APIC_LDR);
 616
 617         if (apic_x2apic_mode(apic))
 618                 return ((logical_id >> 16) == (mda >> 16))
 619                        && (logical_id & mda & 0xffff) != 0;
 620
 621         logical_id = GET_APIC_LOGICAL_ID(logical_id);
 622         mda = GET_APIC_DEST_FIELD(mda);
 623
 624         switch (kvm_apic_get_reg(apic, APIC_DFR)) {
 625         case APIC_DFR_FLAT:
 626                 return (logical_id & mda) != 0;
 627         case APIC_DFR_CLUSTER:
 628                 return ((logical_id >> 4) == (mda >> 4))
 629                        && (logical_id & mda & 0xf) != 0;
 630         default:
 631                 apic_debug("Bad DFR vcpu %d: %08x\n",
 632                            apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
 633                 return false;
 634         }
 635 }
 636
 637 /* KVM APIC implementation has two quirks
 638  *  - dest always begins at 0 while xAPIC MDA has offset 24,
 639  *  - IOxAPIC messages have to be delivered (directly) to x2APIC.
 640  */
 641 static u32 kvm_apic_mda(unsigned int dest_id, struct kvm_lapic *source,
 642                                               struct kvm_lapic *target)
 643 {
 644         bool ipi = source != NULL;
 645         bool x2apic_mda = apic_x2apic_mode(ipi ? source : target);
 646
 647         if (!ipi && dest_id == APIC_BROADCAST && x2apic_mda)
 648                 return X2APIC_BROADCAST;
 649
 650         return x2apic_mda ? dest_id : SET_APIC_DEST_FIELD(dest_id);
 651 }
 652
 653 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 654                            int short_hand, unsigned int dest, int dest_mode)
 655 {
 656         struct kvm_lapic *target = vcpu->arch.apic;
 657         u32 mda = kvm_apic_mda(dest, source, target);
 658
 659         apic_debug("target %p, source %p, dest 0x%x, "
 660                    "dest_mode 0x%x, short_hand 0x%x\n",
 661                    target, source, dest, dest_mode, short_hand);
 662
 663         ASSERT(target);
 664         switch (short_hand) {
 665         case APIC_DEST_NOSHORT:
 666                 if (dest_mode == APIC_DEST_PHYSICAL)
 667                         return kvm_apic_match_physical_addr(target, mda);
 668                 else
 669                         return kvm_apic_match_logical_addr(target, mda);
 670         case APIC_DEST_SELF:
 671                 return target == source;
 672         case APIC_DEST_ALLINC:
 673                 return true;
 674         case APIC_DEST_ALLBUT:
 675                 return target != source;
 676         default:
 677                 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
 678                            short_hand);
 679                 return false;
 680         }
 681 }
 682
 683 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
 684                 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map)
 685 {
 686         struct kvm_apic_map *map;
 687         unsigned long bitmap = 1;
 688         struct kvm_lapic **dst;
 689         int i;
 690         bool ret = false;
 691         bool x2apic_ipi = src && apic_x2apic_mode(src);
 692
 693         *r = -1;
 694
 695         if (irq->shorthand == APIC_DEST_SELF) {
 696                 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
 697                 return true;
 698         }
 699
 700         if (irq->shorthand)
 701                 return false;
 702
 703         if (irq->dest_id == (x2apic_ipi ? X2APIC_BROADCAST : APIC_BROADCAST))
 704                 return false;
 705
 706         rcu_read_lock();
 707         map = rcu_dereference(kvm->arch.apic_map);
 708
 709         if (!map)
 710                 goto out;
 711
 712         ret = true;
 713
 714         if (irq->dest_mode == APIC_DEST_PHYSICAL) {
 715                 if (irq->dest_id >= ARRAY_SIZE(map->phys_map))
 716                         goto out;
 717
 718                 dst = &map->phys_map[irq->dest_id];
 719         } else {
 720                 u32 mda = irq->dest_id << (32 - map->ldr_bits);
 721                 u16 cid = apic_cluster_id(map, mda);
 722
 723                 if (cid >= ARRAY_SIZE(map->logical_map))
 724                         goto out;
 725
 726                 dst = map->logical_map[cid];
 727
 728                 bitmap = apic_logical_id(map, mda);
 729
 730                 if (irq->delivery_mode == APIC_DM_LOWEST) {
 731                         int l = -1;
 732                         for_each_set_bit(i, &bitmap, 16) {
 733                                 if (!dst[i])
 734                                         continue;
 735                                 if (l < 0)
 736                                         l = i;
 737                                 else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0)
 738                                         l = i;
 739                         }
 740
 741                         bitmap = (l >= 0) ? 1 << l : 0;
 742                 }
 743         }
 744
 745         for_each_set_bit(i, &bitmap, 16) {
 746                 if (!dst[i])
 747                         continue;
 748                 if (*r < 0)
 749                         *r = 0;
 750                 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
 751         }
 752 out:
 753         rcu_read_unlock();
 754         return ret;
 755 }
 756
 757 /*
 758  * Add a pending IRQ into lapic.
 759  * Return 1 if successfully added and 0 if discarded.
 760  */
 761 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 762                              int vector, int level, int trig_mode,
 763                              unsigned long *dest_map)
 764 {
 765         int result = 0;
 766         struct kvm_vcpu *vcpu = apic->vcpu;
 767
 768         trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
 769                                   trig_mode, vector);
 770         switch (delivery_mode) {
 771         case APIC_DM_LOWEST:
 772                 vcpu->arch.apic_arb_prio++;
 773         case APIC_DM_FIXED:
 774                 /* FIXME add logic for vcpu on reset */
 775                 if (unlikely(!apic_enabled(apic)))
 776                         break;
 777
 778                 result = 1;
 779
 780                 if (dest_map)
 781                         __set_bit(vcpu->vcpu_id, dest_map);
 782
 783                 if (kvm_x86_ops->deliver_posted_interrupt)
 784                         kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
 785                 else {
 786                         apic_set_irr(vector, apic);
 787
 788                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 789                         kvm_vcpu_kick(vcpu);
 790                 }
 791                 break;
 792
 793         case APIC_DM_REMRD:
 794                 result = 1;
 795                 vcpu->arch.pv.pv_unhalted = 1;
 796                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 797                 kvm_vcpu_kick(vcpu);
 798                 break;
 799
 800         case APIC_DM_SMI:
 801                 apic_debug("Ignoring guest SMI\n");
 802                 break;
 803
 804         case APIC_DM_NMI:
 805                 result = 1;
 806                 kvm_inject_nmi(vcpu);
 807                 kvm_vcpu_kick(vcpu);
 808                 break;
 809
 810         case APIC_DM_INIT:
 811                 if (!trig_mode || level) {
 812                         result = 1;
 813                         /* assumes that there are only KVM_APIC_INIT/SIPI */
 814                         apic->pending_events = (1UL << KVM_APIC_INIT);
 815                         /* make sure pending_events is visible before sending
 816                          * the request */
 817                         smp_wmb();
 818                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 819                         kvm_vcpu_kick(vcpu);
 820                 } else {
 821                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
 822                                    vcpu->vcpu_id);
 823                 }
 824                 break;
 825
 826         case APIC_DM_STARTUP:
 827                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
 828                            vcpu->vcpu_id, vector);
 829                 result = 1;
 830                 apic->sipi_vector = vector;
 831                 /* make sure sipi_vector is visible for the receiver */
 832                 smp_wmb();
 833                 set_bit(KVM_APIC_SIPI, &apic->pending_events);
 834                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 835                 kvm_vcpu_kick(vcpu);
 836                 break;
 837
 838         case APIC_DM_EXTINT:
 839                 /*
 840                  * Should only be called by kvm_apic_local_deliver() with LVT0,
 841                  * before NMI watchdog was enabled. Already handled by
 842                  * kvm_apic_accept_pic_intr().
 843                  */
 844                 break;
 845
 846         default:
 847                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
 848                        delivery_mode);
 849                 break;
 850         }
 851         return result;
 852 }
 853
 854 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
 855 {
 856         return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
 857 }
 858
 859 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
 860 {
 861         if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) &&
 862             kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
 863                 int trigger_mode;
 864                 if (apic_test_vector(vector, apic->regs + APIC_TMR))
 865                         trigger_mode = IOAPIC_LEVEL_TRIG;
 866                 else
 867                         trigger_mode = IOAPIC_EDGE_TRIG;
 868                 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
 869         }
 870 }
 871
 872 static int apic_set_eoi(struct kvm_lapic *apic)
 873 {
 874         int vector = apic_find_highest_isr(apic);
 875
 876         trace_kvm_eoi(apic, vector);
 877
 878         /*
 879          * Not every write EOI will has corresponding ISR,
 880          * one example is when Kernel check timer on setup_IO_APIC
 881          */
 882         if (vector == -1)
 883                 return vector;
 884
 885         apic_clear_isr(vector, apic);
 886         apic_update_ppr(apic);
 887
 888         kvm_ioapic_send_eoi(apic, vector);
 889         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 890         return vector;
 891 }
 892
 893 /*
 894  * this interface assumes a trap-like exit, which has already finished
 895  * desired side effect including vISR and vPPR update.
 896  */
 897 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
 898 {
 899         struct kvm_lapic *apic = vcpu->arch.apic;
 900
 901         trace_kvm_eoi(apic, vector);
 902
 903         kvm_ioapic_send_eoi(apic, vector);
 904         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 905 }
 906 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
 907
 908 static void apic_send_ipi(struct kvm_lapic *apic)
 909 {
 910         u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
 911         u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
 912         struct kvm_lapic_irq irq;
 913
 914         irq.vector = icr_low & APIC_VECTOR_MASK;
 915         irq.delivery_mode = icr_low & APIC_MODE_MASK;
 916         irq.dest_mode = icr_low & APIC_DEST_MASK;
 917         irq.level = icr_low & APIC_INT_ASSERT;
 918         irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
 919         irq.shorthand = icr_low & APIC_SHORT_MASK;
 920         if (apic_x2apic_mode(apic))
 921                 irq.dest_id = icr_high;
 922         else
 923                 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
 924
 925         trace_kvm_apic_ipi(icr_low, irq.dest_id);
 926
 927         apic_debug("icr_high 0x%x, icr_low 0x%x, "
 928                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
 929                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
 930                    icr_high, icr_low, irq.shorthand, irq.dest_id,
 931                    irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
 932                    irq.vector);
 933
 934         kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
 935 }
 936
 937 static u32 apic_get_tmcct(struct kvm_lapic *apic)
 938 {
 939         ktime_t remaining;
 940         s64 ns;
 941         u32 tmcct;
 942
 943         ASSERT(apic != NULL);
 944
 945         /* if initial count is 0, current count should also be 0 */
 946         if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 ||
 947                 apic->lapic_timer.period == 0)
 948                 return 0;
 949
 950         remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
 951         if (ktime_to_ns(remaining) < 0)
 952                 remaining = ktime_set(0, 0);
 953
 954         ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
 955         tmcct = div64_u64(ns,
 956                          (APIC_BUS_CYCLE_NS * apic->divide_count));
 957
 958         return tmcct;
 959 }
 960
 961 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
 962 {
 963         struct kvm_vcpu *vcpu = apic->vcpu;
 964         struct kvm_run *run = vcpu->run;
 965
 966         kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
 967         run->tpr_access.rip = kvm_rip_read(vcpu);
 968         run->tpr_access.is_write = write;
 969 }
 970
 971 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
 972 {
 973         if (apic->vcpu->arch.tpr_access_reporting)
 974                 __report_tpr_access(apic, write);
 975 }
 976
 977 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
 978 {
 979         u32 val = 0;
 980
 981         if (offset >= LAPIC_MMIO_LENGTH)
 982                 return 0;
 983
 984         switch (offset) {
 985         case APIC_ID:
 986                 if (apic_x2apic_mode(apic))
 987                         val = kvm_apic_id(apic);
 988                 else
 989                         val = kvm_apic_id(apic) << 24;
 990                 break;
 991         case APIC_ARBPRI:
 992                 apic_debug("Access APIC ARBPRI register which is for P6\n");
 993                 break;
 994
 995         case APIC_TMCCT:        /* Timer CCR */
 996                 if (apic_lvtt_tscdeadline(apic))
 997                         return 0;
 998
 999                 val = apic_get_tmcct(apic);
1000                 break;
1001         case APIC_PROCPRI:
1002                 apic_update_ppr(apic);
1003                 val = kvm_apic_get_reg(apic, offset);
1004                 break;
1005         case APIC_TASKPRI:
1006                 report_tpr_access(apic, false);
1007                 /* fall thru */
1008         default:
1009                 val = kvm_apic_get_reg(apic, offset);
1010                 break;
1011         }
1012
1013         return val;
1014 }
1015
1016 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1017 {
1018         return container_of(dev, struct kvm_lapic, dev);
1019 }
1020
1021 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1022                 void *data)
1023 {
1024         unsigned char alignment = offset & 0xf;
1025         u32 result;
1026         /* this bitmask has a bit cleared for each reserved register */
1027         static const u64 rmask = 0x43ff01ffffffe70cULL;
1028
1029         if ((alignment + len) > 4) {
1030                 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1031                            offset, len);
1032                 return 1;
1033         }
1034
1035         if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
1036                 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1037                            offset);
1038                 return 1;
1039         }
1040
1041         result = __apic_read(apic, offset & ~0xf);
1042
1043         trace_kvm_apic_read(offset, result);
1044
1045         switch (len) {
1046         case 1:
1047         case 2:
1048         case 4:
1049                 memcpy(data, (char *)&result + alignment, len);
1050                 break;
1051         default:
1052                 printk(KERN_ERR "Local APIC read with len = %x, "
1053                        "should be 1,2, or 4 instead\n", len);
1054                 break;
1055         }
1056         return 0;
1057 }
1058
1059 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1060 {
1061         return kvm_apic_hw_enabled(apic) &&
1062             addr >= apic->base_address &&
1063             addr < apic->base_address + LAPIC_MMIO_LENGTH;
1064 }
1065
1066 static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1067                            gpa_t address, int len, void *data)
1068 {
1069         struct kvm_lapic *apic = to_lapic(this);
1070         u32 offset = address - apic->base_address;
1071
1072         if (!apic_mmio_in_range(apic, address))
1073                 return -EOPNOTSUPP;
1074
1075         apic_reg_read(apic, offset, len, data);
1076
1077         return 0;
1078 }
1079
1080 static void update_divide_count(struct kvm_lapic *apic)
1081 {
1082         u32 tmp1, tmp2, tdcr;
1083
1084         tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
1085         tmp1 = tdcr & 0xf;
1086         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1087         apic->divide_count = 0x1 << (tmp2 & 0x7);
1088
1089         apic_debug("timer divide count is 0x%x\n",
1090                                    apic->divide_count);
1091 }
1092
1093 static void apic_timer_expired(struct kvm_lapic *apic)
1094 {
1095         struct kvm_vcpu *vcpu = apic->vcpu;
1096         wait_queue_head_t *q = &vcpu->wq;
1097         struct kvm_timer *ktimer = &apic->lapic_timer;
1098
1099         if (atomic_read(&apic->lapic_timer.pending))
1100                 return;
1101
1102         atomic_inc(&apic->lapic_timer.pending);
1103         kvm_set_pending_timer(vcpu);
1104
1105         if (waitqueue_active(q))
1106                 wake_up_interruptible(q);
1107
1108         if (apic_lvtt_tscdeadline(apic))
1109                 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1110 }
1111
1112 /*
1113  * On APICv, this test will cause a busy wait
1114  * during a higher-priority task.
1115  */
1116
1117 static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1118 {
1119         struct kvm_lapic *apic = vcpu->arch.apic;
1120         u32 reg = kvm_apic_get_reg(apic, APIC_LVTT);
1121
1122         if (kvm_apic_hw_enabled(apic)) {
1123                 int vec = reg & APIC_VECTOR_MASK;
1124                 void *bitmap = apic->regs + APIC_ISR;
1125
1126                 if (kvm_x86_ops->deliver_posted_interrupt)
1127                         bitmap = apic->regs + APIC_IRR;
1128
1129                 if (apic_test_vector(vec, bitmap))
1130                         return true;
1131         }
1132         return false;
1133 }
1134
1135 void wait_lapic_expire(struct kvm_vcpu *vcpu)
1136 {
1137         struct kvm_lapic *apic = vcpu->arch.apic;
1138         u64 guest_tsc, tsc_deadline;
1139
1140         if (!kvm_vcpu_has_lapic(vcpu))
1141                 return;
1142
1143         if (apic->lapic_timer.expired_tscdeadline == 0)
1144                 return;
1145
1146         if (!lapic_timer_int_injected(vcpu))
1147                 return;
1148
1149         tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1150         apic->lapic_timer.expired_tscdeadline = 0;
1151         guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
1152         trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline);
1153
1154         /* __delay is delay_tsc whenever the hardware has TSC, thus always.  */
1155         if (guest_tsc < tsc_deadline)
1156                 __delay(tsc_deadline - guest_tsc);
1157 }
1158
1159 static void start_apic_timer(struct kvm_lapic *apic)
1160 {
1161         ktime_t now;
1162
1163         atomic_set(&apic->lapic_timer.pending, 0);
1164
1165         if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
1166                 /* lapic timer in oneshot or periodic mode */
1167                 now = apic->lapic_timer.timer.base->get_time();
1168                 apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
1169                             * APIC_BUS_CYCLE_NS * apic->divide_count;
1170
1171                 if (!apic->lapic_timer.period)
1172                         return;
1173                 /*
1174                  * Do not allow the guest to program periodic timers with small
1175                  * interval, since the hrtimers are not throttled by the host
1176                  * scheduler.
1177                  */
1178                 if (apic_lvtt_period(apic)) {
1179                         s64 min_period = min_timer_period_us * 1000LL;
1180
1181                         if (apic->lapic_timer.period < min_period) {
1182                                 pr_info_ratelimited(
1183                                     "kvm: vcpu %i: requested %lld ns "
1184                                     "lapic timer period limited to %lld ns\n",
1185                                     apic->vcpu->vcpu_id,
1186                                     apic->lapic_timer.period, min_period);
1187                                 apic->lapic_timer.period = min_period;
1188                         }
1189                 }
1190
1191                 hrtimer_start(&apic->lapic_timer.timer,
1192                               ktime_add_ns(now, apic->lapic_timer.period),
1193                               HRTIMER_MODE_ABS);
1194
1195                 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1196                            PRIx64 ", "
1197                            "timer initial count 0x%x, period %lldns, "
1198                            "expire @ 0x%016" PRIx64 ".\n", __func__,
1199                            APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1200                            kvm_apic_get_reg(apic, APIC_TMICT),
1201                            apic->lapic_timer.period,
1202                            ktime_to_ns(ktime_add_ns(now,
1203                                         apic->lapic_timer.period)));
1204         } else if (apic_lvtt_tscdeadline(apic)) {
1205                 /* lapic timer in tsc deadline mode */
1206                 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1207                 u64 ns = 0;
1208                 ktime_t expire;
1209                 struct kvm_vcpu *vcpu = apic->vcpu;
1210                 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1211                 unsigned long flags;
1212
1213                 if (unlikely(!tscdeadline || !this_tsc_khz))
1214                         return;
1215
1216                 local_irq_save(flags);
1217
1218                 now = apic->lapic_timer.timer.base->get_time();
1219                 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
1220                 if (likely(tscdeadline > guest_tsc)) {
1221                         ns = (tscdeadline - guest_tsc) * 1000000ULL;
1222                         do_div(ns, this_tsc_khz);
1223                         expire = ktime_add_ns(now, ns);
1224                         expire = ktime_sub_ns(expire, lapic_timer_advance_ns);
1225                         hrtimer_start(&apic->lapic_timer.timer,
1226                                       expire, HRTIMER_MODE_ABS);
1227                 } else
1228                         apic_timer_expired(apic);
1229
1230                 local_irq_restore(flags);
1231         }
1232 }
1233
1234 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1235 {
1236         int nmi_wd_enabled = apic_lvt_nmi_mode(kvm_apic_get_reg(apic, APIC_LVT0));
1237
1238         if (apic_lvt_nmi_mode(lvt0_val)) {
1239                 if (!nmi_wd_enabled) {
1240                         apic_debug("Receive NMI setting on APIC_LVT0 "
1241                                    "for cpu %d\n", apic->vcpu->vcpu_id);
1242                         apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
1243                 }
1244         } else if (nmi_wd_enabled)
1245                 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
1246 }
1247
1248 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1249 {
1250         int ret = 0;
1251
1252         trace_kvm_apic_write(reg, val);
1253
1254         switch (reg) {
1255         case APIC_ID:           /* Local APIC ID */
1256                 if (!apic_x2apic_mode(apic))
1257                         kvm_apic_set_id(apic, val >> 24);
1258                 else
1259                         ret = 1;
1260                 break;
1261
1262         case APIC_TASKPRI:
1263                 report_tpr_access(apic, true);
1264                 apic_set_tpr(apic, val & 0xff);
1265                 break;
1266
1267         case APIC_EOI:
1268                 apic_set_eoi(apic);
1269                 break;
1270
1271         case APIC_LDR:
1272                 if (!apic_x2apic_mode(apic))
1273                         kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1274                 else
1275                         ret = 1;
1276                 break;
1277
1278         case APIC_DFR:
1279                 if (!apic_x2apic_mode(apic)) {
1280                         apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1281                         recalculate_apic_map(apic->vcpu->kvm);
1282                 } else
1283                         ret = 1;
1284                 break;
1285
1286         case APIC_SPIV: {
1287                 u32 mask = 0x3ff;
1288                 if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1289                         mask |= APIC_SPIV_DIRECTED_EOI;
1290                 apic_set_spiv(apic, val & mask);
1291                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1292                         int i;
1293                         u32 lvt_val;
1294
1295                         for (i = 0; i < APIC_LVT_NUM; i++) {
1296                                 lvt_val = kvm_apic_get_reg(apic,
1297                                                        APIC_LVTT + 0x10 * i);
1298                                 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
1299                                              lvt_val | APIC_LVT_MASKED);
1300                         }
1301                         atomic_set(&apic->lapic_timer.pending, 0);
1302
1303                 }
1304                 break;
1305         }
1306         case APIC_ICR:
1307                 /* No delay here, so we always clear the pending bit */
1308                 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1309                 apic_send_ipi(apic);
1310                 break;
1311
1312         case APIC_ICR2:
1313                 if (!apic_x2apic_mode(apic))
1314                         val &= 0xff000000;
1315                 apic_set_reg(apic, APIC_ICR2, val);
1316                 break;
1317
1318         case APIC_LVT0:
1319                 apic_manage_nmi_watchdog(apic, val);
1320         case APIC_LVTTHMR:
1321         case APIC_LVTPC:
1322         case APIC_LVT1:
1323         case APIC_LVTERR:
1324                 /* TODO: Check vector */
1325                 if (!kvm_apic_sw_enabled(apic))
1326                         val |= APIC_LVT_MASKED;
1327
1328                 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1329                 apic_set_reg(apic, reg, val);
1330
1331                 break;
1332
1333         case APIC_LVTT: {
1334                 u32 timer_mode = val & apic->lapic_timer.timer_mode_mask;
1335
1336                 if (apic->lapic_timer.timer_mode != timer_mode) {
1337                         apic->lapic_timer.timer_mode = timer_mode;
1338                         hrtimer_cancel(&apic->lapic_timer.timer);
1339                 }
1340
1341                 if (!kvm_apic_sw_enabled(apic))
1342                         val |= APIC_LVT_MASKED;
1343                 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1344                 apic_set_reg(apic, APIC_LVTT, val);
1345                 break;
1346         }
1347
1348         case APIC_TMICT:
1349                 if (apic_lvtt_tscdeadline(apic))
1350                         break;
1351
1352                 hrtimer_cancel(&apic->lapic_timer.timer);
1353                 apic_set_reg(apic, APIC_TMICT, val);
1354                 start_apic_timer(apic);
1355                 break;
1356
1357         case APIC_TDCR:
1358                 if (val & 4)
1359                         apic_debug("KVM_WRITE:TDCR %x\n", val);
1360                 apic_set_reg(apic, APIC_TDCR, val);
1361                 update_divide_count(apic);
1362                 break;
1363
1364         case APIC_ESR:
1365                 if (apic_x2apic_mode(apic) && val != 0) {
1366                         apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1367                         ret = 1;
1368                 }
1369                 break;
1370
1371         case APIC_SELF_IPI:
1372                 if (apic_x2apic_mode(apic)) {
1373                         apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1374                 } else
1375                         ret = 1;
1376                 break;
1377         default:
1378                 ret = 1;
1379                 break;
1380         }
1381         if (ret)
1382                 apic_debug("Local APIC Write to read-only register %x\n", reg);
1383         return ret;
1384 }
1385
1386 static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1387                             gpa_t address, int len, const void *data)
1388 {
1389         struct kvm_lapic *apic = to_lapic(this);
1390         unsigned int offset = address - apic->base_address;
1391         u32 val;
1392
1393         if (!apic_mmio_in_range(apic, address))
1394                 return -EOPNOTSUPP;
1395
1396         /*
1397          * APIC register must be aligned on 128-bits boundary.
1398          * 32/64/128 bits registers must be accessed thru 32 bits.
1399          * Refer SDM 8.4.1
1400          */
1401         if (len != 4 || (offset & 0xf)) {
1402                 /* Don't shout loud, $infamous_os would cause only noise. */
1403                 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1404                 return 0;
1405         }
1406
1407         val = *(u32*)data;
1408
1409         /* too common printing */
1410         if (offset != APIC_EOI)
1411                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1412                            "0x%x\n", __func__, offset, len, val);
1413
1414         apic_reg_write(apic, offset & 0xff0, val);
1415
1416         return 0;
1417 }
1418
1419 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1420 {
1421         if (kvm_vcpu_has_lapic(vcpu))
1422                 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1423 }
1424 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1425
1426 /* emulate APIC access in a trap manner */
1427 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1428 {
1429         u32 val = 0;
1430
1431         /* hw has done the conditional check and inst decode */
1432         offset &= 0xff0;
1433
1434         apic_reg_read(vcpu->arch.apic, offset, 4, &val);
1435
1436         /* TODO: optimize to just emulate side effect w/o one more write */
1437         apic_reg_write(vcpu->arch.apic, offset, val);
1438 }
1439 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1440
1441 void kvm_free_lapic(struct kvm_vcpu *vcpu)
1442 {
1443         struct kvm_lapic *apic = vcpu->arch.apic;
1444
1445         if (!vcpu->arch.apic)
1446                 return;
1447
1448         hrtimer_cancel(&apic->lapic_timer.timer);
1449
1450         if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1451                 static_key_slow_dec_deferred(&apic_hw_disabled);
1452
1453         if (!apic->sw_enabled)
1454                 static_key_slow_dec_deferred(&apic_sw_disabled);
1455
1456         if (apic->regs)
1457                 free_page((unsigned long)apic->regs);
1458
1459         kfree(apic);
1460 }
1461
1462 /*
1463  *----------------------------------------------------------------------
1464  * LAPIC interface
1465  *----------------------------------------------------------------------
1466  */
1467
1468 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1469 {
1470         struct kvm_lapic *apic = vcpu->arch.apic;
1471
1472         if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1473                         apic_lvtt_period(apic))
1474                 return 0;
1475
1476         return apic->lapic_timer.tscdeadline;
1477 }
1478
1479 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1480 {
1481         struct kvm_lapic *apic = vcpu->arch.apic;
1482
1483         if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1484                         apic_lvtt_period(apic))
1485                 return;
1486
1487         hrtimer_cancel(&apic->lapic_timer.timer);
1488         apic->lapic_timer.tscdeadline = data;
1489         start_apic_timer(apic);
1490 }
1491
1492 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1493 {
1494         struct kvm_lapic *apic = vcpu->arch.apic;
1495
1496         if (!kvm_vcpu_has_lapic(vcpu))
1497                 return;
1498
1499         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1500                      | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
1501 }
1502
1503 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1504 {
1505         u64 tpr;
1506
1507         if (!kvm_vcpu_has_lapic(vcpu))
1508                 return 0;
1509
1510         tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
1511
1512         return (tpr & 0xf0) >> 4;
1513 }
1514
1515 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1516 {
1517         u64 old_value = vcpu->arch.apic_base;
1518         struct kvm_lapic *apic = vcpu->arch.apic;
1519
1520         if (!apic) {
1521                 value |= MSR_IA32_APICBASE_BSP;
1522                 vcpu->arch.apic_base = value;
1523                 return;
1524         }
1525
1526         if (!kvm_vcpu_is_bsp(apic->vcpu))
1527                 value &= ~MSR_IA32_APICBASE_BSP;
1528         vcpu->arch.apic_base = value;
1529
1530         /* update jump label if enable bit changes */
1531         if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
1532                 if (value & MSR_IA32_APICBASE_ENABLE)
1533                         static_key_slow_dec_deferred(&apic_hw_disabled);
1534                 else
1535                         static_key_slow_inc(&apic_hw_disabled.key);
1536                 recalculate_apic_map(vcpu->kvm);
1537         }
1538
1539         if ((old_value ^ value) & X2APIC_ENABLE) {
1540                 if (value & X2APIC_ENABLE) {
1541                         u32 id = kvm_apic_id(apic);
1542                         u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
1543                         kvm_apic_set_ldr(apic, ldr);
1544                         kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1545                 } else
1546                         kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
1547         }
1548
1549         apic->base_address = apic->vcpu->arch.apic_base &
1550                              MSR_IA32_APICBASE_BASE;
1551
1552         if ((value & MSR_IA32_APICBASE_ENABLE) &&
1553              apic->base_address != APIC_DEFAULT_PHYS_BASE)
1554                 pr_warn_once("APIC base relocation is unsupported by KVM");
1555
1556         /* with FSB delivery interrupt, we can restart APIC functionality */
1557         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1558                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1559
1560 }
1561
1562 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
1563 {
1564         struct kvm_lapic *apic;
1565         int i;
1566
1567         apic_debug("%s\n", __func__);
1568
1569         ASSERT(vcpu);
1570         apic = vcpu->arch.apic;
1571         ASSERT(apic != NULL);
1572
1573         /* Stop the timer in case it's a reset to an active apic */
1574         hrtimer_cancel(&apic->lapic_timer.timer);
1575
1576         kvm_apic_set_id(apic, vcpu->vcpu_id);
1577         kvm_apic_set_version(apic->vcpu);
1578
1579         for (i = 0; i < APIC_LVT_NUM; i++)
1580                 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1581         apic->lapic_timer.timer_mode = 0;
1582         apic_set_reg(apic, APIC_LVT0,
1583                      SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1584
1585         apic_set_reg(apic, APIC_DFR, 0xffffffffU);
1586         apic_set_spiv(apic, 0xff);
1587         apic_set_reg(apic, APIC_TASKPRI, 0);
1588         kvm_apic_set_ldr(apic, 0);
1589         apic_set_reg(apic, APIC_ESR, 0);
1590         apic_set_reg(apic, APIC_ICR, 0);
1591         apic_set_reg(apic, APIC_ICR2, 0);
1592         apic_set_reg(apic, APIC_TDCR, 0);
1593         apic_set_reg(apic, APIC_TMICT, 0);
1594         for (i = 0; i < 8; i++) {
1595                 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1596                 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1597                 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1598         }
1599         apic->irr_pending = kvm_apic_vid_enabled(vcpu->kvm);
1600         apic->isr_count = kvm_x86_ops->hwapic_isr_update ? 1 : 0;
1601         apic->highest_isr_cache = -1;
1602         update_divide_count(apic);
1603         atomic_set(&apic->lapic_timer.pending, 0);
1604         if (kvm_vcpu_is_bsp(vcpu))
1605                 kvm_lapic_set_base(vcpu,
1606                                 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
1607         vcpu->arch.pv_eoi.msr_val = 0;
1608         apic_update_ppr(apic);
1609
1610         vcpu->arch.apic_arb_prio = 0;
1611         vcpu->arch.apic_attention = 0;
1612
1613         apic_debug("%s: vcpu=%p, id=%d, base_msr="
1614                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1615                    vcpu, kvm_apic_id(apic),
1616                    vcpu->arch.apic_base, apic->base_address);
1617 }
1618
1619 /*
1620  *----------------------------------------------------------------------
1621  * timer interface
1622  *----------------------------------------------------------------------
1623  */
1624
1625 static bool lapic_is_periodic(struct kvm_lapic *apic)
1626 {
1627         return apic_lvtt_period(apic);
1628 }
1629
1630 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1631 {
1632         struct kvm_lapic *apic = vcpu->arch.apic;
1633
1634         if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
1635                         apic_lvt_enabled(apic, APIC_LVTT))
1636                 return atomic_read(&apic->lapic_timer.pending);
1637
1638         return 0;
1639 }
1640
1641 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1642 {
1643         u32 reg = kvm_apic_get_reg(apic, lvt_type);
1644         int vector, mode, trig_mode;
1645
1646         if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1647                 vector = reg & APIC_VECTOR_MASK;
1648                 mode = reg & APIC_MODE_MASK;
1649                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1650                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1651                                         NULL);
1652         }
1653         return 0;
1654 }
1655
1656 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1657 {
1658         struct kvm_lapic *apic = vcpu->arch.apic;
1659
1660         if (apic)
1661                 kvm_apic_local_deliver(apic, APIC_LVT0);
1662 }
1663
1664 static const struct kvm_io_device_ops apic_mmio_ops = {
1665         .read     = apic_mmio_read,
1666         .write    = apic_mmio_write,
1667 };
1668
1669 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1670 {
1671         struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
1672         struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
1673
1674         apic_timer_expired(apic);
1675
1676         if (lapic_is_periodic(apic)) {
1677                 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1678                 return HRTIMER_RESTART;
1679         } else
1680                 return HRTIMER_NORESTART;
1681 }
1682
1683 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1684 {
1685         struct kvm_lapic *apic;
1686
1687         ASSERT(vcpu != NULL);
1688         apic_debug("apic_init %d\n", vcpu->vcpu_id);
1689
1690         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1691         if (!apic)
1692                 goto nomem;
1693
1694         vcpu->arch.apic = apic;
1695
1696         apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1697         if (!apic->regs) {
1698                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1699                        vcpu->vcpu_id);
1700                 goto nomem_free_apic;
1701         }
1702         apic->vcpu = vcpu;
1703
1704         hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1705                      HRTIMER_MODE_ABS);
1706         apic->lapic_timer.timer.function = apic_timer_fn;
1707
1708         /*
1709          * APIC is created enabled. This will prevent kvm_lapic_set_base from
1710          * thinking that APIC satet has changed.
1711          */
1712         vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
1713         kvm_lapic_set_base(vcpu,
1714                         APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
1715
1716         static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
1717         kvm_lapic_reset(vcpu);
1718         kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1719
1720         return 0;
1721 nomem_free_apic:
1722         kfree(apic);
1723 nomem:
1724         return -ENOMEM;
1725 }
1726
1727 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1728 {
1729         struct kvm_lapic *apic = vcpu->arch.apic;
1730         int highest_irr;
1731
1732         if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic))
1733                 return -1;
1734
1735         apic_update_ppr(apic);
1736         highest_irr = apic_find_highest_irr(apic);
1737         if ((highest_irr == -1) ||
1738             ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
1739                 return -1;
1740         return highest_irr;
1741 }
1742
1743 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1744 {
1745         u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1746         int r = 0;
1747
1748         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
1749                 r = 1;
1750         if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1751             GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1752                 r = 1;
1753         return r;
1754 }
1755
1756 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1757 {
1758         struct kvm_lapic *apic = vcpu->arch.apic;
1759
1760         if (!kvm_vcpu_has_lapic(vcpu))
1761                 return;
1762
1763         if (atomic_read(&apic->lapic_timer.pending) > 0) {
1764                 kvm_apic_local_deliver(apic, APIC_LVTT);
1765                 if (apic_lvtt_tscdeadline(apic))
1766                         apic->lapic_timer.tscdeadline = 0;
1767                 atomic_set(&apic->lapic_timer.pending, 0);
1768         }
1769 }
1770
1771 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1772 {
1773         int vector = kvm_apic_has_interrupt(vcpu);
1774         struct kvm_lapic *apic = vcpu->arch.apic;
1775
1776         if (vector == -1)
1777                 return -1;
1778
1779         /*
1780          * We get here even with APIC virtualization enabled, if doing
1781          * nested virtualization and L1 runs with the "acknowledge interrupt
1782          * on exit" mode.  Then we cannot inject the interrupt via RVI,
1783          * because the process would deliver it through the IDT.
1784          */
1785
1786         apic_set_isr(vector, apic);
1787         apic_update_ppr(apic);
1788         apic_clear_irr(vector, apic);
1789         return vector;
1790 }
1791
1792 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
1793                 struct kvm_lapic_state *s)
1794 {
1795         struct kvm_lapic *apic = vcpu->arch.apic;
1796
1797         kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
1798         /* set SPIV separately to get count of SW disabled APICs right */
1799         apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
1800         memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1801         /* call kvm_apic_set_id() to put apic into apic_map */
1802         kvm_apic_set_id(apic, kvm_apic_id(apic));
1803         kvm_apic_set_version(vcpu);
1804
1805         apic_update_ppr(apic);
1806         hrtimer_cancel(&apic->lapic_timer.timer);
1807         update_divide_count(apic);
1808         start_apic_timer(apic);
1809         apic->irr_pending = true;
1810         apic->isr_count = kvm_x86_ops->hwapic_isr_update ?
1811                                 1 : count_vectors(apic->regs + APIC_ISR);
1812         apic->highest_isr_cache = -1;
1813         if (kvm_x86_ops->hwapic_irr_update)
1814                 kvm_x86_ops->hwapic_irr_update(vcpu,
1815                                 apic_find_highest_irr(apic));
1816         if (unlikely(kvm_x86_ops->hwapic_isr_update))
1817                 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
1818                                 apic_find_highest_isr(apic));
1819         kvm_make_request(KVM_REQ_EVENT, vcpu);
1820         kvm_rtc_eoi_tracking_restore_one(vcpu);
1821 }
1822
1823 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1824 {
1825         struct hrtimer *timer;
1826
1827         if (!kvm_vcpu_has_lapic(vcpu))
1828                 return;
1829
1830         timer = &vcpu->arch.apic->lapic_timer.timer;
1831         if (hrtimer_cancel(timer))
1832                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1833 }
1834
1835 /*
1836  * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1837  *
1838  * Detect whether guest triggered PV EOI since the
1839  * last entry. If yes, set EOI on guests's behalf.
1840  * Clear PV EOI in guest memory in any case.
1841  */
1842 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1843                                         struct kvm_lapic *apic)
1844 {
1845         bool pending;
1846         int vector;
1847         /*
1848          * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1849          * and KVM_PV_EOI_ENABLED in guest memory as follows:
1850          *
1851          * KVM_APIC_PV_EOI_PENDING is unset:
1852          *      -> host disabled PV EOI.
1853          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1854          *      -> host enabled PV EOI, guest did not execute EOI yet.
1855          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1856          *      -> host enabled PV EOI, guest executed EOI.
1857          */
1858         BUG_ON(!pv_eoi_enabled(vcpu));
1859         pending = pv_eoi_get_pending(vcpu);
1860         /*
1861          * Clear pending bit in any case: it will be set again on vmentry.
1862          * While this might not be ideal from performance point of view,
1863          * this makes sure pv eoi is only enabled when we know it's safe.
1864          */
1865         pv_eoi_clr_pending(vcpu);
1866         if (pending)
1867                 return;
1868         vector = apic_set_eoi(apic);
1869         trace_kvm_pv_eoi(apic, vector);
1870 }
1871
1872 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1873 {
1874         u32 data;
1875
1876         if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
1877                 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
1878
1879         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1880                 return;
1881
1882         kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1883                                 sizeof(u32));
1884
1885         apic_set_tpr(vcpu->arch.apic, data & 0xff);
1886 }
1887
1888 /*
1889  * apic_sync_pv_eoi_to_guest - called before vmentry
1890  *
1891  * Detect whether it's safe to enable PV EOI and
1892  * if yes do so.
1893  */
1894 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
1895                                         struct kvm_lapic *apic)
1896 {
1897         if (!pv_eoi_enabled(vcpu) ||
1898             /* IRR set or many bits in ISR: could be nested. */
1899             apic->irr_pending ||
1900             /* Cache not set: could be safe but we don't bother. */
1901             apic->highest_isr_cache == -1 ||
1902             /* Need EOI to update ioapic. */
1903             kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) {
1904                 /*
1905                  * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1906                  * so we need not do anything here.
1907                  */
1908                 return;
1909         }
1910
1911         pv_eoi_set_pending(apic->vcpu);
1912 }
1913
1914 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1915 {
1916         u32 data, tpr;
1917         int max_irr, max_isr;
1918         struct kvm_lapic *apic = vcpu->arch.apic;
1919
1920         apic_sync_pv_eoi_to_guest(vcpu, apic);
1921
1922         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1923                 return;
1924
1925         tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1926         max_irr = apic_find_highest_irr(apic);
1927         if (max_irr < 0)
1928                 max_irr = 0;
1929         max_isr = apic_find_highest_isr(apic);
1930         if (max_isr < 0)
1931                 max_isr = 0;
1932         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1933
1934         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1935                                 sizeof(u32));
1936 }
1937
1938 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1939 {
1940         if (vapic_addr) {
1941                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1942                                         &vcpu->arch.apic->vapic_cache,
1943                                         vapic_addr, sizeof(u32)))
1944                         return -EINVAL;
1945                 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1946         } else {
1947                 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1948         }
1949
1950         vcpu->arch.apic->vapic_addr = vapic_addr;
1951         return 0;
1952 }
1953
1954 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1955 {
1956         struct kvm_lapic *apic = vcpu->arch.apic;
1957         u32 reg = (msr - APIC_BASE_MSR) << 4;
1958
1959         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1960                 return 1;
1961
1962         if (reg == APIC_ICR2)
1963                 return 1;
1964
1965         /* if this is ICR write vector before command */
1966         if (reg == APIC_ICR)
1967                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1968         return apic_reg_write(apic, reg, (u32)data);
1969 }
1970
1971 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1972 {
1973         struct kvm_lapic *apic = vcpu->arch.apic;
1974         u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1975
1976         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1977                 return 1;
1978
1979         if (reg == APIC_DFR || reg == APIC_ICR2) {
1980                 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
1981                            reg);
1982                 return 1;
1983         }
1984
1985         if (apic_reg_read(apic, reg, 4, &low))
1986                 return 1;
1987         if (reg == APIC_ICR)
1988                 apic_reg_read(apic, APIC_ICR2, 4, &high);
1989
1990         *data = (((u64)high) << 32) | low;
1991
1992         return 0;
1993 }
1994
1995 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
1996 {
1997         struct kvm_lapic *apic = vcpu->arch.apic;
1998
1999         if (!kvm_vcpu_has_lapic(vcpu))
2000                 return 1;
2001
2002         /* if this is ICR write vector before command */
2003         if (reg == APIC_ICR)
2004                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2005         return apic_reg_write(apic, reg, (u32)data);
2006 }
2007
2008 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2009 {
2010         struct kvm_lapic *apic = vcpu->arch.apic;
2011         u32 low, high = 0;
2012
2013         if (!kvm_vcpu_has_lapic(vcpu))
2014                 return 1;
2015
2016         if (apic_reg_read(apic, reg, 4, &low))
2017                 return 1;
2018         if (reg == APIC_ICR)
2019                 apic_reg_read(apic, APIC_ICR2, 4, &high);
2020
2021         *data = (((u64)high) << 32) | low;
2022
2023         return 0;
2024 }
2025
2026 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
2027 {
2028         u64 addr = data & ~KVM_MSR_ENABLED;
2029         if (!IS_ALIGNED(addr, 4))
2030                 return 1;
2031
2032         vcpu->arch.pv_eoi.msr_val = data;
2033         if (!pv_eoi_enabled(vcpu))
2034                 return 0;
2035         return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
2036                                          addr, sizeof(u8));
2037 }
2038
2039 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2040 {
2041         struct kvm_lapic *apic = vcpu->arch.apic;
2042         u8 sipi_vector;
2043         unsigned long pe;
2044
2045         if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events)
2046                 return;
2047
2048         pe = xchg(&apic->pending_events, 0);
2049
2050         if (test_bit(KVM_APIC_INIT, &pe)) {
2051                 kvm_lapic_reset(vcpu);
2052                 kvm_vcpu_reset(vcpu);
2053                 if (kvm_vcpu_is_bsp(apic->vcpu))
2054                         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2055                 else
2056                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2057         }
2058         if (test_bit(KVM_APIC_SIPI, &pe) &&
2059             vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2060                 /* evaluate pending_events before reading the vector */
2061                 smp_rmb();
2062                 sipi_vector = apic->sipi_vector;
2063                 apic_debug("vcpu %d received sipi with vector # %x\n",
2064                          vcpu->vcpu_id, sipi_vector);
2065                 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2066                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2067         }
2068 }
2069
2070 void kvm_lapic_init(void)
2071 {
2072         /* do not patch jump label more than once per second */
2073         jump_label_rate_limit(&apic_hw_disabled, HZ);
2074         jump_label_rate_limit(&apic_sw_disabled, HZ);
2075 }