arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include "kvm_cache_regs.h"
  37 #include "x86.h"
  38
  39 #include <asm/cpu.h>
  40 #include <asm/io.h>
  41 #include <asm/desc.h>
  42 #include <asm/vmx.h>
  43 #include <asm/virtext.h>
  44 #include <asm/mce.h>
  45 #include <asm/fpu/internal.h>
  46 #include <asm/perf_event.h>
  47 #include <asm/debugreg.h>
  48 #include <asm/kexec.h>
  49 #include <asm/apic.h>
  50 #include <asm/irq_remapping.h>
  51
  52 #include "trace.h"
  53 #include "pmu.h"
  54
  55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  56 #define __ex_clear(x, reg) \
  57         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  58
  59 MODULE_AUTHOR("Qumranet");
  60 MODULE_LICENSE("GPL");
  61
  62 static const struct x86_cpu_id vmx_cpu_id[] = {
  63         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  64         {}
  65 };
  66 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  67
  68 static bool __read_mostly enable_vpid = 1;
  69 module_param_named(vpid, enable_vpid, bool, 0444);
  70
  71 static bool __read_mostly flexpriority_enabled = 1;
  72 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  73
  74 static bool __read_mostly enable_ept = 1;
  75 module_param_named(ept, enable_ept, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_unrestricted_guest = 1;
  78 module_param_named(unrestricted_guest,
  79                         enable_unrestricted_guest, bool, S_IRUGO);
  80
  81 static bool __read_mostly enable_ept_ad_bits = 1;
  82 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  83
  84 static bool __read_mostly emulate_invalid_guest_state = true;
  85 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  86
  87 static bool __read_mostly vmm_exclusive = 1;
  88 module_param(vmm_exclusive, bool, S_IRUGO);
  89
  90 static bool __read_mostly fasteoi = 1;
  91 module_param(fasteoi, bool, S_IRUGO);
  92
  93 static bool __read_mostly enable_apicv = 1;
  94 module_param(enable_apicv, bool, S_IRUGO);
  95
  96 static bool __read_mostly enable_shadow_vmcs = 1;
  97 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  98 /*
  99  * If nested=1, nested virtualization is supported, i.e., guests may use
 100  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 101  * use VMX instructions.
 102  */
 103 static bool __read_mostly nested = 0;
 104 module_param(nested, bool, S_IRUGO);
 105
 106 static u64 __read_mostly host_xss;
 107
 108 static bool __read_mostly enable_pml = 1;
 109 module_param_named(pml, enable_pml, bool, S_IRUGO);
 110
 111 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 112
 113 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 114 static int __read_mostly cpu_preemption_timer_multi;
 115 static bool __read_mostly enable_preemption_timer = 1;
 116 #ifdef CONFIG_X86_64
 117 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 118 #endif
 119
 120 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 121 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 122 #define KVM_VM_CR0_ALWAYS_ON                                            \
 123         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 124 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 125         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 126          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 127
 128 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 129 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 130
 131 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 132
 133 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 134
 135 /*
 136  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 137  * ple_gap:    upper bound on the amount of time between two successive
 138  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 139  *             According to test, this time is usually smaller than 128 cycles.
 140  * ple_window: upper bound on the amount of time a guest is allowed to execute
 141  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 142  *             less than 2^12 cycles
 143  * Time is measured based on a counter that runs at the same rate as the TSC,
 144  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 145  */
 146 #define KVM_VMX_DEFAULT_PLE_GAP           128
 147 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 148 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 149 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 150 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 151                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 152
 153 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 154 module_param(ple_gap, int, S_IRUGO);
 155
 156 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 157 module_param(ple_window, int, S_IRUGO);
 158
 159 /* Default doubles per-vcpu window every exit. */
 160 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 161 module_param(ple_window_grow, int, S_IRUGO);
 162
 163 /* Default resets per-vcpu window every exit to ple_window. */
 164 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 165 module_param(ple_window_shrink, int, S_IRUGO);
 166
 167 /* Default is to compute the maximum so we can never overflow. */
 168 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 169 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 170 module_param(ple_window_max, int, S_IRUGO);
 171
 172 extern const ulong vmx_return;
 173
 174 #define NR_AUTOLOAD_MSRS 8
 175 #define VMCS02_POOL_SIZE 1
 176
 177 struct vmcs {
 178         u32 revision_id;
 179         u32 abort;
 180         char data[0];
 181 };
 182
 183 /*
 184  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 185  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 186  * loaded on this CPU (so we can clear them if the CPU goes down).
 187  */
 188 struct loaded_vmcs {
 189         struct vmcs *vmcs;
 190         int cpu;
 191         int launched;
 192         struct list_head loaded_vmcss_on_cpu_link;
 193 };
 194
 195 struct shared_msr_entry {
 196         unsigned index;
 197         u64 data;
 198         u64 mask;
 199 };
 200
 201 /*
 202  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 203  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 204  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 205  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 206  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 207  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 208  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 209  * underlying hardware which will be used to run L2.
 210  * This structure is packed to ensure that its layout is identical across
 211  * machines (necessary for live migration).
 212  * If there are changes in this struct, VMCS12_REVISION must be changed.
 213  */
 214 typedef u64 natural_width;
 215 struct __packed vmcs12 {
 216         /* According to the Intel spec, a VMCS region must start with the
 217          * following two fields. Then follow implementation-specific data.
 218          */
 219         u32 revision_id;
 220         u32 abort;
 221
 222         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 223         u32 padding[7]; /* room for future expansion */
 224
 225         u64 io_bitmap_a;
 226         u64 io_bitmap_b;
 227         u64 msr_bitmap;
 228         u64 vm_exit_msr_store_addr;
 229         u64 vm_exit_msr_load_addr;
 230         u64 vm_entry_msr_load_addr;
 231         u64 tsc_offset;
 232         u64 virtual_apic_page_addr;
 233         u64 apic_access_addr;
 234         u64 posted_intr_desc_addr;
 235         u64 ept_pointer;
 236         u64 eoi_exit_bitmap0;
 237         u64 eoi_exit_bitmap1;
 238         u64 eoi_exit_bitmap2;
 239         u64 eoi_exit_bitmap3;
 240         u64 xss_exit_bitmap;
 241         u64 guest_physical_address;
 242         u64 vmcs_link_pointer;
 243         u64 guest_ia32_debugctl;
 244         u64 guest_ia32_pat;
 245         u64 guest_ia32_efer;
 246         u64 guest_ia32_perf_global_ctrl;
 247         u64 guest_pdptr0;
 248         u64 guest_pdptr1;
 249         u64 guest_pdptr2;
 250         u64 guest_pdptr3;
 251         u64 guest_bndcfgs;
 252         u64 host_ia32_pat;
 253         u64 host_ia32_efer;
 254         u64 host_ia32_perf_global_ctrl;
 255         u64 padding64[8]; /* room for future expansion */
 256         /*
 257          * To allow migration of L1 (complete with its L2 guests) between
 258          * machines of different natural widths (32 or 64 bit), we cannot have
 259          * unsigned long fields with no explict size. We use u64 (aliased
 260          * natural_width) instead. Luckily, x86 is little-endian.
 261          */
 262         natural_width cr0_guest_host_mask;
 263         natural_width cr4_guest_host_mask;
 264         natural_width cr0_read_shadow;
 265         natural_width cr4_read_shadow;
 266         natural_width cr3_target_value0;
 267         natural_width cr3_target_value1;
 268         natural_width cr3_target_value2;
 269         natural_width cr3_target_value3;
 270         natural_width exit_qualification;
 271         natural_width guest_linear_address;
 272         natural_width guest_cr0;
 273         natural_width guest_cr3;
 274         natural_width guest_cr4;
 275         natural_width guest_es_base;
 276         natural_width guest_cs_base;
 277         natural_width guest_ss_base;
 278         natural_width guest_ds_base;
 279         natural_width guest_fs_base;
 280         natural_width guest_gs_base;
 281         natural_width guest_ldtr_base;
 282         natural_width guest_tr_base;
 283         natural_width guest_gdtr_base;
 284         natural_width guest_idtr_base;
 285         natural_width guest_dr7;
 286         natural_width guest_rsp;
 287         natural_width guest_rip;
 288         natural_width guest_rflags;
 289         natural_width guest_pending_dbg_exceptions;
 290         natural_width guest_sysenter_esp;
 291         natural_width guest_sysenter_eip;
 292         natural_width host_cr0;
 293         natural_width host_cr3;
 294         natural_width host_cr4;
 295         natural_width host_fs_base;
 296         natural_width host_gs_base;
 297         natural_width host_tr_base;
 298         natural_width host_gdtr_base;
 299         natural_width host_idtr_base;
 300         natural_width host_ia32_sysenter_esp;
 301         natural_width host_ia32_sysenter_eip;
 302         natural_width host_rsp;
 303         natural_width host_rip;
 304         natural_width paddingl[8]; /* room for future expansion */
 305         u32 pin_based_vm_exec_control;
 306         u32 cpu_based_vm_exec_control;
 307         u32 exception_bitmap;
 308         u32 page_fault_error_code_mask;
 309         u32 page_fault_error_code_match;
 310         u32 cr3_target_count;
 311         u32 vm_exit_controls;
 312         u32 vm_exit_msr_store_count;
 313         u32 vm_exit_msr_load_count;
 314         u32 vm_entry_controls;
 315         u32 vm_entry_msr_load_count;
 316         u32 vm_entry_intr_info_field;
 317         u32 vm_entry_exception_error_code;
 318         u32 vm_entry_instruction_len;
 319         u32 tpr_threshold;
 320         u32 secondary_vm_exec_control;
 321         u32 vm_instruction_error;
 322         u32 vm_exit_reason;
 323         u32 vm_exit_intr_info;
 324         u32 vm_exit_intr_error_code;
 325         u32 idt_vectoring_info_field;
 326         u32 idt_vectoring_error_code;
 327         u32 vm_exit_instruction_len;
 328         u32 vmx_instruction_info;
 329         u32 guest_es_limit;
 330         u32 guest_cs_limit;
 331         u32 guest_ss_limit;
 332         u32 guest_ds_limit;
 333         u32 guest_fs_limit;
 334         u32 guest_gs_limit;
 335         u32 guest_ldtr_limit;
 336         u32 guest_tr_limit;
 337         u32 guest_gdtr_limit;
 338         u32 guest_idtr_limit;
 339         u32 guest_es_ar_bytes;
 340         u32 guest_cs_ar_bytes;
 341         u32 guest_ss_ar_bytes;
 342         u32 guest_ds_ar_bytes;
 343         u32 guest_fs_ar_bytes;
 344         u32 guest_gs_ar_bytes;
 345         u32 guest_ldtr_ar_bytes;
 346         u32 guest_tr_ar_bytes;
 347         u32 guest_interruptibility_info;
 348         u32 guest_activity_state;
 349         u32 guest_sysenter_cs;
 350         u32 host_ia32_sysenter_cs;
 351         u32 vmx_preemption_timer_value;
 352         u32 padding32[7]; /* room for future expansion */
 353         u16 virtual_processor_id;
 354         u16 posted_intr_nv;
 355         u16 guest_es_selector;
 356         u16 guest_cs_selector;
 357         u16 guest_ss_selector;
 358         u16 guest_ds_selector;
 359         u16 guest_fs_selector;
 360         u16 guest_gs_selector;
 361         u16 guest_ldtr_selector;
 362         u16 guest_tr_selector;
 363         u16 guest_intr_status;
 364         u16 host_es_selector;
 365         u16 host_cs_selector;
 366         u16 host_ss_selector;
 367         u16 host_ds_selector;
 368         u16 host_fs_selector;
 369         u16 host_gs_selector;
 370         u16 host_tr_selector;
 371 };
 372
 373 /*
 374  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 375  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 376  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 377  */
 378 #define VMCS12_REVISION 0x11e57ed0
 379
 380 /*
 381  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 382  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 383  * current implementation, 4K are reserved to avoid future complications.
 384  */
 385 #define VMCS12_SIZE 0x1000
 386
 387 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 388 struct vmcs02_list {
 389         struct list_head list;
 390         gpa_t vmptr;
 391         struct loaded_vmcs vmcs02;
 392 };
 393
 394 /*
 395  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 396  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 397  */
 398 struct nested_vmx {
 399         /* Has the level1 guest done vmxon? */
 400         bool vmxon;
 401         gpa_t vmxon_ptr;
 402
 403         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 404         gpa_t current_vmptr;
 405         /* The host-usable pointer to the above */
 406         struct page *current_vmcs12_page;
 407         struct vmcs12 *current_vmcs12;
 408         struct vmcs *current_shadow_vmcs;
 409         /*
 410          * Indicates if the shadow vmcs must be updated with the
 411          * data hold by vmcs12
 412          */
 413         bool sync_shadow_vmcs;
 414
 415         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 416         struct list_head vmcs02_pool;
 417         int vmcs02_num;
 418         u64 vmcs01_tsc_offset;
 419         /* L2 must run next, and mustn't decide to exit to L1. */
 420         bool nested_run_pending;
 421         /*
 422          * Guest pages referred to in vmcs02 with host-physical pointers, so
 423          * we must keep them pinned while L2 runs.
 424          */
 425         struct page *apic_access_page;
 426         struct page *virtual_apic_page;
 427         struct page *pi_desc_page;
 428         struct pi_desc *pi_desc;
 429         bool pi_pending;
 430         u16 posted_intr_nv;
 431
 432         struct hrtimer preemption_timer;
 433         bool preemption_timer_expired;
 434
 435         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 436         u64 vmcs01_debugctl;
 437
 438         u16 vpid02;
 439         u16 last_vpid;
 440
 441         u32 nested_vmx_procbased_ctls_low;
 442         u32 nested_vmx_procbased_ctls_high;
 443         u32 nested_vmx_true_procbased_ctls_low;
 444         u32 nested_vmx_secondary_ctls_low;
 445         u32 nested_vmx_secondary_ctls_high;
 446         u32 nested_vmx_pinbased_ctls_low;
 447         u32 nested_vmx_pinbased_ctls_high;
 448         u32 nested_vmx_exit_ctls_low;
 449         u32 nested_vmx_exit_ctls_high;
 450         u32 nested_vmx_true_exit_ctls_low;
 451         u32 nested_vmx_entry_ctls_low;
 452         u32 nested_vmx_entry_ctls_high;
 453         u32 nested_vmx_true_entry_ctls_low;
 454         u32 nested_vmx_misc_low;
 455         u32 nested_vmx_misc_high;
 456         u32 nested_vmx_ept_caps;
 457         u32 nested_vmx_vpid_caps;
 458 };
 459
 460 #define POSTED_INTR_ON  0
 461 #define POSTED_INTR_SN  1
 462
 463 /* Posted-Interrupt Descriptor */
 464 struct pi_desc {
 465         u32 pir[8];     /* Posted interrupt requested */
 466         union {
 467                 struct {
 468                                 /* bit 256 - Outstanding Notification */
 469                         u16     on      : 1,
 470                                 /* bit 257 - Suppress Notification */
 471                                 sn      : 1,
 472                                 /* bit 271:258 - Reserved */
 473                                 rsvd_1  : 14;
 474                                 /* bit 279:272 - Notification Vector */
 475                         u8      nv;
 476                                 /* bit 287:280 - Reserved */
 477                         u8      rsvd_2;
 478                                 /* bit 319:288 - Notification Destination */
 479                         u32     ndst;
 480                 };
 481                 u64 control;
 482         };
 483         u32 rsvd[6];
 484 } __aligned(64);
 485
 486 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 487 {
 488         return test_and_set_bit(POSTED_INTR_ON,
 489                         (unsigned long *)&pi_desc->control);
 490 }
 491
 492 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 493 {
 494         return test_and_clear_bit(POSTED_INTR_ON,
 495                         (unsigned long *)&pi_desc->control);
 496 }
 497
 498 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 499 {
 500         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 501 }
 502
 503 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 504 {
 505         return clear_bit(POSTED_INTR_SN,
 506                         (unsigned long *)&pi_desc->control);
 507 }
 508
 509 static inline void pi_set_sn(struct pi_desc *pi_desc)
 510 {
 511         return set_bit(POSTED_INTR_SN,
 512                         (unsigned long *)&pi_desc->control);
 513 }
 514
 515 static inline int pi_test_on(struct pi_desc *pi_desc)
 516 {
 517         return test_bit(POSTED_INTR_ON,
 518                         (unsigned long *)&pi_desc->control);
 519 }
 520
 521 static inline int pi_test_sn(struct pi_desc *pi_desc)
 522 {
 523         return test_bit(POSTED_INTR_SN,
 524                         (unsigned long *)&pi_desc->control);
 525 }
 526
 527 struct vcpu_vmx {
 528         struct kvm_vcpu       vcpu;
 529         unsigned long         host_rsp;
 530         u8                    fail;
 531         bool                  nmi_known_unmasked;
 532         u32                   exit_intr_info;
 533         u32                   idt_vectoring_info;
 534         ulong                 rflags;
 535         struct shared_msr_entry *guest_msrs;
 536         int                   nmsrs;
 537         int                   save_nmsrs;
 538         unsigned long         host_idt_base;
 539 #ifdef CONFIG_X86_64
 540         u64                   msr_host_kernel_gs_base;
 541         u64                   msr_guest_kernel_gs_base;
 542 #endif
 543         u32 vm_entry_controls_shadow;
 544         u32 vm_exit_controls_shadow;
 545         /*
 546          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 547          * non-nested (L1) guest, it always points to vmcs01. For a nested
 548          * guest (L2), it points to a different VMCS.
 549          */
 550         struct loaded_vmcs    vmcs01;
 551         struct loaded_vmcs   *loaded_vmcs;
 552         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 553         struct msr_autoload {
 554                 unsigned nr;
 555                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 556                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 557         } msr_autoload;
 558         struct {
 559                 int           loaded;
 560                 u16           fs_sel, gs_sel, ldt_sel;
 561 #ifdef CONFIG_X86_64
 562                 u16           ds_sel, es_sel;
 563 #endif
 564                 int           gs_ldt_reload_needed;
 565                 int           fs_reload_needed;
 566                 u64           msr_host_bndcfgs;
 567                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 568         } host_state;
 569         struct {
 570                 int vm86_active;
 571                 ulong save_rflags;
 572                 struct kvm_segment segs[8];
 573         } rmode;
 574         struct {
 575                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 576                 struct kvm_save_segment {
 577                         u16 selector;
 578                         unsigned long base;
 579                         u32 limit;
 580                         u32 ar;
 581                 } seg[8];
 582         } segment_cache;
 583         int vpid;
 584         bool emulation_required;
 585
 586         /* Support for vnmi-less CPUs */
 587         int soft_vnmi_blocked;
 588         ktime_t entry_time;
 589         s64 vnmi_blocked_time;
 590         u32 exit_reason;
 591
 592         /* Posted interrupt descriptor */
 593         struct pi_desc pi_desc;
 594
 595         /* Support for a guest hypervisor (nested VMX) */
 596         struct nested_vmx nested;
 597
 598         /* Dynamic PLE window. */
 599         int ple_window;
 600         bool ple_window_dirty;
 601
 602         /* Support for PML */
 603 #define PML_ENTITY_NUM          512
 604         struct page *pml_pg;
 605
 606         /* apic deadline value in host tsc */
 607         u64 hv_deadline_tsc;
 608
 609         u64 current_tsc_ratio;
 610
 611         bool guest_pkru_valid;
 612         u32 guest_pkru;
 613         u32 host_pkru;
 614
 615         /*
 616          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
 617          * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
 618          * in msr_ia32_feature_control_valid_bits.
 619          */
 620         u64 msr_ia32_feature_control;
 621         u64 msr_ia32_feature_control_valid_bits;
 622 };
 623
 624 enum segment_cache_field {
 625         SEG_FIELD_SEL = 0,
 626         SEG_FIELD_BASE = 1,
 627         SEG_FIELD_LIMIT = 2,
 628         SEG_FIELD_AR = 3,
 629
 630         SEG_FIELD_NR = 4
 631 };
 632
 633 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 634 {
 635         return container_of(vcpu, struct vcpu_vmx, vcpu);
 636 }
 637
 638 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 639 {
 640         return &(to_vmx(vcpu)->pi_desc);
 641 }
 642
 643 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 644 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 645 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 646                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 647
 648
 649 static unsigned long shadow_read_only_fields[] = {
 650         /*
 651          * We do NOT shadow fields that are modified when L0
 652          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 653          * VMXON...) executed by L1.
 654          * For example, VM_INSTRUCTION_ERROR is read
 655          * by L1 if a vmx instruction fails (part of the error path).
 656          * Note the code assumes this logic. If for some reason
 657          * we start shadowing these fields then we need to
 658          * force a shadow sync when L0 emulates vmx instructions
 659          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 660          * by nested_vmx_failValid)
 661          */
 662         VM_EXIT_REASON,
 663         VM_EXIT_INTR_INFO,
 664         VM_EXIT_INSTRUCTION_LEN,
 665         IDT_VECTORING_INFO_FIELD,
 666         IDT_VECTORING_ERROR_CODE,
 667         VM_EXIT_INTR_ERROR_CODE,
 668         EXIT_QUALIFICATION,
 669         GUEST_LINEAR_ADDRESS,
 670         GUEST_PHYSICAL_ADDRESS
 671 };
 672 static int max_shadow_read_only_fields =
 673         ARRAY_SIZE(shadow_read_only_fields);
 674
 675 static unsigned long shadow_read_write_fields[] = {
 676         TPR_THRESHOLD,
 677         GUEST_RIP,
 678         GUEST_RSP,
 679         GUEST_CR0,
 680         GUEST_CR3,
 681         GUEST_CR4,
 682         GUEST_INTERRUPTIBILITY_INFO,
 683         GUEST_RFLAGS,
 684         GUEST_CS_SELECTOR,
 685         GUEST_CS_AR_BYTES,
 686         GUEST_CS_LIMIT,
 687         GUEST_CS_BASE,
 688         GUEST_ES_BASE,
 689         GUEST_BNDCFGS,
 690         CR0_GUEST_HOST_MASK,
 691         CR0_READ_SHADOW,
 692         CR4_READ_SHADOW,
 693         TSC_OFFSET,
 694         EXCEPTION_BITMAP,
 695         CPU_BASED_VM_EXEC_CONTROL,
 696         VM_ENTRY_EXCEPTION_ERROR_CODE,
 697         VM_ENTRY_INTR_INFO_FIELD,
 698         VM_ENTRY_INSTRUCTION_LEN,
 699         VM_ENTRY_EXCEPTION_ERROR_CODE,
 700         HOST_FS_BASE,
 701         HOST_GS_BASE,
 702         HOST_FS_SELECTOR,
 703         HOST_GS_SELECTOR
 704 };
 705 static int max_shadow_read_write_fields =
 706         ARRAY_SIZE(shadow_read_write_fields);
 707
 708 static const unsigned short vmcs_field_to_offset_table[] = {
 709         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 710         FIELD(POSTED_INTR_NV, posted_intr_nv),
 711         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 712         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 713         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 714         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 715         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 716         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 717         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 718         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 719         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 720         FIELD(HOST_ES_SELECTOR, host_es_selector),
 721         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 722         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 723         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 724         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 725         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 726         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 727         FIELD64(IO_BITMAP_A, io_bitmap_a),
 728         FIELD64(IO_BITMAP_B, io_bitmap_b),
 729         FIELD64(MSR_BITMAP, msr_bitmap),
 730         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 731         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 732         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 733         FIELD64(TSC_OFFSET, tsc_offset),
 734         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 735         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 736         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 737         FIELD64(EPT_POINTER, ept_pointer),
 738         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 739         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 740         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 741         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 742         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 743         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 744         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 745         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 746         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 747         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 748         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 749         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 750         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 751         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 752         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 753         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 754         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 755         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 756         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 757         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 758         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 759         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 760         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 761         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 762         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 763         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 764         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 765         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 766         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 767         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 768         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 769         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 770         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 771         FIELD(TPR_THRESHOLD, tpr_threshold),
 772         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 773         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 774         FIELD(VM_EXIT_REASON, vm_exit_reason),
 775         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 776         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 777         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 778         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 779         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 780         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 781         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 782         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 783         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 784         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 785         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 786         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 787         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 788         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 789         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 790         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 791         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 792         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 793         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 794         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 795         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 796         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 797         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 798         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 799         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 800         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 801         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 802         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 803         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 804         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 805         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 806         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 807         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 808         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 809         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 810         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 811         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 812         FIELD(EXIT_QUALIFICATION, exit_qualification),
 813         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 814         FIELD(GUEST_CR0, guest_cr0),
 815         FIELD(GUEST_CR3, guest_cr3),
 816         FIELD(GUEST_CR4, guest_cr4),
 817         FIELD(GUEST_ES_BASE, guest_es_base),
 818         FIELD(GUEST_CS_BASE, guest_cs_base),
 819         FIELD(GUEST_SS_BASE, guest_ss_base),
 820         FIELD(GUEST_DS_BASE, guest_ds_base),
 821         FIELD(GUEST_FS_BASE, guest_fs_base),
 822         FIELD(GUEST_GS_BASE, guest_gs_base),
 823         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 824         FIELD(GUEST_TR_BASE, guest_tr_base),
 825         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 826         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 827         FIELD(GUEST_DR7, guest_dr7),
 828         FIELD(GUEST_RSP, guest_rsp),
 829         FIELD(GUEST_RIP, guest_rip),
 830         FIELD(GUEST_RFLAGS, guest_rflags),
 831         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 832         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 833         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 834         FIELD(HOST_CR0, host_cr0),
 835         FIELD(HOST_CR3, host_cr3),
 836         FIELD(HOST_CR4, host_cr4),
 837         FIELD(HOST_FS_BASE, host_fs_base),
 838         FIELD(HOST_GS_BASE, host_gs_base),
 839         FIELD(HOST_TR_BASE, host_tr_base),
 840         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 841         FIELD(HOST_IDTR_BASE, host_idtr_base),
 842         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 843         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 844         FIELD(HOST_RSP, host_rsp),
 845         FIELD(HOST_RIP, host_rip),
 846 };
 847
 848 static inline short vmcs_field_to_offset(unsigned long field)
 849 {
 850         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 851
 852         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 853             vmcs_field_to_offset_table[field] == 0)
 854                 return -ENOENT;
 855
 856         return vmcs_field_to_offset_table[field];
 857 }
 858
 859 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 860 {
 861         return to_vmx(vcpu)->nested.current_vmcs12;
 862 }
 863
 864 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 865 {
 866         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 867         if (is_error_page(page))
 868                 return NULL;
 869
 870         return page;
 871 }
 872
 873 static void nested_release_page(struct page *page)
 874 {
 875         kvm_release_page_dirty(page);
 876 }
 877
 878 static void nested_release_page_clean(struct page *page)
 879 {
 880         kvm_release_page_clean(page);
 881 }
 882
 883 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 884 static u64 construct_eptp(unsigned long root_hpa);
 885 static void kvm_cpu_vmxon(u64 addr);
 886 static void kvm_cpu_vmxoff(void);
 887 static bool vmx_xsaves_supported(void);
 888 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 889 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 890                             struct kvm_segment *var, int seg);
 891 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 892                             struct kvm_segment *var, int seg);
 893 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 894 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 895 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 896 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 897 static int alloc_identity_pagetable(struct kvm *kvm);
 898
 899 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 900 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 901 /*
 902  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 903  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 904  */
 905 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 906 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 907
 908 /*
 909  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 910  * can find which vCPU should be waken up.
 911  */
 912 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 913 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 914
 915 static unsigned long *vmx_io_bitmap_a;
 916 static unsigned long *vmx_io_bitmap_b;
 917 static unsigned long *vmx_msr_bitmap_legacy;
 918 static unsigned long *vmx_msr_bitmap_longmode;
 919 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 920 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 921 static unsigned long *vmx_msr_bitmap_nested;
 922 static unsigned long *vmx_vmread_bitmap;
 923 static unsigned long *vmx_vmwrite_bitmap;
 924
 925 static bool cpu_has_load_ia32_efer;
 926 static bool cpu_has_load_perf_global_ctrl;
 927
 928 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 929 static DEFINE_SPINLOCK(vmx_vpid_lock);
 930
 931 static struct vmcs_config {
 932         int size;
 933         int order;
 934         u32 revision_id;
 935         u32 pin_based_exec_ctrl;
 936         u32 cpu_based_exec_ctrl;
 937         u32 cpu_based_2nd_exec_ctrl;
 938         u32 vmexit_ctrl;
 939         u32 vmentry_ctrl;
 940 } vmcs_config;
 941
 942 static struct vmx_capability {
 943         u32 ept;
 944         u32 vpid;
 945 } vmx_capability;
 946
 947 #define VMX_SEGMENT_FIELD(seg)                                  \
 948         [VCPU_SREG_##seg] = {                                   \
 949                 .selector = GUEST_##seg##_SELECTOR,             \
 950                 .base = GUEST_##seg##_BASE,                     \
 951                 .limit = GUEST_##seg##_LIMIT,                   \
 952                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 953         }
 954
 955 static const struct kvm_vmx_segment_field {
 956         unsigned selector;
 957         unsigned base;
 958         unsigned limit;
 959         unsigned ar_bytes;
 960 } kvm_vmx_segment_fields[] = {
 961         VMX_SEGMENT_FIELD(CS),
 962         VMX_SEGMENT_FIELD(DS),
 963         VMX_SEGMENT_FIELD(ES),
 964         VMX_SEGMENT_FIELD(FS),
 965         VMX_SEGMENT_FIELD(GS),
 966         VMX_SEGMENT_FIELD(SS),
 967         VMX_SEGMENT_FIELD(TR),
 968         VMX_SEGMENT_FIELD(LDTR),
 969 };
 970
 971 static u64 host_efer;
 972
 973 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 974
 975 /*
 976  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 977  * away by decrementing the array size.
 978  */
 979 static const u32 vmx_msr_index[] = {
 980 #ifdef CONFIG_X86_64
 981         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 982 #endif
 983         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 984 };
 985
 986 static inline bool is_exception_n(u32 intr_info, u8 vector)
 987 {
 988         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 989                              INTR_INFO_VALID_MASK)) ==
 990                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
 991 }
 992
 993 static inline bool is_debug(u32 intr_info)
 994 {
 995         return is_exception_n(intr_info, DB_VECTOR);
 996 }
 997
 998 static inline bool is_breakpoint(u32 intr_info)
 999 {
1000         return is_exception_n(intr_info, BP_VECTOR);
1001 }
1002
1003 static inline bool is_page_fault(u32 intr_info)
1004 {
1005         return is_exception_n(intr_info, PF_VECTOR);
1006 }
1007
1008 static inline bool is_no_device(u32 intr_info)
1009 {
1010         return is_exception_n(intr_info, NM_VECTOR);
1011 }
1012
1013 static inline bool is_invalid_opcode(u32 intr_info)
1014 {
1015         return is_exception_n(intr_info, UD_VECTOR);
1016 }
1017
1018 static inline bool is_external_interrupt(u32 intr_info)
1019 {
1020         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1021                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1022 }
1023
1024 static inline bool is_machine_check(u32 intr_info)
1025 {
1026         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1027                              INTR_INFO_VALID_MASK)) ==
1028                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1029 }
1030
1031 static inline bool cpu_has_vmx_msr_bitmap(void)
1032 {
1033         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1034 }
1035
1036 static inline bool cpu_has_vmx_tpr_shadow(void)
1037 {
1038         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1039 }
1040
1041 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1042 {
1043         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1044 }
1045
1046 static inline bool cpu_has_secondary_exec_ctrls(void)
1047 {
1048         return vmcs_config.cpu_based_exec_ctrl &
1049                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1050 }
1051
1052 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1053 {
1054         return vmcs_config.cpu_based_2nd_exec_ctrl &
1055                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1056 }
1057
1058 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1059 {
1060         return vmcs_config.cpu_based_2nd_exec_ctrl &
1061                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1062 }
1063
1064 static inline bool cpu_has_vmx_apic_register_virt(void)
1065 {
1066         return vmcs_config.cpu_based_2nd_exec_ctrl &
1067                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1068 }
1069
1070 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1071 {
1072         return vmcs_config.cpu_based_2nd_exec_ctrl &
1073                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1074 }
1075
1076 /*
1077  * Comment's format: document - errata name - stepping - processor name.
1078  * Refer from
1079  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1080  */
1081 static u32 vmx_preemption_cpu_tfms[] = {
1082 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
1083 0x000206E6,
1084 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
1085 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1086 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1087 0x00020652,
1088 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1089 0x00020655,
1090 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
1091 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
1092 /*
1093  * 320767.pdf - AAP86  - B1 -
1094  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1095  */
1096 0x000106E5,
1097 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1098 0x000106A0,
1099 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1100 0x000106A1,
1101 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1102 0x000106A4,
1103  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1104  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1105  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1106 0x000106A5,
1107 };
1108
1109 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1110 {
1111         u32 eax = cpuid_eax(0x00000001), i;
1112
1113         /* Clear the reserved bits */
1114         eax &= ~(0x3U << 14 | 0xfU << 28);
1115         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1116                 if (eax == vmx_preemption_cpu_tfms[i])
1117                         return true;
1118
1119         return false;
1120 }
1121
1122 static inline bool cpu_has_vmx_preemption_timer(void)
1123 {
1124         return vmcs_config.pin_based_exec_ctrl &
1125                 PIN_BASED_VMX_PREEMPTION_TIMER;
1126 }
1127
1128 static inline bool cpu_has_vmx_posted_intr(void)
1129 {
1130         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1131                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1132 }
1133
1134 static inline bool cpu_has_vmx_apicv(void)
1135 {
1136         return cpu_has_vmx_apic_register_virt() &&
1137                 cpu_has_vmx_virtual_intr_delivery() &&
1138                 cpu_has_vmx_posted_intr();
1139 }
1140
1141 static inline bool cpu_has_vmx_flexpriority(void)
1142 {
1143         return cpu_has_vmx_tpr_shadow() &&
1144                 cpu_has_vmx_virtualize_apic_accesses();
1145 }
1146
1147 static inline bool cpu_has_vmx_ept_execute_only(void)
1148 {
1149         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1150 }
1151
1152 static inline bool cpu_has_vmx_ept_2m_page(void)
1153 {
1154         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1155 }
1156
1157 static inline bool cpu_has_vmx_ept_1g_page(void)
1158 {
1159         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1160 }
1161
1162 static inline bool cpu_has_vmx_ept_4levels(void)
1163 {
1164         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1165 }
1166
1167 static inline bool cpu_has_vmx_ept_ad_bits(void)
1168 {
1169         return vmx_capability.ept & VMX_EPT_AD_BIT;
1170 }
1171
1172 static inline bool cpu_has_vmx_invept_context(void)
1173 {
1174         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1175 }
1176
1177 static inline bool cpu_has_vmx_invept_global(void)
1178 {
1179         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1180 }
1181
1182 static inline bool cpu_has_vmx_invvpid_single(void)
1183 {
1184         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1185 }
1186
1187 static inline bool cpu_has_vmx_invvpid_global(void)
1188 {
1189         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1190 }
1191
1192 static inline bool cpu_has_vmx_ept(void)
1193 {
1194         return vmcs_config.cpu_based_2nd_exec_ctrl &
1195                 SECONDARY_EXEC_ENABLE_EPT;
1196 }
1197
1198 static inline bool cpu_has_vmx_unrestricted_guest(void)
1199 {
1200         return vmcs_config.cpu_based_2nd_exec_ctrl &
1201                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1202 }
1203
1204 static inline bool cpu_has_vmx_ple(void)
1205 {
1206         return vmcs_config.cpu_based_2nd_exec_ctrl &
1207                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1208 }
1209
1210 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1211 {
1212         return flexpriority_enabled && lapic_in_kernel(vcpu);
1213 }
1214
1215 static inline bool cpu_has_vmx_vpid(void)
1216 {
1217         return vmcs_config.cpu_based_2nd_exec_ctrl &
1218                 SECONDARY_EXEC_ENABLE_VPID;
1219 }
1220
1221 static inline bool cpu_has_vmx_rdtscp(void)
1222 {
1223         return vmcs_config.cpu_based_2nd_exec_ctrl &
1224                 SECONDARY_EXEC_RDTSCP;
1225 }
1226
1227 static inline bool cpu_has_vmx_invpcid(void)
1228 {
1229         return vmcs_config.cpu_based_2nd_exec_ctrl &
1230                 SECONDARY_EXEC_ENABLE_INVPCID;
1231 }
1232
1233 static inline bool cpu_has_virtual_nmis(void)
1234 {
1235         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1236 }
1237
1238 static inline bool cpu_has_vmx_wbinvd_exit(void)
1239 {
1240         return vmcs_config.cpu_based_2nd_exec_ctrl &
1241                 SECONDARY_EXEC_WBINVD_EXITING;
1242 }
1243
1244 static inline bool cpu_has_vmx_shadow_vmcs(void)
1245 {
1246         u64 vmx_msr;
1247         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1248         /* check if the cpu supports writing r/o exit information fields */
1249         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1250                 return false;
1251
1252         return vmcs_config.cpu_based_2nd_exec_ctrl &
1253                 SECONDARY_EXEC_SHADOW_VMCS;
1254 }
1255
1256 static inline bool cpu_has_vmx_pml(void)
1257 {
1258         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1259 }
1260
1261 static inline bool cpu_has_vmx_tsc_scaling(void)
1262 {
1263         return vmcs_config.cpu_based_2nd_exec_ctrl &
1264                 SECONDARY_EXEC_TSC_SCALING;
1265 }
1266
1267 static inline bool report_flexpriority(void)
1268 {
1269         return flexpriority_enabled;
1270 }
1271
1272 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1273 {
1274         return vmcs12->cpu_based_vm_exec_control & bit;
1275 }
1276
1277 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1278 {
1279         return (vmcs12->cpu_based_vm_exec_control &
1280                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1281                 (vmcs12->secondary_vm_exec_control & bit);
1282 }
1283
1284 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1285 {
1286         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1287 }
1288
1289 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1290 {
1291         return vmcs12->pin_based_vm_exec_control &
1292                 PIN_BASED_VMX_PREEMPTION_TIMER;
1293 }
1294
1295 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1296 {
1297         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1298 }
1299
1300 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1301 {
1302         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1303                 vmx_xsaves_supported();
1304 }
1305
1306 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1307 {
1308         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1309 }
1310
1311 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1312 {
1313         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1314 }
1315
1316 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1317 {
1318         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1319 }
1320
1321 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1322 {
1323         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1324 }
1325
1326 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1327 {
1328         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1329 }
1330
1331 static inline bool is_exception(u32 intr_info)
1332 {
1333         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1334                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1335 }
1336
1337 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1338                               u32 exit_intr_info,
1339                               unsigned long exit_qualification);
1340 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1341                         struct vmcs12 *vmcs12,
1342                         u32 reason, unsigned long qualification);
1343
1344 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1345 {
1346         int i;
1347
1348         for (i = 0; i < vmx->nmsrs; ++i)
1349                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1350                         return i;
1351         return -1;
1352 }
1353
1354 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1355 {
1356     struct {
1357         u64 vpid : 16;
1358         u64 rsvd : 48;
1359         u64 gva;
1360     } operand = { vpid, 0, gva };
1361
1362     asm volatile (__ex(ASM_VMX_INVVPID)
1363                   /* CF==1 or ZF==1 --> rc = -1 */
1364                   "; ja 1f ; ud2 ; 1:"
1365                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1366 }
1367
1368 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1369 {
1370         struct {
1371                 u64 eptp, gpa;
1372         } operand = {eptp, gpa};
1373
1374         asm volatile (__ex(ASM_VMX_INVEPT)
1375                         /* CF==1 or ZF==1 --> rc = -1 */
1376                         "; ja 1f ; ud2 ; 1:\n"
1377                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1378 }
1379
1380 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1381 {
1382         int i;
1383
1384         i = __find_msr_index(vmx, msr);
1385         if (i >= 0)
1386                 return &vmx->guest_msrs[i];
1387         return NULL;
1388 }
1389
1390 static void vmcs_clear(struct vmcs *vmcs)
1391 {
1392         u64 phys_addr = __pa(vmcs);
1393         u8 error;
1394
1395         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1396                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1397                       : "cc", "memory");
1398         if (error)
1399                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1400                        vmcs, phys_addr);
1401 }
1402
1403 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1404 {
1405         vmcs_clear(loaded_vmcs->vmcs);
1406         loaded_vmcs->cpu = -1;
1407         loaded_vmcs->launched = 0;
1408 }
1409
1410 static void vmcs_load(struct vmcs *vmcs)
1411 {
1412         u64 phys_addr = __pa(vmcs);
1413         u8 error;
1414
1415         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1416                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1417                         : "cc", "memory");
1418         if (error)
1419                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1420                        vmcs, phys_addr);
1421 }
1422
1423 #ifdef CONFIG_KEXEC_CORE
1424 /*
1425  * This bitmap is used to indicate whether the vmclear
1426  * operation is enabled on all cpus. All disabled by
1427  * default.
1428  */
1429 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1430
1431 static inline void crash_enable_local_vmclear(int cpu)
1432 {
1433         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1434 }
1435
1436 static inline void crash_disable_local_vmclear(int cpu)
1437 {
1438         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1439 }
1440
1441 static inline int crash_local_vmclear_enabled(int cpu)
1442 {
1443         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1444 }
1445
1446 static void crash_vmclear_local_loaded_vmcss(void)
1447 {
1448         int cpu = raw_smp_processor_id();
1449         struct loaded_vmcs *v;
1450
1451         if (!crash_local_vmclear_enabled(cpu))
1452                 return;
1453
1454         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1455                             loaded_vmcss_on_cpu_link)
1456                 vmcs_clear(v->vmcs);
1457 }
1458 #else
1459 static inline void crash_enable_local_vmclear(int cpu) { }
1460 static inline void crash_disable_local_vmclear(int cpu) { }
1461 #endif /* CONFIG_KEXEC_CORE */
1462
1463 static void __loaded_vmcs_clear(void *arg)
1464 {
1465         struct loaded_vmcs *loaded_vmcs = arg;
1466         int cpu = raw_smp_processor_id();
1467
1468         if (loaded_vmcs->cpu != cpu)
1469                 return; /* vcpu migration can race with cpu offline */
1470         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1471                 per_cpu(current_vmcs, cpu) = NULL;
1472         crash_disable_local_vmclear(cpu);
1473         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1474
1475         /*
1476          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1477          * is before setting loaded_vmcs->vcpu to -1 which is done in
1478          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1479          * then adds the vmcs into percpu list before it is deleted.
1480          */
1481         smp_wmb();
1482
1483         loaded_vmcs_init(loaded_vmcs);
1484         crash_enable_local_vmclear(cpu);
1485 }
1486
1487 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1488 {
1489         int cpu = loaded_vmcs->cpu;
1490
1491         if (cpu != -1)
1492                 smp_call_function_single(cpu,
1493                          __loaded_vmcs_clear, loaded_vmcs, 1);
1494 }
1495
1496 static inline void vpid_sync_vcpu_single(int vpid)
1497 {
1498         if (vpid == 0)
1499                 return;
1500
1501         if (cpu_has_vmx_invvpid_single())
1502                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1503 }
1504
1505 static inline void vpid_sync_vcpu_global(void)
1506 {
1507         if (cpu_has_vmx_invvpid_global())
1508                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1509 }
1510
1511 static inline void vpid_sync_context(int vpid)
1512 {
1513         if (cpu_has_vmx_invvpid_single())
1514                 vpid_sync_vcpu_single(vpid);
1515         else
1516                 vpid_sync_vcpu_global();
1517 }
1518
1519 static inline void ept_sync_global(void)
1520 {
1521         if (cpu_has_vmx_invept_global())
1522                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1523 }
1524
1525 static inline void ept_sync_context(u64 eptp)
1526 {
1527         if (enable_ept) {
1528                 if (cpu_has_vmx_invept_context())
1529                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1530                 else
1531                         ept_sync_global();
1532         }
1533 }
1534
1535 static __always_inline void vmcs_check16(unsigned long field)
1536 {
1537         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1538                          "16-bit accessor invalid for 64-bit field");
1539         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1540                          "16-bit accessor invalid for 64-bit high field");
1541         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1542                          "16-bit accessor invalid for 32-bit high field");
1543         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1544                          "16-bit accessor invalid for natural width field");
1545 }
1546
1547 static __always_inline void vmcs_check32(unsigned long field)
1548 {
1549         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1550                          "32-bit accessor invalid for 16-bit field");
1551         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1552                          "32-bit accessor invalid for natural width field");
1553 }
1554
1555 static __always_inline void vmcs_check64(unsigned long field)
1556 {
1557         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1558                          "64-bit accessor invalid for 16-bit field");
1559         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1560                          "64-bit accessor invalid for 64-bit high field");
1561         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1562                          "64-bit accessor invalid for 32-bit field");
1563         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1564                          "64-bit accessor invalid for natural width field");
1565 }
1566
1567 static __always_inline void vmcs_checkl(unsigned long field)
1568 {
1569         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1570                          "Natural width accessor invalid for 16-bit field");
1571         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1572                          "Natural width accessor invalid for 64-bit field");
1573         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1574                          "Natural width accessor invalid for 64-bit high field");
1575         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1576                          "Natural width accessor invalid for 32-bit field");
1577 }
1578
1579 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1580 {
1581         unsigned long value;
1582
1583         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1584                       : "=a"(value) : "d"(field) : "cc");
1585         return value;
1586 }
1587
1588 static __always_inline u16 vmcs_read16(unsigned long field)
1589 {
1590         vmcs_check16(field);
1591         return __vmcs_readl(field);
1592 }
1593
1594 static __always_inline u32 vmcs_read32(unsigned long field)
1595 {
1596         vmcs_check32(field);
1597         return __vmcs_readl(field);
1598 }
1599
1600 static __always_inline u64 vmcs_read64(unsigned long field)
1601 {
1602         vmcs_check64(field);
1603 #ifdef CONFIG_X86_64
1604         return __vmcs_readl(field);
1605 #else
1606         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1607 #endif
1608 }
1609
1610 static __always_inline unsigned long vmcs_readl(unsigned long field)
1611 {
1612         vmcs_checkl(field);
1613         return __vmcs_readl(field);
1614 }
1615
1616 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1617 {
1618         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1619                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1620         dump_stack();
1621 }
1622
1623 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1624 {
1625         u8 error;
1626
1627         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1628                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1629         if (unlikely(error))
1630                 vmwrite_error(field, value);
1631 }
1632
1633 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1634 {
1635         vmcs_check16(field);
1636         __vmcs_writel(field, value);
1637 }
1638
1639 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1640 {
1641         vmcs_check32(field);
1642         __vmcs_writel(field, value);
1643 }
1644
1645 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1646 {
1647         vmcs_check64(field);
1648         __vmcs_writel(field, value);
1649 #ifndef CONFIG_X86_64
1650         asm volatile ("");
1651         __vmcs_writel(field+1, value >> 32);
1652 #endif
1653 }
1654
1655 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1656 {
1657         vmcs_checkl(field);
1658         __vmcs_writel(field, value);
1659 }
1660
1661 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1662 {
1663         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1664                          "vmcs_clear_bits does not support 64-bit fields");
1665         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1666 }
1667
1668 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1669 {
1670         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1671                          "vmcs_set_bits does not support 64-bit fields");
1672         __vmcs_writel(field, __vmcs_readl(field) | mask);
1673 }
1674
1675 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1676 {
1677         vmcs_write32(VM_ENTRY_CONTROLS, val);
1678         vmx->vm_entry_controls_shadow = val;
1679 }
1680
1681 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1682 {
1683         if (vmx->vm_entry_controls_shadow != val)
1684                 vm_entry_controls_init(vmx, val);
1685 }
1686
1687 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1688 {
1689         return vmx->vm_entry_controls_shadow;
1690 }
1691
1692
1693 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1694 {
1695         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1696 }
1697
1698 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1699 {
1700         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1701 }
1702
1703 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1704 {
1705         vmcs_write32(VM_EXIT_CONTROLS, val);
1706         vmx->vm_exit_controls_shadow = val;
1707 }
1708
1709 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1710 {
1711         if (vmx->vm_exit_controls_shadow != val)
1712                 vm_exit_controls_init(vmx, val);
1713 }
1714
1715 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1716 {
1717         return vmx->vm_exit_controls_shadow;
1718 }
1719
1720
1721 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1722 {
1723         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1724 }
1725
1726 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1727 {
1728         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1729 }
1730
1731 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1732 {
1733         vmx->segment_cache.bitmask = 0;
1734 }
1735
1736 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1737                                        unsigned field)
1738 {
1739         bool ret;
1740         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1741
1742         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1743                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1744                 vmx->segment_cache.bitmask = 0;
1745         }
1746         ret = vmx->segment_cache.bitmask & mask;
1747         vmx->segment_cache.bitmask |= mask;
1748         return ret;
1749 }
1750
1751 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1752 {
1753         u16 *p = &vmx->segment_cache.seg[seg].selector;
1754
1755         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1756                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1757         return *p;
1758 }
1759
1760 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1761 {
1762         ulong *p = &vmx->segment_cache.seg[seg].base;
1763
1764         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1765                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1766         return *p;
1767 }
1768
1769 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1770 {
1771         u32 *p = &vmx->segment_cache.seg[seg].limit;
1772
1773         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1774                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1775         return *p;
1776 }
1777
1778 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1779 {
1780         u32 *p = &vmx->segment_cache.seg[seg].ar;
1781
1782         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1783                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1784         return *p;
1785 }
1786
1787 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1788 {
1789         u32 eb;
1790
1791         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1792              (1u << NM_VECTOR) | (1u << DB_VECTOR) | (1u << AC_VECTOR);
1793         if ((vcpu->guest_debug &
1794              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1795             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1796                 eb |= 1u << BP_VECTOR;
1797         if (to_vmx(vcpu)->rmode.vm86_active)
1798                 eb = ~0;
1799         if (enable_ept)
1800                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1801         if (vcpu->fpu_active)
1802                 eb &= ~(1u << NM_VECTOR);
1803
1804         /* When we are running a nested L2 guest and L1 specified for it a
1805          * certain exception bitmap, we must trap the same exceptions and pass
1806          * them to L1. When running L2, we will only handle the exceptions
1807          * specified above if L1 did not want them.
1808          */
1809         if (is_guest_mode(vcpu))
1810                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1811
1812         vmcs_write32(EXCEPTION_BITMAP, eb);
1813 }
1814
1815 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1816                 unsigned long entry, unsigned long exit)
1817 {
1818         vm_entry_controls_clearbit(vmx, entry);
1819         vm_exit_controls_clearbit(vmx, exit);
1820 }
1821
1822 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1823 {
1824         unsigned i;
1825         struct msr_autoload *m = &vmx->msr_autoload;
1826
1827         switch (msr) {
1828         case MSR_EFER:
1829                 if (cpu_has_load_ia32_efer) {
1830                         clear_atomic_switch_msr_special(vmx,
1831                                         VM_ENTRY_LOAD_IA32_EFER,
1832                                         VM_EXIT_LOAD_IA32_EFER);
1833                         return;
1834                 }
1835                 break;
1836         case MSR_CORE_PERF_GLOBAL_CTRL:
1837                 if (cpu_has_load_perf_global_ctrl) {
1838                         clear_atomic_switch_msr_special(vmx,
1839                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1840                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1841                         return;
1842                 }
1843                 break;
1844         }
1845
1846         for (i = 0; i < m->nr; ++i)
1847                 if (m->guest[i].index == msr)
1848                         break;
1849
1850         if (i == m->nr)
1851                 return;
1852         --m->nr;
1853         m->guest[i] = m->guest[m->nr];
1854         m->host[i] = m->host[m->nr];
1855         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1856         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1857 }
1858
1859 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1860                 unsigned long entry, unsigned long exit,
1861                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1862                 u64 guest_val, u64 host_val)
1863 {
1864         vmcs_write64(guest_val_vmcs, guest_val);
1865         vmcs_write64(host_val_vmcs, host_val);
1866         vm_entry_controls_setbit(vmx, entry);
1867         vm_exit_controls_setbit(vmx, exit);
1868 }
1869
1870 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1871                                   u64 guest_val, u64 host_val)
1872 {
1873         unsigned i;
1874         struct msr_autoload *m = &vmx->msr_autoload;
1875
1876         switch (msr) {
1877         case MSR_EFER:
1878                 if (cpu_has_load_ia32_efer) {
1879                         add_atomic_switch_msr_special(vmx,
1880                                         VM_ENTRY_LOAD_IA32_EFER,
1881                                         VM_EXIT_LOAD_IA32_EFER,
1882                                         GUEST_IA32_EFER,
1883                                         HOST_IA32_EFER,
1884                                         guest_val, host_val);
1885                         return;
1886                 }
1887                 break;
1888         case MSR_CORE_PERF_GLOBAL_CTRL:
1889                 if (cpu_has_load_perf_global_ctrl) {
1890                         add_atomic_switch_msr_special(vmx,
1891                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1892                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1893                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1894                                         HOST_IA32_PERF_GLOBAL_CTRL,
1895                                         guest_val, host_val);
1896                         return;
1897                 }
1898                 break;
1899         case MSR_IA32_PEBS_ENABLE:
1900                 /* PEBS needs a quiescent period after being disabled (to write
1901                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
1902                  * provide that period, so a CPU could write host's record into
1903                  * guest's memory.
1904                  */
1905                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1906         }
1907
1908         for (i = 0; i < m->nr; ++i)
1909                 if (m->guest[i].index == msr)
1910                         break;
1911
1912         if (i == NR_AUTOLOAD_MSRS) {
1913                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1914                                 "Can't add msr %x\n", msr);
1915                 return;
1916         } else if (i == m->nr) {
1917                 ++m->nr;
1918                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1919                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1920         }
1921
1922         m->guest[i].index = msr;
1923         m->guest[i].value = guest_val;
1924         m->host[i].index = msr;
1925         m->host[i].value = host_val;
1926 }
1927
1928 static void reload_tss(void)
1929 {
1930         /*
1931          * VT restores TR but not its size.  Useless.
1932          */
1933         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1934         struct desc_struct *descs;
1935
1936         descs = (void *)gdt->address;
1937         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1938         load_TR_desc();
1939 }
1940
1941 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1942 {
1943         u64 guest_efer = vmx->vcpu.arch.efer;
1944         u64 ignore_bits = 0;
1945
1946         if (!enable_ept) {
1947                 /*
1948                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
1949                  * host CPUID is more efficient than testing guest CPUID
1950                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
1951                  */
1952                 if (boot_cpu_has(X86_FEATURE_SMEP))
1953                         guest_efer |= EFER_NX;
1954                 else if (!(guest_efer & EFER_NX))
1955                         ignore_bits |= EFER_NX;
1956         }
1957
1958         /*
1959          * LMA and LME handled by hardware; SCE meaningless outside long mode.
1960          */
1961         ignore_bits |= EFER_SCE;
1962 #ifdef CONFIG_X86_64
1963         ignore_bits |= EFER_LMA | EFER_LME;
1964         /* SCE is meaningful only in long mode on Intel */
1965         if (guest_efer & EFER_LMA)
1966                 ignore_bits &= ~(u64)EFER_SCE;
1967 #endif
1968
1969         clear_atomic_switch_msr(vmx, MSR_EFER);
1970
1971         /*
1972          * On EPT, we can't emulate NX, so we must switch EFER atomically.
1973          * On CPUs that support "load IA32_EFER", always switch EFER
1974          * atomically, since it's faster than switching it manually.
1975          */
1976         if (cpu_has_load_ia32_efer ||
1977             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1978                 if (!(guest_efer & EFER_LMA))
1979                         guest_efer &= ~EFER_LME;
1980                 if (guest_efer != host_efer)
1981                         add_atomic_switch_msr(vmx, MSR_EFER,
1982                                               guest_efer, host_efer);
1983                 return false;
1984         } else {
1985                 guest_efer &= ~ignore_bits;
1986                 guest_efer |= host_efer & ignore_bits;
1987
1988                 vmx->guest_msrs[efer_offset].data = guest_efer;
1989                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1990
1991                 return true;
1992         }
1993 }
1994
1995 static unsigned long segment_base(u16 selector)
1996 {
1997         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1998         struct desc_struct *d;
1999         unsigned long table_base;
2000         unsigned long v;
2001
2002         if (!(selector & ~3))
2003                 return 0;
2004
2005         table_base = gdt->address;
2006
2007         if (selector & 4) {           /* from ldt */
2008                 u16 ldt_selector = kvm_read_ldt();
2009
2010                 if (!(ldt_selector & ~3))
2011                         return 0;
2012
2013                 table_base = segment_base(ldt_selector);
2014         }
2015         d = (struct desc_struct *)(table_base + (selector & ~7));
2016         v = get_desc_base(d);
2017 #ifdef CONFIG_X86_64
2018        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
2019                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
2020 #endif
2021         return v;
2022 }
2023
2024 static inline unsigned long kvm_read_tr_base(void)
2025 {
2026         u16 tr;
2027         asm("str %0" : "=g"(tr));
2028         return segment_base(tr);
2029 }
2030
2031 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2032 {
2033         struct vcpu_vmx *vmx = to_vmx(vcpu);
2034         int i;
2035
2036         if (vmx->host_state.loaded)
2037                 return;
2038
2039         vmx->host_state.loaded = 1;
2040         /*
2041          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
2042          * allow segment selectors with cpl > 0 or ti == 1.
2043          */
2044         vmx->host_state.ldt_sel = kvm_read_ldt();
2045         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2046         savesegment(fs, vmx->host_state.fs_sel);
2047         if (!(vmx->host_state.fs_sel & 7)) {
2048                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2049                 vmx->host_state.fs_reload_needed = 0;
2050         } else {
2051                 vmcs_write16(HOST_FS_SELECTOR, 0);
2052                 vmx->host_state.fs_reload_needed = 1;
2053         }
2054         savesegment(gs, vmx->host_state.gs_sel);
2055         if (!(vmx->host_state.gs_sel & 7))
2056                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2057         else {
2058                 vmcs_write16(HOST_GS_SELECTOR, 0);
2059                 vmx->host_state.gs_ldt_reload_needed = 1;
2060         }
2061
2062 #ifdef CONFIG_X86_64
2063         savesegment(ds, vmx->host_state.ds_sel);
2064         savesegment(es, vmx->host_state.es_sel);
2065 #endif
2066
2067 #ifdef CONFIG_X86_64
2068         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2069         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2070 #else
2071         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2072         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2073 #endif
2074
2075 #ifdef CONFIG_X86_64
2076         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2077         if (is_long_mode(&vmx->vcpu))
2078                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2079 #endif
2080         if (boot_cpu_has(X86_FEATURE_MPX))
2081                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2082         for (i = 0; i < vmx->save_nmsrs; ++i)
2083                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2084                                    vmx->guest_msrs[i].data,
2085                                    vmx->guest_msrs[i].mask);
2086 }
2087
2088 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2089 {
2090         if (!vmx->host_state.loaded)
2091                 return;
2092
2093         ++vmx->vcpu.stat.host_state_reload;
2094         vmx->host_state.loaded = 0;
2095 #ifdef CONFIG_X86_64
2096         if (is_long_mode(&vmx->vcpu))
2097                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2098 #endif
2099         if (vmx->host_state.gs_ldt_reload_needed) {
2100                 kvm_load_ldt(vmx->host_state.ldt_sel);
2101 #ifdef CONFIG_X86_64
2102                 load_gs_index(vmx->host_state.gs_sel);
2103 #else
2104                 loadsegment(gs, vmx->host_state.gs_sel);
2105 #endif
2106         }
2107         if (vmx->host_state.fs_reload_needed)
2108                 loadsegment(fs, vmx->host_state.fs_sel);
2109 #ifdef CONFIG_X86_64
2110         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2111                 loadsegment(ds, vmx->host_state.ds_sel);
2112                 loadsegment(es, vmx->host_state.es_sel);
2113         }
2114 #endif
2115         reload_tss();
2116 #ifdef CONFIG_X86_64
2117         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2118 #endif
2119         if (vmx->host_state.msr_host_bndcfgs)
2120                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2121         /*
2122          * If the FPU is not active (through the host task or
2123          * the guest vcpu), then restore the cr0.TS bit.
2124          */
2125         if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
2126                 stts();
2127         load_gdt(this_cpu_ptr(&host_gdt));
2128 }
2129
2130 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2131 {
2132         preempt_disable();
2133         __vmx_load_host_state(vmx);
2134         preempt_enable();
2135 }
2136
2137 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2138 {
2139         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2140         struct pi_desc old, new;
2141         unsigned int dest;
2142
2143         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2144                 !irq_remapping_cap(IRQ_POSTING_CAP))
2145                 return;
2146
2147         do {
2148                 old.control = new.control = pi_desc->control;
2149
2150                 /*
2151                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2152                  * are two possible cases:
2153                  * 1. After running 'pre_block', context switch
2154                  *    happened. For this case, 'sn' was set in
2155                  *    vmx_vcpu_put(), so we need to clear it here.
2156                  * 2. After running 'pre_block', we were blocked,
2157                  *    and woken up by some other guy. For this case,
2158                  *    we don't need to do anything, 'pi_post_block'
2159                  *    will do everything for us. However, we cannot
2160                  *    check whether it is case #1 or case #2 here
2161                  *    (maybe, not needed), so we also clear sn here,
2162                  *    I think it is not a big deal.
2163                  */
2164                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2165                         if (vcpu->cpu != cpu) {
2166                                 dest = cpu_physical_id(cpu);
2167
2168                                 if (x2apic_enabled())
2169                                         new.ndst = dest;
2170                                 else
2171                                         new.ndst = (dest << 8) & 0xFF00;
2172                         }
2173
2174                         /* set 'NV' to 'notification vector' */
2175                         new.nv = POSTED_INTR_VECTOR;
2176                 }
2177
2178                 /* Allow posting non-urgent interrupts */
2179                 new.sn = 0;
2180         } while (cmpxchg(&pi_desc->control, old.control,
2181                         new.control) != old.control);
2182 }
2183
2184 /*
2185  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2186  * vcpu mutex is already taken.
2187  */
2188 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2189 {
2190         struct vcpu_vmx *vmx = to_vmx(vcpu);
2191         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2192
2193         if (!vmm_exclusive)
2194                 kvm_cpu_vmxon(phys_addr);
2195         else if (vmx->loaded_vmcs->cpu != cpu)
2196                 loaded_vmcs_clear(vmx->loaded_vmcs);
2197
2198         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2199                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2200                 vmcs_load(vmx->loaded_vmcs->vmcs);
2201         }
2202
2203         if (vmx->loaded_vmcs->cpu != cpu) {
2204                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2205                 unsigned long sysenter_esp;
2206
2207                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2208                 local_irq_disable();
2209                 crash_disable_local_vmclear(cpu);
2210
2211                 /*
2212                  * Read loaded_vmcs->cpu should be before fetching
2213                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2214                  * See the comments in __loaded_vmcs_clear().
2215                  */
2216                 smp_rmb();
2217
2218                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2219                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2220                 crash_enable_local_vmclear(cpu);
2221                 local_irq_enable();
2222
2223                 /*
2224                  * Linux uses per-cpu TSS and GDT, so set these when switching
2225                  * processors.
2226                  */
2227                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
2228                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
2229
2230                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2231                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2232
2233                 vmx->loaded_vmcs->cpu = cpu;
2234         }
2235
2236         /* Setup TSC multiplier */
2237         if (kvm_has_tsc_control &&
2238             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) {
2239                 vmx->current_tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2240                 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2241         }
2242
2243         vmx_vcpu_pi_load(vcpu, cpu);
2244         vmx->host_pkru = read_pkru();
2245 }
2246
2247 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2248 {
2249         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2250
2251         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2252                 !irq_remapping_cap(IRQ_POSTING_CAP))
2253                 return;
2254
2255         /* Set SN when the vCPU is preempted */
2256         if (vcpu->preempted)
2257                 pi_set_sn(pi_desc);
2258 }
2259
2260 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2261 {
2262         vmx_vcpu_pi_put(vcpu);
2263
2264         __vmx_load_host_state(to_vmx(vcpu));
2265         if (!vmm_exclusive) {
2266                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2267                 vcpu->cpu = -1;
2268                 kvm_cpu_vmxoff();
2269         }
2270 }
2271
2272 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2273 {
2274         ulong cr0;
2275
2276         if (vcpu->fpu_active)
2277                 return;
2278         vcpu->fpu_active = 1;
2279         cr0 = vmcs_readl(GUEST_CR0);
2280         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2281         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2282         vmcs_writel(GUEST_CR0, cr0);
2283         update_exception_bitmap(vcpu);
2284         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
2285         if (is_guest_mode(vcpu))
2286                 vcpu->arch.cr0_guest_owned_bits &=
2287                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
2288         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2289 }
2290
2291 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2292
2293 /*
2294  * Return the cr0 value that a nested guest would read. This is a combination
2295  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2296  * its hypervisor (cr0_read_shadow).
2297  */
2298 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2299 {
2300         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2301                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2302 }
2303 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2304 {
2305         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2306                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2307 }
2308
2309 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2310 {
2311         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2312          * set this *before* calling this function.
2313          */
2314         vmx_decache_cr0_guest_bits(vcpu);
2315         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2316         update_exception_bitmap(vcpu);
2317         vcpu->arch.cr0_guest_owned_bits = 0;
2318         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2319         if (is_guest_mode(vcpu)) {
2320                 /*
2321                  * L1's specified read shadow might not contain the TS bit,
2322                  * so now that we turned on shadowing of this bit, we need to
2323                  * set this bit of the shadow. Like in nested_vmx_run we need
2324                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2325                  * up-to-date here because we just decached cr0.TS (and we'll
2326                  * only update vmcs12->guest_cr0 on nested exit).
2327                  */
2328                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2329                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2330                         (vcpu->arch.cr0 & X86_CR0_TS);
2331                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2332         } else
2333                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2334 }
2335
2336 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2337 {
2338         unsigned long rflags, save_rflags;
2339
2340         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2341                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2342                 rflags = vmcs_readl(GUEST_RFLAGS);
2343                 if (to_vmx(vcpu)->rmode.vm86_active) {
2344                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2345                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2346                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2347                 }
2348                 to_vmx(vcpu)->rflags = rflags;
2349         }
2350         return to_vmx(vcpu)->rflags;
2351 }
2352
2353 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2354 {
2355         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2356         to_vmx(vcpu)->rflags = rflags;
2357         if (to_vmx(vcpu)->rmode.vm86_active) {
2358                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2359                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2360         }
2361         vmcs_writel(GUEST_RFLAGS, rflags);
2362 }
2363
2364 static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2365 {
2366         return to_vmx(vcpu)->guest_pkru;
2367 }
2368
2369 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2370 {
2371         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2372         int ret = 0;
2373
2374         if (interruptibility & GUEST_INTR_STATE_STI)
2375                 ret |= KVM_X86_SHADOW_INT_STI;
2376         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2377                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2378
2379         return ret;
2380 }
2381
2382 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2383 {
2384         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2385         u32 interruptibility = interruptibility_old;
2386
2387         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2388
2389         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2390                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2391         else if (mask & KVM_X86_SHADOW_INT_STI)
2392                 interruptibility |= GUEST_INTR_STATE_STI;
2393
2394         if ((interruptibility != interruptibility_old))
2395                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2396 }
2397
2398 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2399 {
2400         unsigned long rip;
2401
2402         rip = kvm_rip_read(vcpu);
2403         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2404         kvm_rip_write(vcpu, rip);
2405
2406         /* skipping an emulated instruction also counts */
2407         vmx_set_interrupt_shadow(vcpu, 0);
2408 }
2409
2410 /*
2411  * KVM wants to inject page-faults which it got to the guest. This function
2412  * checks whether in a nested guest, we need to inject them to L1 or L2.
2413  */
2414 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2415 {
2416         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2417
2418         if (!(vmcs12->exception_bitmap & (1u << nr)))
2419                 return 0;
2420
2421         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2422                           vmcs_read32(VM_EXIT_INTR_INFO),
2423                           vmcs_readl(EXIT_QUALIFICATION));
2424         return 1;
2425 }
2426
2427 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2428                                 bool has_error_code, u32 error_code,
2429                                 bool reinject)
2430 {
2431         struct vcpu_vmx *vmx = to_vmx(vcpu);
2432         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2433
2434         if (!reinject && is_guest_mode(vcpu) &&
2435             nested_vmx_check_exception(vcpu, nr))
2436                 return;
2437
2438         if (has_error_code) {
2439                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2440                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2441         }
2442
2443         if (vmx->rmode.vm86_active) {
2444                 int inc_eip = 0;
2445                 if (kvm_exception_is_soft(nr))
2446                         inc_eip = vcpu->arch.event_exit_inst_len;
2447                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2448                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2449                 return;
2450         }
2451
2452         if (kvm_exception_is_soft(nr)) {
2453                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2454                              vmx->vcpu.arch.event_exit_inst_len);
2455                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2456         } else
2457                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2458
2459         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2460 }
2461
2462 static bool vmx_rdtscp_supported(void)
2463 {
2464         return cpu_has_vmx_rdtscp();
2465 }
2466
2467 static bool vmx_invpcid_supported(void)
2468 {
2469         return cpu_has_vmx_invpcid() && enable_ept;
2470 }
2471
2472 /*
2473  * Swap MSR entry in host/guest MSR entry array.
2474  */
2475 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2476 {
2477         struct shared_msr_entry tmp;
2478
2479         tmp = vmx->guest_msrs[to];
2480         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2481         vmx->guest_msrs[from] = tmp;
2482 }
2483
2484 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2485 {
2486         unsigned long *msr_bitmap;
2487
2488         if (is_guest_mode(vcpu))
2489                 msr_bitmap = vmx_msr_bitmap_nested;
2490         else if (cpu_has_secondary_exec_ctrls() &&
2491                  (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2492                   SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
2493                 if (is_long_mode(vcpu))
2494                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2495                 else
2496                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2497         } else {
2498                 if (is_long_mode(vcpu))
2499                         msr_bitmap = vmx_msr_bitmap_longmode;
2500                 else
2501                         msr_bitmap = vmx_msr_bitmap_legacy;
2502         }
2503
2504         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2505 }
2506
2507 /*
2508  * Set up the vmcs to automatically save and restore system
2509  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2510  * mode, as fiddling with msrs is very expensive.
2511  */
2512 static void setup_msrs(struct vcpu_vmx *vmx)
2513 {
2514         int save_nmsrs, index;
2515
2516         save_nmsrs = 0;
2517 #ifdef CONFIG_X86_64
2518         if (is_long_mode(&vmx->vcpu)) {
2519                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2520                 if (index >= 0)
2521                         move_msr_up(vmx, index, save_nmsrs++);
2522                 index = __find_msr_index(vmx, MSR_LSTAR);
2523                 if (index >= 0)
2524                         move_msr_up(vmx, index, save_nmsrs++);
2525                 index = __find_msr_index(vmx, MSR_CSTAR);
2526                 if (index >= 0)
2527                         move_msr_up(vmx, index, save_nmsrs++);
2528                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2529                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2530                         move_msr_up(vmx, index, save_nmsrs++);
2531                 /*
2532                  * MSR_STAR is only needed on long mode guests, and only
2533                  * if efer.sce is enabled.
2534                  */
2535                 index = __find_msr_index(vmx, MSR_STAR);
2536                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2537                         move_msr_up(vmx, index, save_nmsrs++);
2538         }
2539 #endif
2540         index = __find_msr_index(vmx, MSR_EFER);
2541         if (index >= 0 && update_transition_efer(vmx, index))
2542                 move_msr_up(vmx, index, save_nmsrs++);
2543
2544         vmx->save_nmsrs = save_nmsrs;
2545
2546         if (cpu_has_vmx_msr_bitmap())
2547                 vmx_set_msr_bitmap(&vmx->vcpu);
2548 }
2549
2550 /*
2551  * reads and returns guest's timestamp counter "register"
2552  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2553  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2554  */
2555 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2556 {
2557         u64 host_tsc, tsc_offset;
2558
2559         host_tsc = rdtsc();
2560         tsc_offset = vmcs_read64(TSC_OFFSET);
2561         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2562 }
2563
2564 /*
2565  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2566  * counter, even if a nested guest (L2) is currently running.
2567  */
2568 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2569 {
2570         u64 tsc_offset;
2571
2572         tsc_offset = is_guest_mode(vcpu) ?
2573                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2574                 vmcs_read64(TSC_OFFSET);
2575         return host_tsc + tsc_offset;
2576 }
2577
2578 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2579 {
2580         return vmcs_read64(TSC_OFFSET);
2581 }
2582
2583 /*
2584  * writes 'offset' into guest's timestamp counter offset register
2585  */
2586 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2587 {
2588         if (is_guest_mode(vcpu)) {
2589                 /*
2590                  * We're here if L1 chose not to trap WRMSR to TSC. According
2591                  * to the spec, this should set L1's TSC; The offset that L1
2592                  * set for L2 remains unchanged, and still needs to be added
2593                  * to the newly set TSC to get L2's TSC.
2594                  */
2595                 struct vmcs12 *vmcs12;
2596                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2597                 /* recalculate vmcs02.TSC_OFFSET: */
2598                 vmcs12 = get_vmcs12(vcpu);
2599                 vmcs_write64(TSC_OFFSET, offset +
2600                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2601                          vmcs12->tsc_offset : 0));
2602         } else {
2603                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2604                                            vmcs_read64(TSC_OFFSET), offset);
2605                 vmcs_write64(TSC_OFFSET, offset);
2606         }
2607 }
2608
2609 static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment)
2610 {
2611         u64 offset = vmcs_read64(TSC_OFFSET);
2612
2613         vmcs_write64(TSC_OFFSET, offset + adjustment);
2614         if (is_guest_mode(vcpu)) {
2615                 /* Even when running L2, the adjustment needs to apply to L1 */
2616                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2617         } else
2618                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2619                                            offset + adjustment);
2620 }
2621
2622 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2623 {
2624         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2625         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2626 }
2627
2628 /*
2629  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2630  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2631  * all guests if the "nested" module option is off, and can also be disabled
2632  * for a single guest by disabling its VMX cpuid bit.
2633  */
2634 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2635 {
2636         return nested && guest_cpuid_has_vmx(vcpu);
2637 }
2638
2639 /*
2640  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2641  * returned for the various VMX controls MSRs when nested VMX is enabled.
2642  * The same values should also be used to verify that vmcs12 control fields are
2643  * valid during nested entry from L1 to L2.
2644  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2645  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2646  * bit in the high half is on if the corresponding bit in the control field
2647  * may be on. See also vmx_control_verify().
2648  */
2649 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2650 {
2651         /*
2652          * Note that as a general rule, the high half of the MSRs (bits in
2653          * the control fields which may be 1) should be initialized by the
2654          * intersection of the underlying hardware's MSR (i.e., features which
2655          * can be supported) and the list of features we want to expose -
2656          * because they are known to be properly supported in our code.
2657          * Also, usually, the low half of the MSRs (bits which must be 1) can
2658          * be set to 0, meaning that L1 may turn off any of these bits. The
2659          * reason is that if one of these bits is necessary, it will appear
2660          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2661          * fields of vmcs01 and vmcs02, will turn these bits off - and
2662          * nested_vmx_exit_handled() will not pass related exits to L1.
2663          * These rules have exceptions below.
2664          */
2665
2666         /* pin-based controls */
2667         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2668                 vmx->nested.nested_vmx_pinbased_ctls_low,
2669                 vmx->nested.nested_vmx_pinbased_ctls_high);
2670         vmx->nested.nested_vmx_pinbased_ctls_low |=
2671                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2672         vmx->nested.nested_vmx_pinbased_ctls_high &=
2673                 PIN_BASED_EXT_INTR_MASK |
2674                 PIN_BASED_NMI_EXITING |
2675                 PIN_BASED_VIRTUAL_NMIS;
2676         vmx->nested.nested_vmx_pinbased_ctls_high |=
2677                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2678                 PIN_BASED_VMX_PREEMPTION_TIMER;
2679         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2680                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2681                         PIN_BASED_POSTED_INTR;
2682
2683         /* exit controls */
2684         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2685                 vmx->nested.nested_vmx_exit_ctls_low,
2686                 vmx->nested.nested_vmx_exit_ctls_high);
2687         vmx->nested.nested_vmx_exit_ctls_low =
2688                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2689
2690         vmx->nested.nested_vmx_exit_ctls_high &=
2691 #ifdef CONFIG_X86_64
2692                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2693 #endif
2694                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2695         vmx->nested.nested_vmx_exit_ctls_high |=
2696                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2697                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2698                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2699
2700         if (kvm_mpx_supported())
2701                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2702
2703         /* We support free control of debug control saving. */
2704         vmx->nested.nested_vmx_true_exit_ctls_low =
2705                 vmx->nested.nested_vmx_exit_ctls_low &
2706                 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2707
2708         /* entry controls */
2709         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2710                 vmx->nested.nested_vmx_entry_ctls_low,
2711                 vmx->nested.nested_vmx_entry_ctls_high);
2712         vmx->nested.nested_vmx_entry_ctls_low =
2713                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2714         vmx->nested.nested_vmx_entry_ctls_high &=
2715 #ifdef CONFIG_X86_64
2716                 VM_ENTRY_IA32E_MODE |
2717 #endif
2718                 VM_ENTRY_LOAD_IA32_PAT;
2719         vmx->nested.nested_vmx_entry_ctls_high |=
2720                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2721         if (kvm_mpx_supported())
2722                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2723
2724         /* We support free control of debug control loading. */
2725         vmx->nested.nested_vmx_true_entry_ctls_low =
2726                 vmx->nested.nested_vmx_entry_ctls_low &
2727                 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2728
2729         /* cpu-based controls */
2730         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2731                 vmx->nested.nested_vmx_procbased_ctls_low,
2732                 vmx->nested.nested_vmx_procbased_ctls_high);
2733         vmx->nested.nested_vmx_procbased_ctls_low =
2734                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2735         vmx->nested.nested_vmx_procbased_ctls_high &=
2736                 CPU_BASED_VIRTUAL_INTR_PENDING |
2737                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2738                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2739                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2740                 CPU_BASED_CR3_STORE_EXITING |
2741 #ifdef CONFIG_X86_64
2742                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2743 #endif
2744                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2745                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2746                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2747                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2748                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2749         /*
2750          * We can allow some features even when not supported by the
2751          * hardware. For example, L1 can specify an MSR bitmap - and we
2752          * can use it to avoid exits to L1 - even when L0 runs L2
2753          * without MSR bitmaps.
2754          */
2755         vmx->nested.nested_vmx_procbased_ctls_high |=
2756                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2757                 CPU_BASED_USE_MSR_BITMAPS;
2758
2759         /* We support free control of CR3 access interception. */
2760         vmx->nested.nested_vmx_true_procbased_ctls_low =
2761                 vmx->nested.nested_vmx_procbased_ctls_low &
2762                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2763
2764         /* secondary cpu-based controls */
2765         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2766                 vmx->nested.nested_vmx_secondary_ctls_low,
2767                 vmx->nested.nested_vmx_secondary_ctls_high);
2768         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2769         vmx->nested.nested_vmx_secondary_ctls_high &=
2770                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2771                 SECONDARY_EXEC_RDTSCP |
2772                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2773                 SECONDARY_EXEC_ENABLE_VPID |
2774                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2775                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2776                 SECONDARY_EXEC_WBINVD_EXITING |
2777                 SECONDARY_EXEC_XSAVES |
2778                 SECONDARY_EXEC_PCOMMIT;
2779
2780         if (enable_ept) {
2781                 /* nested EPT: emulate EPT also to L1 */
2782                 vmx->nested.nested_vmx_secondary_ctls_high |=
2783                         SECONDARY_EXEC_ENABLE_EPT;
2784                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2785                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2786                          VMX_EPT_INVEPT_BIT;
2787                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2788                 /*
2789                  * For nested guests, we don't do anything specific
2790                  * for single context invalidation. Hence, only advertise
2791                  * support for global context invalidation.
2792                  */
2793                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2794         } else
2795                 vmx->nested.nested_vmx_ept_caps = 0;
2796
2797         /*
2798          * Old versions of KVM use the single-context version without
2799          * checking for support, so declare that it is supported even
2800          * though it is treated as global context.  The alternative is
2801          * not failing the single-context invvpid, and it is worse.
2802          */
2803         if (enable_vpid)
2804                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2805                                 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |
2806                                 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
2807         else
2808                 vmx->nested.nested_vmx_vpid_caps = 0;
2809
2810         if (enable_unrestricted_guest)
2811                 vmx->nested.nested_vmx_secondary_ctls_high |=
2812                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2813
2814         /* miscellaneous data */
2815         rdmsr(MSR_IA32_VMX_MISC,
2816                 vmx->nested.nested_vmx_misc_low,
2817                 vmx->nested.nested_vmx_misc_high);
2818         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2819         vmx->nested.nested_vmx_misc_low |=
2820                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2821                 VMX_MISC_ACTIVITY_HLT;
2822         vmx->nested.nested_vmx_misc_high = 0;
2823 }
2824
2825 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2826 {
2827         /*
2828          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2829          */
2830         return ((control & high) | low) == control;
2831 }
2832
2833 static inline u64 vmx_control_msr(u32 low, u32 high)
2834 {
2835         return low | ((u64)high << 32);
2836 }
2837
2838 /* Returns 0 on success, non-0 otherwise. */
2839 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2840 {
2841         struct vcpu_vmx *vmx = to_vmx(vcpu);
2842
2843         switch (msr_index) {
2844         case MSR_IA32_VMX_BASIC:
2845                 /*
2846                  * This MSR reports some information about VMX support. We
2847                  * should return information about the VMX we emulate for the
2848                  * guest, and the VMCS structure we give it - not about the
2849                  * VMX support of the underlying hardware.
2850                  */
2851                 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2852                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2853                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2854                 break;
2855         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2856         case MSR_IA32_VMX_PINBASED_CTLS:
2857                 *pdata = vmx_control_msr(
2858                         vmx->nested.nested_vmx_pinbased_ctls_low,
2859                         vmx->nested.nested_vmx_pinbased_ctls_high);
2860                 break;
2861         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2862                 *pdata = vmx_control_msr(
2863                         vmx->nested.nested_vmx_true_procbased_ctls_low,
2864                         vmx->nested.nested_vmx_procbased_ctls_high);
2865                 break;
2866         case MSR_IA32_VMX_PROCBASED_CTLS:
2867                 *pdata = vmx_control_msr(
2868                         vmx->nested.nested_vmx_procbased_ctls_low,
2869                         vmx->nested.nested_vmx_procbased_ctls_high);
2870                 break;
2871         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2872                 *pdata = vmx_control_msr(
2873                         vmx->nested.nested_vmx_true_exit_ctls_low,
2874                         vmx->nested.nested_vmx_exit_ctls_high);
2875                 break;
2876         case MSR_IA32_VMX_EXIT_CTLS:
2877                 *pdata = vmx_control_msr(
2878                         vmx->nested.nested_vmx_exit_ctls_low,
2879                         vmx->nested.nested_vmx_exit_ctls_high);
2880                 break;
2881         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2882                 *pdata = vmx_control_msr(
2883                         vmx->nested.nested_vmx_true_entry_ctls_low,
2884                         vmx->nested.nested_vmx_entry_ctls_high);
2885                 break;
2886         case MSR_IA32_VMX_ENTRY_CTLS:
2887                 *pdata = vmx_control_msr(
2888                         vmx->nested.nested_vmx_entry_ctls_low,
2889                         vmx->nested.nested_vmx_entry_ctls_high);
2890                 break;
2891         case MSR_IA32_VMX_MISC:
2892                 *pdata = vmx_control_msr(
2893                         vmx->nested.nested_vmx_misc_low,
2894                         vmx->nested.nested_vmx_misc_high);
2895                 break;
2896         /*
2897          * These MSRs specify bits which the guest must keep fixed (on or off)
2898          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2899          * We picked the standard core2 setting.
2900          */
2901 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2902 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2903         case MSR_IA32_VMX_CR0_FIXED0:
2904                 *pdata = VMXON_CR0_ALWAYSON;
2905                 break;
2906         case MSR_IA32_VMX_CR0_FIXED1:
2907                 *pdata = -1ULL;
2908                 break;
2909         case MSR_IA32_VMX_CR4_FIXED0:
2910                 *pdata = VMXON_CR4_ALWAYSON;
2911                 break;
2912         case MSR_IA32_VMX_CR4_FIXED1:
2913                 *pdata = -1ULL;
2914                 break;
2915         case MSR_IA32_VMX_VMCS_ENUM:
2916                 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2917                 break;
2918         case MSR_IA32_VMX_PROCBASED_CTLS2:
2919                 *pdata = vmx_control_msr(
2920                         vmx->nested.nested_vmx_secondary_ctls_low,
2921                         vmx->nested.nested_vmx_secondary_ctls_high);
2922                 break;
2923         case MSR_IA32_VMX_EPT_VPID_CAP:
2924                 /* Currently, no nested vpid support */
2925                 *pdata = vmx->nested.nested_vmx_ept_caps |
2926                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
2927                 break;
2928         default:
2929                 return 1;
2930         }
2931
2932         return 0;
2933 }
2934
2935 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
2936                                                  uint64_t val)
2937 {
2938         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
2939
2940         return !(val & ~valid_bits);
2941 }
2942
2943 /*
2944  * Reads an msr value (of 'msr_index') into 'pdata'.
2945  * Returns 0 on success, non-0 otherwise.
2946  * Assumes vcpu_load() was already called.
2947  */
2948 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2949 {
2950         struct shared_msr_entry *msr;
2951
2952         switch (msr_info->index) {
2953 #ifdef CONFIG_X86_64
2954         case MSR_FS_BASE:
2955                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
2956                 break;
2957         case MSR_GS_BASE:
2958                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
2959                 break;
2960         case MSR_KERNEL_GS_BASE:
2961                 vmx_load_host_state(to_vmx(vcpu));
2962                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2963                 break;
2964 #endif
2965         case MSR_EFER:
2966                 return kvm_get_msr_common(vcpu, msr_info);
2967         case MSR_IA32_TSC:
2968                 msr_info->data = guest_read_tsc(vcpu);
2969                 break;
2970         case MSR_IA32_SYSENTER_CS:
2971                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
2972                 break;
2973         case MSR_IA32_SYSENTER_EIP:
2974                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
2975                 break;
2976         case MSR_IA32_SYSENTER_ESP:
2977                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
2978                 break;
2979         case MSR_IA32_BNDCFGS:
2980                 if (!kvm_mpx_supported())
2981                         return 1;
2982                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
2983                 break;
2984         case MSR_IA32_MCG_EXT_CTL:
2985                 if (!msr_info->host_initiated &&
2986                     !(to_vmx(vcpu)->msr_ia32_feature_control &
2987                       FEATURE_CONTROL_LMCE))
2988                         return 1;
2989                 msr_info->data = vcpu->arch.mcg_ext_ctl;
2990                 break;
2991         case MSR_IA32_FEATURE_CONTROL:
2992                 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
2993                 break;
2994         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2995                 if (!nested_vmx_allowed(vcpu))
2996                         return 1;
2997                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
2998         case MSR_IA32_XSS:
2999                 if (!vmx_xsaves_supported())
3000                         return 1;
3001                 msr_info->data = vcpu->arch.ia32_xss;
3002                 break;
3003         case MSR_TSC_AUX:
3004                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3005                         return 1;
3006                 /* Otherwise falls through */
3007         default:
3008                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3009                 if (msr) {
3010                         msr_info->data = msr->data;
3011                         break;
3012                 }
3013                 return kvm_get_msr_common(vcpu, msr_info);
3014         }
3015
3016         return 0;
3017 }
3018
3019 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3020
3021 /*
3022  * Writes msr value into into the appropriate "register".
3023  * Returns 0 on success, non-0 otherwise.
3024  * Assumes vcpu_load() was already called.
3025  */
3026 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3027 {
3028         struct vcpu_vmx *vmx = to_vmx(vcpu);
3029         struct shared_msr_entry *msr;
3030         int ret = 0;
3031         u32 msr_index = msr_info->index;
3032         u64 data = msr_info->data;
3033
3034         switch (msr_index) {
3035         case MSR_EFER:
3036                 ret = kvm_set_msr_common(vcpu, msr_info);
3037                 break;
3038 #ifdef CONFIG_X86_64
3039         case MSR_FS_BASE:
3040                 vmx_segment_cache_clear(vmx);
3041                 vmcs_writel(GUEST_FS_BASE, data);
3042                 break;
3043         case MSR_GS_BASE:
3044                 vmx_segment_cache_clear(vmx);
3045                 vmcs_writel(GUEST_GS_BASE, data);
3046                 break;
3047         case MSR_KERNEL_GS_BASE:
3048                 vmx_load_host_state(vmx);
3049                 vmx->msr_guest_kernel_gs_base = data;
3050                 break;
3051 #endif
3052         case MSR_IA32_SYSENTER_CS:
3053                 vmcs_write32(GUEST_SYSENTER_CS, data);
3054                 break;
3055         case MSR_IA32_SYSENTER_EIP:
3056                 vmcs_writel(GUEST_SYSENTER_EIP, data);
3057                 break;
3058         case MSR_IA32_SYSENTER_ESP:
3059                 vmcs_writel(GUEST_SYSENTER_ESP, data);
3060                 break;
3061         case MSR_IA32_BNDCFGS:
3062                 if (!kvm_mpx_supported())
3063                         return 1;
3064                 vmcs_write64(GUEST_BNDCFGS, data);
3065                 break;
3066         case MSR_IA32_TSC:
3067                 kvm_write_tsc(vcpu, msr_info);
3068                 break;
3069         case MSR_IA32_CR_PAT:
3070                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3071                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3072                                 return 1;
3073                         vmcs_write64(GUEST_IA32_PAT, data);
3074                         vcpu->arch.pat = data;
3075                         break;
3076                 }
3077                 ret = kvm_set_msr_common(vcpu, msr_info);
3078                 break;
3079         case MSR_IA32_TSC_ADJUST:
3080                 ret = kvm_set_msr_common(vcpu, msr_info);
3081                 break;
3082         case MSR_IA32_MCG_EXT_CTL:
3083                 if ((!msr_info->host_initiated &&
3084                      !(to_vmx(vcpu)->msr_ia32_feature_control &
3085                        FEATURE_CONTROL_LMCE)) ||
3086                     (data & ~MCG_EXT_CTL_LMCE_EN))
3087                         return 1;
3088                 vcpu->arch.mcg_ext_ctl = data;
3089                 break;
3090         case MSR_IA32_FEATURE_CONTROL:
3091                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3092                     (to_vmx(vcpu)->msr_ia32_feature_control &
3093                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3094                         return 1;
3095                 vmx->msr_ia32_feature_control = data;
3096                 if (msr_info->host_initiated && data == 0)
3097                         vmx_leave_nested(vcpu);
3098                 break;
3099         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3100                 return 1; /* they are read-only */
3101         case MSR_IA32_XSS:
3102                 if (!vmx_xsaves_supported())
3103                         return 1;
3104                 /*
3105                  * The only supported bit as of Skylake is bit 8, but
3106                  * it is not supported on KVM.
3107                  */
3108                 if (data != 0)
3109                         return 1;
3110                 vcpu->arch.ia32_xss = data;
3111                 if (vcpu->arch.ia32_xss != host_xss)
3112                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3113                                 vcpu->arch.ia32_xss, host_xss);
3114                 else
3115                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3116                 break;
3117         case MSR_TSC_AUX:
3118                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3119                         return 1;
3120                 /* Check reserved bit, higher 32 bits should be zero */
3121                 if ((data >> 32) != 0)
3122                         return 1;
3123                 /* Otherwise falls through */
3124         default:
3125                 msr = find_msr_entry(vmx, msr_index);
3126                 if (msr) {
3127                         u64 old_msr_data = msr->data;
3128                         msr->data = data;
3129                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3130                                 preempt_disable();
3131                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3132                                                          msr->mask);
3133                                 preempt_enable();
3134                                 if (ret)
3135                                         msr->data = old_msr_data;
3136                         }
3137                         break;
3138                 }
3139                 ret = kvm_set_msr_common(vcpu, msr_info);
3140         }
3141
3142         return ret;
3143 }
3144
3145 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3146 {
3147         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3148         switch (reg) {
3149         case VCPU_REGS_RSP:
3150                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3151                 break;
3152         case VCPU_REGS_RIP:
3153                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3154                 break;
3155         case VCPU_EXREG_PDPTR:
3156                 if (enable_ept)
3157                         ept_save_pdptrs(vcpu);
3158                 break;
3159         default:
3160                 break;
3161         }
3162 }
3163
3164 static __init int cpu_has_kvm_support(void)
3165 {
3166         return cpu_has_vmx();
3167 }
3168
3169 static __init int vmx_disabled_by_bios(void)
3170 {
3171         u64 msr;
3172
3173         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3174         if (msr & FEATURE_CONTROL_LOCKED) {
3175                 /* launched w/ TXT and VMX disabled */
3176                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3177                         && tboot_enabled())
3178                         return 1;
3179                 /* launched w/o TXT and VMX only enabled w/ TXT */
3180                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3181                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3182                         && !tboot_enabled()) {
3183                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3184                                 "activate TXT before enabling KVM\n");
3185                         return 1;
3186                 }
3187                 /* launched w/o TXT and VMX disabled */
3188                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3189                         && !tboot_enabled())
3190                         return 1;
3191         }
3192
3193         return 0;
3194 }
3195
3196 static void kvm_cpu_vmxon(u64 addr)
3197 {
3198         intel_pt_handle_vmx(1);
3199
3200         asm volatile (ASM_VMX_VMXON_RAX
3201                         : : "a"(&addr), "m"(addr)
3202                         : "memory", "cc");
3203 }
3204
3205 static int hardware_enable(void)
3206 {
3207         int cpu = raw_smp_processor_id();
3208         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3209         u64 old, test_bits;
3210
3211         if (cr4_read_shadow() & X86_CR4_VMXE)
3212                 return -EBUSY;
3213
3214         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3215         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3216         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3217
3218         /*
3219          * Now we can enable the vmclear operation in kdump
3220          * since the loaded_vmcss_on_cpu list on this cpu
3221          * has been initialized.
3222          *
3223          * Though the cpu is not in VMX operation now, there
3224          * is no problem to enable the vmclear operation
3225          * for the loaded_vmcss_on_cpu list is empty!
3226          */
3227         crash_enable_local_vmclear(cpu);
3228
3229         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3230
3231         test_bits = FEATURE_CONTROL_LOCKED;
3232         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3233         if (tboot_enabled())
3234                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3235
3236         if ((old & test_bits) != test_bits) {
3237                 /* enable and lock */
3238                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3239         }
3240         cr4_set_bits(X86_CR4_VMXE);
3241
3242         if (vmm_exclusive) {
3243                 kvm_cpu_vmxon(phys_addr);
3244                 ept_sync_global();
3245         }
3246
3247         native_store_gdt(this_cpu_ptr(&host_gdt));
3248
3249         return 0;
3250 }
3251
3252 static void vmclear_local_loaded_vmcss(void)
3253 {
3254         int cpu = raw_smp_processor_id();
3255         struct loaded_vmcs *v, *n;
3256
3257         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3258                                  loaded_vmcss_on_cpu_link)
3259                 __loaded_vmcs_clear(v);
3260 }
3261
3262
3263 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3264  * tricks.
3265  */
3266 static void kvm_cpu_vmxoff(void)
3267 {
3268         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3269
3270         intel_pt_handle_vmx(0);
3271 }
3272
3273 static void hardware_disable(void)
3274 {
3275         if (vmm_exclusive) {
3276                 vmclear_local_loaded_vmcss();
3277                 kvm_cpu_vmxoff();
3278         }
3279         cr4_clear_bits(X86_CR4_VMXE);
3280 }
3281
3282 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3283                                       u32 msr, u32 *result)
3284 {
3285         u32 vmx_msr_low, vmx_msr_high;
3286         u32 ctl = ctl_min | ctl_opt;
3287
3288         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3289
3290         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3291         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3292
3293         /* Ensure minimum (required) set of control bits are supported. */
3294         if (ctl_min & ~ctl)
3295                 return -EIO;
3296
3297         *result = ctl;
3298         return 0;
3299 }
3300
3301 static __init bool allow_1_setting(u32 msr, u32 ctl)
3302 {
3303         u32 vmx_msr_low, vmx_msr_high;
3304
3305         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3306         return vmx_msr_high & ctl;
3307 }
3308
3309 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3310 {
3311         u32 vmx_msr_low, vmx_msr_high;
3312         u32 min, opt, min2, opt2;
3313         u32 _pin_based_exec_control = 0;
3314         u32 _cpu_based_exec_control = 0;
3315         u32 _cpu_based_2nd_exec_control = 0;
3316         u32 _vmexit_control = 0;
3317         u32 _vmentry_control = 0;
3318
3319         min = CPU_BASED_HLT_EXITING |
3320 #ifdef CONFIG_X86_64
3321               CPU_BASED_CR8_LOAD_EXITING |
3322               CPU_BASED_CR8_STORE_EXITING |
3323 #endif
3324               CPU_BASED_CR3_LOAD_EXITING |
3325               CPU_BASED_CR3_STORE_EXITING |
3326               CPU_BASED_USE_IO_BITMAPS |
3327               CPU_BASED_MOV_DR_EXITING |
3328               CPU_BASED_USE_TSC_OFFSETING |
3329               CPU_BASED_MWAIT_EXITING |
3330               CPU_BASED_MONITOR_EXITING |
3331               CPU_BASED_INVLPG_EXITING |
3332               CPU_BASED_RDPMC_EXITING;
3333
3334         opt = CPU_BASED_TPR_SHADOW |
3335               CPU_BASED_USE_MSR_BITMAPS |
3336               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3337         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3338                                 &_cpu_based_exec_control) < 0)
3339                 return -EIO;
3340 #ifdef CONFIG_X86_64
3341         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3342                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3343                                            ~CPU_BASED_CR8_STORE_EXITING;
3344 #endif
3345         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3346                 min2 = 0;
3347                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3348                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3349                         SECONDARY_EXEC_WBINVD_EXITING |
3350                         SECONDARY_EXEC_ENABLE_VPID |
3351                         SECONDARY_EXEC_ENABLE_EPT |
3352                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3353                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3354                         SECONDARY_EXEC_RDTSCP |
3355                         SECONDARY_EXEC_ENABLE_INVPCID |
3356                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3357                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3358                         SECONDARY_EXEC_SHADOW_VMCS |
3359                         SECONDARY_EXEC_XSAVES |
3360                         SECONDARY_EXEC_ENABLE_PML |
3361                         SECONDARY_EXEC_PCOMMIT |
3362                         SECONDARY_EXEC_TSC_SCALING;
3363                 if (adjust_vmx_controls(min2, opt2,
3364                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3365                                         &_cpu_based_2nd_exec_control) < 0)
3366                         return -EIO;
3367         }
3368 #ifndef CONFIG_X86_64
3369         if (!(_cpu_based_2nd_exec_control &
3370                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3371                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3372 #endif
3373
3374         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3375                 _cpu_based_2nd_exec_control &= ~(
3376                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3377                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3378                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3379
3380         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3381                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3382                    enabled */
3383                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3384                                              CPU_BASED_CR3_STORE_EXITING |
3385                                              CPU_BASED_INVLPG_EXITING);
3386                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3387                       vmx_capability.ept, vmx_capability.vpid);
3388         }
3389
3390         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
3391 #ifdef CONFIG_X86_64
3392         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3393 #endif
3394         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3395                 VM_EXIT_CLEAR_BNDCFGS;
3396         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3397                                 &_vmexit_control) < 0)
3398                 return -EIO;
3399
3400         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3401         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
3402                  PIN_BASED_VMX_PREEMPTION_TIMER;
3403         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3404                                 &_pin_based_exec_control) < 0)
3405                 return -EIO;
3406
3407         if (cpu_has_broken_vmx_preemption_timer())
3408                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3409         if (!(_cpu_based_2nd_exec_control &
3410                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
3411                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3412
3413         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3414         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3415         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3416                                 &_vmentry_control) < 0)
3417                 return -EIO;
3418
3419         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3420
3421         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3422         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3423                 return -EIO;
3424
3425 #ifdef CONFIG_X86_64
3426         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3427         if (vmx_msr_high & (1u<<16))
3428                 return -EIO;
3429 #endif
3430
3431         /* Require Write-Back (WB) memory type for VMCS accesses. */
3432         if (((vmx_msr_high >> 18) & 15) != 6)
3433                 return -EIO;
3434
3435         vmcs_conf->size = vmx_msr_high & 0x1fff;
3436         vmcs_conf->order = get_order(vmcs_config.size);
3437         vmcs_conf->revision_id = vmx_msr_low;
3438
3439         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3440         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3441         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3442         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3443         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3444
3445         cpu_has_load_ia32_efer =
3446                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3447                                 VM_ENTRY_LOAD_IA32_EFER)
3448                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3449                                    VM_EXIT_LOAD_IA32_EFER);
3450
3451         cpu_has_load_perf_global_ctrl =
3452                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3453                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3454                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3455                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3456
3457         /*
3458          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3459          * but due to errata below it can't be used. Workaround is to use
3460          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3461          *
3462          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3463          *
3464          * AAK155             (model 26)
3465          * AAP115             (model 30)
3466          * AAT100             (model 37)
3467          * BC86,AAY89,BD102   (model 44)
3468          * BA97               (model 46)
3469          *
3470          */
3471         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3472                 switch (boot_cpu_data.x86_model) {
3473                 case 26:
3474                 case 30:
3475                 case 37:
3476                 case 44:
3477                 case 46:
3478                         cpu_has_load_perf_global_ctrl = false;
3479                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3480                                         "does not work properly. Using workaround\n");
3481                         break;
3482                 default:
3483                         break;
3484                 }
3485         }
3486
3487         if (boot_cpu_has(X86_FEATURE_XSAVES))
3488                 rdmsrl(MSR_IA32_XSS, host_xss);
3489
3490         return 0;
3491 }
3492
3493 static struct vmcs *alloc_vmcs_cpu(int cpu)
3494 {
3495         int node = cpu_to_node(cpu);
3496         struct page *pages;
3497         struct vmcs *vmcs;
3498
3499         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3500         if (!pages)
3501                 return NULL;
3502         vmcs = page_address(pages);
3503         memset(vmcs, 0, vmcs_config.size);
3504         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3505         return vmcs;
3506 }
3507
3508 static struct vmcs *alloc_vmcs(void)
3509 {
3510         return alloc_vmcs_cpu(raw_smp_processor_id());
3511 }
3512
3513 static void free_vmcs(struct vmcs *vmcs)
3514 {
3515         free_pages((unsigned long)vmcs, vmcs_config.order);
3516 }
3517
3518 /*
3519  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3520  */
3521 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3522 {
3523         if (!loaded_vmcs->vmcs)
3524                 return;
3525         loaded_vmcs_clear(loaded_vmcs);
3526         free_vmcs(loaded_vmcs->vmcs);
3527         loaded_vmcs->vmcs = NULL;
3528 }
3529
3530 static void free_kvm_area(void)
3531 {
3532         int cpu;
3533
3534         for_each_possible_cpu(cpu) {
3535                 free_vmcs(per_cpu(vmxarea, cpu));
3536                 per_cpu(vmxarea, cpu) = NULL;
3537         }
3538 }
3539
3540 static void init_vmcs_shadow_fields(void)
3541 {
3542         int i, j;
3543
3544         /* No checks for read only fields yet */
3545
3546         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3547                 switch (shadow_read_write_fields[i]) {
3548                 case GUEST_BNDCFGS:
3549                         if (!kvm_mpx_supported())
3550                                 continue;
3551                         break;
3552                 default:
3553                         break;
3554                 }
3555
3556                 if (j < i)
3557                         shadow_read_write_fields[j] =
3558                                 shadow_read_write_fields[i];
3559                 j++;
3560         }
3561         max_shadow_read_write_fields = j;
3562
3563         /* shadowed fields guest access without vmexit */
3564         for (i = 0; i < max_shadow_read_write_fields; i++) {
3565                 clear_bit(shadow_read_write_fields[i],
3566                           vmx_vmwrite_bitmap);
3567                 clear_bit(shadow_read_write_fields[i],
3568                           vmx_vmread_bitmap);
3569         }
3570         for (i = 0; i < max_shadow_read_only_fields; i++)
3571                 clear_bit(shadow_read_only_fields[i],
3572                           vmx_vmread_bitmap);
3573 }
3574
3575 static __init int alloc_kvm_area(void)
3576 {
3577         int cpu;
3578
3579         for_each_possible_cpu(cpu) {
3580                 struct vmcs *vmcs;
3581
3582                 vmcs = alloc_vmcs_cpu(cpu);
3583                 if (!vmcs) {
3584                         free_kvm_area();
3585                         return -ENOMEM;
3586                 }
3587
3588                 per_cpu(vmxarea, cpu) = vmcs;
3589         }
3590         return 0;
3591 }
3592
3593 static bool emulation_required(struct kvm_vcpu *vcpu)
3594 {
3595         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3596 }
3597
3598 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3599                 struct kvm_segment *save)
3600 {
3601         if (!emulate_invalid_guest_state) {
3602                 /*
3603                  * CS and SS RPL should be equal during guest entry according
3604                  * to VMX spec, but in reality it is not always so. Since vcpu
3605                  * is in the middle of the transition from real mode to
3606                  * protected mode it is safe to assume that RPL 0 is a good
3607                  * default value.
3608                  */
3609                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3610                         save->selector &= ~SEGMENT_RPL_MASK;
3611                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3612                 save->s = 1;
3613         }
3614         vmx_set_segment(vcpu, save, seg);
3615 }
3616
3617 static void enter_pmode(struct kvm_vcpu *vcpu)
3618 {
3619         unsigned long flags;
3620         struct vcpu_vmx *vmx = to_vmx(vcpu);
3621
3622         /*
3623          * Update real mode segment cache. It may be not up-to-date if sement
3624          * register was written while vcpu was in a guest mode.
3625          */
3626         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3627         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3628         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3629         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3630         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3631         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3632
3633         vmx->rmode.vm86_active = 0;
3634
3635         vmx_segment_cache_clear(vmx);
3636
3637         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3638
3639         flags = vmcs_readl(GUEST_RFLAGS);
3640         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3641         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3642         vmcs_writel(GUEST_RFLAGS, flags);
3643
3644         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3645                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3646
3647         update_exception_bitmap(vcpu);
3648
3649         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3650         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3651         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3652         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3653         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3654         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3655 }
3656
3657 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3658 {
3659         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3660         struct kvm_segment var = *save;
3661
3662         var.dpl = 0x3;
3663         if (seg == VCPU_SREG_CS)
3664                 var.type = 0x3;
3665
3666         if (!emulate_invalid_guest_state) {
3667                 var.selector = var.base >> 4;
3668                 var.base = var.base & 0xffff0;
3669                 var.limit = 0xffff;
3670                 var.g = 0;
3671                 var.db = 0;
3672                 var.present = 1;
3673                 var.s = 1;
3674                 var.l = 0;
3675                 var.unusable = 0;
3676                 var.type = 0x3;
3677                 var.avl = 0;
3678                 if (save->base & 0xf)
3679                         printk_once(KERN_WARNING "kvm: segment base is not "
3680                                         "paragraph aligned when entering "
3681                                         "protected mode (seg=%d)", seg);
3682         }
3683
3684         vmcs_write16(sf->selector, var.selector);
3685         vmcs_write32(sf->base, var.base);
3686         vmcs_write32(sf->limit, var.limit);
3687         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3688 }
3689
3690 static void enter_rmode(struct kvm_vcpu *vcpu)
3691 {
3692         unsigned long flags;
3693         struct vcpu_vmx *vmx = to_vmx(vcpu);
3694
3695         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3696         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3697         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3698         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3699         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3700         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3701         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3702
3703         vmx->rmode.vm86_active = 1;
3704
3705         /*
3706          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3707          * vcpu. Warn the user that an update is overdue.
3708          */
3709         if (!vcpu->kvm->arch.tss_addr)
3710                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3711                              "called before entering vcpu\n");
3712
3713         vmx_segment_cache_clear(vmx);
3714
3715         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3716         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3717         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3718
3719         flags = vmcs_readl(GUEST_RFLAGS);
3720         vmx->rmode.save_rflags = flags;
3721
3722         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3723
3724         vmcs_writel(GUEST_RFLAGS, flags);
3725         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3726         update_exception_bitmap(vcpu);
3727
3728         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3729         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3730         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3731         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3732         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3733         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3734
3735         kvm_mmu_reset_context(vcpu);
3736 }
3737
3738 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3739 {
3740         struct vcpu_vmx *vmx = to_vmx(vcpu);
3741         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3742
3743         if (!msr)
3744                 return;
3745
3746         /*
3747          * Force kernel_gs_base reloading before EFER changes, as control
3748          * of this msr depends on is_long_mode().
3749          */
3750         vmx_load_host_state(to_vmx(vcpu));
3751         vcpu->arch.efer = efer;
3752         if (efer & EFER_LMA) {
3753                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3754                 msr->data = efer;
3755         } else {
3756                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3757
3758                 msr->data = efer & ~EFER_LME;
3759         }
3760         setup_msrs(vmx);
3761 }
3762
3763 #ifdef CONFIG_X86_64
3764
3765 static void enter_lmode(struct kvm_vcpu *vcpu)
3766 {
3767         u32 guest_tr_ar;
3768
3769         vmx_segment_cache_clear(to_vmx(vcpu));
3770
3771         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3772         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3773                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3774                                      __func__);
3775                 vmcs_write32(GUEST_TR_AR_BYTES,
3776                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3777                              | VMX_AR_TYPE_BUSY_64_TSS);
3778         }
3779         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3780 }
3781
3782 static void exit_lmode(struct kvm_vcpu *vcpu)
3783 {
3784         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3785         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3786 }
3787
3788 #endif
3789
3790 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
3791 {
3792         vpid_sync_context(vpid);
3793         if (enable_ept) {
3794                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3795                         return;
3796                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3797         }
3798 }
3799
3800 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3801 {
3802         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
3803 }
3804
3805 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3806 {
3807         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3808
3809         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3810         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3811 }
3812
3813 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3814 {
3815         if (enable_ept && is_paging(vcpu))
3816                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3817         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3818 }
3819
3820 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3821 {
3822         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3823
3824         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3825         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3826 }
3827
3828 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3829 {
3830         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3831
3832         if (!test_bit(VCPU_EXREG_PDPTR,
3833                       (unsigned long *)&vcpu->arch.regs_dirty))
3834                 return;
3835
3836         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3837                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3838                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3839                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3840                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3841         }
3842 }
3843
3844 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3845 {
3846         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3847
3848         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3849                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3850                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3851                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3852                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3853         }
3854
3855         __set_bit(VCPU_EXREG_PDPTR,
3856                   (unsigned long *)&vcpu->arch.regs_avail);
3857         __set_bit(VCPU_EXREG_PDPTR,
3858                   (unsigned long *)&vcpu->arch.regs_dirty);
3859 }
3860
3861 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3862
3863 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3864                                         unsigned long cr0,
3865                                         struct kvm_vcpu *vcpu)
3866 {
3867         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3868                 vmx_decache_cr3(vcpu);
3869         if (!(cr0 & X86_CR0_PG)) {
3870                 /* From paging/starting to nonpaging */
3871                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3872                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3873                              (CPU_BASED_CR3_LOAD_EXITING |
3874                               CPU_BASED_CR3_STORE_EXITING));
3875                 vcpu->arch.cr0 = cr0;
3876                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3877         } else if (!is_paging(vcpu)) {
3878                 /* From nonpaging to paging */
3879                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3880                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3881                              ~(CPU_BASED_CR3_LOAD_EXITING |
3882                                CPU_BASED_CR3_STORE_EXITING));
3883                 vcpu->arch.cr0 = cr0;
3884                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3885         }
3886
3887         if (!(cr0 & X86_CR0_WP))
3888                 *hw_cr0 &= ~X86_CR0_WP;
3889 }
3890
3891 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3892 {
3893         struct vcpu_vmx *vmx = to_vmx(vcpu);
3894         unsigned long hw_cr0;
3895
3896         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3897         if (enable_unrestricted_guest)
3898                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3899         else {
3900                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3901
3902                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3903                         enter_pmode(vcpu);
3904
3905                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3906                         enter_rmode(vcpu);
3907         }
3908
3909 #ifdef CONFIG_X86_64
3910         if (vcpu->arch.efer & EFER_LME) {
3911                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3912                         enter_lmode(vcpu);
3913                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3914                         exit_lmode(vcpu);
3915         }
3916 #endif
3917
3918         if (enable_ept)
3919                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3920
3921         if (!vcpu->fpu_active)
3922                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3923
3924         vmcs_writel(CR0_READ_SHADOW, cr0);
3925         vmcs_writel(GUEST_CR0, hw_cr0);
3926         vcpu->arch.cr0 = cr0;
3927
3928         /* depends on vcpu->arch.cr0 to be set to a new value */
3929         vmx->emulation_required = emulation_required(vcpu);
3930 }
3931
3932 static u64 construct_eptp(unsigned long root_hpa)
3933 {
3934         u64 eptp;
3935
3936         /* TODO write the value reading from MSR */
3937         eptp = VMX_EPT_DEFAULT_MT |
3938                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3939         if (enable_ept_ad_bits)
3940                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3941         eptp |= (root_hpa & PAGE_MASK);
3942
3943         return eptp;
3944 }
3945
3946 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3947 {
3948         unsigned long guest_cr3;
3949         u64 eptp;
3950
3951         guest_cr3 = cr3;
3952         if (enable_ept) {
3953                 eptp = construct_eptp(cr3);
3954                 vmcs_write64(EPT_POINTER, eptp);
3955                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3956                         guest_cr3 = kvm_read_cr3(vcpu);
3957                 else
3958                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3959                 ept_load_pdptrs(vcpu);
3960         }
3961
3962         vmx_flush_tlb(vcpu);
3963         vmcs_writel(GUEST_CR3, guest_cr3);
3964 }
3965
3966 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3967 {
3968         /*
3969          * Pass through host's Machine Check Enable value to hw_cr4, which
3970          * is in force while we are in guest mode.  Do not let guests control
3971          * this bit, even if host CR4.MCE == 0.
3972          */
3973         unsigned long hw_cr4 =
3974                 (cr4_read_shadow() & X86_CR4_MCE) |
3975                 (cr4 & ~X86_CR4_MCE) |
3976                 (to_vmx(vcpu)->rmode.vm86_active ?
3977                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3978
3979         if (cr4 & X86_CR4_VMXE) {
3980                 /*
3981                  * To use VMXON (and later other VMX instructions), a guest
3982                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3983                  * So basically the check on whether to allow nested VMX
3984                  * is here.
3985                  */
3986                 if (!nested_vmx_allowed(vcpu))
3987                         return 1;
3988         }
3989         if (to_vmx(vcpu)->nested.vmxon &&
3990             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3991                 return 1;
3992
3993         vcpu->arch.cr4 = cr4;
3994         if (enable_ept) {
3995                 if (!is_paging(vcpu)) {
3996                         hw_cr4 &= ~X86_CR4_PAE;
3997                         hw_cr4 |= X86_CR4_PSE;
3998                 } else if (!(cr4 & X86_CR4_PAE)) {
3999                         hw_cr4 &= ~X86_CR4_PAE;
4000                 }
4001         }
4002
4003         if (!enable_unrestricted_guest && !is_paging(vcpu))
4004                 /*
4005                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4006                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
4007                  * to be manually disabled when guest switches to non-paging
4008                  * mode.
4009                  *
4010                  * If !enable_unrestricted_guest, the CPU is always running
4011                  * with CR0.PG=1 and CR4 needs to be modified.
4012                  * If enable_unrestricted_guest, the CPU automatically
4013                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4014                  */
4015                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4016
4017         vmcs_writel(CR4_READ_SHADOW, cr4);
4018         vmcs_writel(GUEST_CR4, hw_cr4);
4019         return 0;
4020 }
4021
4022 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4023                             struct kvm_segment *var, int seg)
4024 {
4025         struct vcpu_vmx *vmx = to_vmx(vcpu);
4026         u32 ar;
4027
4028         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4029                 *var = vmx->rmode.segs[seg];
4030                 if (seg == VCPU_SREG_TR
4031                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4032                         return;
4033                 var->base = vmx_read_guest_seg_base(vmx, seg);
4034                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4035                 return;
4036         }
4037         var->base = vmx_read_guest_seg_base(vmx, seg);
4038         var->limit = vmx_read_guest_seg_limit(vmx, seg);
4039         var->selector = vmx_read_guest_seg_selector(vmx, seg);
4040         ar = vmx_read_guest_seg_ar(vmx, seg);
4041         var->unusable = (ar >> 16) & 1;
4042         var->type = ar & 15;
4043         var->s = (ar >> 4) & 1;
4044         var->dpl = (ar >> 5) & 3;
4045         /*
4046          * Some userspaces do not preserve unusable property. Since usable
4047          * segment has to be present according to VMX spec we can use present
4048          * property to amend userspace bug by making unusable segment always
4049          * nonpresent. vmx_segment_access_rights() already marks nonpresent
4050          * segment as unusable.
4051          */
4052         var->present = !var->unusable;
4053         var->avl = (ar >> 12) & 1;
4054         var->l = (ar >> 13) & 1;
4055         var->db = (ar >> 14) & 1;
4056         var->g = (ar >> 15) & 1;
4057 }
4058
4059 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4060 {
4061         struct kvm_segment s;
4062
4063         if (to_vmx(vcpu)->rmode.vm86_active) {
4064                 vmx_get_segment(vcpu, &s, seg);
4065                 return s.base;
4066         }
4067         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4068 }
4069
4070 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4071 {
4072         struct vcpu_vmx *vmx = to_vmx(vcpu);
4073
4074         if (unlikely(vmx->rmode.vm86_active))
4075                 return 0;
4076         else {
4077                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4078                 return VMX_AR_DPL(ar);
4079         }
4080 }
4081
4082 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4083 {
4084         u32 ar;
4085
4086         if (var->unusable || !var->present)
4087                 ar = 1 << 16;
4088         else {
4089                 ar = var->type & 15;
4090                 ar |= (var->s & 1) << 4;
4091                 ar |= (var->dpl & 3) << 5;
4092                 ar |= (var->present & 1) << 7;
4093                 ar |= (var->avl & 1) << 12;
4094                 ar |= (var->l & 1) << 13;
4095                 ar |= (var->db & 1) << 14;
4096                 ar |= (var->g & 1) << 15;
4097         }
4098
4099         return ar;
4100 }
4101
4102 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4103                             struct kvm_segment *var, int seg)
4104 {
4105         struct vcpu_vmx *vmx = to_vmx(vcpu);
4106         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4107
4108         vmx_segment_cache_clear(vmx);
4109
4110         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4111                 vmx->rmode.segs[seg] = *var;
4112                 if (seg == VCPU_SREG_TR)
4113                         vmcs_write16(sf->selector, var->selector);
4114                 else if (var->s)
4115                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4116                 goto out;
4117         }
4118
4119         vmcs_writel(sf->base, var->base);
4120         vmcs_write32(sf->limit, var->limit);
4121         vmcs_write16(sf->selector, var->selector);
4122
4123         /*
4124          *   Fix the "Accessed" bit in AR field of segment registers for older
4125          * qemu binaries.
4126          *   IA32 arch specifies that at the time of processor reset the
4127          * "Accessed" bit in the AR field of segment registers is 1. And qemu
4128          * is setting it to 0 in the userland code. This causes invalid guest
4129          * state vmexit when "unrestricted guest" mode is turned on.
4130          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
4131          * tree. Newer qemu binaries with that qemu fix would not need this
4132          * kvm hack.
4133          */
4134         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4135                 var->type |= 0x1; /* Accessed */
4136
4137         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4138
4139 out:
4140         vmx->emulation_required = emulation_required(vcpu);
4141 }
4142
4143 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4144 {
4145         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4146
4147         *db = (ar >> 14) & 1;
4148         *l = (ar >> 13) & 1;
4149 }
4150
4151 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4152 {
4153         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4154         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4155 }
4156
4157 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4158 {
4159         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4160         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4161 }
4162
4163 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4164 {
4165         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4166         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4167 }
4168
4169 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4170 {
4171         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4172         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4173 }
4174
4175 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4176 {
4177         struct kvm_segment var;
4178         u32 ar;
4179
4180         vmx_get_segment(vcpu, &var, seg);
4181         var.dpl = 0x3;
4182         if (seg == VCPU_SREG_CS)
4183                 var.type = 0x3;
4184         ar = vmx_segment_access_rights(&var);
4185
4186         if (var.base != (var.selector << 4))
4187                 return false;
4188         if (var.limit != 0xffff)
4189                 return false;
4190         if (ar != 0xf3)
4191                 return false;
4192
4193         return true;
4194 }
4195
4196 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4197 {
4198         struct kvm_segment cs;
4199         unsigned int cs_rpl;
4200
4201         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4202         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4203
4204         if (cs.unusable)
4205                 return false;
4206         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4207                 return false;
4208         if (!cs.s)
4209                 return false;
4210         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4211                 if (cs.dpl > cs_rpl)
4212                         return false;
4213         } else {
4214                 if (cs.dpl != cs_rpl)
4215                         return false;
4216         }
4217         if (!cs.present)
4218                 return false;
4219
4220         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4221         return true;
4222 }
4223
4224 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4225 {
4226         struct kvm_segment ss;
4227         unsigned int ss_rpl;
4228
4229         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4230         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4231
4232         if (ss.unusable)
4233                 return true;
4234         if (ss.type != 3 && ss.type != 7)
4235                 return false;
4236         if (!ss.s)
4237                 return false;
4238         if (ss.dpl != ss_rpl) /* DPL != RPL */
4239                 return false;
4240         if (!ss.present)
4241                 return false;
4242
4243         return true;
4244 }
4245
4246 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4247 {
4248         struct kvm_segment var;
4249         unsigned int rpl;
4250
4251         vmx_get_segment(vcpu, &var, seg);
4252         rpl = var.selector & SEGMENT_RPL_MASK;
4253
4254         if (var.unusable)
4255                 return true;
4256         if (!var.s)
4257                 return false;
4258         if (!var.present)
4259                 return false;
4260         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4261                 if (var.dpl < rpl) /* DPL < RPL */
4262                         return false;
4263         }
4264
4265         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4266          * rights flags
4267          */
4268         return true;
4269 }
4270
4271 static bool tr_valid(struct kvm_vcpu *vcpu)
4272 {
4273         struct kvm_segment tr;
4274
4275         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4276
4277         if (tr.unusable)
4278                 return false;
4279         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4280                 return false;
4281         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4282                 return false;
4283         if (!tr.present)
4284                 return false;
4285
4286         return true;
4287 }
4288
4289 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4290 {
4291         struct kvm_segment ldtr;
4292
4293         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4294
4295         if (ldtr.unusable)
4296                 return true;
4297         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4298                 return false;
4299         if (ldtr.type != 2)
4300                 return false;
4301         if (!ldtr.present)
4302                 return false;
4303
4304         return true;
4305 }
4306
4307 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4308 {
4309         struct kvm_segment cs, ss;
4310
4311         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4312         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4313
4314         return ((cs.selector & SEGMENT_RPL_MASK) ==
4315                  (ss.selector & SEGMENT_RPL_MASK));
4316 }
4317
4318 /*
4319  * Check if guest state is valid. Returns true if valid, false if
4320  * not.
4321  * We assume that registers are always usable
4322  */
4323 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4324 {
4325         if (enable_unrestricted_guest)
4326                 return true;
4327
4328         /* real mode guest state checks */
4329         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4330                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4331                         return false;
4332                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4333                         return false;
4334                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4335                         return false;
4336                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4337                         return false;
4338                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4339                         return false;
4340                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4341                         return false;
4342         } else {
4343         /* protected mode guest state checks */
4344                 if (!cs_ss_rpl_check(vcpu))
4345                         return false;
4346                 if (!code_segment_valid(vcpu))
4347                         return false;
4348                 if (!stack_segment_valid(vcpu))
4349                         return false;
4350                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4351                         return false;
4352                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4353                         return false;
4354                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4355                         return false;
4356                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4357                         return false;
4358                 if (!tr_valid(vcpu))
4359                         return false;
4360                 if (!ldtr_valid(vcpu))
4361                         return false;
4362         }
4363         /* TODO:
4364          * - Add checks on RIP
4365          * - Add checks on RFLAGS
4366          */
4367
4368         return true;
4369 }
4370
4371 static int init_rmode_tss(struct kvm *kvm)
4372 {
4373         gfn_t fn;
4374         u16 data = 0;
4375         int idx, r;
4376
4377         idx = srcu_read_lock(&kvm->srcu);
4378         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4379         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4380         if (r < 0)
4381                 goto out;
4382         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4383         r = kvm_write_guest_page(kvm, fn++, &data,
4384                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4385         if (r < 0)
4386                 goto out;
4387         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4388         if (r < 0)
4389                 goto out;
4390         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4391         if (r < 0)
4392                 goto out;
4393         data = ~0;
4394         r = kvm_write_guest_page(kvm, fn, &data,
4395                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4396                                  sizeof(u8));
4397 out:
4398         srcu_read_unlock(&kvm->srcu, idx);
4399         return r;
4400 }
4401
4402 static int init_rmode_identity_map(struct kvm *kvm)
4403 {
4404         int i, idx, r = 0;
4405         kvm_pfn_t identity_map_pfn;
4406         u32 tmp;
4407
4408         if (!enable_ept)
4409                 return 0;
4410
4411         /* Protect kvm->arch.ept_identity_pagetable_done. */
4412         mutex_lock(&kvm->slots_lock);
4413
4414         if (likely(kvm->arch.ept_identity_pagetable_done))
4415                 goto out2;
4416
4417         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4418
4419         r = alloc_identity_pagetable(kvm);
4420         if (r < 0)
4421                 goto out2;
4422
4423         idx = srcu_read_lock(&kvm->srcu);
4424         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4425         if (r < 0)
4426                 goto out;
4427         /* Set up identity-mapping pagetable for EPT in real mode */
4428         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4429                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4430                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4431                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4432                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4433                 if (r < 0)
4434                         goto out;
4435         }
4436         kvm->arch.ept_identity_pagetable_done = true;
4437
4438 out:
4439         srcu_read_unlock(&kvm->srcu, idx);
4440
4441 out2:
4442         mutex_unlock(&kvm->slots_lock);
4443         return r;
4444 }
4445
4446 static void seg_setup(int seg)
4447 {
4448         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4449         unsigned int ar;
4450
4451         vmcs_write16(sf->selector, 0);
4452         vmcs_writel(sf->base, 0);
4453         vmcs_write32(sf->limit, 0xffff);
4454         ar = 0x93;
4455         if (seg == VCPU_SREG_CS)
4456                 ar |= 0x08; /* code segment */
4457
4458         vmcs_write32(sf->ar_bytes, ar);
4459 }
4460
4461 static int alloc_apic_access_page(struct kvm *kvm)
4462 {
4463         struct page *page;
4464         int r = 0;
4465
4466         mutex_lock(&kvm->slots_lock);
4467         if (kvm->arch.apic_access_page_done)
4468                 goto out;
4469         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4470                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4471         if (r)
4472                 goto out;
4473
4474         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4475         if (is_error_page(page)) {
4476                 r = -EFAULT;
4477                 goto out;
4478         }
4479
4480         /*
4481          * Do not pin the page in memory, so that memory hot-unplug
4482          * is able to migrate it.
4483          */
4484         put_page(page);
4485         kvm->arch.apic_access_page_done = true;
4486 out:
4487         mutex_unlock(&kvm->slots_lock);
4488         return r;
4489 }
4490
4491 static int alloc_identity_pagetable(struct kvm *kvm)
4492 {
4493         /* Called with kvm->slots_lock held. */
4494
4495         int r = 0;
4496
4497         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4498
4499         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4500                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4501
4502         return r;
4503 }
4504
4505 static int allocate_vpid(void)
4506 {
4507         int vpid;
4508
4509         if (!enable_vpid)
4510                 return 0;
4511         spin_lock(&vmx_vpid_lock);
4512         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4513         if (vpid < VMX_NR_VPIDS)
4514                 __set_bit(vpid, vmx_vpid_bitmap);
4515         else
4516                 vpid = 0;
4517         spin_unlock(&vmx_vpid_lock);
4518         return vpid;
4519 }
4520
4521 static void free_vpid(int vpid)
4522 {
4523         if (!enable_vpid || vpid == 0)
4524                 return;
4525         spin_lock(&vmx_vpid_lock);
4526         __clear_bit(vpid, vmx_vpid_bitmap);
4527         spin_unlock(&vmx_vpid_lock);
4528 }
4529
4530 #define MSR_TYPE_R      1
4531 #define MSR_TYPE_W      2
4532 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4533                                                 u32 msr, int type)
4534 {
4535         int f = sizeof(unsigned long);
4536
4537         if (!cpu_has_vmx_msr_bitmap())
4538                 return;
4539
4540         /*
4541          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4542          * have the write-low and read-high bitmap offsets the wrong way round.
4543          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4544          */
4545         if (msr <= 0x1fff) {
4546                 if (type & MSR_TYPE_R)
4547                         /* read-low */
4548                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4549
4550                 if (type & MSR_TYPE_W)
4551                         /* write-low */
4552                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4553
4554         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4555                 msr &= 0x1fff;
4556                 if (type & MSR_TYPE_R)
4557                         /* read-high */
4558                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4559
4560                 if (type & MSR_TYPE_W)
4561                         /* write-high */
4562                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4563
4564         }
4565 }
4566
4567 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4568                                                 u32 msr, int type)
4569 {
4570         int f = sizeof(unsigned long);
4571
4572         if (!cpu_has_vmx_msr_bitmap())
4573                 return;
4574
4575         /*
4576          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4577          * have the write-low and read-high bitmap offsets the wrong way round.
4578          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4579          */
4580         if (msr <= 0x1fff) {
4581                 if (type & MSR_TYPE_R)
4582                         /* read-low */
4583                         __set_bit(msr, msr_bitmap + 0x000 / f);
4584
4585                 if (type & MSR_TYPE_W)
4586                         /* write-low */
4587                         __set_bit(msr, msr_bitmap + 0x800 / f);
4588
4589         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4590                 msr &= 0x1fff;
4591                 if (type & MSR_TYPE_R)
4592                         /* read-high */
4593                         __set_bit(msr, msr_bitmap + 0x400 / f);
4594
4595                 if (type & MSR_TYPE_W)
4596                         /* write-high */
4597                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4598
4599         }
4600 }
4601
4602 /*
4603  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4604  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4605  */
4606 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4607                                                unsigned long *msr_bitmap_nested,
4608                                                u32 msr, int type)
4609 {
4610         int f = sizeof(unsigned long);
4611
4612         if (!cpu_has_vmx_msr_bitmap()) {
4613                 WARN_ON(1);
4614                 return;
4615         }
4616
4617         /*
4618          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4619          * have the write-low and read-high bitmap offsets the wrong way round.
4620          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4621          */
4622         if (msr <= 0x1fff) {
4623                 if (type & MSR_TYPE_R &&
4624                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4625                         /* read-low */
4626                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4627
4628                 if (type & MSR_TYPE_W &&
4629                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4630                         /* write-low */
4631                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4632
4633         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4634                 msr &= 0x1fff;
4635                 if (type & MSR_TYPE_R &&
4636                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4637                         /* read-high */
4638                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4639
4640                 if (type & MSR_TYPE_W &&
4641                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4642                         /* write-high */
4643                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4644
4645         }
4646 }
4647
4648 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4649 {
4650         if (!longmode_only)
4651                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4652                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4653         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4654                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4655 }
4656
4657 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4658 {
4659         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4660                         msr, MSR_TYPE_R);
4661         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4662                         msr, MSR_TYPE_R);
4663 }
4664
4665 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4666 {
4667         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4668                         msr, MSR_TYPE_R);
4669         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4670                         msr, MSR_TYPE_R);
4671 }
4672
4673 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4674 {
4675         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4676                         msr, MSR_TYPE_W);
4677         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4678                         msr, MSR_TYPE_W);
4679 }
4680
4681 static bool vmx_get_enable_apicv(void)
4682 {
4683         return enable_apicv;
4684 }
4685
4686 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4687 {
4688         struct vcpu_vmx *vmx = to_vmx(vcpu);
4689         int max_irr;
4690         void *vapic_page;
4691         u16 status;
4692
4693         if (vmx->nested.pi_desc &&
4694             vmx->nested.pi_pending) {
4695                 vmx->nested.pi_pending = false;
4696                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4697                         return 0;
4698
4699                 max_irr = find_last_bit(
4700                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4701
4702                 if (max_irr == 256)
4703                         return 0;
4704
4705                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4706                 if (!vapic_page) {
4707                         WARN_ON(1);
4708                         return -ENOMEM;
4709                 }
4710                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4711                 kunmap(vmx->nested.virtual_apic_page);
4712
4713                 status = vmcs_read16(GUEST_INTR_STATUS);
4714                 if ((u8)max_irr > ((u8)status & 0xff)) {
4715                         status &= ~0xff;
4716                         status |= (u8)max_irr;
4717                         vmcs_write16(GUEST_INTR_STATUS, status);
4718                 }
4719         }
4720         return 0;
4721 }
4722
4723 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4724 {
4725 #ifdef CONFIG_SMP
4726         if (vcpu->mode == IN_GUEST_MODE) {
4727                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4728
4729                 /*
4730                  * Currently, we don't support urgent interrupt,
4731                  * all interrupts are recognized as non-urgent
4732                  * interrupt, so we cannot post interrupts when
4733                  * 'SN' is set.
4734                  *
4735                  * If the vcpu is in guest mode, it means it is
4736                  * running instead of being scheduled out and
4737                  * waiting in the run queue, and that's the only
4738                  * case when 'SN' is set currently, warning if
4739                  * 'SN' is set.
4740                  */
4741                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4742
4743                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4744                                 POSTED_INTR_VECTOR);
4745                 return true;
4746         }
4747 #endif
4748         return false;
4749 }
4750
4751 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4752                                                 int vector)
4753 {
4754         struct vcpu_vmx *vmx = to_vmx(vcpu);
4755
4756         if (is_guest_mode(vcpu) &&
4757             vector == vmx->nested.posted_intr_nv) {
4758                 /* the PIR and ON have been set by L1. */
4759                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4760                 /*
4761                  * If a posted intr is not recognized by hardware,
4762                  * we will accomplish it in the next vmentry.
4763                  */
4764                 vmx->nested.pi_pending = true;
4765                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4766                 return 0;
4767         }
4768         return -1;
4769 }
4770 /*
4771  * Send interrupt to vcpu via posted interrupt way.
4772  * 1. If target vcpu is running(non-root mode), send posted interrupt
4773  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4774  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4775  * interrupt from PIR in next vmentry.
4776  */
4777 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4778 {
4779         struct vcpu_vmx *vmx = to_vmx(vcpu);
4780         int r;
4781
4782         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4783         if (!r)
4784                 return;
4785
4786         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4787                 return;
4788
4789         r = pi_test_and_set_on(&vmx->pi_desc);
4790         kvm_make_request(KVM_REQ_EVENT, vcpu);
4791         if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4792                 kvm_vcpu_kick(vcpu);
4793 }
4794
4795 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4796 {
4797         struct vcpu_vmx *vmx = to_vmx(vcpu);
4798
4799         if (!pi_test_and_clear_on(&vmx->pi_desc))
4800                 return;
4801
4802         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4803 }
4804
4805 /*
4806  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4807  * will not change in the lifetime of the guest.
4808  * Note that host-state that does change is set elsewhere. E.g., host-state
4809  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4810  */
4811 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4812 {
4813         u32 low32, high32;
4814         unsigned long tmpl;
4815         struct desc_ptr dt;
4816         unsigned long cr4;
4817
4818         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4819         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4820
4821         /* Save the most likely value for this task's CR4 in the VMCS. */
4822         cr4 = cr4_read_shadow();
4823         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4824         vmx->host_state.vmcs_host_cr4 = cr4;
4825
4826         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4827 #ifdef CONFIG_X86_64
4828         /*
4829          * Load null selectors, so we can avoid reloading them in
4830          * __vmx_load_host_state(), in case userspace uses the null selectors
4831          * too (the expected case).
4832          */
4833         vmcs_write16(HOST_DS_SELECTOR, 0);
4834         vmcs_write16(HOST_ES_SELECTOR, 0);
4835 #else
4836         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4837         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4838 #endif
4839         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4840         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4841
4842         native_store_idt(&dt);
4843         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4844         vmx->host_idt_base = dt.address;
4845
4846         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4847
4848         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4849         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4850         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4851         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4852
4853         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4854                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4855                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4856         }
4857 }
4858
4859 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4860 {
4861         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4862         if (enable_ept)
4863                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4864         if (is_guest_mode(&vmx->vcpu))
4865                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4866                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4867         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4868 }
4869
4870 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4871 {
4872         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4873
4874         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4875                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4876         /* Enable the preemption timer dynamically */
4877         pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
4878         return pin_based_exec_ctrl;
4879 }
4880
4881 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4882 {
4883         struct vcpu_vmx *vmx = to_vmx(vcpu);
4884
4885         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4886         if (cpu_has_secondary_exec_ctrls()) {
4887                 if (kvm_vcpu_apicv_active(vcpu))
4888                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
4889                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
4890                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4891                 else
4892                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
4893                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
4894                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4895         }
4896
4897         if (cpu_has_vmx_msr_bitmap())
4898                 vmx_set_msr_bitmap(vcpu);
4899 }
4900
4901 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4902 {
4903         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4904
4905         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4906                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4907
4908         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4909                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4910 #ifdef CONFIG_X86_64
4911                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4912                                 CPU_BASED_CR8_LOAD_EXITING;
4913 #endif
4914         }
4915         if (!enable_ept)
4916                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4917                                 CPU_BASED_CR3_LOAD_EXITING  |
4918                                 CPU_BASED_INVLPG_EXITING;
4919         return exec_control;
4920 }
4921
4922 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4923 {
4924         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4925         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
4926                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4927         if (vmx->vpid == 0)
4928                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4929         if (!enable_ept) {
4930                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4931                 enable_unrestricted_guest = 0;
4932                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4933                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4934         }
4935         if (!enable_unrestricted_guest)
4936                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4937         if (!ple_gap)
4938                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4939         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4940                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4941                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4942         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4943         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4944            (handle_vmptrld).
4945            We can NOT enable shadow_vmcs here because we don't have yet
4946            a current VMCS12
4947         */
4948         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4949
4950         if (!enable_pml)
4951                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4952
4953         /* Currently, we allow L1 guest to directly run pcommit instruction. */
4954         exec_control &= ~SECONDARY_EXEC_PCOMMIT;
4955
4956         return exec_control;
4957 }
4958
4959 static void ept_set_mmio_spte_mask(void)
4960 {
4961         /*
4962          * EPT Misconfigurations can be generated if the value of bits 2:0
4963          * of an EPT paging-structure entry is 110b (write/execute).
4964          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4965          * spte.
4966          */
4967         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4968 }
4969
4970 #define VMX_XSS_EXIT_BITMAP 0
4971 /*
4972  * Sets up the vmcs for emulated real mode.
4973  */
4974 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4975 {
4976 #ifdef CONFIG_X86_64
4977         unsigned long a;
4978 #endif
4979         int i;
4980
4981         /* I/O */
4982         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4983         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4984
4985         if (enable_shadow_vmcs) {
4986                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4987                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4988         }
4989         if (cpu_has_vmx_msr_bitmap())
4990                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4991
4992         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4993
4994         /* Control */
4995         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4996         vmx->hv_deadline_tsc = -1;
4997
4998         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4999
5000         if (cpu_has_secondary_exec_ctrls())
5001                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5002                                 vmx_secondary_exec_control(vmx));
5003
5004         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
5005                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5006                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5007                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5008                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5009
5010                 vmcs_write16(GUEST_INTR_STATUS, 0);
5011
5012                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
5013                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
5014         }
5015
5016         if (ple_gap) {
5017                 vmcs_write32(PLE_GAP, ple_gap);
5018                 vmx->ple_window = ple_window;
5019                 vmx->ple_window_dirty = true;
5020         }
5021
5022         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5023         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5024         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
5025
5026         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
5027         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
5028         vmx_set_constant_host_state(vmx);
5029 #ifdef CONFIG_X86_64
5030         rdmsrl(MSR_FS_BASE, a);
5031         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5032         rdmsrl(MSR_GS_BASE, a);
5033         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5034 #else
5035         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5036         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5037 #endif
5038
5039         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5040         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
5041         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
5042         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
5043         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
5044
5045         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5046                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
5047
5048         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
5049                 u32 index = vmx_msr_index[i];
5050                 u32 data_low, data_high;
5051                 int j = vmx->nmsrs;
5052
5053                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5054                         continue;
5055                 if (wrmsr_safe(index, data_low, data_high) < 0)
5056                         continue;
5057                 vmx->guest_msrs[j].index = i;
5058                 vmx->guest_msrs[j].data = 0;
5059                 vmx->guest_msrs[j].mask = -1ull;
5060                 ++vmx->nmsrs;
5061         }
5062
5063
5064         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
5065
5066         /* 22.2.1, 20.8.1 */
5067         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
5068
5069         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
5070         set_cr4_guest_host_mask(vmx);
5071
5072         if (vmx_xsaves_supported())
5073                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5074
5075         return 0;
5076 }
5077
5078 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
5079 {
5080         struct vcpu_vmx *vmx = to_vmx(vcpu);
5081         struct msr_data apic_base_msr;
5082         u64 cr0;
5083
5084         vmx->rmode.vm86_active = 0;
5085
5086         vmx->soft_vnmi_blocked = 0;
5087
5088         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
5089         kvm_set_cr8(vcpu, 0);
5090
5091         if (!init_event) {
5092                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5093                                      MSR_IA32_APICBASE_ENABLE;
5094                 if (kvm_vcpu_is_reset_bsp(vcpu))
5095                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5096                 apic_base_msr.host_initiated = true;
5097                 kvm_set_apic_base(vcpu, &apic_base_msr);
5098         }
5099
5100         vmx_segment_cache_clear(vmx);
5101
5102         seg_setup(VCPU_SREG_CS);
5103         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5104         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5105
5106         seg_setup(VCPU_SREG_DS);
5107         seg_setup(VCPU_SREG_ES);
5108         seg_setup(VCPU_SREG_FS);
5109         seg_setup(VCPU_SREG_GS);
5110         seg_setup(VCPU_SREG_SS);
5111
5112         vmcs_write16(GUEST_TR_SELECTOR, 0);
5113         vmcs_writel(GUEST_TR_BASE, 0);
5114         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5115         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5116
5117         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5118         vmcs_writel(GUEST_LDTR_BASE, 0);
5119         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5120         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5121
5122         if (!init_event) {
5123                 vmcs_write32(GUEST_SYSENTER_CS, 0);
5124                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5125                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5126                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5127         }
5128
5129         vmcs_writel(GUEST_RFLAGS, 0x02);
5130         kvm_rip_write(vcpu, 0xfff0);
5131
5132         vmcs_writel(GUEST_GDTR_BASE, 0);
5133         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5134
5135         vmcs_writel(GUEST_IDTR_BASE, 0);
5136         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5137
5138         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5139         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5140         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5141
5142         setup_msrs(vmx);
5143
5144         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
5145
5146         if (cpu_has_vmx_tpr_shadow() && !init_event) {
5147                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5148                 if (cpu_need_tpr_shadow(vcpu))
5149                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5150                                      __pa(vcpu->arch.apic->regs));
5151                 vmcs_write32(TPR_THRESHOLD, 0);
5152         }
5153
5154         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5155
5156         if (kvm_vcpu_apicv_active(vcpu))
5157                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5158
5159         if (vmx->vpid != 0)
5160                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5161
5162         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5163         vmx->vcpu.arch.cr0 = cr0;
5164         vmx_set_cr0(vcpu, cr0); /* enter rmode */
5165         vmx_set_cr4(vcpu, 0);
5166         vmx_set_efer(vcpu, 0);
5167         vmx_fpu_activate(vcpu);
5168         update_exception_bitmap(vcpu);
5169
5170         vpid_sync_context(vmx->vpid);
5171 }
5172
5173 /*
5174  * In nested virtualization, check if L1 asked to exit on external interrupts.
5175  * For most existing hypervisors, this will always return true.
5176  */
5177 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5178 {
5179         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5180                 PIN_BASED_EXT_INTR_MASK;
5181 }
5182
5183 /*
5184  * In nested virtualization, check if L1 has set
5185  * VM_EXIT_ACK_INTR_ON_EXIT
5186  */
5187 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5188 {
5189         return get_vmcs12(vcpu)->vm_exit_controls &
5190                 VM_EXIT_ACK_INTR_ON_EXIT;
5191 }
5192
5193 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5194 {
5195         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5196                 PIN_BASED_NMI_EXITING;
5197 }
5198
5199 static void enable_irq_window(struct kvm_vcpu *vcpu)
5200 {
5201         u32 cpu_based_vm_exec_control;
5202
5203         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5204         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
5205         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5206 }
5207
5208 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5209 {
5210         u32 cpu_based_vm_exec_control;
5211
5212         if (!cpu_has_virtual_nmis() ||
5213             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5214                 enable_irq_window(vcpu);
5215                 return;
5216         }
5217
5218         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5219         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
5220         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5221 }
5222
5223 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5224 {
5225         struct vcpu_vmx *vmx = to_vmx(vcpu);
5226         uint32_t intr;
5227         int irq = vcpu->arch.interrupt.nr;
5228
5229         trace_kvm_inj_virq(irq);
5230
5231         ++vcpu->stat.irq_injections;
5232         if (vmx->rmode.vm86_active) {
5233                 int inc_eip = 0;
5234                 if (vcpu->arch.interrupt.soft)
5235                         inc_eip = vcpu->arch.event_exit_inst_len;
5236                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5237                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5238                 return;
5239         }
5240         intr = irq | INTR_INFO_VALID_MASK;
5241         if (vcpu->arch.interrupt.soft) {
5242                 intr |= INTR_TYPE_SOFT_INTR;
5243                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5244                              vmx->vcpu.arch.event_exit_inst_len);
5245         } else
5246                 intr |= INTR_TYPE_EXT_INTR;
5247         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5248 }
5249
5250 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5251 {
5252         struct vcpu_vmx *vmx = to_vmx(vcpu);
5253
5254         if (is_guest_mode(vcpu))
5255                 return;
5256
5257         if (!cpu_has_virtual_nmis()) {
5258                 /*
5259                  * Tracking the NMI-blocked state in software is built upon
5260                  * finding the next open IRQ window. This, in turn, depends on
5261                  * well-behaving guests: They have to keep IRQs disabled at
5262                  * least as long as the NMI handler runs. Otherwise we may
5263                  * cause NMI nesting, maybe breaking the guest. But as this is
5264                  * highly unlikely, we can live with the residual risk.
5265                  */
5266                 vmx->soft_vnmi_blocked = 1;
5267                 vmx->vnmi_blocked_time = 0;
5268         }
5269
5270         ++vcpu->stat.nmi_injections;
5271         vmx->nmi_known_unmasked = false;
5272         if (vmx->rmode.vm86_active) {
5273                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5274                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5275                 return;
5276         }
5277         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5278                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5279 }
5280
5281 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5282 {
5283         if (!cpu_has_virtual_nmis())
5284                 return to_vmx(vcpu)->soft_vnmi_blocked;
5285         if (to_vmx(vcpu)->nmi_known_unmasked)
5286                 return false;
5287         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5288 }
5289
5290 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5291 {
5292         struct vcpu_vmx *vmx = to_vmx(vcpu);
5293
5294         if (!cpu_has_virtual_nmis()) {
5295                 if (vmx->soft_vnmi_blocked != masked) {
5296                         vmx->soft_vnmi_blocked = masked;
5297                         vmx->vnmi_blocked_time = 0;
5298                 }
5299         } else {
5300                 vmx->nmi_known_unmasked = !masked;
5301                 if (masked)
5302                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5303                                       GUEST_INTR_STATE_NMI);
5304                 else
5305                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5306                                         GUEST_INTR_STATE_NMI);
5307         }
5308 }
5309
5310 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5311 {
5312         if (to_vmx(vcpu)->nested.nested_run_pending)
5313                 return 0;
5314
5315         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5316                 return 0;
5317
5318         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5319                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5320                    | GUEST_INTR_STATE_NMI));
5321 }
5322
5323 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5324 {
5325         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5326                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5327                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5328                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5329 }
5330
5331 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5332 {
5333         int ret;
5334
5335         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5336                                     PAGE_SIZE * 3);
5337         if (ret)
5338                 return ret;
5339         kvm->arch.tss_addr = addr;
5340         return init_rmode_tss(kvm);
5341 }
5342
5343 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5344 {
5345         switch (vec) {
5346         case BP_VECTOR:
5347                 /*
5348                  * Update instruction length as we may reinject the exception
5349                  * from user space while in guest debugging mode.
5350                  */
5351                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5352                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5353                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5354                         return false;
5355                 /* fall through */
5356         case DB_VECTOR:
5357                 if (vcpu->guest_debug &
5358                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5359                         return false;
5360                 /* fall through */
5361         case DE_VECTOR:
5362         case OF_VECTOR:
5363         case BR_VECTOR:
5364         case UD_VECTOR:
5365         case DF_VECTOR:
5366         case SS_VECTOR:
5367         case GP_VECTOR:
5368         case MF_VECTOR:
5369                 return true;
5370         break;
5371         }
5372         return false;
5373 }
5374
5375 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5376                                   int vec, u32 err_code)
5377 {
5378         /*
5379          * Instruction with address size override prefix opcode 0x67
5380          * Cause the #SS fault with 0 error code in VM86 mode.
5381          */
5382         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5383                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5384                         if (vcpu->arch.halt_request) {
5385                                 vcpu->arch.halt_request = 0;
5386                                 return kvm_vcpu_halt(vcpu);
5387                         }
5388                         return 1;
5389                 }
5390                 return 0;
5391         }
5392
5393         /*
5394          * Forward all other exceptions that are valid in real mode.
5395          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5396          *        the required debugging infrastructure rework.
5397          */
5398         kvm_queue_exception(vcpu, vec);
5399         return 1;
5400 }
5401
5402 /*
5403  * Trigger machine check on the host. We assume all the MSRs are already set up
5404  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5405  * We pass a fake environment to the machine check handler because we want
5406  * the guest to be always treated like user space, no matter what context
5407  * it used internally.
5408  */
5409 static void kvm_machine_check(void)
5410 {
5411 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5412         struct pt_regs regs = {
5413                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5414                 .flags = X86_EFLAGS_IF,
5415         };
5416
5417         do_machine_check(&regs, 0);
5418 #endif
5419 }
5420
5421 static int handle_machine_check(struct kvm_vcpu *vcpu)
5422 {
5423         /* already handled by vcpu_run */
5424         return 1;
5425 }
5426
5427 static int handle_exception(struct kvm_vcpu *vcpu)
5428 {
5429         struct vcpu_vmx *vmx = to_vmx(vcpu);
5430         struct kvm_run *kvm_run = vcpu->run;
5431         u32 intr_info, ex_no, error_code;
5432         unsigned long cr2, rip, dr6;
5433         u32 vect_info;
5434         enum emulation_result er;
5435
5436         vect_info = vmx->idt_vectoring_info;
5437         intr_info = vmx->exit_intr_info;
5438
5439         if (is_machine_check(intr_info))
5440                 return handle_machine_check(vcpu);
5441
5442         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5443                 return 1;  /* already handled by vmx_vcpu_run() */
5444
5445         if (is_no_device(intr_info)) {
5446                 vmx_fpu_activate(vcpu);
5447                 return 1;
5448         }
5449
5450         if (is_invalid_opcode(intr_info)) {
5451                 if (is_guest_mode(vcpu)) {
5452                         kvm_queue_exception(vcpu, UD_VECTOR);
5453                         return 1;
5454                 }
5455                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5456                 if (er != EMULATE_DONE)
5457                         kvm_queue_exception(vcpu, UD_VECTOR);
5458                 return 1;
5459         }
5460
5461         error_code = 0;
5462         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5463                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5464
5465         /*
5466          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5467          * MMIO, it is better to report an internal error.
5468          * See the comments in vmx_handle_exit.
5469          */
5470         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5471             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5472                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5473                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5474                 vcpu->run->internal.ndata = 3;
5475                 vcpu->run->internal.data[0] = vect_info;
5476                 vcpu->run->internal.data[1] = intr_info;
5477                 vcpu->run->internal.data[2] = error_code;
5478                 return 0;
5479         }
5480
5481         if (is_page_fault(intr_info)) {
5482                 /* EPT won't cause page fault directly */
5483                 BUG_ON(enable_ept);
5484                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5485                 trace_kvm_page_fault(cr2, error_code);
5486
5487                 if (kvm_event_needs_reinjection(vcpu))
5488                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5489                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5490         }
5491
5492         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5493
5494         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5495                 return handle_rmode_exception(vcpu, ex_no, error_code);
5496
5497         switch (ex_no) {
5498         case AC_VECTOR:
5499                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5500                 return 1;
5501         case DB_VECTOR:
5502                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5503                 if (!(vcpu->guest_debug &
5504                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5505                         vcpu->arch.dr6 &= ~15;
5506                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5507                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5508                                 skip_emulated_instruction(vcpu);
5509
5510                         kvm_queue_exception(vcpu, DB_VECTOR);
5511                         return 1;
5512                 }
5513                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5514                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5515                 /* fall through */
5516         case BP_VECTOR:
5517                 /*
5518                  * Update instruction length as we may reinject #BP from
5519                  * user space while in guest debugging mode. Reading it for
5520                  * #DB as well causes no harm, it is not used in that case.
5521                  */
5522                 vmx->vcpu.arch.event_exit_inst_len =
5523                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5524                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5525                 rip = kvm_rip_read(vcpu);
5526                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5527                 kvm_run->debug.arch.exception = ex_no;
5528                 break;
5529         default:
5530                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5531                 kvm_run->ex.exception = ex_no;
5532                 kvm_run->ex.error_code = error_code;
5533                 break;
5534         }
5535         return 0;
5536 }
5537
5538 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5539 {
5540         ++vcpu->stat.irq_exits;
5541         return 1;
5542 }
5543
5544 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5545 {
5546         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5547         return 0;
5548 }
5549
5550 static int handle_io(struct kvm_vcpu *vcpu)
5551 {
5552         unsigned long exit_qualification;
5553         int size, in, string;
5554         unsigned port;
5555
5556         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5557         string = (exit_qualification & 16) != 0;
5558         in = (exit_qualification & 8) != 0;
5559
5560         ++vcpu->stat.io_exits;
5561
5562         if (string || in)
5563                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5564
5565         port = exit_qualification >> 16;
5566         size = (exit_qualification & 7) + 1;
5567         skip_emulated_instruction(vcpu);
5568
5569         return kvm_fast_pio_out(vcpu, size, port);
5570 }
5571
5572 static void
5573 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5574 {
5575         /*
5576          * Patch in the VMCALL instruction:
5577          */
5578         hypercall[0] = 0x0f;
5579         hypercall[1] = 0x01;
5580         hypercall[2] = 0xc1;
5581 }
5582
5583 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5584 {
5585         unsigned long always_on = VMXON_CR0_ALWAYSON;
5586         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5587
5588         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5589                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5590             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5591                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5592         return (val & always_on) == always_on;
5593 }
5594
5595 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5596 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5597 {
5598         if (is_guest_mode(vcpu)) {
5599                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5600                 unsigned long orig_val = val;
5601
5602                 /*
5603                  * We get here when L2 changed cr0 in a way that did not change
5604                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5605                  * but did change L0 shadowed bits. So we first calculate the
5606                  * effective cr0 value that L1 would like to write into the
5607                  * hardware. It consists of the L2-owned bits from the new
5608                  * value combined with the L1-owned bits from L1's guest_cr0.
5609                  */
5610                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5611                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5612
5613                 if (!nested_cr0_valid(vcpu, val))
5614                         return 1;
5615
5616                 if (kvm_set_cr0(vcpu, val))
5617                         return 1;
5618                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5619                 return 0;
5620         } else {
5621                 if (to_vmx(vcpu)->nested.vmxon &&
5622                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5623                         return 1;
5624                 return kvm_set_cr0(vcpu, val);
5625         }
5626 }
5627
5628 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5629 {
5630         if (is_guest_mode(vcpu)) {
5631                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5632                 unsigned long orig_val = val;
5633
5634                 /* analogously to handle_set_cr0 */
5635                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5636                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5637                 if (kvm_set_cr4(vcpu, val))
5638                         return 1;
5639                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5640                 return 0;
5641         } else
5642                 return kvm_set_cr4(vcpu, val);
5643 }
5644
5645 /* called to set cr0 as appropriate for clts instruction exit. */
5646 static void handle_clts(struct kvm_vcpu *vcpu)
5647 {
5648         if (is_guest_mode(vcpu)) {
5649                 /*
5650                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5651                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5652                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5653                  */
5654                 vmcs_writel(CR0_READ_SHADOW,
5655                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5656                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5657         } else
5658                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5659 }
5660
5661 static int handle_cr(struct kvm_vcpu *vcpu)
5662 {
5663         unsigned long exit_qualification, val;
5664         int cr;
5665         int reg;
5666         int err;
5667
5668         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5669         cr = exit_qualification & 15;
5670         reg = (exit_qualification >> 8) & 15;
5671         switch ((exit_qualification >> 4) & 3) {
5672         case 0: /* mov to cr */
5673                 val = kvm_register_readl(vcpu, reg);
5674                 trace_kvm_cr_write(cr, val);
5675                 switch (cr) {
5676                 case 0:
5677                         err = handle_set_cr0(vcpu, val);
5678                         kvm_complete_insn_gp(vcpu, err);
5679                         return 1;
5680                 case 3:
5681                         err = kvm_set_cr3(vcpu, val);
5682                         kvm_complete_insn_gp(vcpu, err);
5683                         return 1;
5684                 case 4:
5685                         err = handle_set_cr4(vcpu, val);
5686                         kvm_complete_insn_gp(vcpu, err);
5687                         return 1;
5688                 case 8: {
5689                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5690                                 u8 cr8 = (u8)val;
5691                                 err = kvm_set_cr8(vcpu, cr8);
5692                                 kvm_complete_insn_gp(vcpu, err);
5693                                 if (lapic_in_kernel(vcpu))
5694                                         return 1;
5695                                 if (cr8_prev <= cr8)
5696                                         return 1;
5697                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5698                                 return 0;
5699                         }
5700                 }
5701                 break;
5702         case 2: /* clts */
5703                 handle_clts(vcpu);
5704                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5705                 skip_emulated_instruction(vcpu);
5706                 vmx_fpu_activate(vcpu);
5707                 return 1;
5708         case 1: /*mov from cr*/
5709                 switch (cr) {
5710                 case 3:
5711                         val = kvm_read_cr3(vcpu);
5712                         kvm_register_write(vcpu, reg, val);
5713                         trace_kvm_cr_read(cr, val);
5714                         skip_emulated_instruction(vcpu);
5715                         return 1;
5716                 case 8:
5717                         val = kvm_get_cr8(vcpu);
5718                         kvm_register_write(vcpu, reg, val);
5719                         trace_kvm_cr_read(cr, val);
5720                         skip_emulated_instruction(vcpu);
5721                         return 1;
5722                 }
5723                 break;
5724         case 3: /* lmsw */
5725                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5726                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5727                 kvm_lmsw(vcpu, val);
5728
5729                 skip_emulated_instruction(vcpu);
5730                 return 1;
5731         default:
5732                 break;
5733         }
5734         vcpu->run->exit_reason = 0;
5735         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5736                (int)(exit_qualification >> 4) & 3, cr);
5737         return 0;
5738 }
5739
5740 static int handle_dr(struct kvm_vcpu *vcpu)
5741 {
5742         unsigned long exit_qualification;
5743         int dr, dr7, reg;
5744
5745         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5746         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5747
5748         /* First, if DR does not exist, trigger UD */
5749         if (!kvm_require_dr(vcpu, dr))
5750                 return 1;
5751
5752         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5753         if (!kvm_require_cpl(vcpu, 0))
5754                 return 1;
5755         dr7 = vmcs_readl(GUEST_DR7);
5756         if (dr7 & DR7_GD) {
5757                 /*
5758                  * As the vm-exit takes precedence over the debug trap, we
5759                  * need to emulate the latter, either for the host or the
5760                  * guest debugging itself.
5761                  */
5762                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5763                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5764                         vcpu->run->debug.arch.dr7 = dr7;
5765                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5766                         vcpu->run->debug.arch.exception = DB_VECTOR;
5767                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5768                         return 0;
5769                 } else {
5770                         vcpu->arch.dr6 &= ~15;
5771                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5772                         kvm_queue_exception(vcpu, DB_VECTOR);
5773                         return 1;
5774                 }
5775         }
5776
5777         if (vcpu->guest_debug == 0) {
5778                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5779                                 CPU_BASED_MOV_DR_EXITING);
5780
5781                 /*
5782                  * No more DR vmexits; force a reload of the debug registers
5783                  * and reenter on this instruction.  The next vmexit will
5784                  * retrieve the full state of the debug registers.
5785                  */
5786                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5787                 return 1;
5788         }
5789
5790         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5791         if (exit_qualification & TYPE_MOV_FROM_DR) {
5792                 unsigned long val;
5793
5794                 if (kvm_get_dr(vcpu, dr, &val))
5795                         return 1;
5796                 kvm_register_write(vcpu, reg, val);
5797         } else
5798                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5799                         return 1;
5800
5801         skip_emulated_instruction(vcpu);
5802         return 1;
5803 }
5804
5805 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5806 {
5807         return vcpu->arch.dr6;
5808 }
5809
5810 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5811 {
5812 }
5813
5814 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5815 {
5816         get_debugreg(vcpu->arch.db[0], 0);
5817         get_debugreg(vcpu->arch.db[1], 1);
5818         get_debugreg(vcpu->arch.db[2], 2);
5819         get_debugreg(vcpu->arch.db[3], 3);
5820         get_debugreg(vcpu->arch.dr6, 6);
5821         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5822
5823         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5824         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
5825 }
5826
5827 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5828 {
5829         vmcs_writel(GUEST_DR7, val);
5830 }
5831
5832 static int handle_cpuid(struct kvm_vcpu *vcpu)
5833 {
5834         kvm_emulate_cpuid(vcpu);
5835         return 1;
5836 }
5837
5838 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5839 {
5840         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5841         struct msr_data msr_info;
5842
5843         msr_info.index = ecx;
5844         msr_info.host_initiated = false;
5845         if (vmx_get_msr(vcpu, &msr_info)) {
5846                 trace_kvm_msr_read_ex(ecx);
5847                 kvm_inject_gp(vcpu, 0);
5848                 return 1;
5849         }
5850
5851         trace_kvm_msr_read(ecx, msr_info.data);
5852
5853         /* FIXME: handling of bits 32:63 of rax, rdx */
5854         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5855         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
5856         skip_emulated_instruction(vcpu);
5857         return 1;
5858 }
5859
5860 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5861 {
5862         struct msr_data msr;
5863         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5864         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5865                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5866
5867         msr.data = data;
5868         msr.index = ecx;
5869         msr.host_initiated = false;
5870         if (kvm_set_msr(vcpu, &msr) != 0) {
5871                 trace_kvm_msr_write_ex(ecx, data);
5872                 kvm_inject_gp(vcpu, 0);
5873                 return 1;
5874         }
5875
5876         trace_kvm_msr_write(ecx, data);
5877         skip_emulated_instruction(vcpu);
5878         return 1;
5879 }
5880
5881 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5882 {
5883         kvm_make_request(KVM_REQ_EVENT, vcpu);
5884         return 1;
5885 }
5886
5887 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5888 {
5889         u32 cpu_based_vm_exec_control;
5890
5891         /* clear pending irq */
5892         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5893         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5894         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5895
5896         kvm_make_request(KVM_REQ_EVENT, vcpu);
5897
5898         ++vcpu->stat.irq_window_exits;
5899         return 1;
5900 }
5901
5902 static int handle_halt(struct kvm_vcpu *vcpu)
5903 {
5904         return kvm_emulate_halt(vcpu);
5905 }
5906
5907 static int handle_vmcall(struct kvm_vcpu *vcpu)
5908 {
5909         return kvm_emulate_hypercall(vcpu);
5910 }
5911
5912 static int handle_invd(struct kvm_vcpu *vcpu)
5913 {
5914         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5915 }
5916
5917 static int handle_invlpg(struct kvm_vcpu *vcpu)
5918 {
5919         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5920
5921         kvm_mmu_invlpg(vcpu, exit_qualification);
5922         skip_emulated_instruction(vcpu);
5923         return 1;
5924 }
5925
5926 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5927 {
5928         int err;
5929
5930         err = kvm_rdpmc(vcpu);
5931         kvm_complete_insn_gp(vcpu, err);
5932
5933         return 1;
5934 }
5935
5936 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5937 {
5938         kvm_emulate_wbinvd(vcpu);
5939         return 1;
5940 }
5941
5942 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5943 {
5944         u64 new_bv = kvm_read_edx_eax(vcpu);
5945         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5946
5947         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5948                 skip_emulated_instruction(vcpu);
5949         return 1;
5950 }
5951
5952 static int handle_xsaves(struct kvm_vcpu *vcpu)
5953 {
5954         skip_emulated_instruction(vcpu);
5955         WARN(1, "this should never happen\n");
5956         return 1;
5957 }
5958
5959 static int handle_xrstors(struct kvm_vcpu *vcpu)
5960 {
5961         skip_emulated_instruction(vcpu);
5962         WARN(1, "this should never happen\n");
5963         return 1;
5964 }
5965
5966 static int handle_apic_access(struct kvm_vcpu *vcpu)
5967 {
5968         if (likely(fasteoi)) {
5969                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5970                 int access_type, offset;
5971
5972                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5973                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5974                 /*
5975                  * Sane guest uses MOV to write EOI, with written value
5976                  * not cared. So make a short-circuit here by avoiding
5977                  * heavy instruction emulation.
5978                  */
5979                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5980                     (offset == APIC_EOI)) {
5981                         kvm_lapic_set_eoi(vcpu);
5982                         skip_emulated_instruction(vcpu);
5983                         return 1;
5984                 }
5985         }
5986         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5987 }
5988
5989 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5990 {
5991         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5992         int vector = exit_qualification & 0xff;
5993
5994         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5995         kvm_apic_set_eoi_accelerated(vcpu, vector);
5996         return 1;
5997 }
5998
5999 static int handle_apic_write(struct kvm_vcpu *vcpu)
6000 {
6001         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6002         u32 offset = exit_qualification & 0xfff;
6003
6004         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6005         kvm_apic_write_nodecode(vcpu, offset);
6006         return 1;
6007 }
6008
6009 static int handle_task_switch(struct kvm_vcpu *vcpu)
6010 {
6011         struct vcpu_vmx *vmx = to_vmx(vcpu);
6012         unsigned long exit_qualification;
6013         bool has_error_code = false;
6014         u32 error_code = 0;
6015         u16 tss_selector;
6016         int reason, type, idt_v, idt_index;
6017
6018         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6019         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6020         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6021
6022         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6023
6024         reason = (u32)exit_qualification >> 30;
6025         if (reason == TASK_SWITCH_GATE && idt_v) {
6026                 switch (type) {
6027                 case INTR_TYPE_NMI_INTR:
6028                         vcpu->arch.nmi_injected = false;
6029                         vmx_set_nmi_mask(vcpu, true);
6030                         break;
6031                 case INTR_TYPE_EXT_INTR:
6032                 case INTR_TYPE_SOFT_INTR:
6033                         kvm_clear_interrupt_queue(vcpu);
6034                         break;
6035                 case INTR_TYPE_HARD_EXCEPTION:
6036                         if (vmx->idt_vectoring_info &
6037                             VECTORING_INFO_DELIVER_CODE_MASK) {
6038                                 has_error_code = true;
6039                                 error_code =
6040                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
6041                         }
6042                         /* fall through */
6043                 case INTR_TYPE_SOFT_EXCEPTION:
6044                         kvm_clear_exception_queue(vcpu);
6045                         break;
6046                 default:
6047                         break;
6048                 }
6049         }
6050         tss_selector = exit_qualification;
6051
6052         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6053                        type != INTR_TYPE_EXT_INTR &&
6054                        type != INTR_TYPE_NMI_INTR))
6055                 skip_emulated_instruction(vcpu);
6056
6057         if (kvm_task_switch(vcpu, tss_selector,
6058                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6059                             has_error_code, error_code) == EMULATE_FAIL) {
6060                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6061                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6062                 vcpu->run->internal.ndata = 0;
6063                 return 0;
6064         }
6065
6066         /*
6067          * TODO: What about debug traps on tss switch?
6068          *       Are we supposed to inject them and update dr6?
6069          */
6070
6071         return 1;
6072 }
6073
6074 static int handle_ept_violation(struct kvm_vcpu *vcpu)
6075 {
6076         unsigned long exit_qualification;
6077         gpa_t gpa;
6078         u32 error_code;
6079         int gla_validity;
6080
6081         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6082
6083         gla_validity = (exit_qualification >> 7) & 0x3;
6084         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
6085                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
6086                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
6087                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
6088                         vmcs_readl(GUEST_LINEAR_ADDRESS));
6089                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
6090                         (long unsigned int)exit_qualification);
6091                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6092                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
6093                 return 0;
6094         }
6095
6096         /*
6097          * EPT violation happened while executing iret from NMI,
6098          * "blocked by NMI" bit has to be set before next VM entry.
6099          * There are errata that may cause this bit to not be set:
6100          * AAK134, BY25.
6101          */
6102         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6103                         cpu_has_virtual_nmis() &&
6104                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6105                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6106
6107         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6108         trace_kvm_page_fault(gpa, exit_qualification);
6109
6110         /* It is a write fault? */
6111         error_code = exit_qualification & PFERR_WRITE_MASK;
6112         /* It is a fetch fault? */
6113         error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
6114         /* ept page table is present? */
6115         error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
6116
6117         vcpu->arch.exit_qualification = exit_qualification;
6118
6119         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6120 }
6121
6122 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6123 {
6124         int ret;
6125         gpa_t gpa;
6126
6127         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6128         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6129                 skip_emulated_instruction(vcpu);
6130                 trace_kvm_fast_mmio(gpa);
6131                 return 1;
6132         }
6133
6134         ret = handle_mmio_page_fault(vcpu, gpa, true);
6135         if (likely(ret == RET_MMIO_PF_EMULATE))
6136                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6137                                               EMULATE_DONE;
6138
6139         if (unlikely(ret == RET_MMIO_PF_INVALID))
6140                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6141
6142         if (unlikely(ret == RET_MMIO_PF_RETRY))
6143                 return 1;
6144
6145         /* It is the real ept misconfig */
6146         WARN_ON(1);
6147
6148         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6149         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6150
6151         return 0;
6152 }
6153
6154 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6155 {
6156         u32 cpu_based_vm_exec_control;
6157
6158         /* clear pending NMI */
6159         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6160         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6161         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6162         ++vcpu->stat.nmi_window_exits;
6163         kvm_make_request(KVM_REQ_EVENT, vcpu);
6164
6165         return 1;
6166 }
6167
6168 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6169 {
6170         struct vcpu_vmx *vmx = to_vmx(vcpu);
6171         enum emulation_result err = EMULATE_DONE;
6172         int ret = 1;
6173         u32 cpu_exec_ctrl;
6174         bool intr_window_requested;
6175         unsigned count = 130;
6176
6177         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6178         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6179
6180         while (vmx->emulation_required && count-- != 0) {
6181                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6182                         return handle_interrupt_window(&vmx->vcpu);
6183
6184                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
6185                         return 1;
6186
6187                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6188
6189                 if (err == EMULATE_USER_EXIT) {
6190                         ++vcpu->stat.mmio_exits;
6191                         ret = 0;
6192                         goto out;
6193                 }
6194
6195                 if (err != EMULATE_DONE) {
6196                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6197                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6198                         vcpu->run->internal.ndata = 0;
6199                         return 0;
6200                 }
6201
6202                 if (vcpu->arch.halt_request) {
6203                         vcpu->arch.halt_request = 0;
6204                         ret = kvm_vcpu_halt(vcpu);
6205                         goto out;
6206                 }
6207
6208                 if (signal_pending(current))
6209                         goto out;
6210                 if (need_resched())
6211                         schedule();
6212         }
6213
6214 out:
6215         return ret;
6216 }
6217
6218 static int __grow_ple_window(int val)
6219 {
6220         if (ple_window_grow < 1)
6221                 return ple_window;
6222
6223         val = min(val, ple_window_actual_max);
6224
6225         if (ple_window_grow < ple_window)
6226                 val *= ple_window_grow;
6227         else
6228                 val += ple_window_grow;
6229
6230         return val;
6231 }
6232
6233 static int __shrink_ple_window(int val, int modifier, int minimum)
6234 {
6235         if (modifier < 1)
6236                 return ple_window;
6237
6238         if (modifier < ple_window)
6239                 val /= modifier;
6240         else
6241                 val -= modifier;
6242
6243         return max(val, minimum);
6244 }
6245
6246 static void grow_ple_window(struct kvm_vcpu *vcpu)
6247 {
6248         struct vcpu_vmx *vmx = to_vmx(vcpu);
6249         int old = vmx->ple_window;
6250
6251         vmx->ple_window = __grow_ple_window(old);
6252
6253         if (vmx->ple_window != old)
6254                 vmx->ple_window_dirty = true;
6255
6256         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6257 }
6258
6259 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6260 {
6261         struct vcpu_vmx *vmx = to_vmx(vcpu);
6262         int old = vmx->ple_window;
6263
6264         vmx->ple_window = __shrink_ple_window(old,
6265                                               ple_window_shrink, ple_window);
6266
6267         if (vmx->ple_window != old)
6268                 vmx->ple_window_dirty = true;
6269
6270         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6271 }
6272
6273 /*
6274  * ple_window_actual_max is computed to be one grow_ple_window() below
6275  * ple_window_max. (See __grow_ple_window for the reason.)
6276  * This prevents overflows, because ple_window_max is int.
6277  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6278  * this process.
6279  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6280  */
6281 static void update_ple_window_actual_max(void)
6282 {
6283         ple_window_actual_max =
6284                         __shrink_ple_window(max(ple_window_max, ple_window),
6285                                             ple_window_grow, INT_MIN);
6286 }
6287
6288 /*
6289  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6290  */
6291 static void wakeup_handler(void)
6292 {
6293         struct kvm_vcpu *vcpu;
6294         int cpu = smp_processor_id();
6295
6296         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6297         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6298                         blocked_vcpu_list) {
6299                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6300
6301                 if (pi_test_on(pi_desc) == 1)
6302                         kvm_vcpu_kick(vcpu);
6303         }
6304         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6305 }
6306
6307 static __init int hardware_setup(void)
6308 {
6309         int r = -ENOMEM, i, msr;
6310
6311         rdmsrl_safe(MSR_EFER, &host_efer);
6312
6313         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6314                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6315
6316         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6317         if (!vmx_io_bitmap_a)
6318                 return r;
6319
6320         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6321         if (!vmx_io_bitmap_b)
6322                 goto out;
6323
6324         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6325         if (!vmx_msr_bitmap_legacy)
6326                 goto out1;
6327
6328         vmx_msr_bitmap_legacy_x2apic =
6329                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6330         if (!vmx_msr_bitmap_legacy_x2apic)
6331                 goto out2;
6332
6333         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6334         if (!vmx_msr_bitmap_longmode)
6335                 goto out3;
6336
6337         vmx_msr_bitmap_longmode_x2apic =
6338                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6339         if (!vmx_msr_bitmap_longmode_x2apic)
6340                 goto out4;
6341
6342         if (nested) {
6343                 vmx_msr_bitmap_nested =
6344                         (unsigned long *)__get_free_page(GFP_KERNEL);
6345                 if (!vmx_msr_bitmap_nested)
6346                         goto out5;
6347         }
6348
6349         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6350         if (!vmx_vmread_bitmap)
6351                 goto out6;
6352
6353         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6354         if (!vmx_vmwrite_bitmap)
6355                 goto out7;
6356
6357         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6358         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6359
6360         /*
6361          * Allow direct access to the PC debug port (it is often used for I/O
6362          * delays, but the vmexits simply slow things down).
6363          */
6364         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6365         clear_bit(0x80, vmx_io_bitmap_a);
6366
6367         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6368
6369         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6370         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6371         if (nested)
6372                 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
6373
6374         if (setup_vmcs_config(&vmcs_config) < 0) {
6375                 r = -EIO;
6376                 goto out8;
6377         }
6378
6379         if (boot_cpu_has(X86_FEATURE_NX))
6380                 kvm_enable_efer_bits(EFER_NX);
6381
6382         if (!cpu_has_vmx_vpid())
6383                 enable_vpid = 0;
6384         if (!cpu_has_vmx_shadow_vmcs())
6385                 enable_shadow_vmcs = 0;
6386         if (enable_shadow_vmcs)
6387                 init_vmcs_shadow_fields();
6388
6389         if (!cpu_has_vmx_ept() ||
6390             !cpu_has_vmx_ept_4levels()) {
6391                 enable_ept = 0;
6392                 enable_unrestricted_guest = 0;
6393                 enable_ept_ad_bits = 0;
6394         }
6395
6396         if (!cpu_has_vmx_ept_ad_bits())
6397                 enable_ept_ad_bits = 0;
6398
6399         if (!cpu_has_vmx_unrestricted_guest())
6400                 enable_unrestricted_guest = 0;
6401
6402         if (!cpu_has_vmx_flexpriority())
6403                 flexpriority_enabled = 0;
6404
6405         /*
6406          * set_apic_access_page_addr() is used to reload apic access
6407          * page upon invalidation.  No need to do anything if not
6408          * using the APIC_ACCESS_ADDR VMCS field.
6409          */
6410         if (!flexpriority_enabled)
6411                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6412
6413         if (!cpu_has_vmx_tpr_shadow())
6414                 kvm_x86_ops->update_cr8_intercept = NULL;
6415
6416         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6417                 kvm_disable_largepages();
6418
6419         if (!cpu_has_vmx_ple())
6420                 ple_gap = 0;
6421
6422         if (!cpu_has_vmx_apicv())
6423                 enable_apicv = 0;
6424
6425         if (cpu_has_vmx_tsc_scaling()) {
6426                 kvm_has_tsc_control = true;
6427                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6428                 kvm_tsc_scaling_ratio_frac_bits = 48;
6429         }
6430
6431         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6432         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6433         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6434         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6435         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6436         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6437         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6438
6439         memcpy(vmx_msr_bitmap_legacy_x2apic,
6440                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6441         memcpy(vmx_msr_bitmap_longmode_x2apic,
6442                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6443
6444         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6445
6446         for (msr = 0x800; msr <= 0x8ff; msr++)
6447                 vmx_disable_intercept_msr_read_x2apic(msr);
6448
6449         /* According SDM, in x2apic mode, the whole id reg is used.  But in
6450          * KVM, it only use the highest eight bits. Need to intercept it */
6451         vmx_enable_intercept_msr_read_x2apic(0x802);
6452         /* TMCCT */
6453         vmx_enable_intercept_msr_read_x2apic(0x839);
6454         /* TPR */
6455         vmx_disable_intercept_msr_write_x2apic(0x808);
6456         /* EOI */
6457         vmx_disable_intercept_msr_write_x2apic(0x80b);
6458         /* SELF-IPI */
6459         vmx_disable_intercept_msr_write_x2apic(0x83f);
6460
6461         if (enable_ept) {
6462                 kvm_mmu_set_mask_ptes(0ull,
6463                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6464                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6465                         0ull, VMX_EPT_EXECUTABLE_MASK);
6466                 ept_set_mmio_spte_mask();
6467                 kvm_enable_tdp();
6468         } else
6469                 kvm_disable_tdp();
6470
6471         update_ple_window_actual_max();
6472
6473         /*
6474          * Only enable PML when hardware supports PML feature, and both EPT
6475          * and EPT A/D bit features are enabled -- PML depends on them to work.
6476          */
6477         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6478                 enable_pml = 0;
6479
6480         if (!enable_pml) {
6481                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6482                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6483                 kvm_x86_ops->flush_log_dirty = NULL;
6484                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6485         }
6486
6487         if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6488                 u64 vmx_msr;
6489
6490                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6491                 cpu_preemption_timer_multi =
6492                          vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6493         } else {
6494                 kvm_x86_ops->set_hv_timer = NULL;
6495                 kvm_x86_ops->cancel_hv_timer = NULL;
6496         }
6497
6498         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6499
6500         kvm_mce_cap_supported |= MCG_LMCE_P;
6501
6502         return alloc_kvm_area();
6503
6504 out8:
6505         free_page((unsigned long)vmx_vmwrite_bitmap);
6506 out7:
6507         free_page((unsigned long)vmx_vmread_bitmap);
6508 out6:
6509         if (nested)
6510                 free_page((unsigned long)vmx_msr_bitmap_nested);
6511 out5:
6512         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6513 out4:
6514         free_page((unsigned long)vmx_msr_bitmap_longmode);
6515 out3:
6516         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6517 out2:
6518         free_page((unsigned long)vmx_msr_bitmap_legacy);
6519 out1:
6520         free_page((unsigned long)vmx_io_bitmap_b);
6521 out:
6522         free_page((unsigned long)vmx_io_bitmap_a);
6523
6524     return r;
6525 }
6526
6527 static __exit void hardware_unsetup(void)
6528 {
6529         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6530         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6531         free_page((unsigned long)vmx_msr_bitmap_legacy);
6532         free_page((unsigned long)vmx_msr_bitmap_longmode);
6533         free_page((unsigned long)vmx_io_bitmap_b);
6534         free_page((unsigned long)vmx_io_bitmap_a);
6535         free_page((unsigned long)vmx_vmwrite_bitmap);
6536         free_page((unsigned long)vmx_vmread_bitmap);
6537         if (nested)
6538                 free_page((unsigned long)vmx_msr_bitmap_nested);
6539
6540         free_kvm_area();
6541 }
6542
6543 /*
6544  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6545  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6546  */
6547 static int handle_pause(struct kvm_vcpu *vcpu)
6548 {
6549         if (ple_gap)
6550                 grow_ple_window(vcpu);
6551
6552         skip_emulated_instruction(vcpu);
6553         kvm_vcpu_on_spin(vcpu);
6554
6555         return 1;
6556 }
6557
6558 static int handle_nop(struct kvm_vcpu *vcpu)
6559 {
6560         skip_emulated_instruction(vcpu);
6561         return 1;
6562 }
6563
6564 static int handle_mwait(struct kvm_vcpu *vcpu)
6565 {
6566         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6567         return handle_nop(vcpu);
6568 }
6569
6570 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6571 {
6572         return 1;
6573 }
6574
6575 static int handle_monitor(struct kvm_vcpu *vcpu)
6576 {
6577         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6578         return handle_nop(vcpu);
6579 }
6580
6581 /*
6582  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6583  * We could reuse a single VMCS for all the L2 guests, but we also want the
6584  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6585  * allows keeping them loaded on the processor, and in the future will allow
6586  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6587  * every entry if they never change.
6588  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6589  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6590  *
6591  * The following functions allocate and free a vmcs02 in this pool.
6592  */
6593
6594 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6595 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6596 {
6597         struct vmcs02_list *item;
6598         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6599                 if (item->vmptr == vmx->nested.current_vmptr) {
6600                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6601                         return &item->vmcs02;
6602                 }
6603
6604         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6605                 /* Recycle the least recently used VMCS. */
6606                 item = list_last_entry(&vmx->nested.vmcs02_pool,
6607                                        struct vmcs02_list, list);
6608                 item->vmptr = vmx->nested.current_vmptr;
6609                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6610                 return &item->vmcs02;
6611         }
6612
6613         /* Create a new VMCS */
6614         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6615         if (!item)
6616                 return NULL;
6617         item->vmcs02.vmcs = alloc_vmcs();
6618         if (!item->vmcs02.vmcs) {
6619                 kfree(item);
6620                 return NULL;
6621         }
6622         loaded_vmcs_init(&item->vmcs02);
6623         item->vmptr = vmx->nested.current_vmptr;
6624         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6625         vmx->nested.vmcs02_num++;
6626         return &item->vmcs02;
6627 }
6628
6629 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6630 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6631 {
6632         struct vmcs02_list *item;
6633         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6634                 if (item->vmptr == vmptr) {
6635                         free_loaded_vmcs(&item->vmcs02);
6636                         list_del(&item->list);
6637                         kfree(item);
6638                         vmx->nested.vmcs02_num--;
6639                         return;
6640                 }
6641 }
6642
6643 /*
6644  * Free all VMCSs saved for this vcpu, except the one pointed by
6645  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6646  * must be &vmx->vmcs01.
6647  */
6648 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6649 {
6650         struct vmcs02_list *item, *n;
6651
6652         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6653         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6654                 /*
6655                  * Something will leak if the above WARN triggers.  Better than
6656                  * a use-after-free.
6657                  */
6658                 if (vmx->loaded_vmcs == &item->vmcs02)
6659                         continue;
6660
6661                 free_loaded_vmcs(&item->vmcs02);
6662                 list_del(&item->list);
6663                 kfree(item);
6664                 vmx->nested.vmcs02_num--;
6665         }
6666 }
6667
6668 /*
6669  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6670  * set the success or error code of an emulated VMX instruction, as specified
6671  * by Vol 2B, VMX Instruction Reference, "Conventions".
6672  */
6673 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6674 {
6675         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6676                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6677                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6678 }
6679
6680 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6681 {
6682         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6683                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6684                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6685                         | X86_EFLAGS_CF);
6686 }
6687
6688 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6689                                         u32 vm_instruction_error)
6690 {
6691         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6692                 /*
6693                  * failValid writes the error number to the current VMCS, which
6694                  * can't be done there isn't a current VMCS.
6695                  */
6696                 nested_vmx_failInvalid(vcpu);
6697                 return;
6698         }
6699         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6700                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6701                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6702                         | X86_EFLAGS_ZF);
6703         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6704         /*
6705          * We don't need to force a shadow sync because
6706          * VM_INSTRUCTION_ERROR is not shadowed
6707          */
6708 }
6709
6710 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6711 {
6712         /* TODO: not to reset guest simply here. */
6713         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6714         pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6715 }
6716
6717 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6718 {
6719         struct vcpu_vmx *vmx =
6720                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6721
6722         vmx->nested.preemption_timer_expired = true;
6723         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6724         kvm_vcpu_kick(&vmx->vcpu);
6725
6726         return HRTIMER_NORESTART;
6727 }
6728
6729 /*
6730  * Decode the memory-address operand of a vmx instruction, as recorded on an
6731  * exit caused by such an instruction (run by a guest hypervisor).
6732  * On success, returns 0. When the operand is invalid, returns 1 and throws
6733  * #UD or #GP.
6734  */
6735 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6736                                  unsigned long exit_qualification,
6737                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6738 {
6739         gva_t off;
6740         bool exn;
6741         struct kvm_segment s;
6742
6743         /*
6744          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6745          * Execution", on an exit, vmx_instruction_info holds most of the
6746          * addressing components of the operand. Only the displacement part
6747          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6748          * For how an actual address is calculated from all these components,
6749          * refer to Vol. 1, "Operand Addressing".
6750          */
6751         int  scaling = vmx_instruction_info & 3;
6752         int  addr_size = (vmx_instruction_info >> 7) & 7;
6753         bool is_reg = vmx_instruction_info & (1u << 10);
6754         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6755         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6756         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6757         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6758         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6759
6760         if (is_reg) {
6761                 kvm_queue_exception(vcpu, UD_VECTOR);
6762                 return 1;
6763         }
6764
6765         /* Addr = segment_base + offset */
6766         /* offset = base + [index * scale] + displacement */
6767         off = exit_qualification; /* holds the displacement */
6768         if (base_is_valid)
6769                 off += kvm_register_read(vcpu, base_reg);
6770         if (index_is_valid)
6771                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6772         vmx_get_segment(vcpu, &s, seg_reg);
6773         *ret = s.base + off;
6774
6775         if (addr_size == 1) /* 32 bit */
6776                 *ret &= 0xffffffff;
6777
6778         /* Checks for #GP/#SS exceptions. */
6779         exn = false;
6780         if (is_protmode(vcpu)) {
6781                 /* Protected mode: apply checks for segment validity in the
6782                  * following order:
6783                  * - segment type check (#GP(0) may be thrown)
6784                  * - usability check (#GP(0)/#SS(0))
6785                  * - limit check (#GP(0)/#SS(0))
6786                  */
6787                 if (wr)
6788                         /* #GP(0) if the destination operand is located in a
6789                          * read-only data segment or any code segment.
6790                          */
6791                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6792                 else
6793                         /* #GP(0) if the source operand is located in an
6794                          * execute-only code segment
6795                          */
6796                         exn = ((s.type & 0xa) == 8);
6797         }
6798         if (exn) {
6799                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6800                 return 1;
6801         }
6802         if (is_long_mode(vcpu)) {
6803                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6804                  * non-canonical form. This is an only check for long mode.
6805                  */
6806                 exn = is_noncanonical_address(*ret);
6807         } else if (is_protmode(vcpu)) {
6808                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6809                  */
6810                 exn = (s.unusable != 0);
6811                 /* Protected mode: #GP(0)/#SS(0) if the memory
6812                  * operand is outside the segment limit.
6813                  */
6814                 exn = exn || (off + sizeof(u64) > s.limit);
6815         }
6816         if (exn) {
6817                 kvm_queue_exception_e(vcpu,
6818                                       seg_reg == VCPU_SREG_SS ?
6819                                                 SS_VECTOR : GP_VECTOR,
6820                                       0);
6821                 return 1;
6822         }
6823
6824         return 0;
6825 }
6826
6827 /*
6828  * This function performs the various checks including
6829  * - if it's 4KB aligned
6830  * - No bits beyond the physical address width are set
6831  * - Returns 0 on success or else 1
6832  * (Intel SDM Section 30.3)
6833  */
6834 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6835                                   gpa_t *vmpointer)
6836 {
6837         gva_t gva;
6838         gpa_t vmptr;
6839         struct x86_exception e;
6840         struct page *page;
6841         struct vcpu_vmx *vmx = to_vmx(vcpu);
6842         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6843
6844         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6845                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6846                 return 1;
6847
6848         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6849                                 sizeof(vmptr), &e)) {
6850                 kvm_inject_page_fault(vcpu, &e);
6851                 return 1;
6852         }
6853
6854         switch (exit_reason) {
6855         case EXIT_REASON_VMON:
6856                 /*
6857                  * SDM 3: 24.11.5
6858                  * The first 4 bytes of VMXON region contain the supported
6859                  * VMCS revision identifier
6860                  *
6861                  * Note - IA32_VMX_BASIC[48] will never be 1
6862                  * for the nested case;
6863                  * which replaces physical address width with 32
6864                  *
6865                  */
6866                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6867                         nested_vmx_failInvalid(vcpu);
6868                         skip_emulated_instruction(vcpu);
6869                         return 1;
6870                 }
6871
6872                 page = nested_get_page(vcpu, vmptr);
6873                 if (page == NULL ||
6874                     *(u32 *)kmap(page) != VMCS12_REVISION) {
6875                         nested_vmx_failInvalid(vcpu);
6876                         kunmap(page);
6877                         skip_emulated_instruction(vcpu);
6878                         return 1;
6879                 }
6880                 kunmap(page);
6881                 vmx->nested.vmxon_ptr = vmptr;
6882                 break;
6883         case EXIT_REASON_VMCLEAR:
6884                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6885                         nested_vmx_failValid(vcpu,
6886                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6887                         skip_emulated_instruction(vcpu);
6888                         return 1;
6889                 }
6890
6891                 if (vmptr == vmx->nested.vmxon_ptr) {
6892                         nested_vmx_failValid(vcpu,
6893                                              VMXERR_VMCLEAR_VMXON_POINTER);
6894                         skip_emulated_instruction(vcpu);
6895                         return 1;
6896                 }
6897                 break;
6898         case EXIT_REASON_VMPTRLD:
6899                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6900                         nested_vmx_failValid(vcpu,
6901                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6902                         skip_emulated_instruction(vcpu);
6903                         return 1;
6904                 }
6905
6906                 if (vmptr == vmx->nested.vmxon_ptr) {
6907                         nested_vmx_failValid(vcpu,
6908                                              VMXERR_VMCLEAR_VMXON_POINTER);
6909                         skip_emulated_instruction(vcpu);
6910                         return 1;
6911                 }
6912                 break;
6913         default:
6914                 return 1; /* shouldn't happen */
6915         }
6916
6917         if (vmpointer)
6918                 *vmpointer = vmptr;
6919         return 0;
6920 }
6921
6922 /*
6923  * Emulate the VMXON instruction.
6924  * Currently, we just remember that VMX is active, and do not save or even
6925  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6926  * do not currently need to store anything in that guest-allocated memory
6927  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6928  * argument is different from the VMXON pointer (which the spec says they do).
6929  */
6930 static int handle_vmon(struct kvm_vcpu *vcpu)
6931 {
6932         struct kvm_segment cs;
6933         struct vcpu_vmx *vmx = to_vmx(vcpu);
6934         struct vmcs *shadow_vmcs;
6935         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6936                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6937
6938         /* The Intel VMX Instruction Reference lists a bunch of bits that
6939          * are prerequisite to running VMXON, most notably cr4.VMXE must be
6940          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6941          * Otherwise, we should fail with #UD. We test these now:
6942          */
6943         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6944             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6945             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6946                 kvm_queue_exception(vcpu, UD_VECTOR);
6947                 return 1;
6948         }
6949
6950         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6951         if (is_long_mode(vcpu) && !cs.l) {
6952                 kvm_queue_exception(vcpu, UD_VECTOR);
6953                 return 1;
6954         }
6955
6956         if (vmx_get_cpl(vcpu)) {
6957                 kvm_inject_gp(vcpu, 0);
6958                 return 1;
6959         }
6960
6961         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6962                 return 1;
6963
6964         if (vmx->nested.vmxon) {
6965                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6966                 skip_emulated_instruction(vcpu);
6967                 return 1;
6968         }
6969
6970         if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6971                         != VMXON_NEEDED_FEATURES) {
6972                 kvm_inject_gp(vcpu, 0);
6973                 return 1;
6974         }
6975
6976         if (enable_shadow_vmcs) {
6977                 shadow_vmcs = alloc_vmcs();
6978                 if (!shadow_vmcs)
6979                         return -ENOMEM;
6980                 /* mark vmcs as shadow */
6981                 shadow_vmcs->revision_id |= (1u << 31);
6982                 /* init shadow vmcs */
6983                 vmcs_clear(shadow_vmcs);
6984                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6985         }
6986
6987         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6988         vmx->nested.vmcs02_num = 0;
6989
6990         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6991                      HRTIMER_MODE_REL);
6992         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6993
6994         vmx->nested.vmxon = true;
6995
6996         skip_emulated_instruction(vcpu);
6997         nested_vmx_succeed(vcpu);
6998         return 1;
6999 }
7000
7001 /*
7002  * Intel's VMX Instruction Reference specifies a common set of prerequisites
7003  * for running VMX instructions (except VMXON, whose prerequisites are
7004  * slightly different). It also specifies what exception to inject otherwise.
7005  */
7006 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7007 {
7008         struct kvm_segment cs;
7009         struct vcpu_vmx *vmx = to_vmx(vcpu);
7010
7011         if (!vmx->nested.vmxon) {
7012                 kvm_queue_exception(vcpu, UD_VECTOR);
7013                 return 0;
7014         }
7015
7016         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
7017         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
7018             (is_long_mode(vcpu) && !cs.l)) {
7019                 kvm_queue_exception(vcpu, UD_VECTOR);
7020                 return 0;
7021         }
7022
7023         if (vmx_get_cpl(vcpu)) {
7024                 kvm_inject_gp(vcpu, 0);
7025                 return 0;
7026         }
7027
7028         return 1;
7029 }
7030
7031 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7032 {
7033         if (vmx->nested.current_vmptr == -1ull)
7034                 return;
7035
7036         /* current_vmptr and current_vmcs12 are always set/reset together */
7037         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
7038                 return;
7039
7040         if (enable_shadow_vmcs) {
7041                 /* copy to memory all shadowed fields in case
7042                    they were modified */
7043                 copy_shadow_to_vmcs12(vmx);
7044                 vmx->nested.sync_shadow_vmcs = false;
7045                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
7046                                 SECONDARY_EXEC_SHADOW_VMCS);
7047                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7048         }
7049         vmx->nested.posted_intr_nv = -1;
7050         kunmap(vmx->nested.current_vmcs12_page);
7051         nested_release_page(vmx->nested.current_vmcs12_page);
7052         vmx->nested.current_vmptr = -1ull;
7053         vmx->nested.current_vmcs12 = NULL;
7054 }
7055
7056 /*
7057  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7058  * just stops using VMX.
7059  */
7060 static void free_nested(struct vcpu_vmx *vmx)
7061 {
7062         if (!vmx->nested.vmxon)
7063                 return;
7064
7065         vmx->nested.vmxon = false;
7066         free_vpid(vmx->nested.vpid02);
7067         nested_release_vmcs12(vmx);
7068         if (enable_shadow_vmcs)
7069                 free_vmcs(vmx->nested.current_shadow_vmcs);
7070         /* Unpin physical memory we referred to in current vmcs02 */
7071         if (vmx->nested.apic_access_page) {
7072                 nested_release_page(vmx->nested.apic_access_page);
7073                 vmx->nested.apic_access_page = NULL;
7074         }
7075         if (vmx->nested.virtual_apic_page) {
7076                 nested_release_page(vmx->nested.virtual_apic_page);
7077                 vmx->nested.virtual_apic_page = NULL;
7078         }
7079         if (vmx->nested.pi_desc_page) {
7080                 kunmap(vmx->nested.pi_desc_page);
7081                 nested_release_page(vmx->nested.pi_desc_page);
7082                 vmx->nested.pi_desc_page = NULL;
7083                 vmx->nested.pi_desc = NULL;
7084         }
7085
7086         nested_free_all_saved_vmcss(vmx);
7087 }
7088
7089 /* Emulate the VMXOFF instruction */
7090 static int handle_vmoff(struct kvm_vcpu *vcpu)
7091 {
7092         if (!nested_vmx_check_permission(vcpu))
7093                 return 1;
7094         free_nested(to_vmx(vcpu));
7095         skip_emulated_instruction(vcpu);
7096         nested_vmx_succeed(vcpu);
7097         return 1;
7098 }
7099
7100 /* Emulate the VMCLEAR instruction */
7101 static int handle_vmclear(struct kvm_vcpu *vcpu)
7102 {
7103         struct vcpu_vmx *vmx = to_vmx(vcpu);
7104         gpa_t vmptr;
7105         struct vmcs12 *vmcs12;
7106         struct page *page;
7107
7108         if (!nested_vmx_check_permission(vcpu))
7109                 return 1;
7110
7111         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
7112                 return 1;
7113
7114         if (vmptr == vmx->nested.current_vmptr)
7115                 nested_release_vmcs12(vmx);
7116
7117         page = nested_get_page(vcpu, vmptr);
7118         if (page == NULL) {
7119                 /*
7120                  * For accurate processor emulation, VMCLEAR beyond available
7121                  * physical memory should do nothing at all. However, it is
7122                  * possible that a nested vmx bug, not a guest hypervisor bug,
7123                  * resulted in this case, so let's shut down before doing any
7124                  * more damage:
7125                  */
7126                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7127                 return 1;
7128         }
7129         vmcs12 = kmap(page);
7130         vmcs12->launch_state = 0;
7131         kunmap(page);
7132         nested_release_page(page);
7133
7134         nested_free_vmcs02(vmx, vmptr);
7135
7136         skip_emulated_instruction(vcpu);
7137         nested_vmx_succeed(vcpu);
7138         return 1;
7139 }
7140
7141 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7142
7143 /* Emulate the VMLAUNCH instruction */
7144 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7145 {
7146         return nested_vmx_run(vcpu, true);
7147 }
7148
7149 /* Emulate the VMRESUME instruction */
7150 static int handle_vmresume(struct kvm_vcpu *vcpu)
7151 {
7152
7153         return nested_vmx_run(vcpu, false);
7154 }
7155
7156 enum vmcs_field_type {
7157         VMCS_FIELD_TYPE_U16 = 0,
7158         VMCS_FIELD_TYPE_U64 = 1,
7159         VMCS_FIELD_TYPE_U32 = 2,
7160         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
7161 };
7162
7163 static inline int vmcs_field_type(unsigned long field)
7164 {
7165         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
7166                 return VMCS_FIELD_TYPE_U32;
7167         return (field >> 13) & 0x3 ;
7168 }
7169
7170 static inline int vmcs_field_readonly(unsigned long field)
7171 {
7172         return (((field >> 10) & 0x3) == 1);
7173 }
7174
7175 /*
7176  * Read a vmcs12 field. Since these can have varying lengths and we return
7177  * one type, we chose the biggest type (u64) and zero-extend the return value
7178  * to that size. Note that the caller, handle_vmread, might need to use only
7179  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7180  * 64-bit fields are to be returned).
7181  */
7182 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7183                                   unsigned long field, u64 *ret)
7184 {
7185         short offset = vmcs_field_to_offset(field);
7186         char *p;
7187
7188         if (offset < 0)
7189                 return offset;
7190
7191         p = ((char *)(get_vmcs12(vcpu))) + offset;
7192
7193         switch (vmcs_field_type(field)) {
7194         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7195                 *ret = *((natural_width *)p);
7196                 return 0;
7197         case VMCS_FIELD_TYPE_U16:
7198                 *ret = *((u16 *)p);
7199                 return 0;
7200         case VMCS_FIELD_TYPE_U32:
7201                 *ret = *((u32 *)p);
7202                 return 0;
7203         case VMCS_FIELD_TYPE_U64:
7204                 *ret = *((u64 *)p);
7205                 return 0;
7206         default:
7207                 WARN_ON(1);
7208                 return -ENOENT;
7209         }
7210 }
7211
7212
7213 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7214                                    unsigned long field, u64 field_value){
7215         short offset = vmcs_field_to_offset(field);
7216         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7217         if (offset < 0)
7218                 return offset;
7219
7220         switch (vmcs_field_type(field)) {
7221         case VMCS_FIELD_TYPE_U16:
7222                 *(u16 *)p = field_value;
7223                 return 0;
7224         case VMCS_FIELD_TYPE_U32:
7225                 *(u32 *)p = field_value;
7226                 return 0;
7227         case VMCS_FIELD_TYPE_U64:
7228                 *(u64 *)p = field_value;
7229                 return 0;
7230         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7231                 *(natural_width *)p = field_value;
7232                 return 0;
7233         default:
7234                 WARN_ON(1);
7235                 return -ENOENT;
7236         }
7237
7238 }
7239
7240 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7241 {
7242         int i;
7243         unsigned long field;
7244         u64 field_value;
7245         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7246         const unsigned long *fields = shadow_read_write_fields;
7247         const int num_fields = max_shadow_read_write_fields;
7248
7249         preempt_disable();
7250
7251         vmcs_load(shadow_vmcs);
7252
7253         for (i = 0; i < num_fields; i++) {
7254                 field = fields[i];
7255                 switch (vmcs_field_type(field)) {
7256                 case VMCS_FIELD_TYPE_U16:
7257                         field_value = vmcs_read16(field);
7258                         break;
7259                 case VMCS_FIELD_TYPE_U32:
7260                         field_value = vmcs_read32(field);
7261                         break;
7262                 case VMCS_FIELD_TYPE_U64:
7263                         field_value = vmcs_read64(field);
7264                         break;
7265                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7266                         field_value = vmcs_readl(field);
7267                         break;
7268                 default:
7269                         WARN_ON(1);
7270                         continue;
7271                 }
7272                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7273         }
7274
7275         vmcs_clear(shadow_vmcs);
7276         vmcs_load(vmx->loaded_vmcs->vmcs);
7277
7278         preempt_enable();
7279 }
7280
7281 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7282 {
7283         const unsigned long *fields[] = {
7284                 shadow_read_write_fields,
7285                 shadow_read_only_fields
7286         };
7287         const int max_fields[] = {
7288                 max_shadow_read_write_fields,
7289                 max_shadow_read_only_fields
7290         };
7291         int i, q;
7292         unsigned long field;
7293         u64 field_value = 0;
7294         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7295
7296         vmcs_load(shadow_vmcs);
7297
7298         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7299                 for (i = 0; i < max_fields[q]; i++) {
7300                         field = fields[q][i];
7301                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7302
7303                         switch (vmcs_field_type(field)) {
7304                         case VMCS_FIELD_TYPE_U16:
7305                                 vmcs_write16(field, (u16)field_value);
7306                                 break;
7307                         case VMCS_FIELD_TYPE_U32:
7308                                 vmcs_write32(field, (u32)field_value);
7309                                 break;
7310                         case VMCS_FIELD_TYPE_U64:
7311                                 vmcs_write64(field, (u64)field_value);
7312                                 break;
7313                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7314                                 vmcs_writel(field, (long)field_value);
7315                                 break;
7316                         default:
7317                                 WARN_ON(1);
7318                                 break;
7319                         }
7320                 }
7321         }
7322
7323         vmcs_clear(shadow_vmcs);
7324         vmcs_load(vmx->loaded_vmcs->vmcs);
7325 }
7326
7327 /*
7328  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7329  * used before) all generate the same failure when it is missing.
7330  */
7331 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7332 {
7333         struct vcpu_vmx *vmx = to_vmx(vcpu);
7334         if (vmx->nested.current_vmptr == -1ull) {
7335                 nested_vmx_failInvalid(vcpu);
7336                 skip_emulated_instruction(vcpu);
7337                 return 0;
7338         }
7339         return 1;
7340 }
7341
7342 static int handle_vmread(struct kvm_vcpu *vcpu)
7343 {
7344         unsigned long field;
7345         u64 field_value;
7346         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7347         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7348         gva_t gva = 0;
7349
7350         if (!nested_vmx_check_permission(vcpu) ||
7351             !nested_vmx_check_vmcs12(vcpu))
7352                 return 1;
7353
7354         /* Decode instruction info and find the field to read */
7355         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7356         /* Read the field, zero-extended to a u64 field_value */
7357         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7358                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7359                 skip_emulated_instruction(vcpu);
7360                 return 1;
7361         }
7362         /*
7363          * Now copy part of this value to register or memory, as requested.
7364          * Note that the number of bits actually copied is 32 or 64 depending
7365          * on the guest's mode (32 or 64 bit), not on the given field's length.
7366          */
7367         if (vmx_instruction_info & (1u << 10)) {
7368                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7369                         field_value);
7370         } else {
7371                 if (get_vmx_mem_address(vcpu, exit_qualification,
7372                                 vmx_instruction_info, true, &gva))
7373                         return 1;
7374                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7375                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7376                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7377         }
7378
7379         nested_vmx_succeed(vcpu);
7380         skip_emulated_instruction(vcpu);
7381         return 1;
7382 }
7383
7384
7385 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7386 {
7387         unsigned long field;
7388         gva_t gva;
7389         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7390         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7391         /* The value to write might be 32 or 64 bits, depending on L1's long
7392          * mode, and eventually we need to write that into a field of several
7393          * possible lengths. The code below first zero-extends the value to 64
7394          * bit (field_value), and then copies only the appropriate number of
7395          * bits into the vmcs12 field.
7396          */
7397         u64 field_value = 0;
7398         struct x86_exception e;
7399
7400         if (!nested_vmx_check_permission(vcpu) ||
7401             !nested_vmx_check_vmcs12(vcpu))
7402                 return 1;
7403
7404         if (vmx_instruction_info & (1u << 10))
7405                 field_value = kvm_register_readl(vcpu,
7406                         (((vmx_instruction_info) >> 3) & 0xf));
7407         else {
7408                 if (get_vmx_mem_address(vcpu, exit_qualification,
7409                                 vmx_instruction_info, false, &gva))
7410                         return 1;
7411                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7412                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7413                         kvm_inject_page_fault(vcpu, &e);
7414                         return 1;
7415                 }
7416         }
7417
7418
7419         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7420         if (vmcs_field_readonly(field)) {
7421                 nested_vmx_failValid(vcpu,
7422                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7423                 skip_emulated_instruction(vcpu);
7424                 return 1;
7425         }
7426
7427         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7428                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7429                 skip_emulated_instruction(vcpu);
7430                 return 1;
7431         }
7432
7433         nested_vmx_succeed(vcpu);
7434         skip_emulated_instruction(vcpu);
7435         return 1;
7436 }
7437
7438 /* Emulate the VMPTRLD instruction */
7439 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7440 {
7441         struct vcpu_vmx *vmx = to_vmx(vcpu);
7442         gpa_t vmptr;
7443
7444         if (!nested_vmx_check_permission(vcpu))
7445                 return 1;
7446
7447         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7448                 return 1;
7449
7450         if (vmx->nested.current_vmptr != vmptr) {
7451                 struct vmcs12 *new_vmcs12;
7452                 struct page *page;
7453                 page = nested_get_page(vcpu, vmptr);
7454                 if (page == NULL) {
7455                         nested_vmx_failInvalid(vcpu);
7456                         skip_emulated_instruction(vcpu);
7457                         return 1;
7458                 }
7459                 new_vmcs12 = kmap(page);
7460                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7461                         kunmap(page);
7462                         nested_release_page_clean(page);
7463                         nested_vmx_failValid(vcpu,
7464                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7465                         skip_emulated_instruction(vcpu);
7466                         return 1;
7467                 }
7468
7469                 nested_release_vmcs12(vmx);
7470                 vmx->nested.current_vmptr = vmptr;
7471                 vmx->nested.current_vmcs12 = new_vmcs12;
7472                 vmx->nested.current_vmcs12_page = page;
7473                 if (enable_shadow_vmcs) {
7474                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7475                                       SECONDARY_EXEC_SHADOW_VMCS);
7476                         vmcs_write64(VMCS_LINK_POINTER,
7477                                      __pa(vmx->nested.current_shadow_vmcs));
7478                         vmx->nested.sync_shadow_vmcs = true;
7479                 }
7480         }
7481
7482         nested_vmx_succeed(vcpu);
7483         skip_emulated_instruction(vcpu);
7484         return 1;
7485 }
7486
7487 /* Emulate the VMPTRST instruction */
7488 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7489 {
7490         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7491         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7492         gva_t vmcs_gva;
7493         struct x86_exception e;
7494
7495         if (!nested_vmx_check_permission(vcpu))
7496                 return 1;
7497
7498         if (get_vmx_mem_address(vcpu, exit_qualification,
7499                         vmx_instruction_info, true, &vmcs_gva))
7500                 return 1;
7501         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7502         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7503                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7504                                  sizeof(u64), &e)) {
7505                 kvm_inject_page_fault(vcpu, &e);
7506                 return 1;
7507         }
7508         nested_vmx_succeed(vcpu);
7509         skip_emulated_instruction(vcpu);
7510         return 1;
7511 }
7512
7513 /* Emulate the INVEPT instruction */
7514 static int handle_invept(struct kvm_vcpu *vcpu)
7515 {
7516         struct vcpu_vmx *vmx = to_vmx(vcpu);
7517         u32 vmx_instruction_info, types;
7518         unsigned long type;
7519         gva_t gva;
7520         struct x86_exception e;
7521         struct {
7522                 u64 eptp, gpa;
7523         } operand;
7524
7525         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7526               SECONDARY_EXEC_ENABLE_EPT) ||
7527             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7528                 kvm_queue_exception(vcpu, UD_VECTOR);
7529                 return 1;
7530         }
7531
7532         if (!nested_vmx_check_permission(vcpu))
7533                 return 1;
7534
7535         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7536                 kvm_queue_exception(vcpu, UD_VECTOR);
7537                 return 1;
7538         }
7539
7540         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7541         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7542
7543         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7544
7545         if (!(types & (1UL << type))) {
7546                 nested_vmx_failValid(vcpu,
7547                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7548                 skip_emulated_instruction(vcpu);
7549                 return 1;
7550         }
7551
7552         /* According to the Intel VMX instruction reference, the memory
7553          * operand is read even if it isn't needed (e.g., for type==global)
7554          */
7555         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7556                         vmx_instruction_info, false, &gva))
7557                 return 1;
7558         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7559                                 sizeof(operand), &e)) {
7560                 kvm_inject_page_fault(vcpu, &e);
7561                 return 1;
7562         }
7563
7564         switch (type) {
7565         case VMX_EPT_EXTENT_GLOBAL:
7566                 kvm_mmu_sync_roots(vcpu);
7567                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7568                 nested_vmx_succeed(vcpu);
7569                 break;
7570         default:
7571                 /* Trap single context invalidation invept calls */
7572                 BUG_ON(1);
7573                 break;
7574         }
7575
7576         skip_emulated_instruction(vcpu);
7577         return 1;
7578 }
7579
7580 static int handle_invvpid(struct kvm_vcpu *vcpu)
7581 {
7582         struct vcpu_vmx *vmx = to_vmx(vcpu);
7583         u32 vmx_instruction_info;
7584         unsigned long type, types;
7585         gva_t gva;
7586         struct x86_exception e;
7587         int vpid;
7588
7589         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7590               SECONDARY_EXEC_ENABLE_VPID) ||
7591                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7592                 kvm_queue_exception(vcpu, UD_VECTOR);
7593                 return 1;
7594         }
7595
7596         if (!nested_vmx_check_permission(vcpu))
7597                 return 1;
7598
7599         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7600         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7601
7602         types = (vmx->nested.nested_vmx_vpid_caps >> 8) & 0x7;
7603
7604         if (!(types & (1UL << type))) {
7605                 nested_vmx_failValid(vcpu,
7606                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7607                 skip_emulated_instruction(vcpu);
7608                 return 1;
7609         }
7610
7611         /* according to the intel vmx instruction reference, the memory
7612          * operand is read even if it isn't needed (e.g., for type==global)
7613          */
7614         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7615                         vmx_instruction_info, false, &gva))
7616                 return 1;
7617         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7618                                 sizeof(u32), &e)) {
7619                 kvm_inject_page_fault(vcpu, &e);
7620                 return 1;
7621         }
7622
7623         switch (type) {
7624         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7625                 /*
7626                  * Old versions of KVM use the single-context version so we
7627                  * have to support it; just treat it the same as all-context.
7628                  */
7629         case VMX_VPID_EXTENT_ALL_CONTEXT:
7630                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
7631                 nested_vmx_succeed(vcpu);
7632                 break;
7633         default:
7634                 /* Trap individual address invalidation invvpid calls */
7635                 BUG_ON(1);
7636                 break;
7637         }
7638
7639         skip_emulated_instruction(vcpu);
7640         return 1;
7641 }
7642
7643 static int handle_pml_full(struct kvm_vcpu *vcpu)
7644 {
7645         unsigned long exit_qualification;
7646
7647         trace_kvm_pml_full(vcpu->vcpu_id);
7648
7649         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7650
7651         /*
7652          * PML buffer FULL happened while executing iret from NMI,
7653          * "blocked by NMI" bit has to be set before next VM entry.
7654          */
7655         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7656                         cpu_has_virtual_nmis() &&
7657                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7658                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7659                                 GUEST_INTR_STATE_NMI);
7660
7661         /*
7662          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7663          * here.., and there's no userspace involvement needed for PML.
7664          */
7665         return 1;
7666 }
7667
7668 static int handle_pcommit(struct kvm_vcpu *vcpu)
7669 {
7670         /* we never catch pcommit instruct for L1 guest. */
7671         WARN_ON(1);
7672         return 1;
7673 }
7674
7675 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7676 {
7677         kvm_lapic_expired_hv_timer(vcpu);
7678         return 1;
7679 }
7680
7681 /*
7682  * The exit handlers return 1 if the exit was handled fully and guest execution
7683  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7684  * to be done to userspace and return 0.
7685  */
7686 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7687         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7688         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7689         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7690         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7691         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7692         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7693         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7694         [EXIT_REASON_CPUID]                   = handle_cpuid,
7695         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7696         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7697         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7698         [EXIT_REASON_HLT]                     = handle_halt,
7699         [EXIT_REASON_INVD]                    = handle_invd,
7700         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7701         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7702         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7703         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7704         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7705         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7706         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7707         [EXIT_REASON_VMREAD]                  = handle_vmread,
7708         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7709         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7710         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7711         [EXIT_REASON_VMON]                    = handle_vmon,
7712         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7713         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7714         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7715         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7716         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7717         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7718         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7719         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7720         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7721         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7722         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7723         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7724         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7725         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7726         [EXIT_REASON_INVEPT]                  = handle_invept,
7727         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7728         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7729         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7730         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7731         [EXIT_REASON_PCOMMIT]                 = handle_pcommit,
7732         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
7733 };
7734
7735 static const int kvm_vmx_max_exit_handlers =
7736         ARRAY_SIZE(kvm_vmx_exit_handlers);
7737
7738 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7739                                        struct vmcs12 *vmcs12)
7740 {
7741         unsigned long exit_qualification;
7742         gpa_t bitmap, last_bitmap;
7743         unsigned int port;
7744         int size;
7745         u8 b;
7746
7747         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7748                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7749
7750         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7751
7752         port = exit_qualification >> 16;
7753         size = (exit_qualification & 7) + 1;
7754
7755         last_bitmap = (gpa_t)-1;
7756         b = -1;
7757
7758         while (size > 0) {
7759                 if (port < 0x8000)
7760                         bitmap = vmcs12->io_bitmap_a;
7761                 else if (port < 0x10000)
7762                         bitmap = vmcs12->io_bitmap_b;
7763                 else
7764                         return true;
7765                 bitmap += (port & 0x7fff) / 8;
7766
7767                 if (last_bitmap != bitmap)
7768                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7769                                 return true;
7770                 if (b & (1 << (port & 7)))
7771                         return true;
7772
7773                 port++;
7774                 size--;
7775                 last_bitmap = bitmap;
7776         }
7777
7778         return false;
7779 }
7780
7781 /*
7782  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7783  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7784  * disinterest in the current event (read or write a specific MSR) by using an
7785  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7786  */
7787 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7788         struct vmcs12 *vmcs12, u32 exit_reason)
7789 {
7790         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7791         gpa_t bitmap;
7792
7793         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7794                 return true;
7795
7796         /*
7797          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7798          * for the four combinations of read/write and low/high MSR numbers.
7799          * First we need to figure out which of the four to use:
7800          */
7801         bitmap = vmcs12->msr_bitmap;
7802         if (exit_reason == EXIT_REASON_MSR_WRITE)
7803                 bitmap += 2048;
7804         if (msr_index >= 0xc0000000) {
7805                 msr_index -= 0xc0000000;
7806                 bitmap += 1024;
7807         }
7808
7809         /* Then read the msr_index'th bit from this bitmap: */
7810         if (msr_index < 1024*8) {
7811                 unsigned char b;
7812                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7813                         return true;
7814                 return 1 & (b >> (msr_index & 7));
7815         } else
7816                 return true; /* let L1 handle the wrong parameter */
7817 }
7818
7819 /*
7820  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7821  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7822  * intercept (via guest_host_mask etc.) the current event.
7823  */
7824 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7825         struct vmcs12 *vmcs12)
7826 {
7827         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7828         int cr = exit_qualification & 15;
7829         int reg = (exit_qualification >> 8) & 15;
7830         unsigned long val = kvm_register_readl(vcpu, reg);
7831
7832         switch ((exit_qualification >> 4) & 3) {
7833         case 0: /* mov to cr */
7834                 switch (cr) {
7835                 case 0:
7836                         if (vmcs12->cr0_guest_host_mask &
7837                             (val ^ vmcs12->cr0_read_shadow))
7838                                 return true;
7839                         break;
7840                 case 3:
7841                         if ((vmcs12->cr3_target_count >= 1 &&
7842                                         vmcs12->cr3_target_value0 == val) ||
7843                                 (vmcs12->cr3_target_count >= 2 &&
7844                                         vmcs12->cr3_target_value1 == val) ||
7845                                 (vmcs12->cr3_target_count >= 3 &&
7846                                         vmcs12->cr3_target_value2 == val) ||
7847                                 (vmcs12->cr3_target_count >= 4 &&
7848                                         vmcs12->cr3_target_value3 == val))
7849                                 return false;
7850                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7851                                 return true;
7852                         break;
7853                 case 4:
7854                         if (vmcs12->cr4_guest_host_mask &
7855                             (vmcs12->cr4_read_shadow ^ val))
7856                                 return true;
7857                         break;
7858                 case 8:
7859                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7860                                 return true;
7861                         break;
7862                 }
7863                 break;
7864         case 2: /* clts */
7865                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7866                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7867                         return true;
7868                 break;
7869         case 1: /* mov from cr */
7870                 switch (cr) {
7871                 case 3:
7872                         if (vmcs12->cpu_based_vm_exec_control &
7873                             CPU_BASED_CR3_STORE_EXITING)
7874                                 return true;
7875                         break;
7876                 case 8:
7877                         if (vmcs12->cpu_based_vm_exec_control &
7878                             CPU_BASED_CR8_STORE_EXITING)
7879                                 return true;
7880                         break;
7881                 }
7882                 break;
7883         case 3: /* lmsw */
7884                 /*
7885                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7886                  * cr0. Other attempted changes are ignored, with no exit.
7887                  */
7888                 if (vmcs12->cr0_guest_host_mask & 0xe &
7889                     (val ^ vmcs12->cr0_read_shadow))
7890                         return true;
7891                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7892                     !(vmcs12->cr0_read_shadow & 0x1) &&
7893                     (val & 0x1))
7894                         return true;
7895                 break;
7896         }
7897         return false;
7898 }
7899
7900 /*
7901  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7902  * should handle it ourselves in L0 (and then continue L2). Only call this
7903  * when in is_guest_mode (L2).
7904  */
7905 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7906 {
7907         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7908         struct vcpu_vmx *vmx = to_vmx(vcpu);
7909         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7910         u32 exit_reason = vmx->exit_reason;
7911
7912         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7913                                 vmcs_readl(EXIT_QUALIFICATION),
7914                                 vmx->idt_vectoring_info,
7915                                 intr_info,
7916                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7917                                 KVM_ISA_VMX);
7918
7919         if (vmx->nested.nested_run_pending)
7920                 return false;
7921
7922         if (unlikely(vmx->fail)) {
7923                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7924                                     vmcs_read32(VM_INSTRUCTION_ERROR));
7925                 return true;
7926         }
7927
7928         switch (exit_reason) {
7929         case EXIT_REASON_EXCEPTION_NMI:
7930                 if (!is_exception(intr_info))
7931                         return false;
7932                 else if (is_page_fault(intr_info))
7933                         return enable_ept;
7934                 else if (is_no_device(intr_info) &&
7935                          !(vmcs12->guest_cr0 & X86_CR0_TS))
7936                         return false;
7937                 else if (is_debug(intr_info) &&
7938                          vcpu->guest_debug &
7939                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
7940                         return false;
7941                 else if (is_breakpoint(intr_info) &&
7942                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
7943                         return false;
7944                 return vmcs12->exception_bitmap &
7945                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7946         case EXIT_REASON_EXTERNAL_INTERRUPT:
7947                 return false;
7948         case EXIT_REASON_TRIPLE_FAULT:
7949                 return true;
7950         case EXIT_REASON_PENDING_INTERRUPT:
7951                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7952         case EXIT_REASON_NMI_WINDOW:
7953                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7954         case EXIT_REASON_TASK_SWITCH:
7955                 return true;
7956         case EXIT_REASON_CPUID:
7957                 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7958                         return false;
7959                 return true;
7960         case EXIT_REASON_HLT:
7961                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7962         case EXIT_REASON_INVD:
7963                 return true;
7964         case EXIT_REASON_INVLPG:
7965                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7966         case EXIT_REASON_RDPMC:
7967                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7968         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
7969                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7970         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7971         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7972         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7973         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7974         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7975         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
7976                 /*
7977                  * VMX instructions trap unconditionally. This allows L1 to
7978                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
7979                  */
7980                 return true;
7981         case EXIT_REASON_CR_ACCESS:
7982                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7983         case EXIT_REASON_DR_ACCESS:
7984                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7985         case EXIT_REASON_IO_INSTRUCTION:
7986                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7987         case EXIT_REASON_MSR_READ:
7988         case EXIT_REASON_MSR_WRITE:
7989                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7990         case EXIT_REASON_INVALID_STATE:
7991                 return true;
7992         case EXIT_REASON_MWAIT_INSTRUCTION:
7993                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7994         case EXIT_REASON_MONITOR_TRAP_FLAG:
7995                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
7996         case EXIT_REASON_MONITOR_INSTRUCTION:
7997                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7998         case EXIT_REASON_PAUSE_INSTRUCTION:
7999                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8000                         nested_cpu_has2(vmcs12,
8001                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8002         case EXIT_REASON_MCE_DURING_VMENTRY:
8003                 return false;
8004         case EXIT_REASON_TPR_BELOW_THRESHOLD:
8005                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8006         case EXIT_REASON_APIC_ACCESS:
8007                 return nested_cpu_has2(vmcs12,
8008                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8009         case EXIT_REASON_APIC_WRITE:
8010         case EXIT_REASON_EOI_INDUCED:
8011                 /* apic_write and eoi_induced should exit unconditionally. */
8012                 return true;
8013         case EXIT_REASON_EPT_VIOLATION:
8014                 /*
8015                  * L0 always deals with the EPT violation. If nested EPT is
8016                  * used, and the nested mmu code discovers that the address is
8017                  * missing in the guest EPT table (EPT12), the EPT violation
8018                  * will be injected with nested_ept_inject_page_fault()
8019                  */
8020                 return false;
8021         case EXIT_REASON_EPT_MISCONFIG:
8022                 /*
8023                  * L2 never uses directly L1's EPT, but rather L0's own EPT
8024                  * table (shadow on EPT) or a merged EPT table that L0 built
8025                  * (EPT on EPT). So any problems with the structure of the
8026                  * table is L0's fault.
8027                  */
8028                 return false;
8029         case EXIT_REASON_WBINVD:
8030                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8031         case EXIT_REASON_XSETBV:
8032                 return true;
8033         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8034                 /*
8035                  * This should never happen, since it is not possible to
8036                  * set XSS to a non-zero value---neither in L1 nor in L2.
8037                  * If if it were, XSS would have to be checked against
8038                  * the XSS exit bitmap in vmcs12.
8039                  */
8040                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8041         case EXIT_REASON_PCOMMIT:
8042                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_PCOMMIT);
8043         case EXIT_REASON_PREEMPTION_TIMER:
8044                 return false;
8045         default:
8046                 return true;
8047         }
8048 }
8049
8050 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8051 {
8052         *info1 = vmcs_readl(EXIT_QUALIFICATION);
8053         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8054 }
8055
8056 static int vmx_create_pml_buffer(struct vcpu_vmx *vmx)
8057 {
8058         struct page *pml_pg;
8059
8060         pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
8061         if (!pml_pg)
8062                 return -ENOMEM;
8063
8064         vmx->pml_pg = pml_pg;
8065
8066         vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
8067         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8068
8069         return 0;
8070 }
8071
8072 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8073 {
8074         if (vmx->pml_pg) {
8075                 __free_page(vmx->pml_pg);
8076                 vmx->pml_pg = NULL;
8077         }
8078 }
8079
8080 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8081 {
8082         struct vcpu_vmx *vmx = to_vmx(vcpu);
8083         u64 *pml_buf;
8084         u16 pml_idx;
8085
8086         pml_idx = vmcs_read16(GUEST_PML_INDEX);
8087
8088         /* Do nothing if PML buffer is empty */
8089         if (pml_idx == (PML_ENTITY_NUM - 1))
8090                 return;
8091
8092         /* PML index always points to next available PML buffer entity */
8093         if (pml_idx >= PML_ENTITY_NUM)
8094                 pml_idx = 0;
8095         else
8096                 pml_idx++;
8097
8098         pml_buf = page_address(vmx->pml_pg);
8099         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8100                 u64 gpa;
8101
8102                 gpa = pml_buf[pml_idx];
8103                 WARN_ON(gpa & (PAGE_SIZE - 1));
8104                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8105         }
8106
8107         /* reset PML index */
8108         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8109 }
8110
8111 /*
8112  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8113  * Called before reporting dirty_bitmap to userspace.
8114  */
8115 static void kvm_flush_pml_buffers(struct kvm *kvm)
8116 {
8117         int i;
8118         struct kvm_vcpu *vcpu;
8119         /*
8120          * We only need to kick vcpu out of guest mode here, as PML buffer
8121          * is flushed at beginning of all VMEXITs, and it's obvious that only
8122          * vcpus running in guest are possible to have unflushed GPAs in PML
8123          * buffer.
8124          */
8125         kvm_for_each_vcpu(i, vcpu, kvm)
8126                 kvm_vcpu_kick(vcpu);
8127 }
8128
8129 static void vmx_dump_sel(char *name, uint32_t sel)
8130 {
8131         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8132                name, vmcs_read32(sel),
8133                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8134                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8135                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8136 }
8137
8138 static void vmx_dump_dtsel(char *name, uint32_t limit)
8139 {
8140         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
8141                name, vmcs_read32(limit),
8142                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8143 }
8144
8145 static void dump_vmcs(void)
8146 {
8147         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8148         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8149         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8150         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8151         u32 secondary_exec_control = 0;
8152         unsigned long cr4 = vmcs_readl(GUEST_CR4);
8153         u64 efer = vmcs_read64(GUEST_IA32_EFER);
8154         int i, n;
8155
8156         if (cpu_has_secondary_exec_ctrls())
8157                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8158
8159         pr_err("*** Guest State ***\n");
8160         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8161                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8162                vmcs_readl(CR0_GUEST_HOST_MASK));
8163         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8164                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8165         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8166         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8167             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8168         {
8169                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
8170                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8171                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
8172                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8173         }
8174         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
8175                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8176         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
8177                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8178         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8179                vmcs_readl(GUEST_SYSENTER_ESP),
8180                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8181         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
8182         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
8183         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
8184         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
8185         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
8186         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
8187         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8188         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8189         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8190         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
8191         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8192             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8193                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
8194                        efer, vmcs_read64(GUEST_IA32_PAT));
8195         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
8196                vmcs_read64(GUEST_IA32_DEBUGCTL),
8197                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8198         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8199                 pr_err("PerfGlobCtl = 0x%016llx\n",
8200                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8201         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8202                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8203         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
8204                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8205                vmcs_read32(GUEST_ACTIVITY_STATE));
8206         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8207                 pr_err("InterruptStatus = %04x\n",
8208                        vmcs_read16(GUEST_INTR_STATUS));
8209
8210         pr_err("*** Host State ***\n");
8211         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
8212                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8213         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8214                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8215                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8216                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8217                vmcs_read16(HOST_TR_SELECTOR));
8218         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8219                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8220                vmcs_readl(HOST_TR_BASE));
8221         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8222                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8223         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8224                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8225                vmcs_readl(HOST_CR4));
8226         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8227                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8228                vmcs_read32(HOST_IA32_SYSENTER_CS),
8229                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8230         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8231                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
8232                        vmcs_read64(HOST_IA32_EFER),
8233                        vmcs_read64(HOST_IA32_PAT));
8234         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8235                 pr_err("PerfGlobCtl = 0x%016llx\n",
8236                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8237
8238         pr_err("*** Control State ***\n");
8239         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8240                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8241         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8242         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8243                vmcs_read32(EXCEPTION_BITMAP),
8244                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8245                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8246         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8247                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8248                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8249                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8250         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8251                vmcs_read32(VM_EXIT_INTR_INFO),
8252                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8253                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8254         pr_err("        reason=%08x qualification=%016lx\n",
8255                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8256         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8257                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8258                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8259         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8260         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8261                 pr_err("TSC Multiplier = 0x%016llx\n",
8262                        vmcs_read64(TSC_MULTIPLIER));
8263         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8264                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8265         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8266                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8267         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8268                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8269         n = vmcs_read32(CR3_TARGET_COUNT);
8270         for (i = 0; i + 1 < n; i += 4)
8271                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8272                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8273                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8274         if (i < n)
8275                 pr_err("CR3 target%u=%016lx\n",
8276                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8277         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8278                 pr_err("PLE Gap=%08x Window=%08x\n",
8279                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8280         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8281                 pr_err("Virtual processor ID = 0x%04x\n",
8282                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8283 }
8284
8285 /*
8286  * The guest has exited.  See if we can fix it or if we need userspace
8287  * assistance.
8288  */
8289 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8290 {
8291         struct vcpu_vmx *vmx = to_vmx(vcpu);
8292         u32 exit_reason = vmx->exit_reason;
8293         u32 vectoring_info = vmx->idt_vectoring_info;
8294
8295         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8296
8297         /*
8298          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8299          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8300          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8301          * mode as if vcpus is in root mode, the PML buffer must has been
8302          * flushed already.
8303          */
8304         if (enable_pml)
8305                 vmx_flush_pml_buffer(vcpu);
8306
8307         /* If guest state is invalid, start emulating */
8308         if (vmx->emulation_required)
8309                 return handle_invalid_guest_state(vcpu);
8310
8311         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8312                 nested_vmx_vmexit(vcpu, exit_reason,
8313                                   vmcs_read32(VM_EXIT_INTR_INFO),
8314                                   vmcs_readl(EXIT_QUALIFICATION));
8315                 return 1;
8316         }
8317
8318         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8319                 dump_vmcs();
8320                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8321                 vcpu->run->fail_entry.hardware_entry_failure_reason
8322                         = exit_reason;
8323                 return 0;
8324         }
8325
8326         if (unlikely(vmx->fail)) {
8327                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8328                 vcpu->run->fail_entry.hardware_entry_failure_reason
8329                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8330                 return 0;
8331         }
8332
8333         /*
8334          * Note:
8335          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8336          * delivery event since it indicates guest is accessing MMIO.
8337          * The vm-exit can be triggered again after return to guest that
8338          * will cause infinite loop.
8339          */
8340         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8341                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8342                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8343                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8344                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8345                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8346                 vcpu->run->internal.ndata = 2;
8347                 vcpu->run->internal.data[0] = vectoring_info;
8348                 vcpu->run->internal.data[1] = exit_reason;
8349                 return 0;
8350         }
8351
8352         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8353             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8354                                         get_vmcs12(vcpu))))) {
8355                 if (vmx_interrupt_allowed(vcpu)) {
8356                         vmx->soft_vnmi_blocked = 0;
8357                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8358                            vcpu->arch.nmi_pending) {
8359                         /*
8360                          * This CPU don't support us in finding the end of an
8361                          * NMI-blocked window if the guest runs with IRQs
8362                          * disabled. So we pull the trigger after 1 s of
8363                          * futile waiting, but inform the user about this.
8364                          */
8365                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8366                                "state on VCPU %d after 1 s timeout\n",
8367                                __func__, vcpu->vcpu_id);
8368                         vmx->soft_vnmi_blocked = 0;
8369                 }
8370         }
8371
8372         if (exit_reason < kvm_vmx_max_exit_handlers
8373             && kvm_vmx_exit_handlers[exit_reason])
8374                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8375         else {
8376                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8377                 kvm_queue_exception(vcpu, UD_VECTOR);
8378                 return 1;
8379         }
8380 }
8381
8382 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8383 {
8384         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8385
8386         if (is_guest_mode(vcpu) &&
8387                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8388                 return;
8389
8390         if (irr == -1 || tpr < irr) {
8391                 vmcs_write32(TPR_THRESHOLD, 0);
8392                 return;
8393         }
8394
8395         vmcs_write32(TPR_THRESHOLD, irr);
8396 }
8397
8398 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8399 {
8400         u32 sec_exec_control;
8401
8402         /*
8403          * There is not point to enable virtualize x2apic without enable
8404          * apicv
8405          */
8406         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
8407                                 !kvm_vcpu_apicv_active(vcpu))
8408                 return;
8409
8410         if (!cpu_need_tpr_shadow(vcpu))
8411                 return;
8412
8413         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8414
8415         if (set) {
8416                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8417                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8418         } else {
8419                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8420                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8421         }
8422         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8423
8424         vmx_set_msr_bitmap(vcpu);
8425 }
8426
8427 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8428 {
8429         struct vcpu_vmx *vmx = to_vmx(vcpu);
8430
8431         /*
8432          * Currently we do not handle the nested case where L2 has an
8433          * APIC access page of its own; that page is still pinned.
8434          * Hence, we skip the case where the VCPU is in guest mode _and_
8435          * L1 prepared an APIC access page for L2.
8436          *
8437          * For the case where L1 and L2 share the same APIC access page
8438          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8439          * in the vmcs12), this function will only update either the vmcs01
8440          * or the vmcs02.  If the former, the vmcs02 will be updated by
8441          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8442          * the next L2->L1 exit.
8443          */
8444         if (!is_guest_mode(vcpu) ||
8445             !nested_cpu_has2(vmx->nested.current_vmcs12,
8446                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8447                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8448 }
8449
8450 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
8451 {
8452         u16 status;
8453         u8 old;
8454
8455         if (max_isr == -1)
8456                 max_isr = 0;
8457
8458         status = vmcs_read16(GUEST_INTR_STATUS);
8459         old = status >> 8;
8460         if (max_isr != old) {
8461                 status &= 0xff;
8462                 status |= max_isr << 8;
8463                 vmcs_write16(GUEST_INTR_STATUS, status);
8464         }
8465 }
8466
8467 static void vmx_set_rvi(int vector)
8468 {
8469         u16 status;
8470         u8 old;
8471
8472         if (vector == -1)
8473                 vector = 0;
8474
8475         status = vmcs_read16(GUEST_INTR_STATUS);
8476         old = (u8)status & 0xff;
8477         if ((u8)vector != old) {
8478                 status &= ~0xff;
8479                 status |= (u8)vector;
8480                 vmcs_write16(GUEST_INTR_STATUS, status);
8481         }
8482 }
8483
8484 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8485 {
8486         if (!is_guest_mode(vcpu)) {
8487                 vmx_set_rvi(max_irr);
8488                 return;
8489         }
8490
8491         if (max_irr == -1)
8492                 return;
8493
8494         /*
8495          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8496          * handles it.
8497          */
8498         if (nested_exit_on_intr(vcpu))
8499                 return;
8500
8501         /*
8502          * Else, fall back to pre-APICv interrupt injection since L2
8503          * is run without virtual interrupt delivery.
8504          */
8505         if (!kvm_event_needs_reinjection(vcpu) &&
8506             vmx_interrupt_allowed(vcpu)) {
8507                 kvm_queue_interrupt(vcpu, max_irr, false);
8508                 vmx_inject_irq(vcpu);
8509         }
8510 }
8511
8512 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8513 {
8514         if (!kvm_vcpu_apicv_active(vcpu))
8515                 return;
8516
8517         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8518         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8519         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8520         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8521 }
8522
8523 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8524 {
8525         u32 exit_intr_info;
8526
8527         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8528               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8529                 return;
8530
8531         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8532         exit_intr_info = vmx->exit_intr_info;
8533
8534         /* Handle machine checks before interrupts are enabled */
8535         if (is_machine_check(exit_intr_info))
8536                 kvm_machine_check();
8537
8538         /* We need to handle NMIs before interrupts are enabled */
8539         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
8540             (exit_intr_info & INTR_INFO_VALID_MASK)) {
8541                 kvm_before_handle_nmi(&vmx->vcpu);
8542                 asm("int $2");
8543                 kvm_after_handle_nmi(&vmx->vcpu);
8544         }
8545 }
8546
8547 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8548 {
8549         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8550         register void *__sp asm(_ASM_SP);
8551
8552         /*
8553          * If external interrupt exists, IF bit is set in rflags/eflags on the
8554          * interrupt stack frame, and interrupt will be enabled on a return
8555          * from interrupt handler.
8556          */
8557         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8558                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8559                 unsigned int vector;
8560                 unsigned long entry;
8561                 gate_desc *desc;
8562                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8563 #ifdef CONFIG_X86_64
8564                 unsigned long tmp;
8565 #endif
8566
8567                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8568                 desc = (gate_desc *)vmx->host_idt_base + vector;
8569                 entry = gate_offset(*desc);
8570                 asm volatile(
8571 #ifdef CONFIG_X86_64
8572                         "mov %%" _ASM_SP ", %[sp]\n\t"
8573                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8574                         "push $%c[ss]\n\t"
8575                         "push %[sp]\n\t"
8576 #endif
8577                         "pushf\n\t"
8578                         __ASM_SIZE(push) " $%c[cs]\n\t"
8579                         "call *%[entry]\n\t"
8580                         :
8581 #ifdef CONFIG_X86_64
8582                         [sp]"=&r"(tmp),
8583 #endif
8584                         "+r"(__sp)
8585                         :
8586                         [entry]"r"(entry),
8587                         [ss]"i"(__KERNEL_DS),
8588                         [cs]"i"(__KERNEL_CS)
8589                         );
8590         }
8591 }
8592
8593 static bool vmx_has_high_real_mode_segbase(void)
8594 {
8595         return enable_unrestricted_guest || emulate_invalid_guest_state;
8596 }
8597
8598 static bool vmx_mpx_supported(void)
8599 {
8600         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8601                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8602 }
8603
8604 static bool vmx_xsaves_supported(void)
8605 {
8606         return vmcs_config.cpu_based_2nd_exec_ctrl &
8607                 SECONDARY_EXEC_XSAVES;
8608 }
8609
8610 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8611 {
8612         u32 exit_intr_info;
8613         bool unblock_nmi;
8614         u8 vector;
8615         bool idtv_info_valid;
8616
8617         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8618
8619         if (cpu_has_virtual_nmis()) {
8620                 if (vmx->nmi_known_unmasked)
8621                         return;
8622                 /*
8623                  * Can't use vmx->exit_intr_info since we're not sure what
8624                  * the exit reason is.
8625                  */
8626                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8627                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8628                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8629                 /*
8630                  * SDM 3: 27.7.1.2 (September 2008)
8631                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
8632                  * a guest IRET fault.
8633                  * SDM 3: 23.2.2 (September 2008)
8634                  * Bit 12 is undefined in any of the following cases:
8635                  *  If the VM exit sets the valid bit in the IDT-vectoring
8636                  *   information field.
8637                  *  If the VM exit is due to a double fault.
8638                  */
8639                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8640                     vector != DF_VECTOR && !idtv_info_valid)
8641                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8642                                       GUEST_INTR_STATE_NMI);
8643                 else
8644                         vmx->nmi_known_unmasked =
8645                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8646                                   & GUEST_INTR_STATE_NMI);
8647         } else if (unlikely(vmx->soft_vnmi_blocked))
8648                 vmx->vnmi_blocked_time +=
8649                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8650 }
8651
8652 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8653                                       u32 idt_vectoring_info,
8654                                       int instr_len_field,
8655                                       int error_code_field)
8656 {
8657         u8 vector;
8658         int type;
8659         bool idtv_info_valid;
8660
8661         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8662
8663         vcpu->arch.nmi_injected = false;
8664         kvm_clear_exception_queue(vcpu);
8665         kvm_clear_interrupt_queue(vcpu);
8666
8667         if (!idtv_info_valid)
8668                 return;
8669
8670         kvm_make_request(KVM_REQ_EVENT, vcpu);
8671
8672         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8673         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8674
8675         switch (type) {
8676         case INTR_TYPE_NMI_INTR:
8677                 vcpu->arch.nmi_injected = true;
8678                 /*
8679                  * SDM 3: 27.7.1.2 (September 2008)
8680                  * Clear bit "block by NMI" before VM entry if a NMI
8681                  * delivery faulted.
8682                  */
8683                 vmx_set_nmi_mask(vcpu, false);
8684                 break;
8685         case INTR_TYPE_SOFT_EXCEPTION:
8686                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8687                 /* fall through */
8688         case INTR_TYPE_HARD_EXCEPTION:
8689                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8690                         u32 err = vmcs_read32(error_code_field);
8691                         kvm_requeue_exception_e(vcpu, vector, err);
8692                 } else
8693                         kvm_requeue_exception(vcpu, vector);
8694                 break;
8695         case INTR_TYPE_SOFT_INTR:
8696                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8697                 /* fall through */
8698         case INTR_TYPE_EXT_INTR:
8699                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8700                 break;
8701         default:
8702                 break;
8703         }
8704 }
8705
8706 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8707 {
8708         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8709                                   VM_EXIT_INSTRUCTION_LEN,
8710                                   IDT_VECTORING_ERROR_CODE);
8711 }
8712
8713 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8714 {
8715         __vmx_complete_interrupts(vcpu,
8716                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8717                                   VM_ENTRY_INSTRUCTION_LEN,
8718                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8719
8720         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8721 }
8722
8723 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8724 {
8725         int i, nr_msrs;
8726         struct perf_guest_switch_msr *msrs;
8727
8728         msrs = perf_guest_get_msrs(&nr_msrs);
8729
8730         if (!msrs)
8731                 return;
8732
8733         for (i = 0; i < nr_msrs; i++)
8734                 if (msrs[i].host == msrs[i].guest)
8735                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8736                 else
8737                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8738                                         msrs[i].host);
8739 }
8740
8741 void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
8742 {
8743         struct vcpu_vmx *vmx = to_vmx(vcpu);
8744         u64 tscl;
8745         u32 delta_tsc;
8746
8747         if (vmx->hv_deadline_tsc == -1)
8748                 return;
8749
8750         tscl = rdtsc();
8751         if (vmx->hv_deadline_tsc > tscl)
8752                 /* sure to be 32 bit only because checked on set_hv_timer */
8753                 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
8754                         cpu_preemption_timer_multi);
8755         else
8756                 delta_tsc = 0;
8757
8758         vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
8759 }
8760
8761 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8762 {
8763         struct vcpu_vmx *vmx = to_vmx(vcpu);
8764         unsigned long debugctlmsr, cr4;
8765
8766         /* Record the guest's net vcpu time for enforced NMI injections. */
8767         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8768                 vmx->entry_time = ktime_get();
8769
8770         /* Don't enter VMX if guest state is invalid, let the exit handler
8771            start emulation until we arrive back to a valid state */
8772         if (vmx->emulation_required)
8773                 return;
8774
8775         if (vmx->ple_window_dirty) {
8776                 vmx->ple_window_dirty = false;
8777                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8778         }
8779
8780         if (vmx->nested.sync_shadow_vmcs) {
8781                 copy_vmcs12_to_shadow(vmx);
8782                 vmx->nested.sync_shadow_vmcs = false;
8783         }
8784
8785         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8786                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8787         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8788                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8789
8790         cr4 = cr4_read_shadow();
8791         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8792                 vmcs_writel(HOST_CR4, cr4);
8793                 vmx->host_state.vmcs_host_cr4 = cr4;
8794         }
8795
8796         /* When single-stepping over STI and MOV SS, we must clear the
8797          * corresponding interruptibility bits in the guest state. Otherwise
8798          * vmentry fails as it then expects bit 14 (BS) in pending debug
8799          * exceptions being set, but that's not correct for the guest debugging
8800          * case. */
8801         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8802                 vmx_set_interrupt_shadow(vcpu, 0);
8803
8804         if (vmx->guest_pkru_valid)
8805                 __write_pkru(vmx->guest_pkru);
8806
8807         atomic_switch_perf_msrs(vmx);
8808         debugctlmsr = get_debugctlmsr();
8809
8810         vmx_arm_hv_timer(vcpu);
8811
8812         vmx->__launched = vmx->loaded_vmcs->launched;
8813         asm(
8814                 /* Store host registers */
8815                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8816                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8817                 "push %%" _ASM_CX " \n\t"
8818                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8819                 "je 1f \n\t"
8820                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8821                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8822                 "1: \n\t"
8823                 /* Reload cr2 if changed */
8824                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8825                 "mov %%cr2, %%" _ASM_DX " \n\t"
8826                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8827                 "je 2f \n\t"
8828                 "mov %%" _ASM_AX", %%cr2 \n\t"
8829                 "2: \n\t"
8830                 /* Check if vmlaunch of vmresume is needed */
8831                 "cmpl $0, %c[launched](%0) \n\t"
8832                 /* Load guest registers.  Don't clobber flags. */
8833                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8834                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8835                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8836                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8837                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8838                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8839 #ifdef CONFIG_X86_64
8840                 "mov %c[r8](%0),  %%r8  \n\t"
8841                 "mov %c[r9](%0),  %%r9  \n\t"
8842                 "mov %c[r10](%0), %%r10 \n\t"
8843                 "mov %c[r11](%0), %%r11 \n\t"
8844                 "mov %c[r12](%0), %%r12 \n\t"
8845                 "mov %c[r13](%0), %%r13 \n\t"
8846                 "mov %c[r14](%0), %%r14 \n\t"
8847                 "mov %c[r15](%0), %%r15 \n\t"
8848 #endif
8849                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8850
8851                 /* Enter guest mode */
8852                 "jne 1f \n\t"
8853                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8854                 "jmp 2f \n\t"
8855                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8856                 "2: "
8857                 /* Save guest registers, load host registers, keep flags */
8858                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8859                 "pop %0 \n\t"
8860                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8861                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8862                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8863                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8864                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8865                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8866                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8867 #ifdef CONFIG_X86_64
8868                 "mov %%r8,  %c[r8](%0) \n\t"
8869                 "mov %%r9,  %c[r9](%0) \n\t"
8870                 "mov %%r10, %c[r10](%0) \n\t"
8871                 "mov %%r11, %c[r11](%0) \n\t"
8872                 "mov %%r12, %c[r12](%0) \n\t"
8873                 "mov %%r13, %c[r13](%0) \n\t"
8874                 "mov %%r14, %c[r14](%0) \n\t"
8875                 "mov %%r15, %c[r15](%0) \n\t"
8876 #endif
8877                 "mov %%cr2, %%" _ASM_AX "   \n\t"
8878                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8879
8880                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
8881                 "setbe %c[fail](%0) \n\t"
8882                 ".pushsection .rodata \n\t"
8883                 ".global vmx_return \n\t"
8884                 "vmx_return: " _ASM_PTR " 2b \n\t"
8885                 ".popsection"
8886               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8887                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8888                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8889                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8890                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8891                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8892                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8893                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8894                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8895                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8896                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8897 #ifdef CONFIG_X86_64
8898                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8899                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8900                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8901                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8902                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8903                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8904                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8905                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8906 #endif
8907                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8908                 [wordsize]"i"(sizeof(ulong))
8909               : "cc", "memory"
8910 #ifdef CONFIG_X86_64
8911                 , "rax", "rbx", "rdi", "rsi"
8912                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8913 #else
8914                 , "eax", "ebx", "edi", "esi"
8915 #endif
8916               );
8917
8918         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8919         if (debugctlmsr)
8920                 update_debugctlmsr(debugctlmsr);
8921
8922 #ifndef CONFIG_X86_64
8923         /*
8924          * The sysexit path does not restore ds/es, so we must set them to
8925          * a reasonable value ourselves.
8926          *
8927          * We can't defer this to vmx_load_host_state() since that function
8928          * may be executed in interrupt context, which saves and restore segments
8929          * around it, nullifying its effect.
8930          */
8931         loadsegment(ds, __USER_DS);
8932         loadsegment(es, __USER_DS);
8933 #endif
8934
8935         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8936                                   | (1 << VCPU_EXREG_RFLAGS)
8937                                   | (1 << VCPU_EXREG_PDPTR)
8938                                   | (1 << VCPU_EXREG_SEGMENTS)
8939                                   | (1 << VCPU_EXREG_CR3));
8940         vcpu->arch.regs_dirty = 0;
8941
8942         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8943
8944         vmx->loaded_vmcs->launched = 1;
8945
8946         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8947
8948         /*
8949          * eager fpu is enabled if PKEY is supported and CR4 is switched
8950          * back on host, so it is safe to read guest PKRU from current
8951          * XSAVE.
8952          */
8953         if (boot_cpu_has(X86_FEATURE_OSPKE)) {
8954                 vmx->guest_pkru = __read_pkru();
8955                 if (vmx->guest_pkru != vmx->host_pkru) {
8956                         vmx->guest_pkru_valid = true;
8957                         __write_pkru(vmx->host_pkru);
8958                 } else
8959                         vmx->guest_pkru_valid = false;
8960         }
8961
8962         /*
8963          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8964          * we did not inject a still-pending event to L1 now because of
8965          * nested_run_pending, we need to re-enable this bit.
8966          */
8967         if (vmx->nested.nested_run_pending)
8968                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8969
8970         vmx->nested.nested_run_pending = 0;
8971
8972         vmx_complete_atomic_exit(vmx);
8973         vmx_recover_nmi_blocking(vmx);
8974         vmx_complete_interrupts(vmx);
8975 }
8976
8977 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8978 {
8979         struct vcpu_vmx *vmx = to_vmx(vcpu);
8980         int cpu;
8981
8982         if (vmx->loaded_vmcs == &vmx->vmcs01)
8983                 return;
8984
8985         cpu = get_cpu();
8986         vmx->loaded_vmcs = &vmx->vmcs01;
8987         vmx_vcpu_put(vcpu);
8988         vmx_vcpu_load(vcpu, cpu);
8989         vcpu->cpu = cpu;
8990         put_cpu();
8991 }
8992
8993 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8994 {
8995         struct vcpu_vmx *vmx = to_vmx(vcpu);
8996
8997         if (enable_pml)
8998                 vmx_destroy_pml_buffer(vmx);
8999         free_vpid(vmx->vpid);
9000         leave_guest_mode(vcpu);
9001         vmx_load_vmcs01(vcpu);
9002         free_nested(vmx);
9003         free_loaded_vmcs(vmx->loaded_vmcs);
9004         kfree(vmx->guest_msrs);
9005         kvm_vcpu_uninit(vcpu);
9006         kmem_cache_free(kvm_vcpu_cache, vmx);
9007 }
9008
9009 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
9010 {
9011         int err;
9012         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
9013         int cpu;
9014
9015         if (!vmx)
9016                 return ERR_PTR(-ENOMEM);
9017
9018         vmx->vpid = allocate_vpid();
9019
9020         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9021         if (err)
9022                 goto free_vcpu;
9023
9024         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
9025         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9026                      > PAGE_SIZE);
9027
9028         err = -ENOMEM;
9029         if (!vmx->guest_msrs) {
9030                 goto uninit_vcpu;
9031         }
9032
9033         vmx->loaded_vmcs = &vmx->vmcs01;
9034         vmx->loaded_vmcs->vmcs = alloc_vmcs();
9035         if (!vmx->loaded_vmcs->vmcs)
9036                 goto free_msrs;
9037         if (!vmm_exclusive)
9038                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
9039         loaded_vmcs_init(vmx->loaded_vmcs);
9040         if (!vmm_exclusive)
9041                 kvm_cpu_vmxoff();
9042
9043         cpu = get_cpu();
9044         vmx_vcpu_load(&vmx->vcpu, cpu);
9045         vmx->vcpu.cpu = cpu;
9046         err = vmx_vcpu_setup(vmx);
9047         vmx_vcpu_put(&vmx->vcpu);
9048         put_cpu();
9049         if (err)
9050                 goto free_vmcs;
9051         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9052                 err = alloc_apic_access_page(kvm);
9053                 if (err)
9054                         goto free_vmcs;
9055         }
9056
9057         if (enable_ept) {
9058                 if (!kvm->arch.ept_identity_map_addr)
9059                         kvm->arch.ept_identity_map_addr =
9060                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
9061                 err = init_rmode_identity_map(kvm);
9062                 if (err)
9063                         goto free_vmcs;
9064         }
9065
9066         if (nested) {
9067                 nested_vmx_setup_ctls_msrs(vmx);
9068                 vmx->nested.vpid02 = allocate_vpid();
9069         }
9070
9071         vmx->nested.posted_intr_nv = -1;
9072         vmx->nested.current_vmptr = -1ull;
9073         vmx->nested.current_vmcs12 = NULL;
9074
9075         /*
9076          * If PML is turned on, failure on enabling PML just results in failure
9077          * of creating the vcpu, therefore we can simplify PML logic (by
9078          * avoiding dealing with cases, such as enabling PML partially on vcpus
9079          * for the guest, etc.
9080          */
9081         if (enable_pml) {
9082                 err = vmx_create_pml_buffer(vmx);
9083                 if (err)
9084                         goto free_vmcs;
9085         }
9086
9087         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9088
9089         return &vmx->vcpu;
9090
9091 free_vmcs:
9092         free_vpid(vmx->nested.vpid02);
9093         free_loaded_vmcs(vmx->loaded_vmcs);
9094 free_msrs:
9095         kfree(vmx->guest_msrs);
9096 uninit_vcpu:
9097         kvm_vcpu_uninit(&vmx->vcpu);
9098 free_vcpu:
9099         free_vpid(vmx->vpid);
9100         kmem_cache_free(kvm_vcpu_cache, vmx);
9101         return ERR_PTR(err);
9102 }
9103
9104 static void __init vmx_check_processor_compat(void *rtn)
9105 {
9106         struct vmcs_config vmcs_conf;
9107
9108         *(int *)rtn = 0;
9109         if (setup_vmcs_config(&vmcs_conf) < 0)
9110                 *(int *)rtn = -EIO;
9111         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9112                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9113                                 smp_processor_id());
9114                 *(int *)rtn = -EIO;
9115         }
9116 }
9117
9118 static int get_ept_level(void)
9119 {
9120         return VMX_EPT_DEFAULT_GAW + 1;
9121 }
9122
9123 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
9124 {
9125         u8 cache;
9126         u64 ipat = 0;
9127
9128         /* For VT-d and EPT combination
9129          * 1. MMIO: always map as UC
9130          * 2. EPT with VT-d:
9131          *   a. VT-d without snooping control feature: can't guarantee the
9132          *      result, try to trust guest.
9133          *   b. VT-d with snooping control feature: snooping control feature of
9134          *      VT-d engine can guarantee the cache correctness. Just set it
9135          *      to WB to keep consistent with host. So the same as item 3.
9136          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9137          *    consistent with host MTRR
9138          */
9139         if (is_mmio) {
9140                 cache = MTRR_TYPE_UNCACHABLE;
9141                 goto exit;
9142         }
9143
9144         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9145                 ipat = VMX_EPT_IPAT_BIT;
9146                 cache = MTRR_TYPE_WRBACK;
9147                 goto exit;
9148         }
9149
9150         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9151                 ipat = VMX_EPT_IPAT_BIT;
9152                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9153                         cache = MTRR_TYPE_WRBACK;
9154                 else
9155                         cache = MTRR_TYPE_UNCACHABLE;
9156                 goto exit;
9157         }
9158
9159         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9160
9161 exit:
9162         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9163 }
9164
9165 static int vmx_get_lpage_level(void)
9166 {
9167         if (enable_ept && !cpu_has_vmx_ept_1g_page())
9168                 return PT_DIRECTORY_LEVEL;
9169         else
9170                 /* For shadow and EPT supported 1GB page */
9171                 return PT_PDPE_LEVEL;
9172 }
9173
9174 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9175 {
9176         /*
9177          * These bits in the secondary execution controls field
9178          * are dynamic, the others are mostly based on the hypervisor
9179          * architecture and the guest's CPUID.  Do not touch the
9180          * dynamic bits.
9181          */
9182         u32 mask =
9183                 SECONDARY_EXEC_SHADOW_VMCS |
9184                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9185                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9186
9187         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9188
9189         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9190                      (new_ctl & ~mask) | (cur_ctl & mask));
9191 }
9192
9193 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9194 {
9195         struct kvm_cpuid_entry2 *best;
9196         struct vcpu_vmx *vmx = to_vmx(vcpu);
9197         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
9198
9199         if (vmx_rdtscp_supported()) {
9200                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9201                 if (!rdtscp_enabled)
9202                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
9203
9204                 if (nested) {
9205                         if (rdtscp_enabled)
9206                                 vmx->nested.nested_vmx_secondary_ctls_high |=
9207                                         SECONDARY_EXEC_RDTSCP;
9208                         else
9209                                 vmx->nested.nested_vmx_secondary_ctls_high &=
9210                                         ~SECONDARY_EXEC_RDTSCP;
9211                 }
9212         }
9213
9214         /* Exposing INVPCID only when PCID is exposed */
9215         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9216         if (vmx_invpcid_supported() &&
9217             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9218             !guest_cpuid_has_pcid(vcpu))) {
9219                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
9220
9221                 if (best)
9222                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
9223         }
9224
9225         if (cpu_has_secondary_exec_ctrls())
9226                 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9227
9228         if (static_cpu_has(X86_FEATURE_PCOMMIT) && nested) {
9229                 if (guest_cpuid_has_pcommit(vcpu))
9230                         vmx->nested.nested_vmx_secondary_ctls_high |=
9231                                 SECONDARY_EXEC_PCOMMIT;
9232                 else
9233                         vmx->nested.nested_vmx_secondary_ctls_high &=
9234                                 ~SECONDARY_EXEC_PCOMMIT;
9235         }
9236
9237         if (nested_vmx_allowed(vcpu))
9238                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9239                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9240         else
9241                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9242                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9243 }
9244
9245 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9246 {
9247         if (func == 1 && nested)
9248                 entry->ecx |= bit(X86_FEATURE_VMX);
9249 }
9250
9251 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9252                 struct x86_exception *fault)
9253 {
9254         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9255         u32 exit_reason;
9256
9257         if (fault->error_code & PFERR_RSVD_MASK)
9258                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9259         else
9260                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9261         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
9262         vmcs12->guest_physical_address = fault->address;
9263 }
9264
9265 /* Callbacks for nested_ept_init_mmu_context: */
9266
9267 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9268 {
9269         /* return the page table to be shadowed - in our case, EPT12 */
9270         return get_vmcs12(vcpu)->ept_pointer;
9271 }
9272
9273 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9274 {
9275         WARN_ON(mmu_is_nested(vcpu));
9276         kvm_init_shadow_ept_mmu(vcpu,
9277                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9278                         VMX_EPT_EXECUTE_ONLY_BIT);
9279         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9280         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9281         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9282
9283         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9284 }
9285
9286 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9287 {
9288         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9289 }
9290
9291 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9292                                             u16 error_code)
9293 {
9294         bool inequality, bit;
9295
9296         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9297         inequality =
9298                 (error_code & vmcs12->page_fault_error_code_mask) !=
9299                  vmcs12->page_fault_error_code_match;
9300         return inequality ^ bit;
9301 }
9302
9303 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9304                 struct x86_exception *fault)
9305 {
9306         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9307
9308         WARN_ON(!is_guest_mode(vcpu));
9309
9310         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9311                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9312                                   vmcs_read32(VM_EXIT_INTR_INFO),
9313                                   vmcs_readl(EXIT_QUALIFICATION));
9314         else
9315                 kvm_inject_page_fault(vcpu, fault);
9316 }
9317
9318 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9319                                         struct vmcs12 *vmcs12)
9320 {
9321         struct vcpu_vmx *vmx = to_vmx(vcpu);
9322         int maxphyaddr = cpuid_maxphyaddr(vcpu);
9323
9324         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9325                 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
9326                     vmcs12->apic_access_addr >> maxphyaddr)
9327                         return false;
9328
9329                 /*
9330                  * Translate L1 physical address to host physical
9331                  * address for vmcs02. Keep the page pinned, so this
9332                  * physical address remains valid. We keep a reference
9333                  * to it so we can release it later.
9334                  */
9335                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9336                         nested_release_page(vmx->nested.apic_access_page);
9337                 vmx->nested.apic_access_page =
9338                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9339         }
9340
9341         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9342                 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
9343                     vmcs12->virtual_apic_page_addr >> maxphyaddr)
9344                         return false;
9345
9346                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9347                         nested_release_page(vmx->nested.virtual_apic_page);
9348                 vmx->nested.virtual_apic_page =
9349                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9350
9351                 /*
9352                  * Failing the vm entry is _not_ what the processor does
9353                  * but it's basically the only possibility we have.
9354                  * We could still enter the guest if CR8 load exits are
9355                  * enabled, CR8 store exits are enabled, and virtualize APIC
9356                  * access is disabled; in this case the processor would never
9357                  * use the TPR shadow and we could simply clear the bit from
9358                  * the execution control.  But such a configuration is useless,
9359                  * so let's keep the code simple.
9360                  */
9361                 if (!vmx->nested.virtual_apic_page)
9362                         return false;
9363         }
9364
9365         if (nested_cpu_has_posted_intr(vmcs12)) {
9366                 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
9367                     vmcs12->posted_intr_desc_addr >> maxphyaddr)
9368                         return false;
9369
9370                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9371                         kunmap(vmx->nested.pi_desc_page);
9372                         nested_release_page(vmx->nested.pi_desc_page);
9373                 }
9374                 vmx->nested.pi_desc_page =
9375                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9376                 if (!vmx->nested.pi_desc_page)
9377                         return false;
9378
9379                 vmx->nested.pi_desc =
9380                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9381                 if (!vmx->nested.pi_desc) {
9382                         nested_release_page_clean(vmx->nested.pi_desc_page);
9383                         return false;
9384                 }
9385                 vmx->nested.pi_desc =
9386                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9387                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9388                         (PAGE_SIZE - 1)));
9389         }
9390
9391         return true;
9392 }
9393
9394 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9395 {
9396         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9397         struct vcpu_vmx *vmx = to_vmx(vcpu);
9398
9399         if (vcpu->arch.virtual_tsc_khz == 0)
9400                 return;
9401
9402         /* Make sure short timeouts reliably trigger an immediate vmexit.
9403          * hrtimer_start does not guarantee this. */
9404         if (preemption_timeout <= 1) {
9405                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9406                 return;
9407         }
9408
9409         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9410         preemption_timeout *= 1000000;
9411         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9412         hrtimer_start(&vmx->nested.preemption_timer,
9413                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9414 }
9415
9416 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9417                                                 struct vmcs12 *vmcs12)
9418 {
9419         int maxphyaddr;
9420         u64 addr;
9421
9422         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9423                 return 0;
9424
9425         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9426                 WARN_ON(1);
9427                 return -EINVAL;
9428         }
9429         maxphyaddr = cpuid_maxphyaddr(vcpu);
9430
9431         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9432            ((addr + PAGE_SIZE) >> maxphyaddr))
9433                 return -EINVAL;
9434
9435         return 0;
9436 }
9437
9438 /*
9439  * Merge L0's and L1's MSR bitmap, return false to indicate that
9440  * we do not use the hardware.
9441  */
9442 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9443                                                struct vmcs12 *vmcs12)
9444 {
9445         int msr;
9446         struct page *page;
9447         unsigned long *msr_bitmap;
9448
9449         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9450                 return false;
9451
9452         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9453         if (!page) {
9454                 WARN_ON(1);
9455                 return false;
9456         }
9457         msr_bitmap = (unsigned long *)kmap(page);
9458         if (!msr_bitmap) {
9459                 nested_release_page_clean(page);
9460                 WARN_ON(1);
9461                 return false;
9462         }
9463
9464         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9465                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9466                         for (msr = 0x800; msr <= 0x8ff; msr++)
9467                                 nested_vmx_disable_intercept_for_msr(
9468                                         msr_bitmap,
9469                                         vmx_msr_bitmap_nested,
9470                                         msr, MSR_TYPE_R);
9471                 /* TPR is allowed */
9472                 nested_vmx_disable_intercept_for_msr(msr_bitmap,
9473                                 vmx_msr_bitmap_nested,
9474                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9475                                 MSR_TYPE_R | MSR_TYPE_W);
9476                 if (nested_cpu_has_vid(vmcs12)) {
9477                         /* EOI and self-IPI are allowed */
9478                         nested_vmx_disable_intercept_for_msr(
9479                                 msr_bitmap,
9480                                 vmx_msr_bitmap_nested,
9481                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9482                                 MSR_TYPE_W);
9483                         nested_vmx_disable_intercept_for_msr(
9484                                 msr_bitmap,
9485                                 vmx_msr_bitmap_nested,
9486                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9487                                 MSR_TYPE_W);
9488                 }
9489         } else {
9490                 /*
9491                  * Enable reading intercept of all the x2apic
9492                  * MSRs. We should not rely on vmcs12 to do any
9493                  * optimizations here, it may have been modified
9494                  * by L1.
9495                  */
9496                 for (msr = 0x800; msr <= 0x8ff; msr++)
9497                         __vmx_enable_intercept_for_msr(
9498                                 vmx_msr_bitmap_nested,
9499                                 msr,
9500                                 MSR_TYPE_R);
9501
9502                 __vmx_enable_intercept_for_msr(
9503                                 vmx_msr_bitmap_nested,
9504                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9505                                 MSR_TYPE_W);
9506                 __vmx_enable_intercept_for_msr(
9507                                 vmx_msr_bitmap_nested,
9508                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9509                                 MSR_TYPE_W);
9510                 __vmx_enable_intercept_for_msr(
9511                                 vmx_msr_bitmap_nested,
9512                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9513                                 MSR_TYPE_W);
9514         }
9515         kunmap(page);
9516         nested_release_page_clean(page);
9517
9518         return true;
9519 }
9520
9521 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9522                                            struct vmcs12 *vmcs12)
9523 {
9524         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9525             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9526             !nested_cpu_has_vid(vmcs12) &&
9527             !nested_cpu_has_posted_intr(vmcs12))
9528                 return 0;
9529
9530         /*
9531          * If virtualize x2apic mode is enabled,
9532          * virtualize apic access must be disabled.
9533          */
9534         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9535             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9536                 return -EINVAL;
9537
9538         /*
9539          * If virtual interrupt delivery is enabled,
9540          * we must exit on external interrupts.
9541          */
9542         if (nested_cpu_has_vid(vmcs12) &&
9543            !nested_exit_on_intr(vcpu))
9544                 return -EINVAL;
9545
9546         /*
9547          * bits 15:8 should be zero in posted_intr_nv,
9548          * the descriptor address has been already checked
9549          * in nested_get_vmcs12_pages.
9550          */
9551         if (nested_cpu_has_posted_intr(vmcs12) &&
9552            (!nested_cpu_has_vid(vmcs12) ||
9553             !nested_exit_intr_ack_set(vcpu) ||
9554             vmcs12->posted_intr_nv & 0xff00))
9555                 return -EINVAL;
9556
9557         /* tpr shadow is needed by all apicv features. */
9558         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9559                 return -EINVAL;
9560
9561         return 0;
9562 }
9563
9564 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9565                                        unsigned long count_field,
9566                                        unsigned long addr_field)
9567 {
9568         int maxphyaddr;
9569         u64 count, addr;
9570
9571         if (vmcs12_read_any(vcpu, count_field, &count) ||
9572             vmcs12_read_any(vcpu, addr_field, &addr)) {
9573                 WARN_ON(1);
9574                 return -EINVAL;
9575         }
9576         if (count == 0)
9577                 return 0;
9578         maxphyaddr = cpuid_maxphyaddr(vcpu);
9579         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9580             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9581                 pr_warn_ratelimited(
9582                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9583                         addr_field, maxphyaddr, count, addr);
9584                 return -EINVAL;
9585         }
9586         return 0;
9587 }
9588
9589 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9590                                                 struct vmcs12 *vmcs12)
9591 {
9592         if (vmcs12->vm_exit_msr_load_count == 0 &&
9593             vmcs12->vm_exit_msr_store_count == 0 &&
9594             vmcs12->vm_entry_msr_load_count == 0)
9595                 return 0; /* Fast path */
9596         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9597                                         VM_EXIT_MSR_LOAD_ADDR) ||
9598             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9599                                         VM_EXIT_MSR_STORE_ADDR) ||
9600             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9601                                         VM_ENTRY_MSR_LOAD_ADDR))
9602                 return -EINVAL;
9603         return 0;
9604 }
9605
9606 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9607                                        struct vmx_msr_entry *e)
9608 {
9609         /* x2APIC MSR accesses are not allowed */
9610         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9611                 return -EINVAL;
9612         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9613             e->index == MSR_IA32_UCODE_REV)
9614                 return -EINVAL;
9615         if (e->reserved != 0)
9616                 return -EINVAL;
9617         return 0;
9618 }
9619
9620 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9621                                      struct vmx_msr_entry *e)
9622 {
9623         if (e->index == MSR_FS_BASE ||
9624             e->index == MSR_GS_BASE ||
9625             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9626             nested_vmx_msr_check_common(vcpu, e))
9627                 return -EINVAL;
9628         return 0;
9629 }
9630
9631 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9632                                       struct vmx_msr_entry *e)
9633 {
9634         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9635             nested_vmx_msr_check_common(vcpu, e))
9636                 return -EINVAL;
9637         return 0;
9638 }
9639
9640 /*
9641  * Load guest's/host's msr at nested entry/exit.
9642  * return 0 for success, entry index for failure.
9643  */
9644 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9645 {
9646         u32 i;
9647         struct vmx_msr_entry e;
9648         struct msr_data msr;
9649
9650         msr.host_initiated = false;
9651         for (i = 0; i < count; i++) {
9652                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9653                                         &e, sizeof(e))) {
9654                         pr_warn_ratelimited(
9655                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9656                                 __func__, i, gpa + i * sizeof(e));
9657                         goto fail;
9658                 }
9659                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9660                         pr_warn_ratelimited(
9661                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9662                                 __func__, i, e.index, e.reserved);
9663                         goto fail;
9664                 }
9665                 msr.index = e.index;
9666                 msr.data = e.value;
9667                 if (kvm_set_msr(vcpu, &msr)) {
9668                         pr_warn_ratelimited(
9669                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9670                                 __func__, i, e.index, e.value);
9671                         goto fail;
9672                 }
9673         }
9674         return 0;
9675 fail:
9676         return i + 1;
9677 }
9678
9679 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9680 {
9681         u32 i;
9682         struct vmx_msr_entry e;
9683
9684         for (i = 0; i < count; i++) {
9685                 struct msr_data msr_info;
9686                 if (kvm_vcpu_read_guest(vcpu,
9687                                         gpa + i * sizeof(e),
9688                                         &e, 2 * sizeof(u32))) {
9689                         pr_warn_ratelimited(
9690                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9691                                 __func__, i, gpa + i * sizeof(e));
9692                         return -EINVAL;
9693                 }
9694                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9695                         pr_warn_ratelimited(
9696                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9697                                 __func__, i, e.index, e.reserved);
9698                         return -EINVAL;
9699                 }
9700                 msr_info.host_initiated = false;
9701                 msr_info.index = e.index;
9702                 if (kvm_get_msr(vcpu, &msr_info)) {
9703                         pr_warn_ratelimited(
9704                                 "%s cannot read MSR (%u, 0x%x)\n",
9705                                 __func__, i, e.index);
9706                         return -EINVAL;
9707                 }
9708                 if (kvm_vcpu_write_guest(vcpu,
9709                                          gpa + i * sizeof(e) +
9710                                              offsetof(struct vmx_msr_entry, value),
9711                                          &msr_info.data, sizeof(msr_info.data))) {
9712                         pr_warn_ratelimited(
9713                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9714                                 __func__, i, e.index, msr_info.data);
9715                         return -EINVAL;
9716                 }
9717         }
9718         return 0;
9719 }
9720
9721 /*
9722  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9723  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9724  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9725  * guest in a way that will both be appropriate to L1's requests, and our
9726  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9727  * function also has additional necessary side-effects, like setting various
9728  * vcpu->arch fields.
9729  */
9730 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9731 {
9732         struct vcpu_vmx *vmx = to_vmx(vcpu);
9733         u32 exec_control;
9734
9735         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9736         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9737         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9738         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9739         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9740         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9741         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9742         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9743         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9744         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9745         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9746         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9747         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9748         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9749         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9750         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9751         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9752         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9753         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9754         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9755         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9756         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9757         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9758         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9759         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9760         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9761         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9762         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9763         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9764         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9765         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9766         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9767         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9768         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9769         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9770         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9771
9772         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9773                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9774                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9775         } else {
9776                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9777                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9778         }
9779         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9780                 vmcs12->vm_entry_intr_info_field);
9781         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9782                 vmcs12->vm_entry_exception_error_code);
9783         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9784                 vmcs12->vm_entry_instruction_len);
9785         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9786                 vmcs12->guest_interruptibility_info);
9787         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9788         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9789         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9790                 vmcs12->guest_pending_dbg_exceptions);
9791         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9792         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9793
9794         if (nested_cpu_has_xsaves(vmcs12))
9795                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9796         vmcs_write64(VMCS_LINK_POINTER, -1ull);
9797
9798         exec_control = vmcs12->pin_based_vm_exec_control;
9799         exec_control |= vmcs_config.pin_based_exec_ctrl;
9800         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9801
9802         if (nested_cpu_has_posted_intr(vmcs12)) {
9803                 /*
9804                  * Note that we use L0's vector here and in
9805                  * vmx_deliver_nested_posted_interrupt.
9806                  */
9807                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9808                 vmx->nested.pi_pending = false;
9809                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9810                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9811                         page_to_phys(vmx->nested.pi_desc_page) +
9812                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9813                         (PAGE_SIZE - 1)));
9814         } else
9815                 exec_control &= ~PIN_BASED_POSTED_INTR;
9816
9817         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9818
9819         vmx->nested.preemption_timer_expired = false;
9820         if (nested_cpu_has_preemption_timer(vmcs12))
9821                 vmx_start_preemption_timer(vcpu);
9822
9823         /*
9824          * Whether page-faults are trapped is determined by a combination of
9825          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9826          * If enable_ept, L0 doesn't care about page faults and we should
9827          * set all of these to L1's desires. However, if !enable_ept, L0 does
9828          * care about (at least some) page faults, and because it is not easy
9829          * (if at all possible?) to merge L0 and L1's desires, we simply ask
9830          * to exit on each and every L2 page fault. This is done by setting
9831          * MASK=MATCH=0 and (see below) EB.PF=1.
9832          * Note that below we don't need special code to set EB.PF beyond the
9833          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9834          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9835          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9836          *
9837          * A problem with this approach (when !enable_ept) is that L1 may be
9838          * injected with more page faults than it asked for. This could have
9839          * caused problems, but in practice existing hypervisors don't care.
9840          * To fix this, we will need to emulate the PFEC checking (on the L1
9841          * page tables), using walk_addr(), when injecting PFs to L1.
9842          */
9843         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9844                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9845         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9846                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9847
9848         if (cpu_has_secondary_exec_ctrls()) {
9849                 exec_control = vmx_secondary_exec_control(vmx);
9850
9851                 /* Take the following fields only from vmcs12 */
9852                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9853                                   SECONDARY_EXEC_RDTSCP |
9854                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9855                                   SECONDARY_EXEC_APIC_REGISTER_VIRT |
9856                                   SECONDARY_EXEC_PCOMMIT);
9857                 if (nested_cpu_has(vmcs12,
9858                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9859                         exec_control |= vmcs12->secondary_vm_exec_control;
9860
9861                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9862                         /*
9863                          * If translation failed, no matter: This feature asks
9864                          * to exit when accessing the given address, and if it
9865                          * can never be accessed, this feature won't do
9866                          * anything anyway.
9867                          */
9868                         if (!vmx->nested.apic_access_page)
9869                                 exec_control &=
9870                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9871                         else
9872                                 vmcs_write64(APIC_ACCESS_ADDR,
9873                                   page_to_phys(vmx->nested.apic_access_page));
9874                 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9875                             cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9876                         exec_control |=
9877                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9878                         kvm_vcpu_reload_apic_access_page(vcpu);
9879                 }
9880
9881                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9882                         vmcs_write64(EOI_EXIT_BITMAP0,
9883                                 vmcs12->eoi_exit_bitmap0);
9884                         vmcs_write64(EOI_EXIT_BITMAP1,
9885                                 vmcs12->eoi_exit_bitmap1);
9886                         vmcs_write64(EOI_EXIT_BITMAP2,
9887                                 vmcs12->eoi_exit_bitmap2);
9888                         vmcs_write64(EOI_EXIT_BITMAP3,
9889                                 vmcs12->eoi_exit_bitmap3);
9890                         vmcs_write16(GUEST_INTR_STATUS,
9891                                 vmcs12->guest_intr_status);
9892                 }
9893
9894                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9895         }
9896
9897
9898         /*
9899          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9900          * Some constant fields are set here by vmx_set_constant_host_state().
9901          * Other fields are different per CPU, and will be set later when
9902          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9903          */
9904         vmx_set_constant_host_state(vmx);
9905
9906         /*
9907          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9908          * entry, but only if the current (host) sp changed from the value
9909          * we wrote last (vmx->host_rsp). This cache is no longer relevant
9910          * if we switch vmcs, and rather than hold a separate cache per vmcs,
9911          * here we just force the write to happen on entry.
9912          */
9913         vmx->host_rsp = 0;
9914
9915         exec_control = vmx_exec_control(vmx); /* L0's desires */
9916         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9917         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9918         exec_control &= ~CPU_BASED_TPR_SHADOW;
9919         exec_control |= vmcs12->cpu_based_vm_exec_control;
9920
9921         if (exec_control & CPU_BASED_TPR_SHADOW) {
9922                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9923                                 page_to_phys(vmx->nested.virtual_apic_page));
9924                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9925         }
9926
9927         if (cpu_has_vmx_msr_bitmap() &&
9928             exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9929                 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9930                 /* MSR_BITMAP will be set by following vmx_set_efer. */
9931         } else
9932                 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9933
9934         /*
9935          * Merging of IO bitmap not currently supported.
9936          * Rather, exit every time.
9937          */
9938         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9939         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9940
9941         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9942
9943         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9944          * bitwise-or of what L1 wants to trap for L2, and what we want to
9945          * trap. Note that CR0.TS also needs updating - we do this later.
9946          */
9947         update_exception_bitmap(vcpu);
9948         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9949         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9950
9951         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9952          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9953          * bits are further modified by vmx_set_efer() below.
9954          */
9955         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9956
9957         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9958          * emulated by vmx_set_efer(), below.
9959          */
9960         vm_entry_controls_init(vmx,
9961                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9962                         ~VM_ENTRY_IA32E_MODE) |
9963                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9964
9965         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9966                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9967                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9968         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
9969                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9970
9971
9972         set_cr4_guest_host_mask(vmx);
9973
9974         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9975                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9976
9977         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9978                 vmcs_write64(TSC_OFFSET,
9979                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9980         else
9981                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9982
9983         if (enable_vpid) {
9984                 /*
9985                  * There is no direct mapping between vpid02 and vpid12, the
9986                  * vpid02 is per-vCPU for L0 and reused while the value of
9987                  * vpid12 is changed w/ one invvpid during nested vmentry.
9988                  * The vpid12 is allocated by L1 for L2, so it will not
9989                  * influence global bitmap(for vpid01 and vpid02 allocation)
9990                  * even if spawn a lot of nested vCPUs.
9991                  */
9992                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
9993                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
9994                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
9995                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
9996                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
9997                         }
9998                 } else {
9999                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10000                         vmx_flush_tlb(vcpu);
10001                 }
10002
10003         }
10004
10005         if (nested_cpu_has_ept(vmcs12)) {
10006                 kvm_mmu_unload(vcpu);
10007                 nested_ept_init_mmu_context(vcpu);
10008         }
10009
10010         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
10011                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10012         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10013                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10014         else
10015                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10016         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10017         vmx_set_efer(vcpu, vcpu->arch.efer);
10018
10019         /*
10020          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
10021          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
10022          * The CR0_READ_SHADOW is what L2 should have expected to read given
10023          * the specifications by L1; It's not enough to take
10024          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10025          * have more bits than L1 expected.
10026          */
10027         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10028         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10029
10030         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10031         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10032
10033         /* shadow page tables on either EPT or shadow page tables */
10034         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
10035         kvm_mmu_reset_context(vcpu);
10036
10037         if (!enable_ept)
10038                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10039
10040         /*
10041          * L1 may access the L2's PDPTR, so save them to construct vmcs12
10042          */
10043         if (enable_ept) {
10044                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10045                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10046                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10047                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10048         }
10049
10050         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10051         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
10052 }
10053
10054 /*
10055  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10056  * for running an L2 nested guest.
10057  */
10058 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10059 {
10060         struct vmcs12 *vmcs12;
10061         struct vcpu_vmx *vmx = to_vmx(vcpu);
10062         int cpu;
10063         struct loaded_vmcs *vmcs02;
10064         bool ia32e;
10065         u32 msr_entry_idx;
10066
10067         if (!nested_vmx_check_permission(vcpu) ||
10068             !nested_vmx_check_vmcs12(vcpu))
10069                 return 1;
10070
10071         skip_emulated_instruction(vcpu);
10072         vmcs12 = get_vmcs12(vcpu);
10073
10074         if (enable_shadow_vmcs)
10075                 copy_shadow_to_vmcs12(vmx);
10076
10077         /*
10078          * The nested entry process starts with enforcing various prerequisites
10079          * on vmcs12 as required by the Intel SDM, and act appropriately when
10080          * they fail: As the SDM explains, some conditions should cause the
10081          * instruction to fail, while others will cause the instruction to seem
10082          * to succeed, but return an EXIT_REASON_INVALID_STATE.
10083          * To speed up the normal (success) code path, we should avoid checking
10084          * for misconfigurations which will anyway be caught by the processor
10085          * when using the merged vmcs02.
10086          */
10087         if (vmcs12->launch_state == launch) {
10088                 nested_vmx_failValid(vcpu,
10089                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10090                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10091                 return 1;
10092         }
10093
10094         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10095             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
10096                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10097                 return 1;
10098         }
10099
10100         if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
10101                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10102                 return 1;
10103         }
10104
10105         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
10106                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10107                 return 1;
10108         }
10109
10110         if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
10111                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10112                 return 1;
10113         }
10114
10115         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
10116                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10117                 return 1;
10118         }
10119
10120         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
10121                                 vmx->nested.nested_vmx_true_procbased_ctls_low,
10122                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
10123             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10124                                 vmx->nested.nested_vmx_secondary_ctls_low,
10125                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
10126             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
10127                                 vmx->nested.nested_vmx_pinbased_ctls_low,
10128                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
10129             !vmx_control_verify(vmcs12->vm_exit_controls,
10130                                 vmx->nested.nested_vmx_true_exit_ctls_low,
10131                                 vmx->nested.nested_vmx_exit_ctls_high) ||
10132             !vmx_control_verify(vmcs12->vm_entry_controls,
10133                                 vmx->nested.nested_vmx_true_entry_ctls_low,
10134                                 vmx->nested.nested_vmx_entry_ctls_high))
10135         {
10136                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10137                 return 1;
10138         }
10139
10140         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
10141             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
10142                 nested_vmx_failValid(vcpu,
10143                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
10144                 return 1;
10145         }
10146
10147         if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
10148             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
10149                 nested_vmx_entry_failure(vcpu, vmcs12,
10150                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10151                 return 1;
10152         }
10153         if (vmcs12->vmcs_link_pointer != -1ull) {
10154                 nested_vmx_entry_failure(vcpu, vmcs12,
10155                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
10156                 return 1;
10157         }
10158
10159         /*
10160          * If the load IA32_EFER VM-entry control is 1, the following checks
10161          * are performed on the field for the IA32_EFER MSR:
10162          * - Bits reserved in the IA32_EFER MSR must be 0.
10163          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10164          *   the IA-32e mode guest VM-exit control. It must also be identical
10165          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10166          *   CR0.PG) is 1.
10167          */
10168         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
10169                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10170                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10171                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10172                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10173                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
10174                         nested_vmx_entry_failure(vcpu, vmcs12,
10175                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10176                         return 1;
10177                 }
10178         }
10179
10180         /*
10181          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10182          * IA32_EFER MSR must be 0 in the field for that register. In addition,
10183          * the values of the LMA and LME bits in the field must each be that of
10184          * the host address-space size VM-exit control.
10185          */
10186         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10187                 ia32e = (vmcs12->vm_exit_controls &
10188                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10189                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10190                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10191                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
10192                         nested_vmx_entry_failure(vcpu, vmcs12,
10193                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10194                         return 1;
10195                 }
10196         }
10197
10198         /*
10199          * We're finally done with prerequisite checking, and can start with
10200          * the nested entry.
10201          */
10202
10203         vmcs02 = nested_get_current_vmcs02(vmx);
10204         if (!vmcs02)
10205                 return -ENOMEM;
10206
10207         enter_guest_mode(vcpu);
10208
10209         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
10210
10211         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10212                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10213
10214         cpu = get_cpu();
10215         vmx->loaded_vmcs = vmcs02;
10216         vmx_vcpu_put(vcpu);
10217         vmx_vcpu_load(vcpu, cpu);
10218         vcpu->cpu = cpu;
10219         put_cpu();
10220
10221         vmx_segment_cache_clear(vmx);
10222
10223         prepare_vmcs02(vcpu, vmcs12);
10224
10225         msr_entry_idx = nested_vmx_load_msr(vcpu,
10226                                             vmcs12->vm_entry_msr_load_addr,
10227                                             vmcs12->vm_entry_msr_load_count);
10228         if (msr_entry_idx) {
10229                 leave_guest_mode(vcpu);
10230                 vmx_load_vmcs01(vcpu);
10231                 nested_vmx_entry_failure(vcpu, vmcs12,
10232                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10233                 return 1;
10234         }
10235
10236         vmcs12->launch_state = 1;
10237
10238         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10239                 return kvm_vcpu_halt(vcpu);
10240
10241         vmx->nested.nested_run_pending = 1;
10242
10243         /*
10244          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10245          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10246          * returned as far as L1 is concerned. It will only return (and set
10247          * the success flag) when L2 exits (see nested_vmx_vmexit()).
10248          */
10249         return 1;
10250 }
10251
10252 /*
10253  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10254  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10255  * This function returns the new value we should put in vmcs12.guest_cr0.
10256  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10257  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10258  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10259  *     didn't trap the bit, because if L1 did, so would L0).
10260  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10261  *     been modified by L2, and L1 knows it. So just leave the old value of
10262  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10263  *     isn't relevant, because if L0 traps this bit it can set it to anything.
10264  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10265  *     changed these bits, and therefore they need to be updated, but L0
10266  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10267  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10268  */
10269 static inline unsigned long
10270 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10271 {
10272         return
10273         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10274         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10275         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10276                         vcpu->arch.cr0_guest_owned_bits));
10277 }
10278
10279 static inline unsigned long
10280 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10281 {
10282         return
10283         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10284         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10285         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10286                         vcpu->arch.cr4_guest_owned_bits));
10287 }
10288
10289 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10290                                        struct vmcs12 *vmcs12)
10291 {
10292         u32 idt_vectoring;
10293         unsigned int nr;
10294
10295         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10296                 nr = vcpu->arch.exception.nr;
10297                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10298
10299                 if (kvm_exception_is_soft(nr)) {
10300                         vmcs12->vm_exit_instruction_len =
10301                                 vcpu->arch.event_exit_inst_len;
10302                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10303                 } else
10304                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10305
10306                 if (vcpu->arch.exception.has_error_code) {
10307                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10308                         vmcs12->idt_vectoring_error_code =
10309                                 vcpu->arch.exception.error_code;
10310                 }
10311
10312                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10313         } else if (vcpu->arch.nmi_injected) {
10314                 vmcs12->idt_vectoring_info_field =
10315                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10316         } else if (vcpu->arch.interrupt.pending) {
10317                 nr = vcpu->arch.interrupt.nr;
10318                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10319
10320                 if (vcpu->arch.interrupt.soft) {
10321                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10322                         vmcs12->vm_entry_instruction_len =
10323                                 vcpu->arch.event_exit_inst_len;
10324                 } else
10325                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10326
10327                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10328         }
10329 }
10330
10331 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10332 {
10333         struct vcpu_vmx *vmx = to_vmx(vcpu);
10334
10335         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10336             vmx->nested.preemption_timer_expired) {
10337                 if (vmx->nested.nested_run_pending)
10338                         return -EBUSY;
10339                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10340                 return 0;
10341         }
10342
10343         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10344                 if (vmx->nested.nested_run_pending ||
10345                     vcpu->arch.interrupt.pending)
10346                         return -EBUSY;
10347                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10348                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10349                                   INTR_INFO_VALID_MASK, 0);
10350                 /*
10351                  * The NMI-triggered VM exit counts as injection:
10352                  * clear this one and block further NMIs.
10353                  */
10354                 vcpu->arch.nmi_pending = 0;
10355                 vmx_set_nmi_mask(vcpu, true);
10356                 return 0;
10357         }
10358
10359         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10360             nested_exit_on_intr(vcpu)) {
10361                 if (vmx->nested.nested_run_pending)
10362                         return -EBUSY;
10363                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10364                 return 0;
10365         }
10366
10367         return vmx_complete_nested_posted_interrupt(vcpu);
10368 }
10369
10370 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10371 {
10372         ktime_t remaining =
10373                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10374         u64 value;
10375
10376         if (ktime_to_ns(remaining) <= 0)
10377                 return 0;
10378
10379         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10380         do_div(value, 1000000);
10381         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10382 }
10383
10384 /*
10385  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10386  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10387  * and this function updates it to reflect the changes to the guest state while
10388  * L2 was running (and perhaps made some exits which were handled directly by L0
10389  * without going back to L1), and to reflect the exit reason.
10390  * Note that we do not have to copy here all VMCS fields, just those that
10391  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10392  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10393  * which already writes to vmcs12 directly.
10394  */
10395 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10396                            u32 exit_reason, u32 exit_intr_info,
10397                            unsigned long exit_qualification)
10398 {
10399         /* update guest state fields: */
10400         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10401         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10402
10403         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10404         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10405         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10406
10407         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10408         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10409         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10410         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10411         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10412         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10413         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10414         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10415         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10416         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10417         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10418         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10419         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10420         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10421         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10422         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10423         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10424         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10425         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10426         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10427         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10428         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10429         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10430         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10431         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10432         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10433         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10434         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10435         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10436         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10437         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10438         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10439         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10440         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10441         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10442         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10443
10444         vmcs12->guest_interruptibility_info =
10445                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10446         vmcs12->guest_pending_dbg_exceptions =
10447                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10448         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10449                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10450         else
10451                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10452
10453         if (nested_cpu_has_preemption_timer(vmcs12)) {
10454                 if (vmcs12->vm_exit_controls &
10455                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10456                         vmcs12->vmx_preemption_timer_value =
10457                                 vmx_get_preemption_timer_value(vcpu);
10458                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10459         }
10460
10461         /*
10462          * In some cases (usually, nested EPT), L2 is allowed to change its
10463          * own CR3 without exiting. If it has changed it, we must keep it.
10464          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10465          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10466          *
10467          * Additionally, restore L2's PDPTR to vmcs12.
10468          */
10469         if (enable_ept) {
10470                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10471                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10472                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10473                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10474                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10475         }
10476
10477         if (nested_cpu_has_vid(vmcs12))
10478                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10479
10480         vmcs12->vm_entry_controls =
10481                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10482                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10483
10484         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10485                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10486                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10487         }
10488
10489         /* TODO: These cannot have changed unless we have MSR bitmaps and
10490          * the relevant bit asks not to trap the change */
10491         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10492                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10493         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10494                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10495         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10496         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10497         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10498         if (kvm_mpx_supported())
10499                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10500         if (nested_cpu_has_xsaves(vmcs12))
10501                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10502
10503         /* update exit information fields: */
10504
10505         vmcs12->vm_exit_reason = exit_reason;
10506         vmcs12->exit_qualification = exit_qualification;
10507
10508         vmcs12->vm_exit_intr_info = exit_intr_info;
10509         if ((vmcs12->vm_exit_intr_info &
10510              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10511             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10512                 vmcs12->vm_exit_intr_error_code =
10513                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10514         vmcs12->idt_vectoring_info_field = 0;
10515         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10516         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10517
10518         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10519                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10520                  * instead of reading the real value. */
10521                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10522
10523                 /*
10524                  * Transfer the event that L0 or L1 may wanted to inject into
10525                  * L2 to IDT_VECTORING_INFO_FIELD.
10526                  */
10527                 vmcs12_save_pending_event(vcpu, vmcs12);
10528         }
10529
10530         /*
10531          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10532          * preserved above and would only end up incorrectly in L1.
10533          */
10534         vcpu->arch.nmi_injected = false;
10535         kvm_clear_exception_queue(vcpu);
10536         kvm_clear_interrupt_queue(vcpu);
10537 }
10538
10539 /*
10540  * A part of what we need to when the nested L2 guest exits and we want to
10541  * run its L1 parent, is to reset L1's guest state to the host state specified
10542  * in vmcs12.
10543  * This function is to be called not only on normal nested exit, but also on
10544  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10545  * Failures During or After Loading Guest State").
10546  * This function should be called when the active VMCS is L1's (vmcs01).
10547  */
10548 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10549                                    struct vmcs12 *vmcs12)
10550 {
10551         struct kvm_segment seg;
10552
10553         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10554                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10555         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10556                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10557         else
10558                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10559         vmx_set_efer(vcpu, vcpu->arch.efer);
10560
10561         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10562         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10563         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10564         /*
10565          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10566          * actually changed, because it depends on the current state of
10567          * fpu_active (which may have changed).
10568          * Note that vmx_set_cr0 refers to efer set above.
10569          */
10570         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10571         /*
10572          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10573          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10574          * but we also need to update cr0_guest_host_mask and exception_bitmap.
10575          */
10576         update_exception_bitmap(vcpu);
10577         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10578         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10579
10580         /*
10581          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10582          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10583          */
10584         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10585         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10586
10587         nested_ept_uninit_mmu_context(vcpu);
10588
10589         kvm_set_cr3(vcpu, vmcs12->host_cr3);
10590         kvm_mmu_reset_context(vcpu);
10591
10592         if (!enable_ept)
10593                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10594
10595         if (enable_vpid) {
10596                 /*
10597                  * Trivially support vpid by letting L2s share their parent
10598                  * L1's vpid. TODO: move to a more elaborate solution, giving
10599                  * each L2 its own vpid and exposing the vpid feature to L1.
10600                  */
10601                 vmx_flush_tlb(vcpu);
10602         }
10603
10604
10605         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10606         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10607         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10608         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10609         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10610
10611         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10612         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10613                 vmcs_write64(GUEST_BNDCFGS, 0);
10614
10615         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10616                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10617                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10618         }
10619         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10620                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10621                         vmcs12->host_ia32_perf_global_ctrl);
10622
10623         /* Set L1 segment info according to Intel SDM
10624             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10625         seg = (struct kvm_segment) {
10626                 .base = 0,
10627                 .limit = 0xFFFFFFFF,
10628                 .selector = vmcs12->host_cs_selector,
10629                 .type = 11,
10630                 .present = 1,
10631                 .s = 1,
10632                 .g = 1
10633         };
10634         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10635                 seg.l = 1;
10636         else
10637                 seg.db = 1;
10638         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10639         seg = (struct kvm_segment) {
10640                 .base = 0,
10641                 .limit = 0xFFFFFFFF,
10642                 .type = 3,
10643                 .present = 1,
10644                 .s = 1,
10645                 .db = 1,
10646                 .g = 1
10647         };
10648         seg.selector = vmcs12->host_ds_selector;
10649         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10650         seg.selector = vmcs12->host_es_selector;
10651         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10652         seg.selector = vmcs12->host_ss_selector;
10653         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10654         seg.selector = vmcs12->host_fs_selector;
10655         seg.base = vmcs12->host_fs_base;
10656         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10657         seg.selector = vmcs12->host_gs_selector;
10658         seg.base = vmcs12->host_gs_base;
10659         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10660         seg = (struct kvm_segment) {
10661                 .base = vmcs12->host_tr_base,
10662                 .limit = 0x67,
10663                 .selector = vmcs12->host_tr_selector,
10664                 .type = 11,
10665                 .present = 1
10666         };
10667         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10668
10669         kvm_set_dr(vcpu, 7, 0x400);
10670         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10671
10672         if (cpu_has_vmx_msr_bitmap())
10673                 vmx_set_msr_bitmap(vcpu);
10674
10675         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10676                                 vmcs12->vm_exit_msr_load_count))
10677                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10678 }
10679
10680 /*
10681  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10682  * and modify vmcs12 to make it see what it would expect to see there if
10683  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10684  */
10685 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10686                               u32 exit_intr_info,
10687                               unsigned long exit_qualification)
10688 {
10689         struct vcpu_vmx *vmx = to_vmx(vcpu);
10690         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10691
10692         /* trying to cancel vmlaunch/vmresume is a bug */
10693         WARN_ON_ONCE(vmx->nested.nested_run_pending);
10694
10695         leave_guest_mode(vcpu);
10696         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10697                        exit_qualification);
10698
10699         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10700                                  vmcs12->vm_exit_msr_store_count))
10701                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10702
10703         vmx_load_vmcs01(vcpu);
10704
10705         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10706             && nested_exit_intr_ack_set(vcpu)) {
10707                 int irq = kvm_cpu_get_interrupt(vcpu);
10708                 WARN_ON(irq < 0);
10709                 vmcs12->vm_exit_intr_info = irq |
10710                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10711         }
10712
10713         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10714                                        vmcs12->exit_qualification,
10715                                        vmcs12->idt_vectoring_info_field,
10716                                        vmcs12->vm_exit_intr_info,
10717                                        vmcs12->vm_exit_intr_error_code,
10718                                        KVM_ISA_VMX);
10719
10720         vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10721         vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
10722         vmx_segment_cache_clear(vmx);
10723
10724         /* if no vmcs02 cache requested, remove the one we used */
10725         if (VMCS02_POOL_SIZE == 0)
10726                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10727
10728         load_vmcs12_host_state(vcpu, vmcs12);
10729
10730         /* Update TSC_OFFSET if TSC was changed while L2 ran */
10731         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10732
10733         /* This is needed for same reason as it was needed in prepare_vmcs02 */
10734         vmx->host_rsp = 0;
10735
10736         /* Unpin physical memory we referred to in vmcs02 */
10737         if (vmx->nested.apic_access_page) {
10738                 nested_release_page(vmx->nested.apic_access_page);
10739                 vmx->nested.apic_access_page = NULL;
10740         }
10741         if (vmx->nested.virtual_apic_page) {
10742                 nested_release_page(vmx->nested.virtual_apic_page);
10743                 vmx->nested.virtual_apic_page = NULL;
10744         }
10745         if (vmx->nested.pi_desc_page) {
10746                 kunmap(vmx->nested.pi_desc_page);
10747                 nested_release_page(vmx->nested.pi_desc_page);
10748                 vmx->nested.pi_desc_page = NULL;
10749                 vmx->nested.pi_desc = NULL;
10750         }
10751
10752         /*
10753          * We are now running in L2, mmu_notifier will force to reload the
10754          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10755          */
10756         kvm_vcpu_reload_apic_access_page(vcpu);
10757
10758         /*
10759          * Exiting from L2 to L1, we're now back to L1 which thinks it just
10760          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10761          * success or failure flag accordingly.
10762          */
10763         if (unlikely(vmx->fail)) {
10764                 vmx->fail = 0;
10765                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10766         } else
10767                 nested_vmx_succeed(vcpu);
10768         if (enable_shadow_vmcs)
10769                 vmx->nested.sync_shadow_vmcs = true;
10770
10771         /* in case we halted in L2 */
10772         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10773 }
10774
10775 /*
10776  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10777  */
10778 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10779 {
10780         if (is_guest_mode(vcpu))
10781                 nested_vmx_vmexit(vcpu, -1, 0, 0);
10782         free_nested(to_vmx(vcpu));
10783 }
10784
10785 /*
10786  * L1's failure to enter L2 is a subset of a normal exit, as explained in
10787  * 23.7 "VM-entry failures during or after loading guest state" (this also
10788  * lists the acceptable exit-reason and exit-qualification parameters).
10789  * It should only be called before L2 actually succeeded to run, and when
10790  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10791  */
10792 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10793                         struct vmcs12 *vmcs12,
10794                         u32 reason, unsigned long qualification)
10795 {
10796         load_vmcs12_host_state(vcpu, vmcs12);
10797         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10798         vmcs12->exit_qualification = qualification;
10799         nested_vmx_succeed(vcpu);
10800         if (enable_shadow_vmcs)
10801                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10802 }
10803
10804 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10805                                struct x86_instruction_info *info,
10806                                enum x86_intercept_stage stage)
10807 {
10808         return X86EMUL_CONTINUE;
10809 }
10810
10811 #ifdef CONFIG_X86_64
10812 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
10813 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
10814                                   u64 divisor, u64 *result)
10815 {
10816         u64 low = a << shift, high = a >> (64 - shift);
10817
10818         /* To avoid the overflow on divq */
10819         if (high >= divisor)
10820                 return 1;
10821
10822         /* Low hold the result, high hold rem which is discarded */
10823         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
10824             "rm" (divisor), "0" (low), "1" (high));
10825         *result = low;
10826
10827         return 0;
10828 }
10829
10830 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
10831 {
10832         struct vcpu_vmx *vmx = to_vmx(vcpu);
10833         u64 tscl = rdtsc();
10834         u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
10835         u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
10836
10837         /* Convert to host delta tsc if tsc scaling is enabled */
10838         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
10839                         u64_shl_div_u64(delta_tsc,
10840                                 kvm_tsc_scaling_ratio_frac_bits,
10841                                 vcpu->arch.tsc_scaling_ratio,
10842                                 &delta_tsc))
10843                 return -ERANGE;
10844
10845         /*
10846          * If the delta tsc can't fit in the 32 bit after the multi shift,
10847          * we can't use the preemption timer.
10848          * It's possible that it fits on later vmentries, but checking
10849          * on every vmentry is costly so we just use an hrtimer.
10850          */
10851         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
10852                 return -ERANGE;
10853
10854         vmx->hv_deadline_tsc = tscl + delta_tsc;
10855         vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
10856                         PIN_BASED_VMX_PREEMPTION_TIMER);
10857         return 0;
10858 }
10859
10860 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
10861 {
10862         struct vcpu_vmx *vmx = to_vmx(vcpu);
10863         vmx->hv_deadline_tsc = -1;
10864         vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
10865                         PIN_BASED_VMX_PREEMPTION_TIMER);
10866 }
10867 #endif
10868
10869 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10870 {
10871         if (ple_gap)
10872                 shrink_ple_window(vcpu);
10873 }
10874
10875 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10876                                      struct kvm_memory_slot *slot)
10877 {
10878         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10879         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10880 }
10881
10882 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10883                                        struct kvm_memory_slot *slot)
10884 {
10885         kvm_mmu_slot_set_dirty(kvm, slot);
10886 }
10887
10888 static void vmx_flush_log_dirty(struct kvm *kvm)
10889 {
10890         kvm_flush_pml_buffers(kvm);
10891 }
10892
10893 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10894                                            struct kvm_memory_slot *memslot,
10895                                            gfn_t offset, unsigned long mask)
10896 {
10897         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10898 }
10899
10900 /*
10901  * This routine does the following things for vCPU which is going
10902  * to be blocked if VT-d PI is enabled.
10903  * - Store the vCPU to the wakeup list, so when interrupts happen
10904  *   we can find the right vCPU to wake up.
10905  * - Change the Posted-interrupt descriptor as below:
10906  *      'NDST' <-- vcpu->pre_pcpu
10907  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10908  * - If 'ON' is set during this process, which means at least one
10909  *   interrupt is posted for this vCPU, we cannot block it, in
10910  *   this case, return 1, otherwise, return 0.
10911  *
10912  */
10913 static int pi_pre_block(struct kvm_vcpu *vcpu)
10914 {
10915         unsigned long flags;
10916         unsigned int dest;
10917         struct pi_desc old, new;
10918         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10919
10920         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10921                 !irq_remapping_cap(IRQ_POSTING_CAP))
10922                 return 0;
10923
10924         vcpu->pre_pcpu = vcpu->cpu;
10925         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10926                           vcpu->pre_pcpu), flags);
10927         list_add_tail(&vcpu->blocked_vcpu_list,
10928                       &per_cpu(blocked_vcpu_on_cpu,
10929                       vcpu->pre_pcpu));
10930         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
10931                                vcpu->pre_pcpu), flags);
10932
10933         do {
10934                 old.control = new.control = pi_desc->control;
10935
10936                 /*
10937                  * We should not block the vCPU if
10938                  * an interrupt is posted for it.
10939                  */
10940                 if (pi_test_on(pi_desc) == 1) {
10941                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10942                                           vcpu->pre_pcpu), flags);
10943                         list_del(&vcpu->blocked_vcpu_list);
10944                         spin_unlock_irqrestore(
10945                                         &per_cpu(blocked_vcpu_on_cpu_lock,
10946                                         vcpu->pre_pcpu), flags);
10947                         vcpu->pre_pcpu = -1;
10948
10949                         return 1;
10950                 }
10951
10952                 WARN((pi_desc->sn == 1),
10953                      "Warning: SN field of posted-interrupts "
10954                      "is set before blocking\n");
10955
10956                 /*
10957                  * Since vCPU can be preempted during this process,
10958                  * vcpu->cpu could be different with pre_pcpu, we
10959                  * need to set pre_pcpu as the destination of wakeup
10960                  * notification event, then we can find the right vCPU
10961                  * to wakeup in wakeup handler if interrupts happen
10962                  * when the vCPU is in blocked state.
10963                  */
10964                 dest = cpu_physical_id(vcpu->pre_pcpu);
10965
10966                 if (x2apic_enabled())
10967                         new.ndst = dest;
10968                 else
10969                         new.ndst = (dest << 8) & 0xFF00;
10970
10971                 /* set 'NV' to 'wakeup vector' */
10972                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
10973         } while (cmpxchg(&pi_desc->control, old.control,
10974                         new.control) != old.control);
10975
10976         return 0;
10977 }
10978
10979 static int vmx_pre_block(struct kvm_vcpu *vcpu)
10980 {
10981         if (pi_pre_block(vcpu))
10982                 return 1;
10983
10984         if (kvm_lapic_hv_timer_in_use(vcpu))
10985                 kvm_lapic_switch_to_sw_timer(vcpu);
10986
10987         return 0;
10988 }
10989
10990 static void pi_post_block(struct kvm_vcpu *vcpu)
10991 {
10992         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10993         struct pi_desc old, new;
10994         unsigned int dest;
10995         unsigned long flags;
10996
10997         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10998                 !irq_remapping_cap(IRQ_POSTING_CAP))
10999                 return;
11000
11001         do {
11002                 old.control = new.control = pi_desc->control;
11003
11004                 dest = cpu_physical_id(vcpu->cpu);
11005
11006                 if (x2apic_enabled())
11007                         new.ndst = dest;
11008                 else
11009                         new.ndst = (dest << 8) & 0xFF00;
11010
11011                 /* Allow posting non-urgent interrupts */
11012                 new.sn = 0;
11013
11014                 /* set 'NV' to 'notification vector' */
11015                 new.nv = POSTED_INTR_VECTOR;
11016         } while (cmpxchg(&pi_desc->control, old.control,
11017                         new.control) != old.control);
11018
11019         if(vcpu->pre_pcpu != -1) {
11020                 spin_lock_irqsave(
11021                         &per_cpu(blocked_vcpu_on_cpu_lock,
11022                         vcpu->pre_pcpu), flags);
11023                 list_del(&vcpu->blocked_vcpu_list);
11024                 spin_unlock_irqrestore(
11025                         &per_cpu(blocked_vcpu_on_cpu_lock,
11026                         vcpu->pre_pcpu), flags);
11027                 vcpu->pre_pcpu = -1;
11028         }
11029 }
11030
11031 static void vmx_post_block(struct kvm_vcpu *vcpu)
11032 {
11033         if (kvm_x86_ops->set_hv_timer)
11034                 kvm_lapic_switch_to_hv_timer(vcpu);
11035
11036         pi_post_block(vcpu);
11037 }
11038
11039 /*
11040  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11041  *
11042  * @kvm: kvm
11043  * @host_irq: host irq of the interrupt
11044  * @guest_irq: gsi of the interrupt
11045  * @set: set or unset PI
11046  * returns 0 on success, < 0 on failure
11047  */
11048 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11049                               uint32_t guest_irq, bool set)
11050 {
11051         struct kvm_kernel_irq_routing_entry *e;
11052         struct kvm_irq_routing_table *irq_rt;
11053         struct kvm_lapic_irq irq;
11054         struct kvm_vcpu *vcpu;
11055         struct vcpu_data vcpu_info;
11056         int idx, ret = -EINVAL;
11057
11058         if (!kvm_arch_has_assigned_device(kvm) ||
11059                 !irq_remapping_cap(IRQ_POSTING_CAP))
11060                 return 0;
11061
11062         idx = srcu_read_lock(&kvm->irq_srcu);
11063         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11064         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
11065
11066         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11067                 if (e->type != KVM_IRQ_ROUTING_MSI)
11068                         continue;
11069                 /*
11070                  * VT-d PI cannot support posting multicast/broadcast
11071                  * interrupts to a vCPU, we still use interrupt remapping
11072                  * for these kind of interrupts.
11073                  *
11074                  * For lowest-priority interrupts, we only support
11075                  * those with single CPU as the destination, e.g. user
11076                  * configures the interrupts via /proc/irq or uses
11077                  * irqbalance to make the interrupts single-CPU.
11078                  *
11079                  * We will support full lowest-priority interrupt later.
11080                  */
11081
11082                 kvm_set_msi_irq(e, &irq);
11083                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11084                         /*
11085                          * Make sure the IRTE is in remapped mode if
11086                          * we don't handle it in posted mode.
11087                          */
11088                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11089                         if (ret < 0) {
11090                                 printk(KERN_INFO
11091                                    "failed to back to remapped mode, irq: %u\n",
11092                                    host_irq);
11093                                 goto out;
11094                         }
11095
11096                         continue;
11097                 }
11098
11099                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11100                 vcpu_info.vector = irq.vector;
11101
11102                 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
11103                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11104
11105                 if (set)
11106                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11107                 else {
11108                         /* suppress notification event before unposting */
11109                         pi_set_sn(vcpu_to_pi_desc(vcpu));
11110                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11111                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
11112                 }
11113
11114                 if (ret < 0) {
11115                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
11116                                         __func__);
11117                         goto out;
11118                 }
11119         }
11120
11121         ret = 0;
11122 out:
11123         srcu_read_unlock(&kvm->irq_srcu, idx);
11124         return ret;
11125 }
11126
11127 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11128 {
11129         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11130                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11131                         FEATURE_CONTROL_LMCE;
11132         else
11133                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11134                         ~FEATURE_CONTROL_LMCE;
11135 }
11136
11137 static struct kvm_x86_ops vmx_x86_ops = {
11138         .cpu_has_kvm_support = cpu_has_kvm_support,
11139         .disabled_by_bios = vmx_disabled_by_bios,
11140         .hardware_setup = hardware_setup,
11141         .hardware_unsetup = hardware_unsetup,
11142         .check_processor_compatibility = vmx_check_processor_compat,
11143         .hardware_enable = hardware_enable,
11144         .hardware_disable = hardware_disable,
11145         .cpu_has_accelerated_tpr = report_flexpriority,
11146         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
11147
11148         .vcpu_create = vmx_create_vcpu,
11149         .vcpu_free = vmx_free_vcpu,
11150         .vcpu_reset = vmx_vcpu_reset,
11151
11152         .prepare_guest_switch = vmx_save_host_state,
11153         .vcpu_load = vmx_vcpu_load,
11154         .vcpu_put = vmx_vcpu_put,
11155
11156         .update_bp_intercept = update_exception_bitmap,
11157         .get_msr = vmx_get_msr,
11158         .set_msr = vmx_set_msr,
11159         .get_segment_base = vmx_get_segment_base,
11160         .get_segment = vmx_get_segment,
11161         .set_segment = vmx_set_segment,
11162         .get_cpl = vmx_get_cpl,
11163         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
11164         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
11165         .decache_cr3 = vmx_decache_cr3,
11166         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
11167         .set_cr0 = vmx_set_cr0,
11168         .set_cr3 = vmx_set_cr3,
11169         .set_cr4 = vmx_set_cr4,
11170         .set_efer = vmx_set_efer,
11171         .get_idt = vmx_get_idt,
11172         .set_idt = vmx_set_idt,
11173         .get_gdt = vmx_get_gdt,
11174         .set_gdt = vmx_set_gdt,
11175         .get_dr6 = vmx_get_dr6,
11176         .set_dr6 = vmx_set_dr6,
11177         .set_dr7 = vmx_set_dr7,
11178         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
11179         .cache_reg = vmx_cache_reg,
11180         .get_rflags = vmx_get_rflags,
11181         .set_rflags = vmx_set_rflags,
11182
11183         .get_pkru = vmx_get_pkru,
11184
11185         .fpu_activate = vmx_fpu_activate,
11186         .fpu_deactivate = vmx_fpu_deactivate,
11187
11188         .tlb_flush = vmx_flush_tlb,
11189
11190         .run = vmx_vcpu_run,
11191         .handle_exit = vmx_handle_exit,
11192         .skip_emulated_instruction = skip_emulated_instruction,
11193         .set_interrupt_shadow = vmx_set_interrupt_shadow,
11194         .get_interrupt_shadow = vmx_get_interrupt_shadow,
11195         .patch_hypercall = vmx_patch_hypercall,
11196         .set_irq = vmx_inject_irq,
11197         .set_nmi = vmx_inject_nmi,
11198         .queue_exception = vmx_queue_exception,
11199         .cancel_injection = vmx_cancel_injection,
11200         .interrupt_allowed = vmx_interrupt_allowed,
11201         .nmi_allowed = vmx_nmi_allowed,
11202         .get_nmi_mask = vmx_get_nmi_mask,
11203         .set_nmi_mask = vmx_set_nmi_mask,
11204         .enable_nmi_window = enable_nmi_window,
11205         .enable_irq_window = enable_irq_window,
11206         .update_cr8_intercept = update_cr8_intercept,
11207         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
11208         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
11209         .get_enable_apicv = vmx_get_enable_apicv,
11210         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
11211         .load_eoi_exitmap = vmx_load_eoi_exitmap,
11212         .hwapic_irr_update = vmx_hwapic_irr_update,
11213         .hwapic_isr_update = vmx_hwapic_isr_update,
11214         .sync_pir_to_irr = vmx_sync_pir_to_irr,
11215         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
11216
11217         .set_tss_addr = vmx_set_tss_addr,
11218         .get_tdp_level = get_ept_level,
11219         .get_mt_mask = vmx_get_mt_mask,
11220
11221         .get_exit_info = vmx_get_exit_info,
11222
11223         .get_lpage_level = vmx_get_lpage_level,
11224
11225         .cpuid_update = vmx_cpuid_update,
11226
11227         .rdtscp_supported = vmx_rdtscp_supported,
11228         .invpcid_supported = vmx_invpcid_supported,
11229
11230         .set_supported_cpuid = vmx_set_supported_cpuid,
11231
11232         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
11233
11234         .read_tsc_offset = vmx_read_tsc_offset,
11235         .write_tsc_offset = vmx_write_tsc_offset,
11236         .adjust_tsc_offset_guest = vmx_adjust_tsc_offset_guest,
11237         .read_l1_tsc = vmx_read_l1_tsc,
11238
11239         .set_tdp_cr3 = vmx_set_cr3,
11240
11241         .check_intercept = vmx_check_intercept,
11242         .handle_external_intr = vmx_handle_external_intr,
11243         .mpx_supported = vmx_mpx_supported,
11244         .xsaves_supported = vmx_xsaves_supported,
11245
11246         .check_nested_events = vmx_check_nested_events,
11247
11248         .sched_in = vmx_sched_in,
11249
11250         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11251         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11252         .flush_log_dirty = vmx_flush_log_dirty,
11253         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
11254
11255         .pre_block = vmx_pre_block,
11256         .post_block = vmx_post_block,
11257
11258         .pmu_ops = &intel_pmu_ops,
11259
11260         .update_pi_irte = vmx_update_pi_irte,
11261
11262 #ifdef CONFIG_X86_64
11263         .set_hv_timer = vmx_set_hv_timer,
11264         .cancel_hv_timer = vmx_cancel_hv_timer,
11265 #endif
11266
11267         .setup_mce = vmx_setup_mce,
11268 };
11269
11270 static int __init vmx_init(void)
11271 {
11272         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11273                      __alignof__(struct vcpu_vmx), THIS_MODULE);
11274         if (r)
11275                 return r;
11276
11277 #ifdef CONFIG_KEXEC_CORE
11278         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11279                            crash_vmclear_local_loaded_vmcss);
11280 #endif
11281
11282         return 0;
11283 }
11284
11285 static void __exit vmx_exit(void)
11286 {
11287 #ifdef CONFIG_KEXEC_CORE
11288         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
11289         synchronize_rcu();
11290 #endif
11291
11292         kvm_exit();
11293 }
11294
11295 module_init(vmx_init)
11296 module_exit(vmx_exit)